| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect,WB_InterConnect,Wishbone_InterConnect,flow completed,0h20m20s0ms,0h13m25s0ms,4550.4132231404965,1.21,2275.2066115702482,2.03,6495.17,2753,0,0,0,0,0,0,0,44,0,0,-1,406828,29272,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,324970555.0,0.0,12.15,8.88,4.15,4.47,-1,8583,11058,396,2871,0,0,0,8561,77,20,53,966,4519,46,10,377,379,319,22,792,16716,0,17508,50.0,20.0,20,AREA 0,5,50,1,153.6,153.18,0.65,0.3,sky130_fd_sc_hd,2,4 |
