commit 1360a12d7f00b669bc05201778f2a12e04a83d5f
author onurkrts <1997karatas@gmail.com> Mon Mar 21 20:24:27 2022 +0300
committer onurkrts <1997karatas@gmail.com> Mon Mar 21 20:24:27 2022 +0300
tree cdc9733c2c027629f2128659d79556fc6d190fbd
parent f9bc20f55b5f2474af3cae63726ead28624c0c52

new run 2

.gitignore.bak

diff --git a/.gitignore.bak b/.gitignore.bak
deleted file mode 100644
index 0f43869..0000000
--- a/.gitignore.bak
+++ /dev/null
@@ -1,11 +0,0 @@
-precheck_results
-*.hex*
-*.lst
-*.vcd
-*.gtkw
-*.vvp
-mgmt_core_wrapper
-caravel
-mgmt_core_wrapper
-maglef
-mag

verilog/gl/user_project_wrapper.v

diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 2ebb37a..ecae883 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -1,6 +1,12 @@
 module user_project_wrapper (user_clock2,
     vccd1,
+    vccd2,
+    vdda1,
+    vdda2,
+    vssa1,
+    vssa2,
     vssd1,
+    vssd2,
     wb_clk_i,
     wb_rst_i,
     wbs_ack_o,
@@ -21,7 +27,13 @@
     wbs_sel_i);
  input user_clock2;
  input vccd1;
+ input vccd2;
+ input vdda1;
+ input vdda2;
+ input vssa1;
+ input vssa2;
  input vssd1;
+ input vssd2;
  input wb_clk_i;
  input wb_rst_i;
  output wbs_ack_o;