fix rom reset

missed setting WITH_ROM_RESET, so ROM values were uninitialized.
diff --git a/openlane/4ft4/config.tcl b/openlane/4ft4/config.tcl
index 56c84be..5bb9551 100755
--- a/openlane/4ft4/config.tcl
+++ b/openlane/4ft4/config.tcl
@@ -5,7 +5,10 @@
 
 set ::env(DESIGN_NAME) top_4ft4
 
-set ::env(SYNTH_DEFINES) [list "NO_TRISTATE" "ROM_FILE_BASE=\"${script_dir}/../../verilog/rtl/4ft4_rom\"" "ROM_CAPACITY=256"]
+set ::env(SYNTH_DEFINES) [list "NO_TRISTATE" \
+                               "ROM_FILE_BASE=\"${script_dir}/../../verilog/rtl/4ft4_rom\"" \
+                               "ROM_CAPACITY=256" \
+                               "WITH_ROM_RESET" ]
 
 set ::env(VERILOG_FILES) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \