commit 75d46a20aa31bf5788680d9bdf638b767ac06b8e
author Andrew Foote <afoote97@gmail.com> Mon Mar 21 09:32:12 2022 -0700
committer Andrew Foote <afoote97@gmail.com> Mon Mar 21 10:22:07 2022 -0700
tree c429d5dc4d85a95c9d15af132e6e9388c1ee1df7
parent 4b9b4bd1ac2d395556283d0d9bdb5c213bb79409

update 4ft4 submodule & 4ft4_top

connect rom in & ram out to gpio.

add LA probes for halt and reset.

4ft4

diff --git a/4ft4 b/4ft4
index 29c58f8..9417585 160000
--- a/4ft4
+++ b/4ft4
@@ -1 +1 @@
-Subproject commit 29c58f8e6708e35a8777bd6f3543aac852e843d2
+Subproject commit 9417585b62b77f0bda72091bcc064eb2b8b623a8

verilog/dv/4ft4_fib/4ft4_fib.c

diff --git a/verilog/dv/4ft4_fib/4ft4_fib.c b/verilog/dv/4ft4_fib/4ft4_fib.c
index 8336c2a..f24b222 100644
--- a/verilog/dv/4ft4_fib/4ft4_fib.c
+++ b/verilog/dv/4ft4_fib/4ft4_fib.c
@@ -149,6 +149,10 @@
   // ISZ 14
   0x7e,
   0x5b,
+  // LDM 7
+  0xd7,
+  // WMP
+  0xe1
 };
 
 void main()
@@ -196,6 +200,20 @@
     reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
     reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
 
+    reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+
+    reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+    reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+    reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+    reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+
      /* Apply configuration */
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);

verilog/rtl/4ft4_top.v

diff --git a/verilog/rtl/4ft4_top.v b/verilog/rtl/4ft4_top.v
index b823795..17f4fec 100644
--- a/verilog/rtl/4ft4_top.v
+++ b/verilog/rtl/4ft4_top.v
@@ -24,10 +24,36 @@
     output [2:0] irq
 );
 
+wire halt;
+assign halt = (~la_oenb[0]) ? la_data_in[0] : 1'b0;
+
+wire la_reset;
+wire reset;
+
+assign la_reset = (~la_oenb[32]) ? la_data_in[32] : 1'b0;
+assign reset = la_reset | wb_reset_i;
+
+wire [3:0] rom_in;
+assign rom_in = io_in[3:0];
+assign io_oeb[3:0] = 4'hf;
+
+wire [7:0] ram_out;
+assign io_out[11:4] = ram_out;
+assign io_oeb[11:4] = {8{reset}};
+
+assign io_out[`MPRJ_IO_PADS-1:12] = 0;
+assign io_oeb[`MPRJ_IO_PADS-1:12] = 0;
+
+assign la_data_out = {{56{1'b0}}, ram_out, {64{1'b0}}};
+
+assign irq = 3'b000;
+
 wb_system sys(
     .clock(wb_clock_i),
-    .reset(wb_reset_i),
-    .rom_out(),
+    .reset(reset),
+    .halt(halt),
+    .rom_in(rom_in),
+    .ram_out(ram_out),
 
     .wb_data_i(wb_data_i),
     .wb_addr_i(wb_addr_i),