initial checkpoint of 4ft4 as a caravel user project

openlane/4ft4/config.json

diff --git a/openlane/4ft4/config.json b/openlane/4ft4/config.json
new file mode 100644
index 0000000..fcf32ab
--- /dev/null
+++ b/openlane/4ft4/config.json
@@ -0,0 +1,30 @@
+{
+    "PDK"                      : "sky130A",
+    "STD_CELL_LIBRARY"         : "sky130_fd_sc_hd",
+    "CARAVEL_ROOT"             : "../../caravel",
+    "CLOCK_NET"                : "counter.clk",
+    "CLOCK_PERIOD"             : "10",
+    "CLOCK_PORT"               : "wb_clk_i",
+    "DESIGN_IS_CORE"           : "0",
+    "DESIGN_NAME"              : "user_proj_example",
+    "DIE_AREA"                 : "0 0 900 600",
+    "DIODE_INSERTION_STRATEGY" : "4",
+    "FP_PIN_ORDER_CFG"         : "pin_order.cfg",
+    "FP_SIZING"                : "absolute",
+    "GLB_RT_MAXLAYER"          : "5",
+    "GND_NETS"                 : "vssd1",
+    "PL_BASIC_PLACEMENT"       : "1",
+    "PL_TARGET_DENSITY"        : "0.05",
+    "RUN_CVC"                  : "1",
+    "VDD_NETS"                 : "vccd1",
+    "VERILOG_FILES"            : ["../../caravel/verilog/rtl/defines.v",
+                                  "../../verilog/rtl/4ft4_top.v",
+                                  "../../4ft4/rtl/wb_system.v",
+                                  "../../4ft4/rtl/cpu.v",
+                                  "../../4ft4/rtl/cpu_control.v",
+                                  "../../4ft4/rtl/alu.v",
+                                  "../../4ft4/rtl/datapath.v",
+                                  "../../4ft4/rtl/pc_stack.v",
+                                  "../../4ft4/rtl/rom.v",
+                                  "../../4ft4/rtl/ram.v"]
+}

openlane/4ft4/config.tcl

diff --git a/openlane/4ft4/config.tcl b/openlane/4ft4/config.tcl
new file mode 100755
index 0000000..9ba8c1d
--- /dev/null
+++ b/openlane/4ft4/config.tcl
@@ -0,0 +1,54 @@
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) top_4ft4
+
+set ::env(SYNTH_DEFINES) [list "NO_TRISTATE" "ROM_HEX_FILE=\"${script_dir}/../../verilog/rtl/4ft4_rom.hex\"" "ROM_CAPACITY=128"]
+
+set ::env(VERILOG_FILES) "\
+	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+	$script_dir/../../verilog/rtl/4ft4_top.v \
+	$script_dir/../../4ft4/rtl/wb_system.v \
+	$script_dir/../../4ft4/rtl/cpu.v \
+	$script_dir/../../4ft4/rtl/cpu_control.v \
+	$script_dir/../../4ft4/rtl/alu.v \
+	$script_dir/../../4ft4/rtl/datapath.v \
+	$script_dir/../../4ft4/rtl/pc_stack.v \
+	$script_dir/../../4ft4/rtl/rom.v \
+	$script_dir/../../4ft4/rtl/ram.v"
+
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(CLOCK_PORT) "wb_clock_i"
+set ::env(CLOCK_NET) "wb_clock_i"
+set ::env(CLOCK_PERIOD) "10"
+
+#set ::env(FP_SIZING) absolute
+#set ::env(DIE_AREA) "0 0 900 900"
+
+set ::env(FP_SIZING) relative
+set ::env(FP_CORE_UTIL) 10
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::env(PL_BASIC_PLACEMENT) 0
+set ::env(PL_TARGET_DENSITY) 0.12
+
+# Maximum layer used for routing is metal 4.
+# This is because this macro will be inserted in a top level (user_project_wrapper)
+# where the PDN is planned on metal 5. So, to avoid having shorts between routes
+# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.
+# 
+# set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(RT_MAX_LAYER) {met4}
+
+# You can draw more power domains if you need to
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+# If you're going to use multiple power domains, then disable cvc run.
+set ::env(RUN_CVC) 1

openlane/4ft4/pin_order.cfg

diff --git a/openlane/4ft4/pin_order.cfg b/openlane/4ft4/pin_order.cfg
new file mode 100644
index 0000000..2fda806
--- /dev/null
+++ b/openlane/4ft4/pin_order.cfg
@@ -0,0 +1,10 @@
+#BUS_SORT
+
+#S
+wb_.*
+wbs_.*
+la_.*
+irq.*
+
+#N
+io_.*

verilog/rtl/4ft4_top.v

diff --git a/verilog/rtl/4ft4_top.v b/verilog/rtl/4ft4_top.v
new file mode 100644
index 0000000..b823795
--- /dev/null
+++ b/verilog/rtl/4ft4_top.v
@@ -0,0 +1,41 @@
+`default_nettype none
+
+module top_4ft4(
+`ifdef USE_POWER_PINS
+    inout vccd1, // User area 1 1.8V supply
+    inout vssd1, // User area 1 digital ground
+`endif
+    input wb_clock_i,
+    input wb_reset_i,
+    input wb_strobe_i,
+    input wb_cyc_i,
+    input wb_we_i,
+    input [3:0] wb_sel_i,
+    input [31:0] wb_data_i,
+    input [31:0] wb_addr_i,
+    output [31:0] wb_data_o,
+    output wb_ack_o,
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb,
+    input  [`MPRJ_IO_PADS-1:0] io_in,
+    output [`MPRJ_IO_PADS-1:0] io_out,
+    output [`MPRJ_IO_PADS-1:0] io_oeb,
+    output [2:0] irq
+);
+
+wb_system sys(
+    .clock(wb_clock_i),
+    .reset(wb_reset_i),
+    .rom_out(),
+
+    .wb_data_i(wb_data_i),
+    .wb_addr_i(wb_addr_i),
+    .wb_cyc_i(wb_cyc_i),
+    .wb_strobe_i(wb_strobe_i),
+    .wb_we_i(wb_we_i),
+    .wb_data_o(wb_data_o),
+    .wb_ack_o(wb_ack_o)
+);
+
+endmodule