| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/home/andrew/mpw/caravel_user_project/openlane/4ft4,top_4ft4,4ft4,flow completed,0h36m26s0ms,0h16m58s0ms,92347.14147893812,0.6314001610250001,23086.78536973453,25.57,3631.77,14577,0,0,0,0,0,0,0,36,0,0,-1,1240433,162301,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,861511212.0,0.0,56.7,56.23,26.88,35.63,-1,5843,9592,568,4288,0,0,0,8196,44,5,58,80,798,31,5,3284,2915,2894,27,572,8640,0,9212,100.0,10.0,10,AREA 0,5,25,1,153.6,153.18,0.27,0.3,sky130_fd_sc_hd,4,4 |
