commit 29e4bd4cc5326c9a6420394b70e2ef76ad364aa1
author Steve Goldsmith <steve@aurifexlabs.com> Tue Mar 22 02:32:10 2022 +0000
committer Steve Goldsmith <steve@aurifexlabs.com> Tue Mar 22 02:32:10 2022 +0000
tree b467be3c6ef06d97a029ee3f0936a8ec165dd556
parent fd08fc0f557a678f3774b8bde5d4cc3813f9c39f

Touched up readme.

README.md

diff --git a/README.md b/README.md
index cc9538c..6861371 100644
--- a/README.md
+++ b/README.md
@@ -1,8 +1,11 @@
 # PSRAM Interface with PRNG
 
 PSRAM and integration: Steve Goldsmith, Lead Instructor, Aurifex Labs, https://aurifexlabs.com
+
 PRNG: Zhenle Cao
 
+Many thanks to Matt Venn!
+
 ## Design
 
 ### PSRAM Interface
@@ -51,6 +54,7 @@
 
 To run:
 cd verilog/rtl/unit_test
+
 sby cover.sby
 
 To run again:
@@ -62,6 +66,8 @@
 Tests include:
 - read
 - write
+- 2 reads
+- 2 writes
 - read and write
 
 ### Caravel Test
@@ -69,6 +75,7 @@
 To run:
 
 make verify-la_test2-rtl
+
 make verify-la_test2-gl
 
 This only tests that the PSRAM state machine advances to state 2.