Update SSTL test circuit

* Add lvs extraction script
3 files changed
tree: 2cb18fadcf0bb545f7e9e72312531967d0dd87aa
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. netgen/
  6. openlane/
  7. verilog/
  8. xschem/
  9. .gitignore
  10. LICENSE
  11. Makefile
  12. README.md
README.md

DDR3 SSTL Caravel Analog Project

License

A (possibly temporary) location for DDR3 SSTL test circuit project.


Refer to README for this sample project documentation.