commit: 234fad614541431a47d7fd1e091b032677b94fbb
[log] [tgz]
author: Derek H-M <derekcom16@gmail.com>
Mon Feb 14 19:59:00 2022 -0800
committer: Derek H-M <derekcom16@gmail.com>
Mon Feb 14 19:59:00 2022 -0800
tree: 462a7fe3d5760658a65f4b889f1c8a3c815375b2
parent: 497da8643c42c1e47a0d72077b3e1bff4f46b26b [diff]

Add more to SSTL test cell

* TODO: seperate digital and I/O logic to use two seprate
  power supplies

mag/proj_sstl_test.mag[diff]

1 file changed

tree: 462a7fe3d5760658a65f4b889f1c8a3c815375b2

README.md

DDR3 SSTL Caravel Analog Project

A (possibly temporary) location for DDR3 SSTL test circuit project.

Refer to README for this sample project documentation.