Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-031 / d67d63285a3a4b6d8c57f011b36d446764a3fcfb
commitd67d63285a3a4b6d8c57f011b36d446764a3fcfb[log] [tgz]
authorDerek H-M <derekcom16@gmail.com>Sun Mar 06 13:07:14 2022 -0800
committerDerek H-M <derekcom16@gmail.com>Sun Mar 06 13:07:14 2022 -0800
treecbd780773e7b6dbaee1189b0e9f8f78d3fa524a1
parent475b7bc003053b02881f50edf5703d4030690c58 [diff]
Add series resistor to data input

* Some basic esd protection
* Fix drc issue from previous commit
3 files changed
tree: cbd780773e7b6dbaee1189b0e9f8f78d3fa524a1
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. netgen/
  6. openlane/
  7. verilog/
  8. xschem/
  9. caravel
  10. .gitignore
  11. .magicrc
  12. LICENSE
  13. Makefile
  14. README.md
README.md

DDR3 SSTL Caravel Analog Project

License

A (possibly temporary) location for DDR3 SSTL test circuit project.

Refer to README for this sample project documentation.