commit: d67d63285a3a4b6d8c57f011b36d446764a3fcfb
[log] [tgz]
author: Derek H-M <derekcom16@gmail.com>
Sun Mar 06 13:07:14 2022 -0800
committer: Derek H-M <derekcom16@gmail.com>
Sun Mar 06 13:07:14 2022 -0800
tree: cbd780773e7b6dbaee1189b0e9f8f78d3fa524a1
parent: 475b7bc003053b02881f50edf5703d4030690c58 [diff]

Add series resistor to data input

* Some basic esd protection
* Fix drc issue from previous commit

3 files changed

tree: cbd780773e7b6dbaee1189b0e9f8f78d3fa524a1

README.md

DDR3 SSTL Caravel Analog Project

A (possibly temporary) location for DDR3 SSTL test circuit project.

Refer to README for this sample project documentation.