Add config sreg testbench * Some minor fixes
diff --git a/xschem/cfg_shift_register.sch b/xschem/cfg_shift_register.sch index eccb4a3..e074680 100644 --- a/xschem/cfg_shift_register.sch +++ b/xschem/cfg_shift_register.sch
@@ -45,22 +45,30 @@ N 1300 -70 1300 -40 { lab=q[5]} N 1500 -70 1500 -40 { lab=q[6]} N 1700 -70 1700 -40 { lab=q[7]} +N 310 -30 1720 -30 { lab=xxx} C {sky130/sky130_stdcells/dfxtp_1.sym} 190 -80 0 0 {name=x1 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ } C {devices/ipin.sym} 70 -120 0 0 {name=p1 lab=clk} -C {devices/opin.sym} 300 -40 1 0 {name=p3 lab=q[0]} -C {devices/opin.sym} 500 -40 1 0 {name=p4 lab=q[1] +C {devices/bus_connect.sym} 310 -30 0 1 {name=l3 lab=q[0]} +C {devices/bus_connect.sym} 510 -30 0 1 {name=l4 lab=q[1] } -C {devices/opin.sym} 700 -40 1 0 {name=p5 lab=q[2] +C {devices/bus_connect.sym} 710 -30 0 1 {name=l1 lab=q[2] + } -C {devices/opin.sym} 900 -40 1 0 {name=p6 lab=q[3] +C {devices/bus_connect.sym} 910 -30 0 1 {name=l2 lab=q[3] + } -C {devices/opin.sym} 1100 -40 1 0 {name=p7 lab=q[4] +C {devices/bus_connect.sym} 1110 -30 0 1 {name=l5 lab=q[4] + } -C {devices/opin.sym} 1300 -40 1 0 {name=p8 lab=q[5] +C {devices/bus_connect.sym} 1310 -30 0 1 {name=l6 lab=q[5] + } -C {devices/opin.sym} 1500 -40 1 0 {name=p9 lab=q[6] +C {devices/bus_connect.sym} 1510 -30 0 1 {name=l7 lab=q[6] + } -C {devices/opin.sym} 1700 -40 1 0 {name=p10 lab=q[7]} +C {devices/bus_connect.sym} 1710 -30 0 1 {name=l8 lab=q[7] + +} C {devices/ipin.sym} 100 -40 3 0 {name=p2 lab=d_in} C {devices/code_shown.sym} 120 -210 0 0 {name=MODELS only_toplevel=true @@ -77,3 +85,4 @@ C {sky130/sky130_stdcells/dfxtp_1.sym} 1190 -80 0 0 {name=x6 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ } C {sky130/sky130_stdcells/dfxtp_1.sym} 1390 -80 0 0 {name=x7 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ } C {sky130/sky130_stdcells/dfxtp_1.sym} 1590 -80 0 0 {name=x8 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ } +C {devices/opin.sym} 1720 -30 0 0 {name=p3 lab=q[7:0]}
diff --git a/xschem/cfg_shift_register.sym b/xschem/cfg_shift_register.sym new file mode 100644 index 0000000..ccf31b2 --- /dev/null +++ b/xschem/cfg_shift_register.sym
@@ -0,0 +1,24 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @@clk @@d_in @@q[7:0] @VDD @GND @symname" +template="name=X1 VDD=VDD GND=GND" +extra="VDD GND"} +V {} +S {} +E {} +L 4 560 -160 600 -160 {} +L 4 60 -160 100 -160 {} +L 4 60 -100 100 -100 {} +B 5 57.5 -102.5 62.5 -97.5 {name=clk +dir=in} +B 5 57.5 -162.5 62.5 -157.5 {name=d_in +dir=in} +B 5 597.5 -162.5 602.5 -157.5 {name=q[7:0] +dir=out} +P 4 5 100 -200 560 -200 560 -80 100 -80 100 -200 {} +T {CONFIG SREG} 180 -150 0 0 0.8 0.8 {} +T {@name} 290 -220 0 0 0.3 0.3 {} +T {clk} 100 -110 0 0 0.3 0.3 {} +T {d_in} 100 -170 0 0 0.3 0.3 {} +T {q[7:0]} 510 -170 0 0 0.3 0.3 {}
diff --git a/xschem/cfg_shift_register_tb.sch b/xschem/cfg_shift_register_tb.sch new file mode 100644 index 0000000..4425a88 --- /dev/null +++ b/xschem/cfg_shift_register_tb.sch
@@ -0,0 +1,56 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 130 -180 170 -180 { lab=#net1} +N 710 -180 760 -180 { lab=q[7:0]} +N 30 -180 70 -180 { lab=d_d_in} +N 30 -120 70 -120 { lab=d_clk} +N 130 -120 170 -120 { lab=#net2} +C {xschem/cfg_shift_register.sym} 110 -20 0 0 {name=x3 VDD=VDD GND=GND} +C {devices/dac_bridge.sym} 100 -180 0 0 {name=A1 dac_bridge_model=dac_1v5} +C {devices/code_shown.sym} 20 -60 0 0 {name=s1 only_toplevel=false +value=".model dac_1v5 dac_bridge(out_low=0.0 out_high=1.5 ++ out_undef=0.75 input_load=1e-12 t_rise=100e-12 t_fall=100e-12)"} +C {devices/dac_bridge.sym} 100 -120 0 0 {name=A2 dac_bridge_model=dac_1v5} +C {devices/lab_wire.sym} 760 -180 0 0 {name=l1 sig_type=std_logic lab=q[7:0]} +C {devices/code.sym} 710 -120 0 0 {name=STIMULI +only_toplevel=true +place=end +value=" +* power voltage +vvdd VDD 0 1.5 + +** STATIC CONTOL + + +** Signal +a_source [d_clk d_d_in] d_source1 +.model d_source1 d_source(input_file=\\"cfg_sreg_din.txt\\") + + +.control +save all +set temp=27 + +* RUN SIMULATION +tran 1n 20n + +* OUTPUT +set hcopydevtype = svg +hardcopy ./sreg_tb.svg net1-2 net2-2 \\"q[0]\\" \\"q[1]\\"+2 \\"q[2]\\"+4 \\"q[3]\\"+6 \\"q[4]\\"+8 \\"q[5]\\"+10 \\"q[6]\\"+12 \\"q[7]\\"+14 title 'SSTL Test Circuit' + +.endc +"} +C {devices/code.sym} 850 -120 0 0 {name=MODELS +only_toplevel=true +format="tcleval( @value )" +value="** Local library links to pdk +.lib sky130/libs/tt_lib.spice tt +.include \\\\$::SKYWATER_STDCELLS\\\\/sky130_fd_sc_hd.spice +" +spice_ignore=false} +C {devices/lab_wire.sym} 70 -120 0 0 {name=l2 sig_type=std_logic lab=d_clk} +C {devices/lab_wire.sym} 70 -180 0 0 {name=l3 sig_type=std_logic lab=d_d_in}
diff --git a/xschem/cfg_shift_register_tb.spice b/xschem/cfg_shift_register_tb.spice new file mode 100644 index 0000000..9a2a4b2 --- /dev/null +++ b/xschem/cfg_shift_register_tb.spice
@@ -0,0 +1,64 @@ +**.subckt cfg_shift_register_tb +x3 net2 net1 q[7] q[6] q[5] q[4] q[3] q[2] q[1] q[0] VDD GND cfg_shift_register +A1 [ d_d_in ] [ net1 ] dac_1v5 +A2 [ d_clk ] [ net2 ] dac_1v5 +**** begin user architecture code + +.model dac_1v5 dac_bridge(out_low=0.0 out_high=1.5 out_undef=0.75 input_load=1e-12 t_rise=100e-12 ++ t_fall=100e-12) + + ** Local library links to pdk +.lib sky130/libs/tt_lib.spice tt +.include /home/derekhm/proj/caravan-project/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice + +**** end user architecture code +**.ends + +* expanding symbol: xschem/cfg_shift_register.sym # of pins=3 +* sym_path: /home/derekhm/proj/caravan-project/xschem/cfg_shift_register.sym +* sch_path: /home/derekhm/proj/caravan-project/xschem/cfg_shift_register.sch +.subckt cfg_shift_register clk d_in q[7] q[6] q[5] q[4] q[3] q[2] q[1] q[0] VDD GND +*.ipin clk +*.ipin d_in +*.opin q[7],q[6],q[5],q[4],q[3],q[2],q[1],q[0] +x1 clk d_in GND GND VDD VDD q[0] sky130_fd_sc_hd__dfxtp_1 +x2 clk q[0] GND GND VDD VDD q[1] sky130_fd_sc_hd__dfxtp_1 +x3 clk q[1] GND GND VDD VDD q[2] sky130_fd_sc_hd__dfxtp_1 +x4 clk q[2] GND GND VDD VDD q[3] sky130_fd_sc_hd__dfxtp_1 +x5 clk q[3] GND GND VDD VDD q[4] sky130_fd_sc_hd__dfxtp_1 +x6 clk q[4] GND GND VDD VDD q[5] sky130_fd_sc_hd__dfxtp_1 +x7 clk q[5] GND GND VDD VDD q[6] sky130_fd_sc_hd__dfxtp_1 +x8 clk q[6] GND GND VDD VDD q[7] sky130_fd_sc_hd__dfxtp_1 +.ends + +**** begin user architecture code + + +* power voltage +vvdd VDD 0 1.5 + +** STATIC CONTOL + + +** Signal +a_source [d_clk d_d_in] d_source1 +.model d_source1 d_source(input_file="cfg_sreg_din.txt") + + +.control +save all +set temp=27 + +* RUN SIMULATION +tran 1n 20n + +* OUTPUT +set hcopydevtype = svg +hardcopy ./sreg_tb.svg net1-2 net2-2 "q[0]" "q[1]"+2 "q[2]"+4 "q[3]"+6 "q[4]"+8 "q[5]"+10 "q[6]"+12 ++ "q[7]"+14 title 'SSTL Test Circuit' + +.endc + + +**** end user architecture code +.end
diff --git a/xschem/cfg_sreg_din.txt b/xschem/cfg_sreg_din.txt new file mode 100755 index 0000000..57cc849 --- /dev/null +++ b/xschem/cfg_sreg_din.txt
@@ -0,0 +1,17 @@ +* time, d_clk d_d_in +0n 0s 1s +1n 1s 1s +2n 0s 0s +3n 1s 0s +4n 0s 1s +5n 1s 1s +6n 0s 0s +7n 1s 0s +8n 0s 1s +9n 1s 1s +10n 0s 0s +11n 1s 0s +12n 0s 1s +13n 1s 1s +14n 0s 0s +15n 1s 0s \ No newline at end of file
diff --git a/xschem/proj_sstl_test_tb.spice b/xschem/proj_sstl_test_tb.spice index 0de2513..e3cb41b 100644 --- a/xschem/proj_sstl_test_tb.spice +++ b/xschem/proj_sstl_test_tb.spice
@@ -9,12 +9,12 @@ **** begin user architecture code ** Local library links to pdk .lib ./sky130/libs/tt_lib.spice tt -.include /home/derekhm/cad/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice +.include /home/derekhm/proj/caravan-project/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice **** end user architecture code **.ends -* expanding symbol: /home/derekhm/proj/caravan-project/xschem/proj_sstl_test.sym # of pins=14 +* expanding symbol: xschem/proj_sstl_test.sym # of pins=14 * sym_path: /home/derekhm/proj/caravan-project/xschem/proj_sstl_test.sym * sch_path: /home/derekhm/proj/caravan-project/xschem/proj_sstl_test.sch .subckt proj_sstl_test rx_leg_ctrl[6] rx_leg_ctrl[5] rx_leg_ctrl[4] rx_leg_ctrl[3] rx_leg_ctrl[2] @@ -69,7 +69,7 @@ .ends -* expanding symbol: /home/derekhm/proj/caravan-project/xschem/SSTL/SSTL.sym # of pins=5 +* expanding symbol: xschem/SSTL/SSTL.sym # of pins=5 * sym_path: /home/derekhm/proj/caravan-project/xschem/SSTL/SSTL.sym * sch_path: /home/derekhm/proj/caravan-project/xschem/SSTL/SSTL.sch .subckt SSTL DQ pd_ctrl[6] pd_ctrl[5] pd_ctrl[4] pd_ctrl[3] pd_ctrl[2] pd_ctrl[1] pd_ctrl[0]