commit: ca80b78a7ca83b24d4699593af4384a3a7816122
[log] [tgz]
author: Derek H-M <derekcom16@gmail.com>
Wed Mar 02 07:51:25 2022 -0800
committer: Derek H-M <derekcom16@gmail.com>
Wed Mar 02 07:51:25 2022 -0800
tree: 0090424cfa2e898ca016e780a33f09267f253d94
parent: 952a1b0a95db6e88e57350b7ef338ffc08e827c1 [diff]

Add config sreg testbench

* Some minor fixes

xschem/cfg_shift_register.sch[diff]
xschem/cfg_shift_register.sym[Added - diff]
xschem/cfg_shift_register_tb.sch[Added - diff]
xschem/cfg_shift_register_tb.spice[Added - diff]
xschem/cfg_sreg_din.txt[Added - diff]
xschem/proj_sstl_test_tb.spice[diff]

6 files changed

tree: 0090424cfa2e898ca016e780a33f09267f253d94

README.md

DDR3 SSTL Caravel Analog Project

A (possibly temporary) location for DDR3 SSTL test circuit project.

Refer to README for this sample project documentation.