Add schematic and spice TB for proj_sstl_test cell
diff --git a/mag/lvs_netgen.tcl b/mag/lvs_netgen.tcl
index 585fb6e..7f63507 100755
--- a/mag/lvs_netgen.tcl
+++ b/mag/lvs_netgen.tcl
@@ -4,4 +4,4 @@
select top cell;
ext2spice -o "lvs_[cellname list self].spice";
# Replace names with:
-# sed -i "s/sky130_fd_sc_hd__/extr_sky130_fd_sc_hd__/g" lvs_SSTL.spice
\ No newline at end of file
+# exec sed -i "s/sky130_fd_sc_hd__/extr_sky130_fd_sc_hd__/g" "lvs_[cellname list self].spice";
\ No newline at end of file
diff --git a/mag/pex_netgen.tcl b/mag/pex_netgen.tcl
new file mode 100755
index 0000000..6bef599
--- /dev/null
+++ b/mag/pex_netgen.tcl
@@ -0,0 +1,23 @@
+# Tim's Cap-Res extraction procedure
+
+set NAME [cellname list self];
+select top cell;
+# (Flattening improves resistance extraction)
+flatten "[list $NAME]_flat";
+load "[list $NAME]_flat";
+select top cell;
+
+extract do resistance;
+extract all;
+
+ext2sim labels on;
+ext2sim;
+
+extresist tolerance 10;
+extresist all;
+
+ext2spice lvs;
+ext2spice cthresh 0.1;
+ext2spice rthresh 10
+ext2spice extresist on;
+ext2spice -o "pex_[list $NAME].spice";
diff --git a/xschem/SSTL/SSTL.sch b/xschem/SSTL/SSTL.sch
new file mode 100644
index 0000000..4a367ee
--- /dev/null
+++ b/xschem/SSTL/SSTL.sch
@@ -0,0 +1,234 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 640 -1000 640 -880 { lab=DQ}
+N 1200 -1000 1200 -880 { lab=DQ}
+N 1760 -1000 1760 -880 { lab=DQ}
+N 2320 -1000 2320 -880 { lab=DQ}
+N 2880 -1000 2880 -880 { lab=DQ}
+N 3440 -1000 3440 -880 { lab=DQ}
+N 4000 -1000 4000 -880 { lab=DQ}
+N 1200 -940 1760 -940 { lab=DQ}
+N 1760 -940 2320 -940 { lab=DQ}
+N 2320 -940 2880 -940 { lab=DQ}
+N 2880 -940 3440 -940 { lab=DQ}
+N 3440 -940 4000 -940 { lab=DQ}
+N 4000 -940 4120 -940 { lab=DQ}
+N 640 -940 1200 -940 { lab=DQ}
+N 140 -1000 160 -1000 { lab=n_pu_ctrl[6]}
+N 120 -1220 680 -1220 { lab=n_pu_ctrl[6:0]
+bus=true}
+N 140 -1210 140 -1000 { lab=n_pu_ctrl[6]}
+N 120 -700 680 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 120 -660 680 -660 { lab=pd_ctrl_buff[6:0]
+bus=true}
+N 140 -880 140 -670 { lab=pd_ctrl_buff[6]}
+N 140 -880 160 -880 { lab=pd_ctrl_buff[6]}
+N 700 -1000 720 -1000 { lab=n_pu_ctrl[5]}
+N 680 -1220 1240 -1220 { lab=n_pu_ctrl[6:0]
+bus=true}
+N 700 -1210 700 -1000 { lab=n_pu_ctrl[5]}
+N 680 -700 1240 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 680 -660 1240 -660 { lab=pd_ctrl_buff[6:0]
+bus=true}
+N 700 -880 700 -670 { lab=pd_ctrl_buff[5]}
+N 700 -880 720 -880 { lab=pd_ctrl_buff[5]}
+N 1260 -1000 1280 -1000 { lab=n_pu_ctrl[4]}
+N 1240 -1220 1800 -1220 { lab=n_pu_ctrl[6:0]
+bus=true}
+N 1260 -1210 1260 -1000 { lab=n_pu_ctrl[4]}
+N 1240 -700 1800 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 1240 -660 1800 -660 { lab=pd_ctrl_buff[6:0]
+bus=true}
+N 1260 -880 1260 -670 { lab=pd_ctrl_buff[4]}
+N 1260 -880 1280 -880 { lab=pd_ctrl_buff[4]}
+N 1820 -1000 1840 -1000 { lab=n_pu_ctrl[3]}
+N 1800 -1220 2360 -1220 { lab=n_pu_ctrl[6:0]
+bus=true}
+N 1820 -1210 1820 -1000 { lab=n_pu_ctrl[3]}
+N 1800 -700 2360 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 1800 -660 2360 -660 { lab=pd_ctrl_buff[6:0]
+bus=true}
+N 1820 -880 1820 -670 { lab=pd_ctrl_buff[3]}
+N 1820 -880 1840 -880 { lab=pd_ctrl_buff[3]}
+N 2380 -1000 2400 -1000 { lab=n_pu_ctrl[2]}
+N 2360 -1220 2920 -1220 { lab=n_pu_ctrl[6:0]
+bus=true}
+N 2380 -1210 2380 -1000 { lab=n_pu_ctrl[2]}
+N 2360 -700 2920 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 2360 -660 2920 -660 { lab=pd_ctrl_buff[6:0]
+bus=true}
+N 2380 -880 2380 -670 { lab=pd_ctrl_buff[2]}
+N 2380 -880 2400 -880 { lab=pd_ctrl_buff[2]}
+N 2940 -1000 2960 -1000 { lab=n_pu_ctrl[1]}
+N 2920 -1220 3480 -1220 { lab=n_pu_ctrl[6:0]
+bus=true}
+N 2940 -1210 2940 -1000 { lab=n_pu_ctrl[1]}
+N 2920 -700 3480 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 2920 -660 3480 -660 { lab=pd_ctrl_buff[6:0]
+bus=true}
+N 2940 -880 2940 -670 { lab=pd_ctrl_buff[1]}
+N 2940 -880 2960 -880 { lab=pd_ctrl_buff[1]}
+N 3500 -1000 3520 -1000 { lab=n_pu_ctrl[0]}
+N 3480 -1220 4040 -1220 { lab=n_pu_ctrl[6:0]
+bus=true}
+N 3500 -1210 3500 -1000 { lab=n_pu_ctrl[0]}
+N 3480 -700 4040 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 3480 -660 4040 -660 { lab=pd_ctrl_buff[6:0]
+bus=true}
+N 3500 -880 3500 -670 { lab=pd_ctrl_buff[0]}
+N 3500 -880 3520 -880 { lab=pd_ctrl_buff[0]}
+N 240 -580 280 -580 { lab=pdc4[6:0]
+bus=true}
+N 20 -1180 40 -1180 { lab=pu_cal_ctrl[3:0]
+bus=true}
+N 20 -700 120 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 360 -1300 420 -1300 { lab=n_pu_ctrl[6:0]
+bus=true}
+N 420 -1300 420 -1220 { lab=n_pu_ctrl[6:0]
+bus=true}
+N 360 -580 420 -580 { lab=pd_ctrl_buff[6:0]
+bus=true}
+N 420 -660 420 -580 { lab=pd_ctrl_buff[6:0]
+bus=true}
+N 280 -1360 280 -1300 { lab=puc4[6:0]
+bus=true}
+N 360 -1360 360 -1300 { lab=n_pu_ctrl[6:0]
+bus=true}
+N 20 -580 50 -580 { lab=pd_ctrl[6:0] bus=true}
+N 130 -580 160 -580 { lab=pdc2[6:0] bus=true}
+N 20 -1300 120 -1300 { lab=pu_ctrl[6:0] bus=true}
+N 200 -1300 280 -1300 { lab=puc4[6:0] bus=true}
+N 280 -1420 280 -1360 { lab=puc4[6:0]
+bus=true}
+N 360 -1420 360 -1360 { lab=n_pu_ctrl[6:0]
+bus=true}
+N 160 -1180 160 -1120 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 160 -1180 720 -1180 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 720 -1180 720 -1120 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 720 -1180 1280 -1180 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 1280 -1180 1280 -1120 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 1280 -1180 1840 -1180 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 1840 -1180 1840 -1120 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 1840 -1180 2400 -1180 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 2400 -1180 2400 -1120 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 2400 -1180 2960 -1180 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 2960 -1180 2960 -1120 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 2960 -1180 3520 -1180 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 3520 -1180 3520 -1120 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 3520 -1180 4080 -1180 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 120 -1180 160 -1180 { lab=n_pu_cal_ctrl[3:0]
+bus=true}
+N 160 -760 160 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 720 -760 720 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 1280 -760 1280 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 1840 -760 1840 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 2400 -760 2400 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 2960 -760 2960 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+N 3520 -760 3520 -700 { lab=pd_cal_ctrl[3:0]
+bus=true}
+C {p-leg.sym} 140 -940 0 0 {name=X1}
+C {n-leg.sym} 140 -700 0 0 {name=X2}
+C {p-leg.sym} 700 -940 0 0 {name=X3}
+C {n-leg.sym} 700 -700 0 0 {name=X4}
+C {p-leg.sym} 1260 -940 0 0 {name=X5}
+C {n-leg.sym} 1260 -700 0 0 {name=X6}
+C {p-leg.sym} 1820 -940 0 0 {name=X7}
+C {n-leg.sym} 1820 -700 0 0 {name=X8}
+C {p-leg.sym} 2380 -940 0 0 {name=X9}
+C {n-leg.sym} 2380 -700 0 0 {name=X10}
+C {p-leg.sym} 2940 -940 0 0 {name=X11}
+C {n-leg.sym} 2940 -700 0 0 {name=X12}
+C {p-leg.sym} 3500 -940 0 0 {name=X13}
+C {n-leg.sym} 3500 -700 0 0 {name=X14}
+C {devices/iopin.sym} 4120 -940 0 0 {name=p1 lab=DQ}
+C {devices/title.sym} 150 -30 0 0 {name=l1 author="Derek H-M"}
+C {devices/bus_connect.sym} 130 -1220 1 0 {name=l2 lab=n_pu_ctrl[6]}
+C {devices/bus_connect.sym} 150 -660 3 0 {name=l5 lab=pd_ctrl_buff[6]}
+C {devices/bus_connect.sym} 690 -1220 1 0 {name=l6 lab=n_pu_ctrl[5]}
+C {devices/bus_connect.sym} 710 -660 3 0 {name=l9 lab=pd_ctrl_buff[5]}
+C {devices/bus_connect.sym} 1250 -1220 1 0 {name=l10 lab=n_pu_ctrl[4]
+}
+C {devices/bus_connect.sym} 1270 -660 3 0 {name=l13 lab=pd_ctrl_buff[4]}
+C {devices/bus_connect.sym} 1810 -1220 1 0 {name=l14 lab=n_pu_ctrl[3]}
+C {devices/bus_connect.sym} 1830 -660 3 0 {name=l17 lab=pd_ctrl_buff[3]}
+C {devices/bus_connect.sym} 2370 -1220 1 0 {name=l18 lab=n_pu_ctrl[2]}
+C {devices/bus_connect.sym} 2390 -660 3 0 {name=l21 lab=pd_ctrl_buff[2]}
+C {devices/bus_connect.sym} 2930 -1220 1 0 {name=l22 lab=n_pu_ctrl[1]}
+C {devices/bus_connect.sym} 2950 -660 3 0 {name=l25 lab=pd_ctrl_buff[1]}
+C {devices/bus_connect.sym} 3490 -1220 1 0 {name=l26 lab=n_pu_ctrl[0]}
+C {devices/bus_connect.sym} 3510 -660 3 0 {name=l29 lab=pd_ctrl_buff[0]}
+C {sky130_stdcells/clkinv_4.sym} 200 -580 0 0 {name=xpd_buff_4[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/clkbuf_8.sym} 320 -580 0 0 {name=xpd_buff_6[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/clkbuf_16.sym} 160 -1300 0 0 {name=xpu_buff_4[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/clkinv_16.sym} 320 -1300 0 0 {name=xpu_buff_6[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {devices/ipin.sym} 20 -1180 0 0 {name=p2 lab=pu_cal_ctrl[3:0]}
+C {sky130/sky130_stdcells/inv_1.sym} 80 -1180 0 0 {name=xpu_cal_inv[3:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {devices/lab_wire.sym} 380 -1220 0 0 {name=l30 sig_type=std_logic lab=n_pu_ctrl[6:0]}
+C {devices/lab_wire.sym} 380 -1180 0 0 {name=l31 sig_type=std_logic lab=n_pu_cal_ctrl[3:0]}
+C {devices/ipin.sym} 20 -700 0 0 {name=p3 lab=pd_cal_ctrl[3:0]}
+C {devices/lab_wire.sym} 360 -700 0 0 {name=l32 sig_type=std_logic lab=pd_cal_ctrl[3:0]}
+C {devices/ipin.sym} 20 -1300 0 0 {name=p4 lab=pu_ctrl[6:0]}
+C {devices/ipin.sym} 20 -580 0 0 {name=p5 lab=pd_ctrl[6:0]}
+C {devices/lab_wire.sym} 360 -660 0 0 {name=l33 sig_type=std_logic lab=pd_ctrl_buff[6:0]}
+C {devices/lab_wire.sym} 280 -1300 0 0 {name=l34 sig_type=std_logic lab=puc4[6:0]}
+C {devices/lab_wire.sym} 280 -580 0 0 {name=l36 sig_type=std_logic lab=pdc4[6:0]}
+C {sky130_stdcells/clkinv_16.sym} 320 -1360 0 0 {name=xpu_buff_2[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/clkinv_4.sym} 90 -580 0 0 {name=xpd_buff_1[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {devices/lab_wire.sym} 160 -580 0 0 {name=l47 sig_type=std_logic lab=pdc2[6:0]}
+C {sky130_stdcells/clkinv_16.sym} 320 -1420 0 0 {name=xpu_buff_1[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {devices/code_shown.sym} 500 -1350 0 0 {name=MODELS
+only_toplevel=true
+place=header
+format="tcleval( @value )"
+value="** Local library links to pdk
+.include \\\\$::SKYWATER_STDCELLS\\\\/sky130_fd_sc_hd.spice
+"
+spice_ignore=false}
diff --git a/xschem/SSTL/SSTL.sym b/xschem/SSTL/SSTL.sym
new file mode 100644
index 0000000..ea10f70
--- /dev/null
+++ b/xschem/SSTL/SSTL.sym
@@ -0,0 +1,32 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @@DQ @@pd_ctrl[6:0] @@pu_ctrl[6:0] @@pd_cal_ctrl[3:0] @@pu_cal_ctrl[3:0] @VDD @GND @symname"
+template="name=X1 VDD=VDD GND=GND"
+extra="VDD GND"}
+V {}
+S {}
+E {}
+L 4 460 -120 500 -120 {}
+L 4 20 -60 60 -60 {}
+L 4 20 -90 60 -90 {}
+L 4 20 -180 60 -180 {}
+L 4 20 -150 60 -150 {}
+B 5 497.5 -122.5 502.5 -117.5 {name=DQ
+dir=inout}
+B 5 17.5 -62.5 22.5 -57.5 {name=pd_ctrl[6:0]
+dir=in}
+B 5 17.5 -92.5 22.5 -87.5 {name=pd_cal_ctrl[3:0]
+dir=in}
+B 5 17.5 -182.5 22.5 -177.5 {name=pu_ctrl[6:0]
+dir=in}
+B 5 17.5 -152.5 22.5 -147.5 {name=pu_cal_ctrl[3:0]
+dir=in}
+P 4 5 60 -200 460 -200 460 -40 60 -40 60 -200 {}
+T {DDR3 SSTL} 150 -140 0 0 0.8 0.8 {}
+T {DQ} 430 -130 0 0 0.3 0.3 {}
+T {pd_ctrl[6:0]} 70 -70 0 0 0.3 0.3 {}
+T {pd_cal_ctrl[3:0]} 70 -100 0 0 0.3 0.3 {}
+T {@name} 230 -230 0 0 0.3 0.3 {}
+T {pu_ctrl[6:0]} 70 -190 0 0 0.3 0.3 {}
+T {pu_cal_ctrl[3:0]} 70 -160 0 0 0.3 0.3 {}
diff --git a/xschem/SSTL/n-leg.sch b/xschem/SSTL/n-leg.sch
new file mode 100644
index 0000000..18fc6ce
--- /dev/null
+++ b/xschem/SSTL/n-leg.sch
@@ -0,0 +1,144 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 730 -360 730 -320 { lab=DQ}
+N 730 -260 730 -220 { lab=vpulldown}
+N 730 -160 730 -120 { lab=GND}
+N 730 -190 730 -160 { lab=GND}
+N 400 -390 410 -390 { lab=GND}
+N 620 -390 630 -390 { lab=GND}
+N 400 -420 620 -420 { lab=DQ}
+N 400 -360 620 -360 { lab=vpulldown}
+N 400 -290 410 -290 { lab=GND}
+N 620 -290 630 -290 { lab=GND}
+N 400 -320 540 -320 { lab=DQ}
+N 400 -260 540 -260 { lab=vpulldown}
+N 470 -420 470 -320 { lab=DQ}
+N 490 -360 490 -260 { lab=vpulldown}
+N 540 -320 620 -320 { lab=DQ}
+N 540 -260 620 -260 { lab=vpulldown}
+N 620 -320 730 -320 { lab=DQ}
+N 620 -260 730 -260 { lab=vpulldown}
+N 730 -420 750 -420 { lab=DQ}
+N 290 -390 360 -390 { lab=cal_ctrl[0]}
+N 290 -290 360 -290 { lab=cal_ctrl[2]}
+N 280 -480 280 -250 { lab=cal_ctrl[3:0]
+bus=true}
+N 580 -390 580 -340 { lab=cal_ctrl[1]}
+N 290 -340 580 -340 { lab=cal_ctrl[1]}
+N 580 -290 580 -240 { lab=cal_ctrl[3]}
+N 290 -240 580 -240 { lab=cal_ctrl[3]}
+N 270 -480 280 -480 { lab=cal_ctrl[3:0]
+bus=true}
+N 610 -190 620 -190 { lab=pd_ctrl}
+N 680 -190 690 -190 { lab=#net1}
+N 730 -420 730 -360 { lab=DQ}
+N 620 -190 680 -190 {}
+C {devices/title.sym} 160 -30 0 0 {name=l1 author="Derek H-M"}
+C {sky130_fd_pr/res_generic_po.sym} 730 -290 0 0 {name=R1
+W=0.33
+L=1.7
+model=res_generic_po
+mult=1}
+C {devices/gnd.sym} 730 -120 0 0 {name=l4 lab=GND}
+C {sky130/sky130_fd_pr/nfet_01v8.sym} 710 -190 0 0 {name=n1
+L=0.15
+W=0.65
+nf=1
+mult=48
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 730 -240 0 0 {name=l2 sig_type=std_logic lab=vpulldown}
+C {sky130/sky130_fd_pr/nfet_01v8.sym} 380 -390 0 0 {name=nctrl0
+L=0.15
+W=0.65
+nf=1
+mult=32
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {devices/gnd.sym} 410 -390 0 0 {name=l5 lab=GND}
+C {sky130/sky130_fd_pr/nfet_01v8.sym} 600 -390 0 0 {name=nctrl1
+L=0.15
+W=0.65
+nf=1
+mult=8
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {devices/gnd.sym} 630 -390 0 0 {name=l9 lab=GND}
+C {sky130/sky130_fd_pr/nfet_01v8.sym} 380 -290 0 0 {name=nctrl2
+L=0.15
+W=0.65
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {devices/gnd.sym} 410 -290 0 0 {name=l11 lab=GND}
+C {sky130/sky130_fd_pr/nfet_01v8.sym} 600 -290 0 0 {name=nctrl3
+L=0.15
+W=0.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {devices/gnd.sym} 630 -290 0 0 {name=l13 lab=GND}
+C {devices/iopin.sym} 750 -420 0 0 {name=p1 lab=DQ}
+C {devices/ipin.sym} 610 -190 0 0 {name=p2 lab=pd_ctrl}
+C {devices/bus_connect.sym} 280 -250 1 0 {name=l3 lab=cal_ctrl[3]}
+C {devices/bus_connect.sym} 280 -350 1 0 {name=l6 lab=cal_ctrl[1]}
+C {devices/bus_connect.sym} 280 -300 1 0 {name=l7 lab=cal_ctrl[2]}
+C {devices/bus_connect.sym} 280 -400 1 0 {name=l8 lab=cal_ctrl[0]}
+C {devices/ipin.sym} 270 -480 0 0 {name=p3 lab=cal_ctrl[3:0]}
diff --git a/xschem/SSTL/n-leg.sym b/xschem/SSTL/n-leg.sym
new file mode 100644
index 0000000..db74bbd
--- /dev/null
+++ b/xschem/SSTL/n-leg.sym
@@ -0,0 +1,24 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @@DQ @@pd_ctrl @@cal_ctrl[3:0] @symname"
+template="name=X1"}
+V {}
+S {}
+E {}
+L 4 460 -180 500 -180 {}
+L 4 20 -180 60 -180 {}
+L 4 20 -60 60 -60 {}
+B 5 497.5 -182.5 502.5 -177.5 {name=DQ
+dir=inout}
+B 5 17.5 -182.5 22.5 -177.5 {name=pd_ctrl
+dir=in}
+B 5 17.5 -62.5 22.5 -57.5 {name=cal_ctrl[3:0]
+dir=in}
+P 4 5 60 -200 460 -200 460 -40 60 -40 60 -200 {}
+T {240 Ohm
+Pulldown} 160 -170 0 0 0.8 0.8 {}
+T {DQ} 430 -190 0 0 0.3 0.3 {}
+T {pd_ctrl} 70 -190 0 0 0.3 0.3 {}
+T {cal_ctrl[3:0]} 70 -70 0 0 0.3 0.3 {}
+T {@name} 230 -230 0 0 0.3 0.3 {}
diff --git a/xschem/SSTL/n-leg_tb.sch b/xschem/SSTL/n-leg_tb.sch
new file mode 100644
index 0000000..05a803f
--- /dev/null
+++ b/xschem/SSTL/n-leg_tb.sch
@@ -0,0 +1,99 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1020 -520 1020 -490 { lab=VDDQ}
+N 500 -220 500 -210 { lab=cal_ctrl[3]}
+N 500 -150 500 -140 { lab=GND}
+N 370 -220 370 -210 { lab=cal_ctrl[2]}
+N 370 -150 370 -140 { lab=GND}
+N 240 -220 240 -210 { lab=cal_ctrl[1]}
+N 240 -150 240 -140 { lab=GND}
+N 100 -220 100 -210 { lab=cal_ctrl[0]}
+N 100 -150 100 -140 { lab=GND}
+N 1020 -430 1020 -410 { lab=DQ}
+N 490 -350 490 -330 { lab=GND}
+N 500 -280 500 -220 { lab=cal_ctrl[3]}
+N 370 -280 370 -220 { lab=cal_ctrl[2]}
+N 240 -280 240 -220 { lab=cal_ctrl[1]}
+N 100 -280 100 -220 { lab=cal_ctrl[0]}
+N 90 -290 540 -290 {lab=cal_ctrl[3:0]
+bus=true}
+N 490 -410 540 -410 { lab=pd_ctrl}
+C {devices/title.sym} 160 -30 0 0 {name=l1 author="Derek H-M"}
+C {devices/code.sym} 790 -200 0 0 {name=STIMULI
+only_toplevel=true
+place=end
+value="
+
+* power voltage
+vvddq VDDQ 0 0
+
+.control
+save all
+set temp=SED_temp_SED
+
+* RUN SIMULATION
+dc vvddq 0.3 1.2 0.05
+* OUTPUT
+print v(vddq)/i(vtest)
+wrdata out/SED_plotName_SED/SED_plotName_SED.txt v(vddq)/i(vtest)
+set hcopydevtype = svg
+hardcopy ./out/SED_plotName_SED/SED_plotName_SED.svg vddq/I(vtest) vs vddq title 'Resistance vs pin voltage'
+
+.endc
+"}
+C {devices/code.sym} 930 -200 0 0 {name=MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="** Local library links to pdk
+.lib ./sky130/libs/SED_process_SED_lib.spice SED_process_SED
+"
+spice_ignore=false}
+C {devices/lab_pin.sym} 1020 -520 0 0 {name=l3 sig_type=std_logic lab=VDDQ
+}
+C {devices/ammeter.sym} 1020 -460 0 0 {name=vtest}
+C {devices/gnd.sym} 490 -340 0 0 {name=l4 lab=GND}
+C {devices/vsource.sym} 490 -380 0 0 {name=Vgate value=SED_vg_SED}
+C {devices/vsource.sym} 100 -180 0 0 {name=Vctrl0
+*value=0
+value=SED_vctrl0_SED}
+C {devices/gnd.sym} 500 -140 0 0 {name=l7 lab=GND}
+C {devices/gnd.sym} 370 -140 0 0 {name=l15 lab=GND}
+C {devices/gnd.sym} 240 -140 0 0 {name=l17 lab=GND}
+C {devices/gnd.sym} 100 -140 0 0 {name=l19 lab=GND}
+C {devices/vsource.sym} 240 -180 0 0 {name=Vctrl1
+*value=0
+value=SED_vctrl1_SED}
+C {devices/vsource.sym} 370 -180 0 0 {name=Vctrl2
+*value=0
+value=SED_vctrl2_SED}
+C {devices/vsource.sym} 500 -180 0 0 {name=Vctrl3
+*value=0
+value=SED_vctrl3_SED}
+C {n-leg.sym} 520 -230 0 0 {name=X1}
+C {devices/bus_connect.sym} 90 -290 1 0 {name=l2 lab=cal_ctrl[0]}
+C {devices/bus_connect.sym} 230 -290 1 0 {name=l5 lab=cal_ctrl[1]}
+C {devices/bus_connect.sym} 490 -290 1 0 {name=l6 lab=cal_ctrl[3]}
+C {devices/bus_connect.sym} 360 -290 1 0 {name=l8 lab=cal_ctrl[2]}
+C {devices/lab_pin.sym} 490 -410 0 0 {name=l10 sig_type=std_logic lab=pd_ctrl}
+C {devices/lab_pin.sym} 1020 -410 2 0 {name=l11 sig_type=std_logic lab=DQ}
+C {devices/lab_wire.sym} 480 -290 0 0 {name=l12 sig_type=std_logic_vector lab=cal_ctrl[3:0]}
diff --git a/xschem/SSTL/p-leg.sch b/xschem/SSTL/p-leg.sch
new file mode 100644
index 0000000..6ec2b7c
--- /dev/null
+++ b/xschem/SSTL/p-leg.sch
@@ -0,0 +1,146 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 340 -390 360 -390 { lab=n_cal_ctrl[0]}
+N 560 -390 580 -390 { lab=n_cal_ctrl[1]}
+N 400 -420 620 -420 { lab=#net1}
+N 400 -360 620 -360 { lab=DQ}
+N 340 -290 360 -290 { lab=n_cal_ctrl[2]}
+N 560 -290 580 -290 { lab=n_cal_ctrl[3]}
+N 400 -320 540 -320 { lab=#net1}
+N 400 -260 540 -260 { lab=DQ}
+N 470 -420 470 -320 { lab=#net1}
+N 490 -360 490 -260 { lab=DQ}
+N 540 -320 620 -320 { lab=#net1}
+N 540 -260 620 -260 { lab=DQ}
+N 730 -420 730 -320 { lab=#net1}
+N 400 -390 410 -390 { lab=VDD}
+N 620 -390 630 -390 { lab=VDD}
+N 400 -290 410 -290 { lab=VDD}
+N 620 -290 630 -290 { lab=VDD}
+N 240 -450 260 -450 { lab=n_cal_ctrl[3:0]
+bus=true}
+N 270 -390 340 -390 { lab=n_cal_ctrl[0]}
+N 270 -340 560 -340 { lab=n_cal_ctrl[1]}
+N 560 -390 560 -340 { lab=n_cal_ctrl[1]}
+N 270 -290 340 -290 { lab=n_cal_ctrl[2]}
+N 270 -240 560 -240 { lab=n_cal_ctrl[3]}
+N 560 -290 560 -240 { lab=n_cal_ctrl[3]}
+N 260 -450 260 -250 {bus=true lab=n_cal_ctrl[3:0]}
+N 730 -180 820 -180 { lab=DQ}
+N 620 -320 730 -320 { lab=#net1}
+N 620 -260 730 -260 { lab=DQ}
+N 730 -520 730 -480 { lab=VDD}
+N 730 -480 730 -450 { lab=VDD}
+N 730 -260 730 -240 { lab=DQ}
+N 590 -450 610 -450 { lab=n_pu_ctrl}
+N 670 -450 690 -450 { lab=n_pu_ctrl}
+N 610 -450 670 -450 { lab=n_pu_ctrl}
+N 730 -240 730 -180 { lab=DQ}
+C {devices/title.sym} 160 -30 0 0 {name=l1 author="Derek H-M"}
+C {devices/vdd.sym} 730 -520 0 0 {name=l3 lab=VDD}
+C {sky130/sky130_fd_pr/res_generic_po.sym} 730 -290 0 0 {name=R1
+W=0.33
+L=1.8
+model=res_generic_po
+mult=1}
+C {devices/vdd.sym} 410 -390 1 0 {name=l5 lab=VDD}
+C {devices/vdd.sym} 630 -390 1 0 {name=l9 lab=VDD}
+C {devices/vdd.sym} 410 -290 1 0 {name=l11 lab=VDD}
+C {devices/vdd.sym} 630 -290 1 0 {name=l13 lab=VDD}
+C {devices/ipin.sym} 240 -450 0 0 {name=p1 lab=n_cal_ctrl[3:0]}
+C {devices/bus_connect.sym} 260 -400 1 0 {name=l6 lab=n_cal_ctrl[0]}
+C {devices/bus_connect.sym} 260 -300 1 0 {name=l2 lab=n_cal_ctrl[2]}
+C {devices/bus_connect.sym} 260 -350 1 0 {name=l8 lab=n_cal_ctrl[1]}
+C {devices/bus_connect.sym} 260 -250 1 0 {name=l4 lab=n_cal_ctrl[3]}
+C {devices/ipin.sym} 590 -450 0 0 {name=p2 lab=n_pu_ctrl}
+C {devices/iopin.sym} 820 -180 0 0 {name=p3 lab=DQ}
+C {sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 710 -450 0 0 {name=Mpullup
+L=0.35
+W=1
+nf=1
+mult=96
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 380 -390 0 0 {name=Mctrl0
+L=0.35
+W=1
+nf=1
+mult=48
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 600 -390 0 0 {name=Mctrl1
+L=0.35
+W=1
+nf=1
+mult=24
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 380 -290 0 0 {name=Mctrl2
+L=0.35
+W=1
+nf=1
+mult=12
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 600 -290 0 0 {name=Mctrl3
+L=0.35
+W=1
+nf=1
+mult=6
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
diff --git a/xschem/SSTL/p-leg.sym b/xschem/SSTL/p-leg.sym
new file mode 100644
index 0000000..3eab95f
--- /dev/null
+++ b/xschem/SSTL/p-leg.sym
@@ -0,0 +1,24 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @@DQ @@n_pu_ctrl @@n_cal_ctrl[3:0] @symname"
+template="name=X1"}
+V {}
+S {}
+E {}
+L 4 460 -60 500 -60 {}
+L 4 20 -60 60 -60 {}
+L 4 20 -180 60 -180 {}
+B 5 497.5 -62.5 502.5 -57.5 {name=DQ
+dir=inout}
+B 5 17.5 -62.5 22.5 -57.5 {name=n_pu_ctrl
+dir=in}
+B 5 17.5 -182.5 22.5 -177.5 {name=n_cal_ctrl[3:0]
+dir=in}
+P 4 5 60 -200 460 -200 460 -40 60 -40 60 -200 {}
+T {240 Ohm
+Pullup} 160 -170 0 0 0.8 0.8 {}
+T {DQ} 430 -70 0 0 0.3 0.3 {}
+T {n_pu_ctrl} 70 -70 0 0 0.3 0.3 {}
+T {n_cal_ctrl[3:0]} 70 -190 0 0 0.3 0.3 {}
+T {@name} 230 -230 0 0 0.3 0.3 {}
diff --git a/xschem/SSTL/p-leg_tb.sch b/xschem/SSTL/p-leg_tb.sch
new file mode 100644
index 0000000..1b30736
--- /dev/null
+++ b/xschem/SSTL/p-leg_tb.sch
@@ -0,0 +1,104 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 530 -490 530 -480 { lab=VDD}
+N 400 -490 400 -480 { lab=VDD}
+N 270 -490 270 -480 { lab=VDD}
+N 130 -490 130 -480 { lab=VDD}
+N 490 -320 490 -310 { lab=VDD}
+N 1050 -250 1050 -230 { lab=DQ}
+N 1050 -170 1050 -150 { lab=VDDQ}
+N 570 -120 570 -100 { lab=VDDQ}
+N 140 -370 570 -370 { lab=n_cal_ctrl[3:0]
+bus=true}
+N 530 -420 530 -380 { lab=n_cal_ctrl[3]}
+N 400 -420 400 -380 { lab=n_cal_ctrl[2]}
+N 270 -420 270 -380 { lab=n_cal_ctrl[1]}
+N 130 -420 130 -380 { lab=n_cal_ctrl[0]}
+N 490 -250 570 -250 { lab=n_pu_ctrl}
+N 570 -200 570 -180 { lab=v1v5}
+C {devices/title.sym} 160 -30 0 0 {name=l1 author="Derek H-M"}
+C {devices/code.sym} 670 -180 0 0 {name=STIMULI
+only_toplevel=true
+place=end
+value="
+
+* power voltage
+vvdd VDD 0 SED_vdd_SED
+vv1v5 v1v5 0 1.5
+
+.control
+save all
+set temp=SED_temp_SED
+
+* RUN SIMULATION
+dc Vpinvoltage 0.3 1.2 0.05
+* OUTPUT
+print (SED_vdd_SED-vddq)/i(vtest)
+wrdata out/SED_plotName_SED/SED_plotName_SED.txt (SED_vdd_SED-vddq)/i(vtest)
+set hcopydevtype = svg
+hardcopy ./out/SED_plotName_SED/SED_plotName_SED.svg (SED_vdd_SED-vddq)/I(vtest) vs vddq title 'Resistance vs pin voltage'
+
+.endc
+"}
+C {devices/code.sym} 810 -180 0 0 {name=MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="** Local library links to pdk
+.lib ./sky130/libs/SED_process_SED_lib.spice SED_process_SED
+"
+spice_ignore=false}
+C {devices/vsource.sym} 130 -450 0 0 {name=Vctrl0
+*value=0
+value=SED_vctrl0_SED}
+C {devices/vsource.sym} 270 -450 0 0 {name=Vctrl1
+*value=0
+value=SED_vctrl1_SED}
+C {devices/vsource.sym} 400 -450 0 0 {name=Vctrl2
+*value=0
+value=SED_vctrl2_SED}
+C {devices/vsource.sym} 530 -450 0 0 {name=Vctrl3
+*value=0
+value=SED_vctrl3_SED}
+C {devices/vsource.sym} 490 -280 0 0 {name=Vgate
+value=SED_vg_SED
+}
+C {devices/vdd.sym} 490 -320 0 0 {name=l2 lab=VDD}
+C {devices/ammeter.sym} 1050 -200 0 0 {name=Vtest}
+C {devices/lab_pin.sym} 1050 -150 0 0 {name=l4 sig_type=std_logic lab=VDDQ}
+C {devices/vdd.sym} 530 -490 0 0 {name=l7 lab=VDD}
+C {devices/vdd.sym} 400 -490 0 0 {name=l15 lab=VDD}
+C {devices/vdd.sym} 270 -490 0 0 {name=l17 lab=VDD}
+C {devices/vdd.sym} 130 -490 0 0 {name=l19 lab=VDD}
+C {devices/vsource.sym} 570 -150 0 0 {name=Vpinvoltage
+value=0
+}
+C {devices/lab_pin.sym} 570 -100 0 0 {name=l24 sig_type=std_logic lab=VDDQ}
+C {p-leg.sym} 550 -190 0 0 {name=X1}
+C {devices/bus_connect.sym} 540 -370 3 0 {name=l3 lab=n_cal_ctrl[3]}
+C {devices/bus_connect.sym} 410 -370 3 0 {name=l5 lab=n_cal_ctrl[2]}
+C {devices/bus_connect.sym} 280 -370 3 0 {name=l6 lab=n_cal_ctrl[1]}
+C {devices/bus_connect.sym} 140 -370 3 0 {name=l8 lab=n_cal_ctrl[0]}
+C {devices/lab_wire.sym} 350 -370 2 0 {name=l9 sig_type=std_logic lab=n_cal_ctrl[3:0]}
+C {devices/lab_pin.sym} 490 -250 0 0 {name=l10 sig_type=std_logic lab=n_pu_ctrl}
+C {devices/lab_pin.sym} 1050 -250 2 0 {name=l11 sig_type=std_logic lab=DQ}
+C {devices/lab_pin.sym} 570 -200 0 0 {name=l12 sig_type=std_logic lab=v1v5}
diff --git a/xschem/SSTL/post_layout_SSTL.sym b/xschem/SSTL/post_layout_SSTL.sym
new file mode 100644
index 0000000..0b2e2cc
--- /dev/null
+++ b/xschem/SSTL/post_layout_SSTL.sym
@@ -0,0 +1,39 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @@pd_cal_ctrl[0:3] @@pd_ctrl[0:6] @@pu_cal_ctrl[0:3] @@pu_ctrl[0:6] @@DQ @@VDD @@GND SSTL_flat"
+template="name=X1"}
+V {}
+S {}
+E {}
+L 4 460 -120 500 -120 {}
+L 4 20 -60 60 -60 {}
+L 4 20 -90 60 -90 {}
+L 4 20 -180 60 -180 {}
+L 4 20 -150 60 -150 {}
+L 4 100 -240 100 -200 {}
+L 4 100 -40 100 0 {}
+B 5 497.5 -122.5 502.5 -117.5 {name=DQ
+dir=inout}
+B 5 17.5 -62.5 22.5 -57.5 {name=pd_ctrl[0:6]
+dir=in}
+B 5 17.5 -92.5 22.5 -87.5 {name=pd_cal_ctrl[0:3]
+dir=in}
+B 5 17.5 -182.5 22.5 -177.5 {name=pu_ctrl[0:6]
+dir=in}
+B 5 17.5 -152.5 22.5 -147.5 {name=pu_cal_ctrl[0:3]
+dir=in}
+B 5 97.5 -242.5 102.5 -237.5 {name=VDD
+dir=in}
+B 5 97.5 -2.5 102.5 2.5 {name=GND
+dir=in}
+P 4 5 60 -200 460 -200 460 -40 60 -40 60 -200 {}
+T {POST LAYOUT DDR3 SSTL} 80 -140 0 0 0.5 0.5 {}
+T {DQ} 430 -130 0 0 0.3 0.3 {}
+T {pd_ctrl[0:6]} 70 -70 0 0 0.3 0.3 {}
+T {pd_cal_ctrl[0:3]} 70 -100 0 0 0.3 0.3 {}
+T {@name} 230 -230 0 0 0.3 0.3 {}
+T {pu_ctrl[0:6]} 70 -190 0 0 0.3 0.3 {}
+T {pu_cal_ctrl[0:3]} 70 -160 0 0 0.3 0.3 {}
+T {VDD} 110 -220 0 0 0.2 0.2 {}
+T {GND} 110 -30 0 0 0.2 0.2 {}
diff --git a/xschem/SSTL/post_layout_sstl_res_tb.sch b/xschem/SSTL/post_layout_sstl_res_tb.sch
new file mode 100644
index 0000000..8b15b13
--- /dev/null
+++ b/xschem/SSTL/post_layout_sstl_res_tb.sch
@@ -0,0 +1,101 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 860 -330 880 -330 { lab=DQ}
+N 350 -390 380 -390 { lab=pu_ctrl[0:6]}
+N 350 -360 380 -360 { lab=pu_cal[0:3]}
+N 350 -300 380 -300 { lab=pd_cal[0:3]}
+N 350 -270 380 -270 { lab=pd_ctrl[0:6]}
+C {devices/title.sym} 160 -30 0 0 {name=l1 author="Derek H-M"}
+C {devices/code.sym} 790 -200 0 0 {name=STIMULI
+only_toplevel=true
+place=end
+value="
+* power voltage
+vvddq VDDQ 0 0
+vvdd VDD 0 SED_vdd_SED
+
+** CALIBRATION CONTROL **
+* PULLUP
+vpu_cal0 pu_cal[0] 0 SED_pucal0_SED
+vpu_cal1 pu_cal[1] 0 SED_pucal1_SED
+vpu_cal2 pu_cal[2] 0 SED_pucal2_SED
+vpu_cal3 pu_cal[3] 0 SED_pucal3_SED
+* PULLDOWN
+vpd_cal0 pd_cal[0] 0 SED_pdcal0_SED
+vpd_cal1 pd_cal[1] 0 SED_pdcal1_SED
+vpd_cal2 pd_cal[2] 0 SED_pdcal2_SED
+vpd_cal3 pd_cal[3] 0 SED_pdcal3_SED
+
+** LEG ENABLE/DISABLE CONTROL
+* PULLUP
+vpu_ctrl0 pu_ctrl[0] 0 SED_puctrl0_SED
+vpu_ctrl1 pu_ctrl[1] 0 SED_puctrl1_SED
+vpu_ctrl2 pu_ctrl[2] 0 SED_puctrl2_SED
+vpu_ctrl3 pu_ctrl[3] 0 SED_puctrl3_SED
+vpu_ctrl4 pu_ctrl[4] 0 SED_puctrl4_SED
+vpu_ctrl5 pu_ctrl[5] 0 SED_puctrl5_SED
+vpu_ctrl6 pu_ctrl[6] 0 SED_puctrl6_SED
+* PULLDOWN
+vpd_ctrl0 pd_ctrl[0] 0 SED_pdctrl0_SED
+vpd_ctrl1 pd_ctrl[1] 0 SED_pdctrl1_SED
+vpd_ctrl2 pd_ctrl[2] 0 SED_pdctrl2_SED
+vpd_ctrl3 pd_ctrl[3] 0 SED_pdctrl3_SED
+vpd_ctrl4 pd_ctrl[4] 0 SED_pdctrl4_SED
+vpd_ctrl5 pd_ctrl[5] 0 SED_pdctrl5_SED
+vpd_ctrl6 pd_ctrl[6] 0 SED_pdctrl6_SED
+
+
+.control
+set num_threads=1
+save all
+set temp=SED_temp_SED
+
+* RUN SIMULATION
+dc vvddq 0.3 1.2 0.05
+* OUTPUT
+print i(vtest)
+wrdata out/SED_plotName_SED/SED_plotName_SED.txt i(vtest)
+set hcopydevtype = svg
+hardcopy ./out/SED_plotName_SED/SED_plotName_SED.svg I(vtest) vs vddq title 'Resistance vs pin voltage'
+
+.endc
+"}
+C {devices/code.sym} 930 -200 0 0 {name=MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="** Local library links to pdk
+.lib ./sky130/libs/SED_process_SED_lib.spice SED_process_SED
+.include \\\\$::SKYWATER_STDCELLS\\\\/sky130_fd_sc_hd.spice
+.include ./layout/pex_SSTL.spice
+"
+spice_ignore=false}
+C {devices/ammeter.sym} 910 -330 3 0 {name=vtest}
+C {devices/lab_wire.sym} 860 -330 2 0 {name=l9 sig_type=std_logic lab=DQ}
+C {devices/lab_wire.sym} 940 -330 2 0 {name=l11 sig_type=std_logic lab=VDDQ}
+C {devices/lab_pin.sym} 350 -390 0 0 {name=l3 sig_type=std_logic lab=pu_ctrl[0:6]}
+C {devices/lab_pin.sym} 350 -270 0 0 {name=l10 sig_type=std_logic lab=pd_ctrl[0:6]}
+C {devices/lab_pin.sym} 350 -360 0 0 {name=l13 sig_type=std_logic lab=pu_cal[0:3]}
+C {devices/lab_pin.sym} 350 -300 0 0 {name=l14 sig_type=std_logic lab=pd_cal[0:3]}
+C {schem/post_layout_SSTL.sym} 360 -210 0 0 {name=X1}
+C {devices/gnd.sym} 460 -210 0 0 {name=l2 lab=GND}
+C {devices/vdd.sym} 460 -450 0 0 {name=l4 lab=VDD}
diff --git a/xschem/SSTL/post_layout_sstl_slew_tb.sch b/xschem/SSTL/post_layout_sstl_slew_tb.sch
new file mode 100644
index 0000000..2f4d23f
--- /dev/null
+++ b/xschem/SSTL/post_layout_sstl_slew_tb.sch
@@ -0,0 +1,171 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 350 -360 380 -360 { lab=pu_cal[0:3]}
+N 350 -300 380 -300 { lab=pd_cal[0:3]}
+N 860 -330 990 -330 { lab=DQ}
+N 930 -270 930 -260 { lab=GND}
+N 1110 -270 1110 -250 { lab=GND}
+N 1110 -270 1150 -270 { lab=GND}
+N 1150 -280 1150 -270 { lab=GND}
+N 1050 -330 1110 -330 { lab=VDDQ}
+N 1150 -330 1150 -320 { lab=VDD}
+N -40 -390 -20 -390 { lab=pub1[0:6]}
+N 60 -390 80 -390 { lab=pub2[0:6]}
+N 160 -390 180 -390 { lab=pub3[0:6]}
+N -40 -270 -20 -270 { lab=pdb1[0:6]}
+N 60 -270 80 -270 { lab=pdb2[0:6]}
+N 160 -270 180 -270 { lab=pdb3[0:6]}
+N 260 -390 380 -390 { lab=pub4[0:6]}
+N 260 -270 360 -270 { lab=pdb4[0:6]}
+N 360 -270 380 -270 { lab=pdb4[0:6]}
+C {devices/title.sym} 160 -30 0 0 {name=l1 author="Derek H-M"}
+C {devices/code.sym} 790 -200 0 0 {name=STIMULI
+only_toplevel=true
+place=end
+value="
+* power voltage
+vvdd VDD 0 SED_vdd_SED
+
+** CALIBRATION CONTROL **
+* PULLUP
+vpu_cal0 pu_cal[0] 0 SED_pucal0_SED
+vpu_cal1 pu_cal[1] 0 SED_pucal1_SED
+vpu_cal2 pu_cal[2] 0 SED_pucal2_SED
+vpu_cal3 pu_cal[3] 0 SED_pucal3_SED
+* PULLDOWN
+vpd_cal0 pd_cal[0] 0 SED_pdcal0_SED
+vpd_cal1 pd_cal[1] 0 SED_pdcal1_SED
+vpd_cal2 pd_cal[2] 0 SED_pdcal2_SED
+vpd_cal3 pd_cal[3] 0 SED_pdcal3_SED
+
+** LEG ENABLE/DISABLE CONTROL
+* PULLUP
+* vlow, vhigh, delay, risetime, falltime, pulsewidth, period, phase
+vpu_ctrl0 pu_ctrl[0] 0 0 PULSE 0 SED_puctrl0_SED 1n 10p 10p 5n 10n 0
+vpu_ctrl1 pu_ctrl[1] 0 0 PULSE 0 SED_puctrl1_SED 1n 10p 10p 5n 10n 0
+vpu_ctrl2 pu_ctrl[2] 0 0 PULSE 0 SED_puctrl2_SED 1n 10p 10p 5n 10n 0
+vpu_ctrl3 pu_ctrl[3] 0 0 PULSE 0 SED_puctrl3_SED 1n 10p 10p 5n 10n 0
+vpu_ctrl4 pu_ctrl[4] 0 0 PULSE 0 SED_puctrl4_SED 1n 10p 10p 5n 10n 0
+vpu_ctrl5 pu_ctrl[5] 0 0 PULSE 0 SED_puctrl5_SED 1n 10p 10p 5n 10n 0
+vpu_ctrl6 pu_ctrl[6] 0 0 PULSE 0 SED_puctrl6_SED 1n 10p 10p 5n 10n 0
+* PULLDOWN (delay was set to 1.1n for better slew...)
+vpd_ctrl0 VDD pd_ctrl[0] 0 PULSE 0 SED_pdctrl0_SED 1n 10p 10p 5n 10n 0
+vpd_ctrl1 VDD pd_ctrl[1] 0 PULSE 0 SED_pdctrl1_SED 1n 10p 10p 5n 10n 0
+vpd_ctrl2 VDD pd_ctrl[2] 0 PULSE 0 SED_pdctrl2_SED 1n 10p 10p 5n 10n 0
+vpd_ctrl3 VDD pd_ctrl[3] 0 PULSE 0 SED_pdctrl3_SED 1n 10p 10p 5n 10n 0
+vpd_ctrl4 VDD pd_ctrl[4] 0 PULSE 0 SED_pdctrl4_SED 1n 10p 10p 5n 10n 0
+vpd_ctrl5 VDD pd_ctrl[5] 0 PULSE 0 SED_pdctrl5_SED 1n 10p 10p 5n 10n 0
+vpd_ctrl6 VDD pd_ctrl[6] 0 PULSE 0 SED_pdctrl6_SED 1n 10p 10p 5n 10n 0
+
+.control
+save all
+set temp=SED_temp_SED
+
+* RUN SIMULATION
+tran 1p 8n
+* Measure rise time
+meas tran tdiff_rise trig dq val=SED_volac_SED rise=1 targ dq val=SED_vohac_SED rise=1
+* Measure fall time
+meas tran tdiff_fall trig dq val=SED_vohac_SED fall=1 targ dq val=SED_volac_SED fall=1
+
+* OUTPUT
+wrdata ./out/SED_plotName_SED/SED_plotName_SED.txt tdiff_rise tdiff_fall
+set hcopydevtype = svg
+hardcopy ./out/SED_plotName_SED/SED_plotName_SED.svg dq pu_in_test_4 pd_in_test_4 title 'DQ vs time'
+
+hardcopy ./out/SED_plotName_SED/SED_plotName_SED_DBG.svg
++ pu_in_test_4
++ pd_in_test_4
++ \\"x1.p-leg_6/n_cal_ctrl[0]\\"
++ \\"x1.p-leg_6/n_cal_ctrl[1]\\"
++ \\"x1.p-leg_6/n_cal_ctrl[2]\\"
++ \\"x1.p-leg_6/n_cal_ctrl[3]\\"
+
+hardcopy ./out/SED_plotName_SED/SED_plotName_SED_DBG2.svg
++ pu_in_test_4
++ pd_in_test_4
++ \\"x1.p-leg_0/n_pu_ctrl\\"
++ \\"x1.n-leg_0/pd_ctrl\\"
+
+
+
+*plot dq pu_in_test_4 pd_in_test_4 x1.v_pu_ctrl_0 x1.v_pd_ctrl_0
+
+.endc
+"}
+C {devices/code.sym} 930 -200 0 0 {name=MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="** Local library links to pdk
+.lib ./sky130/libs/SED_process_SED_lib.spice SED_process_SED
+.include \\\\$::SKYWATER_STDCELLS\\\\/sky130_fd_sc_hd.spice
+.include ./layout/pex_SSTL.spice
+"
+spice_ignore=false}
+C {devices/lab_wire.sym} 860 -330 2 0 {name=l9 sig_type=std_logic lab=DQ}
+C {devices/lab_wire.sym} 1050 -330 0 1 {name=l11 sig_type=std_logic lab=VDDQ}
+C {devices/lab_pin.sym} -120 -390 0 0 {name=l3 sig_type=std_logic lab=pu_ctrl[0:6]}
+C {devices/lab_pin.sym} -120 -270 0 0 {name=l10 sig_type=std_logic lab=pd_ctrl[0:6]}
+C {devices/lab_pin.sym} 350 -360 0 0 {name=l13 sig_type=std_logic lab=pu_cal[0:3]}
+C {devices/lab_pin.sym} 350 -300 0 0 {name=l14 sig_type=std_logic lab=pd_cal[0:3]}
+C {devices/res.sym} 1020 -330 1 0 {name=Rtb
+value=25
+footprint=1206
+device=resistor
+m=1}
+C {devices/capa.sym} 930 -300 0 0 {name=Cpad
+m=1
+value=1.4p
+*value=491f
+footprint=1206
+device="ceramic capacitor"}
+C {devices/gnd.sym} 930 -260 0 0 {name=l2 lab=GND}
+C {devices/vcvs.sym} 1110 -300 0 1 {name=Ehalf_vdd
+value=0.5}
+C {devices/gnd.sym} 1110 -250 0 0 {name=l4 lab=GND}
+C {devices/vdd.sym} 1150 -330 0 0 {name=l5 lab=VDD}
+C {sky130/sky130_stdcells/clkinv_1.sym} -80 -390 0 0 {name=xpui1[0:6] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkinv_1.sym} -80 -270 0 0 {name=xpdi1[0:6] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {devices/lab_wire.sym} -20 -390 0 0 {name=l6 sig_type=std_logic lab=pub1[0:6]}
+C {devices/lab_wire.sym} 80 -390 0 0 {name=l7 sig_type=std_logic lab=pub2[0:6]}
+C {devices/lab_wire.sym} 180 -390 0 0 {name=l8 sig_type=std_logic lab=pub3[0:6]}
+C {devices/lab_wire.sym} 330 -390 0 0 {name=l12 sig_type=std_logic lab=pub4[0:6]}
+C {devices/lab_wire.sym} -20 -270 0 0 {name=l15 sig_type=std_logic lab=pdb1[0:6]}
+C {devices/lab_wire.sym} 80 -270 0 0 {name=l16 sig_type=std_logic lab=pdb2[0:6]}
+C {devices/lab_wire.sym} 180 -270 0 0 {name=l17 sig_type=std_logic lab=pdb3[0:6]}
+C {devices/lab_wire.sym} 330 -270 0 0 {name=l18 sig_type=std_logic lab=pdb4[0:6]}
+C {devices/vsource.sym} 300 -540 1 0 {name=Vtest9 value=0}
+C {devices/lab_pin.sym} 270 -540 0 0 {name=l43 sig_type=std_logic lab=pub4[0]}
+C {devices/lab_pin.sym} 330 -540 0 1 {name=l44 sig_type=std_logic lab=pu_in_test_4}
+C {devices/vsource.sym} 300 -480 1 0 {name=Vtest10 value=0}
+C {devices/lab_pin.sym} 270 -480 0 0 {name=l45 sig_type=std_logic lab=pdb4[0]}
+C {devices/lab_pin.sym} 330 -480 0 1 {name=l46 sig_type=std_logic lab=pd_in_test_4}
+C {sky130/sky130_stdcells/clkinv_1.sym} 20 -390 0 0 {name=xpui2[0:6] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkinv_1.sym} 120 -390 0 0 {name=xpui3[0:6] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkinv_1.sym} 220 -390 0 0 {name=xpui4[0:6] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkinv_1.sym} 20 -270 0 0 {name=xpui5[0:6] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkinv_1.sym} 120 -270 0 0 {name=xpui6[0:6] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkinv_1.sym} 220 -270 0 0 {name=xpui7[0:6] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {schem/post_layout_SSTL.sym} 360 -210 0 0 {name=X1}
+C {devices/gnd.sym} 460 -210 0 0 {name=l19 lab=GND}
+C {devices/vdd.sym} 460 -450 0 0 {name=l20 lab=VDD}
diff --git a/xschem/SSTL/sstl_res_tb.sch b/xschem/SSTL/sstl_res_tb.sch
new file mode 100644
index 0000000..8f166eb
--- /dev/null
+++ b/xschem/SSTL/sstl_res_tb.sch
@@ -0,0 +1,98 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 860 -330 880 -330 { lab=DQ}
+N 350 -390 380 -390 { lab=pu_ctrl[6:0]}
+N 350 -360 380 -360 { lab=pu_cal[3:0]}
+N 350 -300 380 -300 { lab=pd_cal[3:0]}
+N 350 -270 380 -270 { lab=pd_ctrl[6:0]}
+C {devices/title.sym} 160 -30 0 0 {name=l1 author="Derek H-M"}
+C {devices/code.sym} 790 -200 0 0 {name=STIMULI
+only_toplevel=true
+place=end
+value="
+* power voltage
+vvddq VDDQ 0 0
+vvdd VDD 0 SED_vdd_SED
+
+** CALIBRATION CONTROL **
+* PULLUP
+vpu_cal0 pu_cal[0] 0 SED_pucal0_SED
+vpu_cal1 pu_cal[1] 0 SED_pucal1_SED
+vpu_cal2 pu_cal[2] 0 SED_pucal2_SED
+vpu_cal3 pu_cal[3] 0 SED_pucal3_SED
+* PULLDOWN
+vpd_cal0 pd_cal[0] 0 SED_pdcal0_SED
+vpd_cal1 pd_cal[1] 0 SED_pdcal1_SED
+vpd_cal2 pd_cal[2] 0 SED_pdcal2_SED
+vpd_cal3 pd_cal[3] 0 SED_pdcal3_SED
+
+** LEG ENABLE/DISABLE CONTROL
+* PULLUP
+vpu_ctrl0 pu_ctrl[0] 0 SED_puctrl0_SED
+vpu_ctrl1 pu_ctrl[1] 0 SED_puctrl1_SED
+vpu_ctrl2 pu_ctrl[2] 0 SED_puctrl2_SED
+vpu_ctrl3 pu_ctrl[3] 0 SED_puctrl3_SED
+vpu_ctrl4 pu_ctrl[4] 0 SED_puctrl4_SED
+vpu_ctrl5 pu_ctrl[5] 0 SED_puctrl5_SED
+vpu_ctrl6 pu_ctrl[6] 0 SED_puctrl6_SED
+* PULLDOWN
+vpd_ctrl0 pd_ctrl[0] 0 SED_pdctrl0_SED
+vpd_ctrl1 pd_ctrl[1] 0 SED_pdctrl1_SED
+vpd_ctrl2 pd_ctrl[2] 0 SED_pdctrl2_SED
+vpd_ctrl3 pd_ctrl[3] 0 SED_pdctrl3_SED
+vpd_ctrl4 pd_ctrl[4] 0 SED_pdctrl4_SED
+vpd_ctrl5 pd_ctrl[5] 0 SED_pdctrl5_SED
+vpd_ctrl6 pd_ctrl[6] 0 SED_pdctrl6_SED
+
+
+.control
+set num_threads=1
+save all
+set temp=SED_temp_SED
+
+* RUN SIMULATION
+dc vvddq 0.3 1.2 0.05
+* OUTPUT
+print i(vtest)
+wrdata out/SED_plotName_SED/SED_plotName_SED.txt i(vtest)
+set hcopydevtype = svg
+hardcopy ./out/SED_plotName_SED/SED_plotName_SED.svg I(vtest) vs vddq title 'Resistance vs pin voltage'
+
+.endc
+"}
+C {devices/code.sym} 930 -200 0 0 {name=MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="** Local library links to pdk
+.lib ./sky130/libs/SED_process_SED_lib.spice SED_process_SED
+.include \\\\$::SKYWATER_STDCELLS\\\\/sky130_fd_sc_hd.spice
+"
+spice_ignore=false}
+C {devices/ammeter.sym} 910 -330 3 0 {name=vtest}
+C {devices/lab_wire.sym} 860 -330 2 0 {name=l9 sig_type=std_logic lab=DQ}
+C {devices/lab_wire.sym} 940 -330 2 0 {name=l11 sig_type=std_logic lab=VDDQ}
+C {devices/lab_pin.sym} 350 -390 0 0 {name=l3 sig_type=std_logic lab=pu_ctrl[6:0]}
+C {devices/lab_pin.sym} 350 -270 0 0 {name=l10 sig_type=std_logic lab=pd_ctrl[6:0]}
+C {devices/lab_pin.sym} 350 -360 0 0 {name=l13 sig_type=std_logic lab=pu_cal[3:0]}
+C {devices/lab_pin.sym} 350 -300 0 0 {name=l14 sig_type=std_logic lab=pd_cal[3:0]}
+C {schem/SSTL.sym} 360 -210 0 0 {name=X1 VDD=VDD GND=GND}
diff --git a/xschem/SSTL/sstl_slew_tb.sch b/xschem/SSTL/sstl_slew_tb.sch
new file mode 100644
index 0000000..3e24388
--- /dev/null
+++ b/xschem/SSTL/sstl_slew_tb.sch
@@ -0,0 +1,152 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 350 -360 380 -360 { lab=pu_cal[3:0]}
+N 350 -300 380 -300 { lab=pd_cal[3:0]}
+N 860 -330 990 -330 { lab=DQ}
+N 930 -270 930 -260 { lab=GND}
+N 1110 -270 1110 -250 { lab=GND}
+N 1110 -270 1150 -270 { lab=GND}
+N 1150 -280 1150 -270 { lab=GND}
+N 1050 -330 1110 -330 { lab=VDDQ}
+N 1150 -330 1150 -320 { lab=VDD}
+N -40 -390 -20 -390 { lab=pub1[6:0]}
+N 60 -390 80 -390 { lab=pub2[6:0]}
+N 160 -390 180 -390 { lab=pub3[6:0]}
+N -40 -270 -20 -270 { lab=pdb1[6:0]}
+N 60 -270 80 -270 { lab=pdb2[6:0]}
+N 160 -270 180 -270 { lab=pdb3[6:0]}
+N 260 -390 380 -390 { lab=pub4[6:0]}
+N 260 -270 360 -270 { lab=pdb4[6:0]}
+N 360 -270 380 -270 { lab=pdb4[6:0]}
+C {devices/title.sym} 160 -30 0 0 {name=l1 author="Derek H-M"}
+C {devices/code.sym} 790 -200 0 0 {name=STIMULI
+only_toplevel=true
+place=end
+value="
+* power voltage
+vvdd VDD 0 SED_vdd_SED
+
+** CALIBRATION CONTROL **
+* PULLUP
+vpu_cal0 pu_cal[0] 0 SED_pucal0_SED
+vpu_cal1 pu_cal[1] 0 SED_pucal1_SED
+vpu_cal2 pu_cal[2] 0 SED_pucal2_SED
+vpu_cal3 pu_cal[3] 0 SED_pucal3_SED
+* PULLDOWN
+vpd_cal0 pd_cal[0] 0 SED_pdcal0_SED
+vpd_cal1 pd_cal[1] 0 SED_pdcal1_SED
+vpd_cal2 pd_cal[2] 0 SED_pdcal2_SED
+vpd_cal3 pd_cal[3] 0 SED_pdcal3_SED
+
+** LEG ENABLE/DISABLE CONTROL
+* PULLUP
+* vlow, vhigh, delay, risetime, falltime, pulsewidth, period, phase
+vpu_ctrl0 pu_ctrl[0] 0 0 PULSE 0 SED_puctrl0_SED 1n 10p 10p 5n 10n 0
+vpu_ctrl1 pu_ctrl[1] 0 0 PULSE 0 SED_puctrl1_SED 1n 10p 10p 5n 10n 0
+vpu_ctrl2 pu_ctrl[2] 0 0 PULSE 0 SED_puctrl2_SED 1n 10p 10p 5n 10n 0
+vpu_ctrl3 pu_ctrl[3] 0 0 PULSE 0 SED_puctrl3_SED 1n 10p 10p 5n 10n 0
+vpu_ctrl4 pu_ctrl[4] 0 0 PULSE 0 SED_puctrl4_SED 1n 10p 10p 5n 10n 0
+vpu_ctrl5 pu_ctrl[5] 0 0 PULSE 0 SED_puctrl5_SED 1n 10p 10p 5n 10n 0
+vpu_ctrl6 pu_ctrl[6] 0 0 PULSE 0 SED_puctrl6_SED 1n 10p 10p 5n 10n 0
+* PULLDOWN (delay was set to 1.1n for better slew...)
+vpd_ctrl0 VDD pd_ctrl[0] 0 PULSE 0 SED_pdctrl0_SED 1n 10p 10p 5n 10n 0
+vpd_ctrl1 VDD pd_ctrl[1] 0 PULSE 0 SED_pdctrl1_SED 1n 10p 10p 5n 10n 0
+vpd_ctrl2 VDD pd_ctrl[2] 0 PULSE 0 SED_pdctrl2_SED 1n 10p 10p 5n 10n 0
+vpd_ctrl3 VDD pd_ctrl[3] 0 PULSE 0 SED_pdctrl3_SED 1n 10p 10p 5n 10n 0
+vpd_ctrl4 VDD pd_ctrl[4] 0 PULSE 0 SED_pdctrl4_SED 1n 10p 10p 5n 10n 0
+vpd_ctrl5 VDD pd_ctrl[5] 0 PULSE 0 SED_pdctrl5_SED 1n 10p 10p 5n 10n 0
+vpd_ctrl6 VDD pd_ctrl[6] 0 PULSE 0 SED_pdctrl6_SED 1n 10p 10p 5n 10n 0
+
+.control
+save all
+set temp=SED_temp_SED
+
+* RUN SIMULATION
+tran 1p 8n
+* Measure rise time
+meas tran tdiff_rise trig dq val=SED_volac_SED rise=1 targ dq val=SED_vohac_SED rise=1
+* Measure fall time
+meas tran tdiff_fall trig dq val=SED_vohac_SED fall=1 targ dq val=SED_volac_SED fall=1
+
+* OUTPUT
+wrdata ./out/SED_plotName_SED/SED_plotName_SED.txt tdiff_rise tdiff_fall
+set hcopydevtype = svg
+hardcopy ./out/SED_plotName_SED/SED_plotName_SED.svg dq pu_in_test_4 pd_in_test_4 title 'DQ vs time'
+
+*plot dq pu_in_test_4 pd_in_test_4 x1.v_pu_ctrl_0 x1.v_pd_ctrl_0
+
+.endc
+"}
+C {devices/code.sym} 930 -200 0 0 {name=MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="** Local library links to pdk
+.lib ./sky130/libs/SED_process_SED_lib.spice SED_process_SED
+.include \\\\$::SKYWATER_STDCELLS\\\\/sky130_fd_sc_hd.spice
+"
+spice_ignore=false}
+C {devices/lab_wire.sym} 860 -330 2 0 {name=l9 sig_type=std_logic lab=DQ}
+C {devices/lab_wire.sym} 1050 -330 0 1 {name=l11 sig_type=std_logic lab=VDDQ}
+C {devices/lab_pin.sym} -120 -390 0 0 {name=l3 sig_type=std_logic lab=pu_ctrl[6:0]}
+C {devices/lab_pin.sym} -120 -270 0 0 {name=l10 sig_type=std_logic lab=pd_ctrl[6:0]}
+C {devices/lab_pin.sym} 350 -360 0 0 {name=l13 sig_type=std_logic lab=pu_cal[3:0]}
+C {devices/lab_pin.sym} 350 -300 0 0 {name=l14 sig_type=std_logic lab=pd_cal[3:0]}
+C {devices/res.sym} 1020 -330 1 0 {name=Rtb
+value=25
+footprint=1206
+device=resistor
+m=1}
+C {devices/capa.sym} 930 -300 0 0 {name=Cpad
+m=1
+value=1.4p
+*value=491f
+footprint=1206
+device="ceramic capacitor"}
+C {devices/gnd.sym} 930 -260 0 0 {name=l2 lab=GND}
+C {devices/vcvs.sym} 1110 -300 0 1 {name=Ehalf_vdd
+value=0.5}
+C {devices/gnd.sym} 1110 -250 0 0 {name=l4 lab=GND}
+C {devices/vdd.sym} 1150 -330 0 0 {name=l5 lab=VDD}
+C {sky130/sky130_stdcells/clkinv_1.sym} -80 -390 0 0 {name=xpui1[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkinv_1.sym} -80 -270 0 0 {name=xpdi1[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {devices/lab_wire.sym} -20 -390 0 0 {name=l6 sig_type=std_logic lab=pub1[6:0]}
+C {devices/lab_wire.sym} 80 -390 0 0 {name=l7 sig_type=std_logic lab=pub2[6:0]}
+C {devices/lab_wire.sym} 180 -390 0 0 {name=l8 sig_type=std_logic lab=pub3[6:0]}
+C {devices/lab_wire.sym} 330 -390 0 0 {name=l12 sig_type=std_logic lab=pub4[6:0]}
+C {devices/lab_wire.sym} -20 -270 0 0 {name=l15 sig_type=std_logic lab=pdb1[6:0]}
+C {devices/lab_wire.sym} 80 -270 0 0 {name=l16 sig_type=std_logic lab=pdb2[6:0]}
+C {devices/lab_wire.sym} 180 -270 0 0 {name=l17 sig_type=std_logic lab=pdb3[6:0]}
+C {devices/lab_wire.sym} 330 -270 0 0 {name=l18 sig_type=std_logic lab=pdb4[6:0]}
+C {devices/vsource.sym} 330 -540 1 0 {name=Vtest9 value=0}
+C {devices/lab_pin.sym} 300 -540 0 0 {name=l43 sig_type=std_logic lab=pub4[0]}
+C {devices/lab_pin.sym} 360 -540 0 1 {name=l44 sig_type=std_logic lab=pu_in_test_4}
+C {devices/vsource.sym} 330 -480 1 0 {name=Vtest10 value=0}
+C {devices/lab_pin.sym} 300 -480 0 0 {name=l45 sig_type=std_logic lab=pdb4[0]}
+C {devices/lab_pin.sym} 360 -480 0 1 {name=l46 sig_type=std_logic lab=pd_in_test_4}
+C {sky130/sky130_stdcells/clkinv_1.sym} 20 -390 0 0 {name=xpui2[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkinv_1.sym} 120 -390 0 0 {name=xpui3[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkinv_1.sym} 220 -390 0 0 {name=xpui4[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkinv_1.sym} 20 -270 0 0 {name=xpui5[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkinv_1.sym} 120 -270 0 0 {name=xpui6[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkinv_1.sym} 220 -270 0 0 {name=xpui7[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {schem/SSTL.sym} 360 -210 0 0 {name=X1 VDD=VDD GND=GND}
diff --git a/xschem/SSTL/test_pd_res.sch b/xschem/SSTL/test_pd_res.sch
new file mode 100644
index 0000000..7116d7e
--- /dev/null
+++ b/xschem/SSTL/test_pd_res.sch
@@ -0,0 +1,86 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 660 -390 660 -350 { lab=#net1}
+N 660 -480 660 -450 { lab=VDDQ}
+N 660 -290 660 -250 { lab=vpulldown}
+N 660 -190 660 -150 { lab=GND}
+N 570 -220 620 -220 { lab=#net2}
+N 570 -160 660 -160 { lab=GND}
+N 660 -220 660 -190 { lab=GND}
+C {devices/title.sym} 160 -30 0 0 {name=l1 author="Derek H-M"}
+C {devices/code.sym} 840 -200 0 0 {name=STIMULI
+only_toplevel=true
+place=end
+value="
+
+* power voltage
+vvddq VDDQ 0 0
+
+.control
+save all
+set temp=SED_temp_SED
+
+* RUN SIMULATION
+dc vvddq 0.3 1.2 0.05
+* OUTPUT
+print v(vddq)/i(vtest)
+wrdata out/SED_outName_SED/SED_plotName_SED.txt v(vddq)/i(vtest)
+set hcopydevtype = svg
+hardcopy ./out/SED_outName_SED/SED_plotName_SED.svg vddq/I(vtest) vs vddq title 'Resistance vs pin voltage'
+
+.endc
+"}
+C {devices/code.sym} 980 -200 0 0 {name=MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="** Local library links to pdk
+.lib ./sky130/libs/SED_process_SED_lib.spice SED_process_SED
+"
+spice_ignore=false}
+C {sky130_fd_pr/res_generic_po.sym} 660 -320 0 0 {name=R1
+W=0.33
+*L=1.73
+L=1.7
+model=res_generic_po
+mult=1}
+C {devices/lab_pin.sym} 660 -480 0 0 {name=l3 sig_type=std_logic lab=VDDQ
+}
+C {devices/ammeter.sym} 660 -420 0 0 {name=vtest}
+C {devices/gnd.sym} 660 -150 0 0 {name=l4 lab=GND}
+C {sky130/sky130_fd_pr/nfet_01v8.sym} 640 -220 0 0 {name=n1
+L=0.15
+W=0.65
+nf=1
+*mult=64
+mult=48
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 660 -270 0 0 {name=l2 sig_type=std_logic lab=vpulldown}
+C {devices/vsource.sym} 570 -190 0 0 {name=Vgate value=SED_vg_SED}
diff --git a/xschem/SSTL/test_pu_res.sch b/xschem/SSTL/test_pu_res.sch
new file mode 100644
index 0000000..008cc44
--- /dev/null
+++ b/xschem/SSTL/test_pu_res.sch
@@ -0,0 +1,90 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 540 -480 600 -480 { lab=#net1}
+N 640 -450 640 -430 { lab=#net2}
+N 640 -370 640 -350 { lab=#net3}
+N 640 -290 640 -270 { lab=VDDQ}
+N 750 -120 750 -100 { lab=VDDQ}
+N 640 -550 640 -510 { lab=VDD}
+N 640 -510 640 -480 { lab=VDD}
+N 540 -540 640 -540 { lab=VDD}
+N 750 -190 750 -180 { lab=v1v5}
+C {devices/title.sym} 160 -30 0 0 {name=l1 author="Derek H-M"}
+C {devices/code.sym} 840 -200 0 0 {name=STIMULI
+only_toplevel=true
+place=end
+value="
+
+* power voltage
+vvdd VDD 0 SED_vdd_SED
+vv1v5 v1v5 0 1.5
+
+*.param rwidth=4.6
+
+.control
+save all
+set temp=SED_temp_SED
+
+* RUN SIMULATION
+dc Vpinvoltage 0.3 1.2 0.05
+* OUTPUT
+print (SED_vdd_SED-vddq)/i(vtest)
+wrdata out/SED_outName_SED/SED_plotName_SED.txt (SED_vdd_SED-vddq)/i(vtest)
+set hcopydevtype = svg
+hardcopy ./out/SED_outName_SED/SED_plotName_SED.svg (SED_vdd_SED-vddq)/I(vtest) vs vddq title 'Resistance vs pin voltage'
+
+.endc
+"}
+C {devices/code.sym} 980 -200 0 0 {name=MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="** Local library links to pdk
+.lib ./sky130/libs/SED_process_SED_lib.spice SED_process_SED
+"
+spice_ignore=false}
+C {devices/vsource.sym} 540 -510 0 0 {name=Vgate value=SED_vg_SED}
+C {devices/vdd.sym} 640 -540 0 0 {name=l6 lab=VDD}
+C {sky130_fd_pr/res_generic_po.sym} 640 -400 0 0 {name=R1
+W=0.33
+L=1.8
+model=res_generic_po
+mult=1}
+C {devices/ammeter.sym} 640 -320 0 0 {name=vtest}
+C {devices/lab_pin.sym} 640 -270 0 0 {name=l7 sig_type=std_logic lab=VDDQ}
+C {devices/vsource.sym} 750 -150 0 0 {name=Vpinvoltage value=0}
+C {devices/lab_pin.sym} 750 -100 0 0 {name=l3 sig_type=std_logic lab=VDDQ}
+C {sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 620 -480 0 0 {name=M3
+L=0.35
+W=1
+nf=1
+mult=96
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 750 -190 0 0 {name=l2 sig_type=std_logic lab=v1v5}
diff --git a/xschem/analog_wrapper_tb.sch b/xschem/example_por/analog_wrapper_tb.sch
similarity index 100%
rename from xschem/analog_wrapper_tb.sch
rename to xschem/example_por/analog_wrapper_tb.sch
diff --git a/xschem/analog_wrapper_tb.spice b/xschem/example_por/analog_wrapper_tb.spice
similarity index 100%
rename from xschem/analog_wrapper_tb.spice
rename to xschem/example_por/analog_wrapper_tb.spice
diff --git a/xschem/current_test.spice b/xschem/example_por/current_test.spice
similarity index 100%
rename from xschem/current_test.spice
rename to xschem/example_por/current_test.spice
diff --git a/xschem/example_por.sch b/xschem/example_por/example_por.sch
similarity index 100%
rename from xschem/example_por.sch
rename to xschem/example_por/example_por.sch
diff --git a/xschem/example_por.sym b/xschem/example_por/example_por.sym
similarity index 100%
rename from xschem/example_por.sym
rename to xschem/example_por/example_por.sym
diff --git a/xschem/example_por_tb.sch b/xschem/example_por/example_por_tb.sch
similarity index 100%
rename from xschem/example_por_tb.sch
rename to xschem/example_por/example_por_tb.sch
diff --git a/xschem/example_por_tb.spice b/xschem/example_por/example_por_tb.spice
similarity index 100%
rename from xschem/example_por_tb.spice
rename to xschem/example_por/example_por_tb.spice
diff --git a/xschem/example_por_tb.spice.orig b/xschem/example_por/example_por_tb.spice.orig
similarity index 100%
rename from xschem/example_por_tb.spice.orig
rename to xschem/example_por/example_por_tb.spice.orig
diff --git a/xschem/test.data b/xschem/example_por/test.data
similarity index 100%
rename from xschem/test.data
rename to xschem/example_por/test.data
diff --git a/xschem/threshold_test_tb.spice b/xschem/example_por/threshold_test_tb.spice
similarity index 100%
rename from xschem/threshold_test_tb.spice
rename to xschem/example_por/threshold_test_tb.spice
diff --git a/xschem/proj_sstl_test.sch b/xschem/proj_sstl_test.sch
new file mode 100644
index 0000000..d752cb3
--- /dev/null
+++ b/xschem/proj_sstl_test.sch
@@ -0,0 +1,113 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1950 -590 1950 -430 { lab=n_tx_DQ}
+N 1950 -240 1990 -240 { lab=tx_DQ}
+N 1990 -590 1990 -240 { lab=tx_DQ}
+N 170 -340 280 -340 { lab=rx_pu_cal[3:0]}
+N 170 -280 280 -280 { lab=rx_pd_cal[3:0]}
+N 170 -370 280 -370 { lab=rx_leg_ctrl[6:0]}
+N 260 -370 260 -250 { lab=rx_leg_ctrl[6:0]}
+N 260 -250 280 -250 { lab=rx_leg_ctrl[6:0]}
+N 760 -330 790 -330 { lab=rx_DQ}
+N 870 -330 880 -330 { lab=#net1}
+N 960 -350 960 -330 { lab=#net2}
+N 960 -350 1000 -350 { lab=#net2}
+N 1000 -200 1000 -190 { lab=d_sel_1}
+N 970 -230 970 -190 { lab=d_sel_0}
+N 970 -230 1000 -230 { lab=d_sel_0}
+N 860 -300 860 -190 { lab=data_0}
+N 860 -300 970 -300 { lab=data_0}
+N 970 -390 970 -300 { lab=data_0}
+N 970 -390 1000 -390 { lab=data_0}
+N 890 -290 890 -190 { lab=data_2}
+N 890 -290 980 -290 { lab=data_2}
+N 980 -310 980 -290 { lab=data_2}
+N 980 -310 1000 -310 { lab=data_2}
+N 920 -270 920 -190 { lab=data_3}
+N 920 -270 1000 -270 { lab=data_3}
+N 1080 -330 1100 -330 { lab=d_out}
+N 1090 -330 1090 -280 { lab=d_out}
+N 1330 -180 1470 -180 { lab=#net3}
+N 1330 -300 1470 -300 { lab=#net4}
+N 1330 -370 1330 -300 { lab=#net4}
+N 1330 -370 1470 -370 { lab=#net4}
+N 1340 -490 1340 -180 { lab=#net3}
+N 1340 -490 1470 -490 { lab=#net3}
+N 1460 -460 1470 -460 { lab=tx_pu_cal[3:0]}
+N 1460 -460 1460 -270 { lab=tx_pu_cal[3:0]}
+N 1460 -270 1470 -270 { lab=tx_pu_cal[3:0]}
+N 1460 -270 1460 -150 { lab=tx_pu_cal[3:0]}
+N 1440 -400 1470 -400 { lab=tx_pd_cal[3:0]}
+N 1440 -400 1440 -150 { lab=tx_pd_cal[3:0]}
+N 1440 -210 1470 -210 { lab=tx_pd_cal[3:0]}
+N 1200 -320 1210 -320 { lab=#net5}
+N 760 -590 760 -310 { lab=rx_DQ}
+N 1200 -160 1200 -150 { lab=tx_leg_ctrl[6:0]}
+N 1200 -160 1210 -160 { lab=tx_leg_ctrl[6:0]}
+N 1200 -280 1200 -160 { lab=tx_leg_ctrl[6:0]}
+N 1200 -280 1210 -280 { lab=tx_leg_ctrl[6:0]}
+N 1180 -330 1180 -320 { lab=#net5}
+N 1180 -320 1200 -320 { lab=#net5}
+N 1090 -280 1090 -200 { lab=d_out}
+N 1090 -200 1210 -200 { lab=d_out}
+C {/home/derekhm/proj/caravan-project/xschem/SSTL/SSTL.sym} 260 -190 0 0 {name=X1 VDD=IOVDD GND=GND}
+C {/home/derekhm/proj/caravan-project/xschem/SSTL/SSTL.sym} 1450 -120 0 0 {name=X2 VDD=IOVDD GND=GND}
+C {/home/derekhm/proj/caravan-project/xschem/SSTL/SSTL.sym} 1450 -310 0 0 {name=X3 VDD=IOVDD GND=GND}
+C {devices/iopin.sym} 760 -590 3 0 {name=p1 lab=rx_DQ
+}
+C {devices/ipin.sym} 170 -340 0 0 {name=p2 lab=rx_pu_cal[3:0]}
+C {devices/ipin.sym} 170 -280 0 0 {name=p3 lab=rx_pd_cal[3:0]}
+C {devices/ipin.sym} 170 -370 0 0 {name=p4 lab=rx_leg_ctrl[6:0]}
+C {devices/ipin.sym} 860 -190 3 0 {name=p5 lab=data_0}
+C {devices/ipin.sym} 890 -190 3 0 {name=p6 lab=data_2
+}
+C {devices/ipin.sym} 920 -190 3 0 {name=p7 lab=data_3
+}
+C {devices/ipin.sym} 970 -190 3 0 {name=p8 lab=d_sel_0
+
+}
+C {devices/ipin.sym} 1000 -190 3 0 {name=p9 lab=d_sel_1
+
+}
+C {devices/iopin.sym} 1990 -590 3 0 {name=p10 lab=tx_DQ
+}
+C {devices/iopin.sym} 1950 -590 3 0 {name=p11 lab=n_tx_DQ
+}
+C {sky130/sky130_stdcells/clkbuf_2.sym} 830 -330 0 0 {name=x1 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkbuf_2.sym} 920 -330 0 0 {name=x2 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/mux4_1.sym} 1040 -330 0 0 {name=x3 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/clkinv_2.sym} 1140 -330 0 0 {name=x4 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/and2_1.sym} 1270 -180 0 0 {name=xn_and[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130/sky130_stdcells/and2_1.sym} 1270 -300 0 0 {name=xand[6:0] VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {devices/ipin.sym} 1460 -150 3 0 {name=p12 lab=tx_pu_cal[3:0]}
+C {devices/ipin.sym} 1440 -150 3 0 {name=p13 lab=tx_pd_cal[3:0]}
+C {devices/ipin.sym} 1200 -150 3 0 {name=p14 lab=tx_leg_ctrl[6:0]}
+C {devices/code_shown.sym} 250 -520 0 0 {name=MODELS
+only_toplevel=true
+place=header
+format="tcleval( @value )"
+value="** Local library links to pdk
+.include \\\\$::SKYWATER_STDCELLS\\\\/sky130_fd_sc_hd.spice
+"
+spice_ignore=false}
+C {devices/lab_wire.sym} 1090 -300 3 0 {name=l1 sig_type=std_logic lab=d_out}
diff --git a/xschem/proj_sstl_test.spice b/xschem/proj_sstl_test.spice
new file mode 100644
index 0000000..ba11cf3
--- /dev/null
+++ b/xschem/proj_sstl_test.spice
@@ -0,0 +1,189 @@
+ ** Local library links to pdk
+.include /home/derekhm/cad/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+**.subckt proj_sstl_test rx_DQ rx_pu_cal[3],rx_pu_cal[2],rx_pu_cal[1],rx_pu_cal[0]
+*+ rx_pd_cal[3],rx_pd_cal[2],rx_pd_cal[1],rx_pd_cal[0]
+*+ rx_leg_ctrl[6],rx_leg_ctrl[5],rx_leg_ctrl[4],rx_leg_ctrl[3],rx_leg_ctrl[2],rx_leg_ctrl[1],rx_leg_ctrl[0] data_0 data_2 data_3 d_sel_0 d_sel_1 tx_DQ n_tx_DQ
+*+ tx_pu_cal[3],tx_pu_cal[2],tx_pu_cal[1],tx_pu_cal[0] tx_pd_cal[3],tx_pd_cal[2],tx_pd_cal[1],tx_pd_cal[0]
+*+ tx_leg_ctrl[6],tx_leg_ctrl[5],tx_leg_ctrl[4],tx_leg_ctrl[3],tx_leg_ctrl[2],tx_leg_ctrl[1],tx_leg_ctrl[0]
+*.iopin rx_DQ
+*.ipin rx_pu_cal[3],rx_pu_cal[2],rx_pu_cal[1],rx_pu_cal[0]
+*.ipin rx_pd_cal[3],rx_pd_cal[2],rx_pd_cal[1],rx_pd_cal[0]
+*.ipin
+*+ rx_leg_ctrl[6],rx_leg_ctrl[5],rx_leg_ctrl[4],rx_leg_ctrl[3],rx_leg_ctrl[2],rx_leg_ctrl[1],rx_leg_ctrl[0]
+*.ipin data_0
+*.ipin data_2
+*.ipin data_3
+*.ipin d_sel_0
+*.ipin d_sel_1
+*.iopin tx_DQ
+*.iopin n_tx_DQ
+*.ipin tx_pu_cal[3],tx_pu_cal[2],tx_pu_cal[1],tx_pu_cal[0]
+*.ipin tx_pd_cal[3],tx_pd_cal[2],tx_pd_cal[1],tx_pd_cal[0]
+*.ipin
+*+ tx_leg_ctrl[6],tx_leg_ctrl[5],tx_leg_ctrl[4],tx_leg_ctrl[3],tx_leg_ctrl[2],tx_leg_ctrl[1],tx_leg_ctrl[0]
+X1 rx_DQ rx_leg_ctrl[6] rx_leg_ctrl[5] rx_leg_ctrl[4] rx_leg_ctrl[3] rx_leg_ctrl[2] rx_leg_ctrl[1]
++ rx_leg_ctrl[0] rx_leg_ctrl[6] rx_leg_ctrl[5] rx_leg_ctrl[4] rx_leg_ctrl[3] rx_leg_ctrl[2] rx_leg_ctrl[1]
++ rx_leg_ctrl[0] rx_pd_cal[3] rx_pd_cal[2] rx_pd_cal[1] rx_pd_cal[0] rx_pu_cal[3] rx_pu_cal[2] rx_pu_cal[1]
++ rx_pu_cal[0] IOVDD GND SSTL
+X2 tx_DQ net4[6] net4[5] net4[4] net4[3] net4[2] net4[1] net4[0] net5[6] net5[5] net5[4] net5[3]
++ net5[2] net5[1] net5[0] tx_pd_cal[3] tx_pd_cal[2] tx_pd_cal[1] tx_pd_cal[0] tx_pu_cal[3] tx_pu_cal[2]
++ tx_pu_cal[1] tx_pu_cal[0] IOVDD GND SSTL
+X3 n_tx_DQ net5[6] net5[5] net5[4] net5[3] net5[2] net5[1] net5[0] net4[6] net4[5] net4[4] net4[3]
++ net4[2] net4[1] net4[0] tx_pd_cal[3] tx_pd_cal[2] tx_pd_cal[1] tx_pd_cal[0] tx_pu_cal[3] tx_pu_cal[2]
++ tx_pu_cal[1] tx_pu_cal[0] IOVDD GND SSTL
+x1 rx_DQ GND GND VDD VDD net1 sky130_fd_sc_hd__clkbuf_2
+x2 net1 GND GND VDD VDD net2 sky130_fd_sc_hd__clkbuf_2
+x3 data_0 net2 data_2 data_3 d_sel_0 d_sel_1 GND GND VDD VDD net3 sky130_fd_sc_hd__mux4_1
+x4 net3 GND GND VDD VDD net6 sky130_fd_sc_hd__clkinv_2
+xn_and[6] net3 tx_leg_ctrl[6] GND GND VDD VDD net4[6] sky130_fd_sc_hd__and2_1
+xn_and[5] net3 tx_leg_ctrl[5] GND GND VDD VDD net4[5] sky130_fd_sc_hd__and2_1
+xn_and[4] net3 tx_leg_ctrl[4] GND GND VDD VDD net4[4] sky130_fd_sc_hd__and2_1
+xn_and[3] net3 tx_leg_ctrl[3] GND GND VDD VDD net4[3] sky130_fd_sc_hd__and2_1
+xn_and[2] net3 tx_leg_ctrl[2] GND GND VDD VDD net4[2] sky130_fd_sc_hd__and2_1
+xn_and[1] net3 tx_leg_ctrl[1] GND GND VDD VDD net4[1] sky130_fd_sc_hd__and2_1
+xn_and[0] net3 tx_leg_ctrl[0] GND GND VDD VDD net4[0] sky130_fd_sc_hd__and2_1
+xand[6] net6 tx_leg_ctrl[6] GND GND VDD VDD net5[6] sky130_fd_sc_hd__and2_1
+xand[5] net6 tx_leg_ctrl[5] GND GND VDD VDD net5[5] sky130_fd_sc_hd__and2_1
+xand[4] net6 tx_leg_ctrl[4] GND GND VDD VDD net5[4] sky130_fd_sc_hd__and2_1
+xand[3] net6 tx_leg_ctrl[3] GND GND VDD VDD net5[3] sky130_fd_sc_hd__and2_1
+xand[2] net6 tx_leg_ctrl[2] GND GND VDD VDD net5[2] sky130_fd_sc_hd__and2_1
+xand[1] net6 tx_leg_ctrl[1] GND GND VDD VDD net5[1] sky130_fd_sc_hd__and2_1
+xand[0] net6 tx_leg_ctrl[0] GND GND VDD VDD net5[0] sky130_fd_sc_hd__and2_1
+**.ends
+
+* expanding symbol: /home/derekhm/proj/caravan-project/xschem/SSTL/SSTL.sym # of pins=5
+* sym_path: /home/derekhm/proj/caravan-project/xschem/SSTL/SSTL.sym
+* sch_path: /home/derekhm/proj/caravan-project/xschem/SSTL/SSTL.sch
+.subckt SSTL DQ pd_ctrl[6] pd_ctrl[5] pd_ctrl[4] pd_ctrl[3] pd_ctrl[2] pd_ctrl[1] pd_ctrl[0]
++ pu_ctrl[6] pu_ctrl[5] pu_ctrl[4] pu_ctrl[3] pu_ctrl[2] pu_ctrl[1] pu_ctrl[0] pd_cal_ctrl[3] pd_cal_ctrl[2]
++ pd_cal_ctrl[1] pd_cal_ctrl[0] pu_cal_ctrl[3] pu_cal_ctrl[2] pu_cal_ctrl[1] pu_cal_ctrl[0] VDD GND
+*.iopin DQ
+*.ipin pu_cal_ctrl[3],pu_cal_ctrl[2],pu_cal_ctrl[1],pu_cal_ctrl[0]
+*.ipin pd_cal_ctrl[3],pd_cal_ctrl[2],pd_cal_ctrl[1],pd_cal_ctrl[0]
+*.ipin pu_ctrl[6],pu_ctrl[5],pu_ctrl[4],pu_ctrl[3],pu_ctrl[2],pu_ctrl[1],pu_ctrl[0]
+*.ipin pd_ctrl[6],pd_ctrl[5],pd_ctrl[4],pd_ctrl[3],pd_ctrl[2],pd_ctrl[1],pd_ctrl[0]
+X1 DQ n_pu_ctrl[6] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X2 DQ pd_ctrl_buff[6] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+X3 DQ n_pu_ctrl[5] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X4 DQ pd_ctrl_buff[5] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+X5 DQ n_pu_ctrl[4] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X6 DQ pd_ctrl_buff[4] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+X7 DQ n_pu_ctrl[3] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X8 DQ pd_ctrl_buff[3] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+X9 DQ n_pu_ctrl[2] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X10 DQ pd_ctrl_buff[2] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+X11 DQ n_pu_ctrl[1] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X12 DQ pd_ctrl_buff[1] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+X13 DQ n_pu_ctrl[0] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X14 DQ pd_ctrl_buff[0] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+xpd_buff_4[6] pdc2[6] GND GND VDD VDD pdc4[6] sky130_fd_sc_hd__clkinv_4
+xpd_buff_4[5] pdc2[5] GND GND VDD VDD pdc4[5] sky130_fd_sc_hd__clkinv_4
+xpd_buff_4[4] pdc2[4] GND GND VDD VDD pdc4[4] sky130_fd_sc_hd__clkinv_4
+xpd_buff_4[3] pdc2[3] GND GND VDD VDD pdc4[3] sky130_fd_sc_hd__clkinv_4
+xpd_buff_4[2] pdc2[2] GND GND VDD VDD pdc4[2] sky130_fd_sc_hd__clkinv_4
+xpd_buff_4[1] pdc2[1] GND GND VDD VDD pdc4[1] sky130_fd_sc_hd__clkinv_4
+xpd_buff_4[0] pdc2[0] GND GND VDD VDD pdc4[0] sky130_fd_sc_hd__clkinv_4
+xpd_buff_6[6] pdc4[6] GND GND VDD VDD pd_ctrl_buff[6] sky130_fd_sc_hd__clkbuf_8
+xpd_buff_6[5] pdc4[5] GND GND VDD VDD pd_ctrl_buff[5] sky130_fd_sc_hd__clkbuf_8
+xpd_buff_6[4] pdc4[4] GND GND VDD VDD pd_ctrl_buff[4] sky130_fd_sc_hd__clkbuf_8
+xpd_buff_6[3] pdc4[3] GND GND VDD VDD pd_ctrl_buff[3] sky130_fd_sc_hd__clkbuf_8
+xpd_buff_6[2] pdc4[2] GND GND VDD VDD pd_ctrl_buff[2] sky130_fd_sc_hd__clkbuf_8
+xpd_buff_6[1] pdc4[1] GND GND VDD VDD pd_ctrl_buff[1] sky130_fd_sc_hd__clkbuf_8
+xpd_buff_6[0] pdc4[0] GND GND VDD VDD pd_ctrl_buff[0] sky130_fd_sc_hd__clkbuf_8
+xpu_buff_4[6] pu_ctrl[6] GND GND VDD VDD puc4[6] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_4[5] pu_ctrl[5] GND GND VDD VDD puc4[5] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_4[4] pu_ctrl[4] GND GND VDD VDD puc4[4] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_4[3] pu_ctrl[3] GND GND VDD VDD puc4[3] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_4[2] pu_ctrl[2] GND GND VDD VDD puc4[2] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_4[1] pu_ctrl[1] GND GND VDD VDD puc4[1] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_4[0] pu_ctrl[0] GND GND VDD VDD puc4[0] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_6[6] puc4[6] GND GND VDD VDD n_pu_ctrl[6] sky130_fd_sc_hd__clkinv_16
+xpu_buff_6[5] puc4[5] GND GND VDD VDD n_pu_ctrl[5] sky130_fd_sc_hd__clkinv_16
+xpu_buff_6[4] puc4[4] GND GND VDD VDD n_pu_ctrl[4] sky130_fd_sc_hd__clkinv_16
+xpu_buff_6[3] puc4[3] GND GND VDD VDD n_pu_ctrl[3] sky130_fd_sc_hd__clkinv_16
+xpu_buff_6[2] puc4[2] GND GND VDD VDD n_pu_ctrl[2] sky130_fd_sc_hd__clkinv_16
+xpu_buff_6[1] puc4[1] GND GND VDD VDD n_pu_ctrl[1] sky130_fd_sc_hd__clkinv_16
+xpu_buff_6[0] puc4[0] GND GND VDD VDD n_pu_ctrl[0] sky130_fd_sc_hd__clkinv_16
+xpu_cal_inv[3] pu_cal_ctrl[3] GND GND VDD VDD n_pu_cal_ctrl[3] sky130_fd_sc_hd__inv_1
+xpu_cal_inv[2] pu_cal_ctrl[2] GND GND VDD VDD n_pu_cal_ctrl[2] sky130_fd_sc_hd__inv_1
+xpu_cal_inv[1] pu_cal_ctrl[1] GND GND VDD VDD n_pu_cal_ctrl[1] sky130_fd_sc_hd__inv_1
+xpu_cal_inv[0] pu_cal_ctrl[0] GND GND VDD VDD n_pu_cal_ctrl[0] sky130_fd_sc_hd__inv_1
+xpu_buff_2[6] puc4[6] GND GND VDD VDD n_pu_ctrl[6] sky130_fd_sc_hd__clkinv_16
+xpu_buff_2[5] puc4[5] GND GND VDD VDD n_pu_ctrl[5] sky130_fd_sc_hd__clkinv_16
+xpu_buff_2[4] puc4[4] GND GND VDD VDD n_pu_ctrl[4] sky130_fd_sc_hd__clkinv_16
+xpu_buff_2[3] puc4[3] GND GND VDD VDD n_pu_ctrl[3] sky130_fd_sc_hd__clkinv_16
+xpu_buff_2[2] puc4[2] GND GND VDD VDD n_pu_ctrl[2] sky130_fd_sc_hd__clkinv_16
+xpu_buff_2[1] puc4[1] GND GND VDD VDD n_pu_ctrl[1] sky130_fd_sc_hd__clkinv_16
+xpu_buff_2[0] puc4[0] GND GND VDD VDD n_pu_ctrl[0] sky130_fd_sc_hd__clkinv_16
+xpd_buff_1[6] pd_ctrl[6] GND GND VDD VDD pdc2[6] sky130_fd_sc_hd__clkinv_4
+xpd_buff_1[5] pd_ctrl[5] GND GND VDD VDD pdc2[5] sky130_fd_sc_hd__clkinv_4
+xpd_buff_1[4] pd_ctrl[4] GND GND VDD VDD pdc2[4] sky130_fd_sc_hd__clkinv_4
+xpd_buff_1[3] pd_ctrl[3] GND GND VDD VDD pdc2[3] sky130_fd_sc_hd__clkinv_4
+xpd_buff_1[2] pd_ctrl[2] GND GND VDD VDD pdc2[2] sky130_fd_sc_hd__clkinv_4
+xpd_buff_1[1] pd_ctrl[1] GND GND VDD VDD pdc2[1] sky130_fd_sc_hd__clkinv_4
+xpd_buff_1[0] pd_ctrl[0] GND GND VDD VDD pdc2[0] sky130_fd_sc_hd__clkinv_4
+xpu_buff_1[6] puc4[6] GND GND VDD VDD n_pu_ctrl[6] sky130_fd_sc_hd__clkinv_16
+xpu_buff_1[5] puc4[5] GND GND VDD VDD n_pu_ctrl[5] sky130_fd_sc_hd__clkinv_16
+xpu_buff_1[4] puc4[4] GND GND VDD VDD n_pu_ctrl[4] sky130_fd_sc_hd__clkinv_16
+xpu_buff_1[3] puc4[3] GND GND VDD VDD n_pu_ctrl[3] sky130_fd_sc_hd__clkinv_16
+xpu_buff_1[2] puc4[2] GND GND VDD VDD n_pu_ctrl[2] sky130_fd_sc_hd__clkinv_16
+xpu_buff_1[1] puc4[1] GND GND VDD VDD n_pu_ctrl[1] sky130_fd_sc_hd__clkinv_16
+xpu_buff_1[0] puc4[0] GND GND VDD VDD n_pu_ctrl[0] sky130_fd_sc_hd__clkinv_16
+.ends
+
+
+* expanding symbol: p-leg.sym # of pins=3
+* sym_path: /home/derekhm/proj/caravan-project/xschem/SSTL/p-leg.sym
+* sch_path: /home/derekhm/proj/caravan-project/xschem/SSTL/p-leg.sch
+.subckt p-leg DQ n_pu_ctrl n_cal_ctrl[3] n_cal_ctrl[2] n_cal_ctrl[1] n_cal_ctrl[0]
+*.ipin n_cal_ctrl[3],n_cal_ctrl[2],n_cal_ctrl[1],n_cal_ctrl[0]
+*.ipin n_pu_ctrl
+*.iopin DQ
+R1 DQ net1 sky130_fd_pr__res_generic_po W=0.33 L=1.8 m=1
+XMpullup net1 n_pu_ctrl VDD VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=96 m=96
+XMctrl0 DQ n_cal_ctrl[0] net1 VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=48 m=48
+XMctrl1 DQ n_cal_ctrl[1] net1 VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=24 m=24
+XMctrl2 DQ n_cal_ctrl[2] net1 VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=12 m=12
+XMctrl3 DQ n_cal_ctrl[3] net1 VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6
+.ends
+
+
+* expanding symbol: n-leg.sym # of pins=3
+* sym_path: /home/derekhm/proj/caravan-project/xschem/SSTL/n-leg.sym
+* sch_path: /home/derekhm/proj/caravan-project/xschem/SSTL/n-leg.sch
+.subckt n-leg DQ pd_ctrl cal_ctrl[3] cal_ctrl[2] cal_ctrl[1] cal_ctrl[0]
+*.iopin DQ
+*.ipin pd_ctrl
+*.ipin cal_ctrl[3],cal_ctrl[2],cal_ctrl[1],cal_ctrl[0]
+R1 vpulldown DQ sky130_fd_pr__res_generic_po W=0.33 L=1.7 m=1
+Xn1 vpulldown pd_ctrl GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.65 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=48 m=48
+Xnctrl0 DQ cal_ctrl[0] vpulldown GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.65 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=32 m=32
+Xnctrl1 DQ cal_ctrl[1] vpulldown GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.65 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8
+Xnctrl2 DQ cal_ctrl[2] vpulldown GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.65 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+Xnctrl3 DQ cal_ctrl[3] vpulldown GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL VDD
+.GLOBAL GND
+.end
diff --git a/xschem/proj_sstl_test.sym b/xschem/proj_sstl_test.sym
new file mode 100644
index 0000000..18d0076
--- /dev/null
+++ b/xschem/proj_sstl_test.sym
@@ -0,0 +1,69 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @@rx_leg_ctrl[6:0] @@rx_pu_cal[3:0] @@rx_pd_cal[3:0] @@tx_leg_ctrl[6:0] @@tx_pu_cal[3:0] @@tx_pd_cal[3:0] @@data_0 @@data_2 @@data_3 @@d_sel_0 @@d_sel_1 @@rx_DQ @@tx_DQ @@n_tx_DQ @VDD @IOVDD @GND @symname"
+template="name=X1 IOVDD=IOVDD VDD=VDD GND=GND"
+extra="VDD IOVDD GND"}
+V {}
+S {}
+E {}
+L 4 50 -40 90 -40 {}
+L 4 160 -340 160 -300 {}
+L 4 50 -60 90 -60 {}
+L 4 50 -80 90 -80 {}
+L 4 540 -80 580 -80 {}
+L 4 540 -60 580 -60 {}
+L 4 540 -40 580 -40 {}
+L 4 220 -20 220 20 {}
+L 4 240 -20 240 20 {}
+L 4 260 -20 260 20 {}
+L 4 300 -20 300 20 {}
+L 4 320 -20 320 20 {}
+L 4 460 -340 460 -300 {}
+L 4 500 -340 500 -300 {}
+B 5 157.5 -342.5 162.5 -337.5 {name=rx_DQ
+dir=inout}
+B 5 47.5 -42.5 52.5 -37.5 {name=rx_pd_cal[3:0]
+dir=in}
+B 5 47.5 -62.5 52.5 -57.5 {name=rx_pu_cal[3:0]
+dir=in}
+B 5 47.5 -82.5 52.5 -77.5 {name=rx_leg_ctrl[6:0]
+dir=in}
+B 5 577.5 -82.5 582.5 -77.5 {name=tx_leg_ctrl[6:0]
+dir=in}
+B 5 577.5 -62.5 582.5 -57.5 {name=tx_pu_cal[3:0]
+dir=in}
+B 5 577.5 -42.5 582.5 -37.5 {name=tx_pd_cal[3:0]
+dir=in}
+B 5 217.5 17.5 222.5 22.5 {name=data_0
+dir=in}
+B 5 237.5 17.5 242.5 22.5 {name=data_2
+dir=in}
+B 5 257.5 17.5 262.5 22.5 {name=data_3
+dir=in}
+B 5 297.5 17.5 302.5 22.5 {name=d_sel_0
+dir=in}
+B 5 317.5 17.5 322.5 22.5 {name=d_sel_1
+dir=in}
+B 5 457.5 -342.5 462.5 -337.5 {name=tx_DQ
+dir=inout}
+B 5 497.5 -342.5 502.5 -337.5 {name=n_tx_DQ
+dir=inout}
+P 4 5 90 -300 540 -300 540 -20 90 -20 90 -300 {}
+T {SSTL TEST CIRCUIT} 110 -190 0 0 0.8 0.8 {}
+T {pd_ctrl[6:0]} 120 -210 0 0 0.3 0.3 {}
+T {@name} 290 -320 0 0 0.3 0.3 {}
+T {rx_DQ} 140 -300 0 0 0.3 0.3 {}
+T {rx_pd_cal[3:0]} 90 -50 0 0 0.3 0.3 {}
+T {rx_pu_cal[3:0]} 90 -70 0 0 0.3 0.3 {}
+T {rx_leg_ctrl[6:0]} 90 -90 0 0 0.3 0.3 {}
+T {tx_leg_ctrl[6:0]} 420 -90 0 0 0.3 0.3 {}
+T {tx_pu_cal[3:0]} 420 -70 0 0 0.3 0.3 {}
+T {tx_pd_cal[3:0]} 420 -50 0 0 0.3 0.3 {}
+T {data_0} 230 -80 1 0 0.3 0.3 {}
+T {data_2} 250 -80 1 0 0.3 0.3 {}
+T {data_3} 270 -80 1 0 0.3 0.3 {}
+T {d_sel_0} 310 -80 1 0 0.3 0.3 {}
+T {d_sel_1} 330 -80 1 0 0.3 0.3 {}
+T {tx_DQ} 470 -290 1 0 0.3 0.3 {}
+T {n_tx_DQ} 510 -290 1 0 0.3 0.3 {}
diff --git a/xschem/proj_sstl_test_tb.sch b/xschem/proj_sstl_test_tb.sch
new file mode 100644
index 0000000..5967a1f
--- /dev/null
+++ b/xschem/proj_sstl_test_tb.sch
@@ -0,0 +1,175 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 180 -210 200 -210 { lab=rx_leg_ctrl[6:0]}
+N 180 -190 200 -190 { lab=rx_pu_cal[3:0]}
+N 180 -170 200 -170 { lab=rx_pd_cal[3:0]}
+N 160 -470 310 -470 { lab=rx_DQ}
+N 650 -470 780 -470 { lab=n_tx_DQ}
+N 610 -490 610 -470 { lab=tx_DQ}
+N 610 -490 780 -490 { lab=tx_DQ}
+N 730 -210 750 -210 { lab=tx_leg_ctrl[6:0]}
+N 730 -190 750 -190 { lab=tx_pu_cal[3:0]}
+N 730 -170 750 -170 { lab=tx_pd_cal[3:0]}
+N 370 -110 370 -90 { lab=data_0}
+N 390 -110 390 -90 { lab=data_2}
+N 410 -110 410 -90 { lab=data_3}
+N 450 -110 450 -90 { lab=d_sel_0}
+N 470 -110 470 -90 { lab=d_sel_1}
+N 60 -470 100 -470 { lab=data_in}
+C {/home/derekhm/proj/caravan-project/xschem/proj_sstl_test.sym} 150 -130 0 0 {name=X1 IOVDD=IOVDD VDD=VDD GND=GND}
+C {devices/lab_wire.sym} 290 -470 0 0 {name=l2 sig_type=std_logic lab=rx_DQ}
+C {devices/lab_wire.sym} 780 -490 0 1 {name=l3 sig_type=std_logic lab=tx_DQ}
+C {devices/lab_wire.sym} 780 -470 0 1 {name=l4 sig_type=std_logic lab=n_tx_DQ}
+C {devices/lab_wire.sym} 180 -210 0 0 {name=l5 sig_type=std_logic lab=rx_leg_ctrl[6:0]
+}
+C {devices/lab_wire.sym} 180 -190 0 0 {name=l6 sig_type=std_logic lab=rx_pu_cal[3:0]
+
+}
+C {devices/lab_wire.sym} 180 -170 0 0 {name=l7 sig_type=std_logic lab=rx_pd_cal[3:0]
+
+
+}
+C {devices/lab_wire.sym} 750 -210 0 1 {name=l8 sig_type=std_logic lab=tx_leg_ctrl[6:0]
+
+}
+C {devices/lab_wire.sym} 750 -190 0 1 {name=l9 sig_type=std_logic lab=tx_pu_cal[3:0]
+
+
+}
+C {devices/lab_wire.sym} 750 -170 0 1 {name=l10 sig_type=std_logic lab=tx_pd_cal[3:0]
+
+
+
+}
+C {devices/lab_wire.sym} 370 -90 3 0 {name=l11 sig_type=std_logic lab=data_0
+}
+C {devices/lab_wire.sym} 390 -90 3 0 {name=l12 sig_type=std_logic lab=data_2
+
+}
+C {devices/lab_wire.sym} 410 -90 3 0 {name=l13 sig_type=std_logic lab=data_3
+
+
+}
+C {devices/lab_wire.sym} 450 -90 3 0 {name=l14 sig_type=std_logic lab=d_sel_0
+
+
+
+}
+C {devices/lab_wire.sym} 470 -90 3 0 {name=l15 sig_type=std_logic lab=d_sel_1
+
+
+
+
+}
+C {devices/code.sym} 760 -130 0 0 {name=STIMULI
+only_toplevel=true
+place=end
+value="
+* power voltage
+vvdd VDD 0 1.5
+
+** STATIC CONTOL
+vrx_leg_ctrl[0] rx_leg_ctrl[0] VDD 0
+vrx_leg_ctrl[1] rx_leg_ctrl[1] VDD 0
+vrx_leg_ctrl[2] rx_leg_ctrl[2] VDD 0
+vrx_leg_ctrl[3] rx_leg_ctrl[3] 0 0
+vrx_leg_ctrl[4] rx_leg_ctrl[4] 0 0
+vrx_leg_ctrl[5] rx_leg_ctrl[5] 0 0
+vrx_leg_ctrl[6] rx_leg_ctrl[6] 0 0
+
+vtx_leg_ctrl[0] tx_leg_ctrl[0] VDD 0
+vtx_leg_ctrl[1] tx_leg_ctrl[1] VDD 0
+vtx_leg_ctrl[2] tx_leg_ctrl[2] VDD 0
+vtx_leg_ctrl[3] tx_leg_ctrl[3] VDD 0
+vtx_leg_ctrl[4] tx_leg_ctrl[4] VDD 0
+vtx_leg_ctrl[5] tx_leg_ctrl[5] VDD 0
+vtx_leg_ctrl[6] tx_leg_ctrl[6] VDD 0
+
+vtx_pu_cal[3] tx_pu_cal[3] 0 0
+vtx_pu_cal[2] tx_pu_cal[2] VDD 0
+vtx_pu_cal[1] tx_pu_cal[1] VDD 0
+vtx_pu_cal[0] tx_pu_cal[0] VDD 0
+
+vtx_pd_cal[3] tx_pd_cal[3] 0 0
+vtx_pd_cal[2] tx_pd_cal[2] VDD 0
+vtx_pd_cal[1] tx_pd_cal[1] VDD 0
+vtx_pd_cal[0] tx_pd_cal[0] VDD 0
+
+vrx_pu_cal[3] rx_pu_cal[3] 0 0
+vrx_pu_cal[2] rx_pu_cal[2] VDD 0
+vrx_pu_cal[1] rx_pu_cal[1] VDD 0
+vrx_pu_cal[0] rx_pu_cal[0] VDD 0
+
+vrx_pd_cal[3] rx_pd_cal[3] 0 0
+vrx_pd_cal[2] rx_pd_cal[2] VDD 0
+vrx_pd_cal[1] rx_pd_cal[1] VDD 0
+vrx_pd_cal[0] rx_pd_cal[0] VDD 0
+
+vd0 data_0 0 0
+vd2 data_2 VDD 0
+vd3 data_3 0 0
+
+vs1 d_sel_1 0 0
+vs0 d_sel_0 VDD 0
+
+
+** Signal
+* vlow, vhigh, delay, risetime, falltime, pulsewidth, period, phase
+* vpu_ctrl0 pu_ctrl[0] 0 0 PULSE 0 SED_puctrl0_SED 1n 10p 10p 5n 10n 0
+vsig data_in 0 0 PULSE 0 1.5 1n 10p 10p 5n 10n 0
+
+
+.control
+save all
+set temp=27
+
+* RUN SIMULATION
+tran 1p 8n
+
+* OUTPUT
+set hcopydevtype = svg
+hardcopy ./sstl_test_proj.svg rx_DQ tx_DQ n_tx_DQ title 'SSTL Test Circuit'
+hardcopy ./sstl_test_proj_2.svg rx_DQ x1.d_out title 'SSTL Test Circuit'
+
+.endc
+"}
+C {devices/code.sym} 910 -130 0 0 {name=MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="** Local library links to pdk
+.lib ./sky130/libs/tt_lib.spice tt
+.include \\\\$::SKYWATER_STDCELLS\\\\/sky130_fd_sc_hd.spice
+"
+spice_ignore=false}
+C {devices/capa.sym} 190 -440 0 0 {name=C1
+m=1
+value=1p
+footprint=1206
+device="ceramic capacitor"}
+C {devices/res.sym} 130 -470 1 0 {name=R1
+value=10
+footprint=1206
+device=resistor
+m=1}
+C {devices/lab_wire.sym} 60 -470 0 0 {name=l1 sig_type=std_logic lab=data_in}
+C {devices/gnd.sym} 190 -410 0 0 {name=l16 lab=GND}
diff --git a/xschem/proj_sstl_test_tb.spice b/xschem/proj_sstl_test_tb.spice
new file mode 100644
index 0000000..0de2513
--- /dev/null
+++ b/xschem/proj_sstl_test_tb.spice
@@ -0,0 +1,279 @@
+**.subckt proj_sstl_test_tb
+X1 rx_leg_ctrl[6] rx_leg_ctrl[5] rx_leg_ctrl[4] rx_leg_ctrl[3] rx_leg_ctrl[2] rx_leg_ctrl[1]
++ rx_leg_ctrl[0] rx_pu_cal[3] rx_pu_cal[2] rx_pu_cal[1] rx_pu_cal[0] rx_pd_cal[3] rx_pd_cal[2] rx_pd_cal[1]
++ rx_pd_cal[0] tx_leg_ctrl[6] tx_leg_ctrl[5] tx_leg_ctrl[4] tx_leg_ctrl[3] tx_leg_ctrl[2] tx_leg_ctrl[1]
++ tx_leg_ctrl[0] tx_pu_cal[3] tx_pu_cal[2] tx_pu_cal[1] tx_pu_cal[0] tx_pd_cal[3] tx_pd_cal[2] tx_pd_cal[1]
++ tx_pd_cal[0] data_0 data_2 data_3 d_sel_0 d_sel_1 rx_DQ tx_DQ n_tx_DQ VDD IOVDD GND proj_sstl_test
+C1 rx_DQ GND 1p m=1
+R1 rx_DQ data_in 10 m=1
+**** begin user architecture code
+ ** Local library links to pdk
+.lib ./sky130/libs/tt_lib.spice tt
+.include /home/derekhm/cad/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: /home/derekhm/proj/caravan-project/xschem/proj_sstl_test.sym # of pins=14
+* sym_path: /home/derekhm/proj/caravan-project/xschem/proj_sstl_test.sym
+* sch_path: /home/derekhm/proj/caravan-project/xschem/proj_sstl_test.sch
+.subckt proj_sstl_test rx_leg_ctrl[6] rx_leg_ctrl[5] rx_leg_ctrl[4] rx_leg_ctrl[3] rx_leg_ctrl[2]
++ rx_leg_ctrl[1] rx_leg_ctrl[0] rx_pu_cal[3] rx_pu_cal[2] rx_pu_cal[1] rx_pu_cal[0] rx_pd_cal[3] rx_pd_cal[2]
++ rx_pd_cal[1] rx_pd_cal[0] tx_leg_ctrl[6] tx_leg_ctrl[5] tx_leg_ctrl[4] tx_leg_ctrl[3] tx_leg_ctrl[2]
++ tx_leg_ctrl[1] tx_leg_ctrl[0] tx_pu_cal[3] tx_pu_cal[2] tx_pu_cal[1] tx_pu_cal[0] tx_pd_cal[3] tx_pd_cal[2]
++ tx_pd_cal[1] tx_pd_cal[0] data_0 data_2 data_3 d_sel_0 d_sel_1 rx_DQ tx_DQ n_tx_DQ VDD IOVDD GND
+*.iopin rx_DQ
+*.ipin rx_pu_cal[3],rx_pu_cal[2],rx_pu_cal[1],rx_pu_cal[0]
+*.ipin rx_pd_cal[3],rx_pd_cal[2],rx_pd_cal[1],rx_pd_cal[0]
+*.ipin
+*+ rx_leg_ctrl[6],rx_leg_ctrl[5],rx_leg_ctrl[4],rx_leg_ctrl[3],rx_leg_ctrl[2],rx_leg_ctrl[1],rx_leg_ctrl[0]
+*.ipin data_0
+*.ipin data_2
+*.ipin data_3
+*.ipin d_sel_0
+*.ipin d_sel_1
+*.iopin tx_DQ
+*.iopin n_tx_DQ
+*.ipin tx_pu_cal[3],tx_pu_cal[2],tx_pu_cal[1],tx_pu_cal[0]
+*.ipin tx_pd_cal[3],tx_pd_cal[2],tx_pd_cal[1],tx_pd_cal[0]
+*.ipin
+*+ tx_leg_ctrl[6],tx_leg_ctrl[5],tx_leg_ctrl[4],tx_leg_ctrl[3],tx_leg_ctrl[2],tx_leg_ctrl[1],tx_leg_ctrl[0]
+X1 rx_DQ rx_leg_ctrl[6] rx_leg_ctrl[5] rx_leg_ctrl[4] rx_leg_ctrl[3] rx_leg_ctrl[2] rx_leg_ctrl[1]
++ rx_leg_ctrl[0] rx_leg_ctrl[6] rx_leg_ctrl[5] rx_leg_ctrl[4] rx_leg_ctrl[3] rx_leg_ctrl[2] rx_leg_ctrl[1]
++ rx_leg_ctrl[0] rx_pd_cal[3] rx_pd_cal[2] rx_pd_cal[1] rx_pd_cal[0] rx_pu_cal[3] rx_pu_cal[2] rx_pu_cal[1]
++ rx_pu_cal[0] IOVDD GND SSTL
+X2 tx_DQ net3[6] net3[5] net3[4] net3[3] net3[2] net3[1] net3[0] net4[6] net4[5] net4[4] net4[3]
++ net4[2] net4[1] net4[0] tx_pd_cal[3] tx_pd_cal[2] tx_pd_cal[1] tx_pd_cal[0] tx_pu_cal[3] tx_pu_cal[2]
++ tx_pu_cal[1] tx_pu_cal[0] IOVDD GND SSTL
+X3 n_tx_DQ net4[6] net4[5] net4[4] net4[3] net4[2] net4[1] net4[0] net3[6] net3[5] net3[4] net3[3]
++ net3[2] net3[1] net3[0] tx_pd_cal[3] tx_pd_cal[2] tx_pd_cal[1] tx_pd_cal[0] tx_pu_cal[3] tx_pu_cal[2]
++ tx_pu_cal[1] tx_pu_cal[0] IOVDD GND SSTL
+x1 rx_DQ GND GND VDD VDD net1 sky130_fd_sc_hd__clkbuf_2
+x2 net1 GND GND VDD VDD net2 sky130_fd_sc_hd__clkbuf_2
+x3 data_0 net2 data_2 data_3 d_sel_0 d_sel_1 GND GND VDD VDD d_out sky130_fd_sc_hd__mux4_1
+x4 d_out GND GND VDD VDD net5 sky130_fd_sc_hd__clkinv_2
+xn_and[6] d_out tx_leg_ctrl[6] GND GND VDD VDD net3[6] sky130_fd_sc_hd__and2_1
+xn_and[5] d_out tx_leg_ctrl[5] GND GND VDD VDD net3[5] sky130_fd_sc_hd__and2_1
+xn_and[4] d_out tx_leg_ctrl[4] GND GND VDD VDD net3[4] sky130_fd_sc_hd__and2_1
+xn_and[3] d_out tx_leg_ctrl[3] GND GND VDD VDD net3[3] sky130_fd_sc_hd__and2_1
+xn_and[2] d_out tx_leg_ctrl[2] GND GND VDD VDD net3[2] sky130_fd_sc_hd__and2_1
+xn_and[1] d_out tx_leg_ctrl[1] GND GND VDD VDD net3[1] sky130_fd_sc_hd__and2_1
+xn_and[0] d_out tx_leg_ctrl[0] GND GND VDD VDD net3[0] sky130_fd_sc_hd__and2_1
+xand[6] net5 tx_leg_ctrl[6] GND GND VDD VDD net4[6] sky130_fd_sc_hd__and2_1
+xand[5] net5 tx_leg_ctrl[5] GND GND VDD VDD net4[5] sky130_fd_sc_hd__and2_1
+xand[4] net5 tx_leg_ctrl[4] GND GND VDD VDD net4[4] sky130_fd_sc_hd__and2_1
+xand[3] net5 tx_leg_ctrl[3] GND GND VDD VDD net4[3] sky130_fd_sc_hd__and2_1
+xand[2] net5 tx_leg_ctrl[2] GND GND VDD VDD net4[2] sky130_fd_sc_hd__and2_1
+xand[1] net5 tx_leg_ctrl[1] GND GND VDD VDD net4[1] sky130_fd_sc_hd__and2_1
+xand[0] net5 tx_leg_ctrl[0] GND GND VDD VDD net4[0] sky130_fd_sc_hd__and2_1
+.ends
+
+
+* expanding symbol: /home/derekhm/proj/caravan-project/xschem/SSTL/SSTL.sym # of pins=5
+* sym_path: /home/derekhm/proj/caravan-project/xschem/SSTL/SSTL.sym
+* sch_path: /home/derekhm/proj/caravan-project/xschem/SSTL/SSTL.sch
+.subckt SSTL DQ pd_ctrl[6] pd_ctrl[5] pd_ctrl[4] pd_ctrl[3] pd_ctrl[2] pd_ctrl[1] pd_ctrl[0]
++ pu_ctrl[6] pu_ctrl[5] pu_ctrl[4] pu_ctrl[3] pu_ctrl[2] pu_ctrl[1] pu_ctrl[0] pd_cal_ctrl[3] pd_cal_ctrl[2]
++ pd_cal_ctrl[1] pd_cal_ctrl[0] pu_cal_ctrl[3] pu_cal_ctrl[2] pu_cal_ctrl[1] pu_cal_ctrl[0] VDD GND
+*.iopin DQ
+*.ipin pu_cal_ctrl[3],pu_cal_ctrl[2],pu_cal_ctrl[1],pu_cal_ctrl[0]
+*.ipin pd_cal_ctrl[3],pd_cal_ctrl[2],pd_cal_ctrl[1],pd_cal_ctrl[0]
+*.ipin pu_ctrl[6],pu_ctrl[5],pu_ctrl[4],pu_ctrl[3],pu_ctrl[2],pu_ctrl[1],pu_ctrl[0]
+*.ipin pd_ctrl[6],pd_ctrl[5],pd_ctrl[4],pd_ctrl[3],pd_ctrl[2],pd_ctrl[1],pd_ctrl[0]
+X1 DQ n_pu_ctrl[6] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X2 DQ pd_ctrl_buff[6] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+X3 DQ n_pu_ctrl[5] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X4 DQ pd_ctrl_buff[5] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+X5 DQ n_pu_ctrl[4] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X6 DQ pd_ctrl_buff[4] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+X7 DQ n_pu_ctrl[3] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X8 DQ pd_ctrl_buff[3] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+X9 DQ n_pu_ctrl[2] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X10 DQ pd_ctrl_buff[2] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+X11 DQ n_pu_ctrl[1] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X12 DQ pd_ctrl_buff[1] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+X13 DQ n_pu_ctrl[0] n_pu_cal_ctrl[3] n_pu_cal_ctrl[2] n_pu_cal_ctrl[1] n_pu_cal_ctrl[0] p-leg
+X14 DQ pd_ctrl_buff[0] pd_cal_ctrl[3] pd_cal_ctrl[2] pd_cal_ctrl[1] pd_cal_ctrl[0] n-leg
+xpd_buff_4[6] pdc2[6] GND GND VDD VDD pdc4[6] sky130_fd_sc_hd__clkinv_4
+xpd_buff_4[5] pdc2[5] GND GND VDD VDD pdc4[5] sky130_fd_sc_hd__clkinv_4
+xpd_buff_4[4] pdc2[4] GND GND VDD VDD pdc4[4] sky130_fd_sc_hd__clkinv_4
+xpd_buff_4[3] pdc2[3] GND GND VDD VDD pdc4[3] sky130_fd_sc_hd__clkinv_4
+xpd_buff_4[2] pdc2[2] GND GND VDD VDD pdc4[2] sky130_fd_sc_hd__clkinv_4
+xpd_buff_4[1] pdc2[1] GND GND VDD VDD pdc4[1] sky130_fd_sc_hd__clkinv_4
+xpd_buff_4[0] pdc2[0] GND GND VDD VDD pdc4[0] sky130_fd_sc_hd__clkinv_4
+xpd_buff_6[6] pdc4[6] GND GND VDD VDD pd_ctrl_buff[6] sky130_fd_sc_hd__clkbuf_8
+xpd_buff_6[5] pdc4[5] GND GND VDD VDD pd_ctrl_buff[5] sky130_fd_sc_hd__clkbuf_8
+xpd_buff_6[4] pdc4[4] GND GND VDD VDD pd_ctrl_buff[4] sky130_fd_sc_hd__clkbuf_8
+xpd_buff_6[3] pdc4[3] GND GND VDD VDD pd_ctrl_buff[3] sky130_fd_sc_hd__clkbuf_8
+xpd_buff_6[2] pdc4[2] GND GND VDD VDD pd_ctrl_buff[2] sky130_fd_sc_hd__clkbuf_8
+xpd_buff_6[1] pdc4[1] GND GND VDD VDD pd_ctrl_buff[1] sky130_fd_sc_hd__clkbuf_8
+xpd_buff_6[0] pdc4[0] GND GND VDD VDD pd_ctrl_buff[0] sky130_fd_sc_hd__clkbuf_8
+xpu_buff_4[6] pu_ctrl[6] GND GND VDD VDD puc4[6] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_4[5] pu_ctrl[5] GND GND VDD VDD puc4[5] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_4[4] pu_ctrl[4] GND GND VDD VDD puc4[4] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_4[3] pu_ctrl[3] GND GND VDD VDD puc4[3] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_4[2] pu_ctrl[2] GND GND VDD VDD puc4[2] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_4[1] pu_ctrl[1] GND GND VDD VDD puc4[1] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_4[0] pu_ctrl[0] GND GND VDD VDD puc4[0] sky130_fd_sc_hd__clkbuf_16
+xpu_buff_6[6] puc4[6] GND GND VDD VDD n_pu_ctrl[6] sky130_fd_sc_hd__clkinv_16
+xpu_buff_6[5] puc4[5] GND GND VDD VDD n_pu_ctrl[5] sky130_fd_sc_hd__clkinv_16
+xpu_buff_6[4] puc4[4] GND GND VDD VDD n_pu_ctrl[4] sky130_fd_sc_hd__clkinv_16
+xpu_buff_6[3] puc4[3] GND GND VDD VDD n_pu_ctrl[3] sky130_fd_sc_hd__clkinv_16
+xpu_buff_6[2] puc4[2] GND GND VDD VDD n_pu_ctrl[2] sky130_fd_sc_hd__clkinv_16
+xpu_buff_6[1] puc4[1] GND GND VDD VDD n_pu_ctrl[1] sky130_fd_sc_hd__clkinv_16
+xpu_buff_6[0] puc4[0] GND GND VDD VDD n_pu_ctrl[0] sky130_fd_sc_hd__clkinv_16
+xpu_cal_inv[3] pu_cal_ctrl[3] GND GND VDD VDD n_pu_cal_ctrl[3] sky130_fd_sc_hd__inv_1
+xpu_cal_inv[2] pu_cal_ctrl[2] GND GND VDD VDD n_pu_cal_ctrl[2] sky130_fd_sc_hd__inv_1
+xpu_cal_inv[1] pu_cal_ctrl[1] GND GND VDD VDD n_pu_cal_ctrl[1] sky130_fd_sc_hd__inv_1
+xpu_cal_inv[0] pu_cal_ctrl[0] GND GND VDD VDD n_pu_cal_ctrl[0] sky130_fd_sc_hd__inv_1
+xpu_buff_2[6] puc4[6] GND GND VDD VDD n_pu_ctrl[6] sky130_fd_sc_hd__clkinv_16
+xpu_buff_2[5] puc4[5] GND GND VDD VDD n_pu_ctrl[5] sky130_fd_sc_hd__clkinv_16
+xpu_buff_2[4] puc4[4] GND GND VDD VDD n_pu_ctrl[4] sky130_fd_sc_hd__clkinv_16
+xpu_buff_2[3] puc4[3] GND GND VDD VDD n_pu_ctrl[3] sky130_fd_sc_hd__clkinv_16
+xpu_buff_2[2] puc4[2] GND GND VDD VDD n_pu_ctrl[2] sky130_fd_sc_hd__clkinv_16
+xpu_buff_2[1] puc4[1] GND GND VDD VDD n_pu_ctrl[1] sky130_fd_sc_hd__clkinv_16
+xpu_buff_2[0] puc4[0] GND GND VDD VDD n_pu_ctrl[0] sky130_fd_sc_hd__clkinv_16
+xpd_buff_1[6] pd_ctrl[6] GND GND VDD VDD pdc2[6] sky130_fd_sc_hd__clkinv_4
+xpd_buff_1[5] pd_ctrl[5] GND GND VDD VDD pdc2[5] sky130_fd_sc_hd__clkinv_4
+xpd_buff_1[4] pd_ctrl[4] GND GND VDD VDD pdc2[4] sky130_fd_sc_hd__clkinv_4
+xpd_buff_1[3] pd_ctrl[3] GND GND VDD VDD pdc2[3] sky130_fd_sc_hd__clkinv_4
+xpd_buff_1[2] pd_ctrl[2] GND GND VDD VDD pdc2[2] sky130_fd_sc_hd__clkinv_4
+xpd_buff_1[1] pd_ctrl[1] GND GND VDD VDD pdc2[1] sky130_fd_sc_hd__clkinv_4
+xpd_buff_1[0] pd_ctrl[0] GND GND VDD VDD pdc2[0] sky130_fd_sc_hd__clkinv_4
+xpu_buff_1[6] puc4[6] GND GND VDD VDD n_pu_ctrl[6] sky130_fd_sc_hd__clkinv_16
+xpu_buff_1[5] puc4[5] GND GND VDD VDD n_pu_ctrl[5] sky130_fd_sc_hd__clkinv_16
+xpu_buff_1[4] puc4[4] GND GND VDD VDD n_pu_ctrl[4] sky130_fd_sc_hd__clkinv_16
+xpu_buff_1[3] puc4[3] GND GND VDD VDD n_pu_ctrl[3] sky130_fd_sc_hd__clkinv_16
+xpu_buff_1[2] puc4[2] GND GND VDD VDD n_pu_ctrl[2] sky130_fd_sc_hd__clkinv_16
+xpu_buff_1[1] puc4[1] GND GND VDD VDD n_pu_ctrl[1] sky130_fd_sc_hd__clkinv_16
+xpu_buff_1[0] puc4[0] GND GND VDD VDD n_pu_ctrl[0] sky130_fd_sc_hd__clkinv_16
+.ends
+
+
+* expanding symbol: p-leg.sym # of pins=3
+* sym_path: /home/derekhm/proj/caravan-project/xschem/SSTL/p-leg.sym
+* sch_path: /home/derekhm/proj/caravan-project/xschem/SSTL/p-leg.sch
+.subckt p-leg DQ n_pu_ctrl n_cal_ctrl[3] n_cal_ctrl[2] n_cal_ctrl[1] n_cal_ctrl[0]
+*.ipin n_cal_ctrl[3],n_cal_ctrl[2],n_cal_ctrl[1],n_cal_ctrl[0]
+*.ipin n_pu_ctrl
+*.iopin DQ
+R1 DQ net1 sky130_fd_pr__res_generic_po W=0.33 L=1.8 m=1
+XMpullup net1 n_pu_ctrl VDD VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=96 m=96
+XMctrl0 DQ n_cal_ctrl[0] net1 VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=48 m=48
+XMctrl1 DQ n_cal_ctrl[1] net1 VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=24 m=24
+XMctrl2 DQ n_cal_ctrl[2] net1 VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=12 m=12
+XMctrl3 DQ n_cal_ctrl[3] net1 VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6
+.ends
+
+
+* expanding symbol: n-leg.sym # of pins=3
+* sym_path: /home/derekhm/proj/caravan-project/xschem/SSTL/n-leg.sym
+* sch_path: /home/derekhm/proj/caravan-project/xschem/SSTL/n-leg.sch
+.subckt n-leg DQ pd_ctrl cal_ctrl[3] cal_ctrl[2] cal_ctrl[1] cal_ctrl[0]
+*.iopin DQ
+*.ipin pd_ctrl
+*.ipin cal_ctrl[3],cal_ctrl[2],cal_ctrl[1],cal_ctrl[0]
+R1 vpulldown DQ sky130_fd_pr__res_generic_po W=0.33 L=1.7 m=1
+Xn1 vpulldown pd_ctrl GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.65 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=48 m=48
+Xnctrl0 DQ cal_ctrl[0] vpulldown GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.65 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=32 m=32
+Xnctrl1 DQ cal_ctrl[1] vpulldown GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.65 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8
+Xnctrl2 DQ cal_ctrl[2] vpulldown GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.65 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+Xnctrl3 DQ cal_ctrl[3] vpulldown GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.GLOBAL VDD
+**** begin user architecture code
+
+
+* power voltage
+vvdd VDD 0 1.5
+
+** STATIC CONTOL
+vrx_leg_ctrl[0] rx_leg_ctrl[0] VDD 0
+vrx_leg_ctrl[1] rx_leg_ctrl[1] VDD 0
+vrx_leg_ctrl[2] rx_leg_ctrl[2] VDD 0
+vrx_leg_ctrl[3] rx_leg_ctrl[3] 0 0
+vrx_leg_ctrl[4] rx_leg_ctrl[4] 0 0
+vrx_leg_ctrl[5] rx_leg_ctrl[5] 0 0
+vrx_leg_ctrl[6] rx_leg_ctrl[6] 0 0
+
+vtx_leg_ctrl[0] tx_leg_ctrl[0] VDD 0
+vtx_leg_ctrl[1] tx_leg_ctrl[1] VDD 0
+vtx_leg_ctrl[2] tx_leg_ctrl[2] VDD 0
+vtx_leg_ctrl[3] tx_leg_ctrl[3] VDD 0
+vtx_leg_ctrl[4] tx_leg_ctrl[4] VDD 0
+vtx_leg_ctrl[5] tx_leg_ctrl[5] VDD 0
+vtx_leg_ctrl[6] tx_leg_ctrl[6] VDD 0
+
+vtx_pu_cal[3] tx_pu_cal[3] 0 0
+vtx_pu_cal[2] tx_pu_cal[2] VDD 0
+vtx_pu_cal[1] tx_pu_cal[1] VDD 0
+vtx_pu_cal[0] tx_pu_cal[0] VDD 0
+
+vtx_pd_cal[3] tx_pd_cal[3] 0 0
+vtx_pd_cal[2] tx_pd_cal[2] VDD 0
+vtx_pd_cal[1] tx_pd_cal[1] VDD 0
+vtx_pd_cal[0] tx_pd_cal[0] VDD 0
+
+vrx_pu_cal[3] rx_pu_cal[3] 0 0
+vrx_pu_cal[2] rx_pu_cal[2] VDD 0
+vrx_pu_cal[1] rx_pu_cal[1] VDD 0
+vrx_pu_cal[0] rx_pu_cal[0] VDD 0
+
+vrx_pd_cal[3] rx_pd_cal[3] 0 0
+vrx_pd_cal[2] rx_pd_cal[2] VDD 0
+vrx_pd_cal[1] rx_pd_cal[1] VDD 0
+vrx_pd_cal[0] rx_pd_cal[0] VDD 0
+
+vd0 data_0 0 0
+vd2 data_2 VDD 0
+vd3 data_3 0 0
+
+vs1 d_sel_1 0 0
+vs0 d_sel_0 VDD 0
+
+
+** Signal
+* vlow, vhigh, delay, risetime, falltime, pulsewidth, period, phase
+* vpu_ctrl0 pu_ctrl[0] 0 0 PULSE 0 SED_puctrl0_SED 1n 10p 10p 5n 10n 0
+vsig data_in 0 0 PULSE 0 1.5 1n 10p 10p 5n 10n 0
+
+
+.control
+save all
+set temp=27
+
+* RUN SIMULATION
+tran 1p 8n
+
+* OUTPUT
+set hcopydevtype = svg
+hardcopy ./sstl_test_proj.svg rx_DQ tx_DQ n_tx_DQ title 'SSTL Test Circuit'
+hardcopy ./sstl_test_proj_2.svg rx_DQ x1.d_out title 'SSTL Test Circuit'
+
+.endc
+
+
+**** end user architecture code
+.end
