commit: 8b6681d9ad48619ba5b9479fa2c39b56a2ff5edd
[log] [tgz]
author: Derek H-M <derekcom16@gmail.com>
Tue Mar 01 15:51:57 2022 -0800
committer: Derek H-M <derekcom16@gmail.com>
Tue Mar 01 15:51:57 2022 -0800
tree: 257cb8afb67e4d8151e7318cfcc5b84e0b7fa9f4
parent: b57872691788a90c8218b3d24cd3cfb5737f5ed8 [diff]

Add schematic and spice TB for proj_sstl_test cell

mag/lvs_netgen.tcl[diff]
mag/pex_netgen.tcl[Added - diff]
xschem/SSTL/SSTL.sch[Added - diff]
xschem/SSTL/SSTL.sym[Added - diff]
xschem/SSTL/n-leg.sch[Added - diff]
xschem/SSTL/n-leg.sym[Added - diff]
xschem/SSTL/n-leg_tb.sch[Added - diff]
xschem/SSTL/p-leg.sch[Added - diff]
xschem/SSTL/p-leg.sym[Added - diff]
xschem/SSTL/p-leg_tb.sch[Added - diff]
xschem/SSTL/post_layout_SSTL.sym[Added - diff]
xschem/SSTL/post_layout_sstl_res_tb.sch[Added - diff]
xschem/SSTL/post_layout_sstl_slew_tb.sch[Added - diff]
xschem/SSTL/sstl_res_tb.sch[Added - diff]
xschem/SSTL/sstl_slew_tb.sch[Added - diff]
xschem/SSTL/test_pd_res.sch[Added - diff]
xschem/SSTL/test_pu_res.sch[Added - diff]
xschem/example_por/analog_wrapper_tb.sch[Renamed from xschem/analog_wrapper_tb.sch - diff]
xschem/example_por/analog_wrapper_tb.spice[Renamed from xschem/analog_wrapper_tb.spice - diff]
xschem/example_por/current_test.spice[Renamed from xschem/current_test.spice - diff]
xschem/example_por/example_por.sch[Renamed from xschem/example_por.sch - diff]
xschem/example_por/example_por.sym[Renamed from xschem/example_por.sym - diff]
xschem/example_por/example_por_tb.sch[Renamed from xschem/example_por_tb.sch - diff]
xschem/example_por/example_por_tb.spice[Renamed from xschem/example_por_tb.spice - diff]
xschem/example_por/example_por_tb.spice.orig[Renamed from xschem/example_por_tb.spice.orig - diff]
xschem/example_por/test.data[Renamed from xschem/test.data - diff]
xschem/example_por/threshold_test_tb.spice[Renamed from xschem/threshold_test_tb.spice - diff]
xschem/proj_sstl_test.sch[Added - diff]
xschem/proj_sstl_test.spice[Added - diff]
xschem/proj_sstl_test.sym[Added - diff]
xschem/proj_sstl_test_tb.sch[Added - diff]
xschem/proj_sstl_test_tb.spice[Added - diff]

32 files changed

tree: 257cb8afb67e4d8151e7318cfcc5b84e0b7fa9f4

README.md

DDR3 SSTL Caravel Analog Project

A (possibly temporary) location for DDR3 SSTL test circuit project.

Refer to README for this sample project documentation.