| commit | 8b6681d9ad48619ba5b9479fa2c39b56a2ff5edd | [log] [tgz] |
|---|---|---|
| author | Derek H-M <derekcom16@gmail.com> | Tue Mar 01 15:51:57 2022 -0800 |
| committer | Derek H-M <derekcom16@gmail.com> | Tue Mar 01 15:51:57 2022 -0800 |
| tree | 257cb8afb67e4d8151e7318cfcc5b84e0b7fa9f4 | |
| parent | b57872691788a90c8218b3d24cd3cfb5737f5ed8 [diff] |
Add schematic and spice TB for proj_sstl_test cell
A (possibly temporary) location for DDR3 SSTL test circuit project.
Refer to README for this sample project documentation.