| /root/DDR3_SSTL_TEST/.magicrc |
| /root/DDR3_SSTL_TEST/Makefile |
| /root/DDR3_SSTL_TEST/docs/Makefile |
| /root/DDR3_SSTL_TEST/docs/environment.yml |
| /root/DDR3_SSTL_TEST/docs/source/conf.py |
| /root/DDR3_SSTL_TEST/docs/source/index.rst |
| /root/DDR3_SSTL_TEST/mag/lvs_netgen.tcl |
| /root/DDR3_SSTL_TEST/mag/pex_netgen.tcl |
| /root/DDR3_SSTL_TEST/mag/SSTL/lvs_netgen.tcl |
| /root/DDR3_SSTL_TEST/mag/SSTL/pex_netgen.tcl |
| /root/DDR3_SSTL_TEST/netgen/run_lvs_por.sh |
| /root/DDR3_SSTL_TEST/netgen/run_lvs_wrapper_verilog.sh |
| /root/DDR3_SSTL_TEST/netgen/run_lvs_wrapper_xschem.sh |
| /root/DDR3_SSTL_TEST/verilog/dv/Makefile |
| /root/DDR3_SSTL_TEST/verilog/dv/mprj_por/Makefile |
| /root/DDR3_SSTL_TEST/verilog/dv/mprj_por/mprj_por.c |
| /root/DDR3_SSTL_TEST/verilog/dv/mprj_por/mprj_por_tb.v |
| /root/DDR3_SSTL_TEST/verilog/rtl/cfg_shift_register.v |
| /root/DDR3_SSTL_TEST/verilog/rtl/user_analog_project_wrapper.v |
| /root/DDR3_SSTL_TEST/verilog/rtl/example_por/example_por.v |
| /root/DDR3_SSTL_TEST/verilog/rtl/example_por/uprj_analog_netlists.v |
| /root/DDR3_SSTL_TEST/verilog/rtl/example_por/user_analog_proj_example.v |
| /root/DDR3_SSTL_TEST/verilog/rtl/example_por/user_analog_project_wrapper.v |
| /root/DDR3_SSTL_TEST/xschem/.spiceinit |
| /root/DDR3_SSTL_TEST/xschem/cfg_shift_register.sch |
| /root/DDR3_SSTL_TEST/xschem/cfg_shift_register.sym |
| /root/DDR3_SSTL_TEST/xschem/cfg_shift_register_tb.sch |
| /root/DDR3_SSTL_TEST/xschem/prb_gen_tb.sch |
| /root/DDR3_SSTL_TEST/xschem/prbs_gen.sch |
| /root/DDR3_SSTL_TEST/xschem/prbs_gen.sym |
| /root/DDR3_SSTL_TEST/xschem/proj_sstl_test.sch |
| /root/DDR3_SSTL_TEST/xschem/proj_sstl_test.sym |
| /root/DDR3_SSTL_TEST/xschem/proj_sstl_test_tb.sch |
| /root/DDR3_SSTL_TEST/xschem/user_analog_project_wrapper.sch |
| /root/DDR3_SSTL_TEST/xschem/user_analog_project_wrapper.sym |
| /root/DDR3_SSTL_TEST/xschem/xschemrc |
| /root/DDR3_SSTL_TEST/xschem/SSTL/SSTL.sch |
| /root/DDR3_SSTL_TEST/xschem/SSTL/SSTL.sym |
| /root/DDR3_SSTL_TEST/xschem/SSTL/n-leg.sch |
| /root/DDR3_SSTL_TEST/xschem/SSTL/n-leg.sym |
| /root/DDR3_SSTL_TEST/xschem/SSTL/n-leg_tb.sch |
| /root/DDR3_SSTL_TEST/xschem/SSTL/p-leg.sch |
| /root/DDR3_SSTL_TEST/xschem/SSTL/p-leg.sym |
| /root/DDR3_SSTL_TEST/xschem/SSTL/p-leg_tb.sch |
| /root/DDR3_SSTL_TEST/xschem/SSTL/post_layout_SSTL.sym |
| /root/DDR3_SSTL_TEST/xschem/SSTL/post_layout_sstl_res_tb.sch |
| /root/DDR3_SSTL_TEST/xschem/SSTL/post_layout_sstl_slew_tb.sch |
| /root/DDR3_SSTL_TEST/xschem/SSTL/sstl_res_tb.sch |
| /root/DDR3_SSTL_TEST/xschem/SSTL/sstl_slew_tb.sch |
| /root/DDR3_SSTL_TEST/xschem/SSTL/test_pd_res.sch |
| /root/DDR3_SSTL_TEST/xschem/SSTL/test_pu_res.sch |
| /root/DDR3_SSTL_TEST/xschem/example_por/analog_wrapper_tb.sch |
| /root/DDR3_SSTL_TEST/xschem/example_por/example_por.sch |
| /root/DDR3_SSTL_TEST/xschem/example_por/example_por.sym |
| /root/DDR3_SSTL_TEST/xschem/example_por/example_por_tb.sch |
| /root/DDR3_SSTL_TEST/xschem/example_por/example_por_tb.spice.orig |
| /root/DDR3_SSTL_TEST/xschem/example_por/test.data |
