commit	cb891f646496bce5b7aaf15d954a6128c6606413	[log] [tgz]
author	yct000 <yahyacantugrul@gmail.com>	Mon Mar 14 13:00:04 2022 +0300
committer	yct000 <yahyacantugrul@gmail.com>	Mon Mar 14 13:00:04 2022 +0300
tree	40e3cb1aba9bd69cba3bee5c4ddfaee382264d35
parent	b3ac77dd3737f2aa461199484538fd91c363deed [diff]

add rtl

verilog/rtl/UART_GFA.v[Added - diff]
verilog/rtl/UART_alici.v[Added - diff]
verilog/rtl/UART_verici.v[Added - diff]
verilog/rtl/adres_tekleyici.v[Added - diff]
verilog/rtl/aritmetik_mantik_birimi.v[Added - diff]
verilog/rtl/axil_interconnect.v[Added - diff]
verilog/rtl/axil_slave_gfa.v[Added - diff]
verilog/rtl/baslangic_bellegi.v[Added - diff]
verilog/rtl/bellek_islem_birimi.v[Added - diff]
verilog/rtl/buyruk_bellegi_sram.v[Added - diff]
verilog/rtl/c0_system.v[Added - diff]
verilog/rtl/cekirdek.v[Added - diff]
verilog/rtl/dallanma_birimi.v[Added - diff]
verilog/rtl/denetim_durum_birimi.v[Added - diff]
verilog/rtl/getir_coz.v[Added - diff]
verilog/rtl/iki_bit_adimli_bolucu.v[Added - diff]
verilog/rtl/iki_bit_adimli_carpici.v[Added - diff]
verilog/rtl/mikroislem.vh[Added - diff]
verilog/rtl/on_taraf.v[Added - diff]
verilog/rtl/sabitler.vh[Added - diff]
verilog/rtl/tamsayi_bolme_birimi.v[Added - diff]
verilog/rtl/tamsayi_carpma_birimi.v[Added - diff]
verilog/rtl/uprj_netlists.v[Deleted - diff]
verilog/rtl/user_proj_example.v[diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/user_project_wrapper_org.v[Added - diff]
verilog/rtl/veri_bellegi_sram.v[Added - diff]
verilog/rtl/yazmac_obegi.v[Added - diff]
verilog/rtl/yazmac_oku_yurut.v[Added - diff]
verilog/rtl/yazmac_yaz.v[Added - diff]

30 files changed

tree: 40e3cb1aba9bd69cba3bee5c4ddfaee382264d35

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.