commit | 26b5c1ec72b2032c7804cdf17303ac3c3e109e98 | [log] [tgz] |
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author | yct000 <yahyacantugrul@gmail.com> | Mon Mar 14 18:10:49 2022 +0300 |
committer | yct000 <yahyacantugrul@gmail.com> | Mon Mar 14 18:10:49 2022 +0300 |
tree | a9e2f8d11884c1d8c5856e0372e6eeb53af9af13 | |
parent | 24254599e08d7423449f0f60974f0a5ef218f475 [diff] |
update readme
This repo contains the RISC-V based K0 SoC that utilizes caravel
chip user space. K0 is an silicon-proven SoC that has a RISC-V core (RV32-IM ISA) and AN UART module @ 115200 baudrate. The repo also contains all required files to run all RV32-IM ISA tests.
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user_project_wrapper
.user_project_wrapper
at verilog/gl/user_project_wrapper.vuser_project_wrapper
adheres to the same pin order specified at pin\_order
user_project_wrapper
adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs
mpw-precheck