add config files
diff --git a/Makefile b/Makefile
index e787f93..6182d1b 100644
--- a/Makefile
+++ b/Makefile
@@ -66,7 +66,7 @@
blocks=$(shell cd openlane && find * -maxdepth 0 -type d)
.PHONY: $(blocks)
$(blocks):
- export CARAVEL_ROOT=$(CARAVEL_ROOT) && cd openlane && $(MAKE) $*
+ export CARAVEL_ROOT=$(CARAVEL_ROOT) && cd openlane && $(MAKE) $@
dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
dv-targets-rtl=$(dv_patterns:%=verify-%-rtl)
@@ -74,7 +74,7 @@
dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf)
TARGET_PATH=$(shell pwd)
-verify_command="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+verify_command="cd ${TARGET_PATH}/verilog/dv/test_c0 && export SIM=${SIM} && make"
dv_base_dependencies=simenv
docker_run_verify=\
docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
@@ -119,6 +119,42 @@
rm -f ./lef/$*.lef
rm -f ./maglef/*.maglef
+
+rv-tests=$(shell cd verilog/dv/test_c0/coe && find * -maxdepth 0 -type d)
+rv-tests-rtl=$(rv-tests:%=test-%-rtl)
+rv-tests-gl=$(rv-tests:%=test-%-gl)
+rv-tests-gl-sdf=$(rv-tests:%=test-%-gl-sdf)
+
+.PHONY: test
+test: $(rv-tests)
+
+$(rv-tests-rtl): SIM=RTL
+$(rv-tests-rtl): test-%-rtl: $(dv_base_dependencies)
+ python3 $(PWD)/verilog/dv/test_c0/coe2verilog.py $*
+ $(docker_run_verify)
+ python3 $(PWD)/verilog/dv/test_c0/check_res.py RTL
+
+$(rv-tests-gl): SIM=GL
+$(rv-tests-gl): test-%-gl: $(dv_base_dependencies)
+ python3 $(PWD)/verilog/dv/test_c0/coe2verilog.py $*
+ $(docker_run_verify)
+ python3 $(PWD)/verilog/dv/test_c0/check_res.py GL
+
+$(rv-tests-gl-sdf): SIM=GL_SDF
+$(rv-tests-gl-sdf): test-%-gl-sdf: $(dv_base_dependencies)
+ python3 $(PWD)/verilog/dv/test_c0/coe2verilog.py $*
+ $(docker_run_verify)
+ python3 $(PWD)/verilog/dv/test_c0/check_res.py GL
+
+.PHONY: clean_test
+clean_test:
+ rm -f ./verilog/dv/test_c0/*.txt
+ rm -f ./verilog/dv/test_c0/*.vcd
+ rm -f ./verilog/dv/test_c0/*.hex
+ rm -f ./verilog/dv/test_c0/*.hexe
+ rm -f ./verilog/dv/test_c0/*.lst
+ rm -f ./verilog/dv/test_c0/c0_uart_prog_tb.v
+
make_what=setup $(blocks) $(dv-targets-rtl) $(dv-targets-gl) $(dv-targets-gl-sdf) $(clean-targets)
.PHONY: what
what:
diff --git a/openlane/c0_system/config.tcl b/openlane/c0_system/config.tcl
new file mode 100755
index 0000000..f42d1a8
--- /dev/null
+++ b/openlane/c0_system/config.tcl
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) c0_system
+
+set ::env(VERILOG_FILES) "\
+ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/sabitler.vh \
+ $script_dir/../../verilog/rtl/mikroislem.vh \
+ $script_dir/../../verilog/rtl/c0_system.v \
+ $script_dir/../../verilog/rtl/getir_coz.v \
+ $script_dir/../../verilog/rtl/adres_tekleyici.v \
+ $script_dir/../../verilog/rtl/aritmetik_mantik_birimi.v \
+ $script_dir/../../verilog/rtl/baslangic_bellegi.v \
+ $script_dir/../../verilog/rtl/bellek_islem_birimi.v \
+ $script_dir/../../verilog/rtl/buyruk_bellegi_sram.v \
+ $script_dir/../../verilog/rtl/cekirdek.v \
+ $script_dir/../../verilog/rtl/dallanma_birimi.v \
+ $script_dir/../../verilog/rtl/denetim_durum_birimi.v \
+ $script_dir/../../verilog/rtl/on_taraf.v \
+ $script_dir/../../verilog/rtl/veri_bellegi_sram.v \
+ $script_dir/../../verilog/rtl/yazmac_obegi.v \
+ $script_dir/../../verilog/rtl/yazmac_oku_yurut.v \
+ $script_dir/../../verilog/rtl/yazmac_yaz.v \
+ $script_dir/../../verilog/rtl/UART_GFA.v \
+ $script_dir/../../verilog/rtl/UART_alici.v \
+ $script_dir/../../verilog/rtl/UART_verici.v \
+ $script_dir/../../verilog/rtl/iki_bit_adimli_bolucu.v \
+ $script_dir/../../verilog/rtl/axil_interconnect.v \
+ $script_dir/../../verilog/rtl/iki_bit_adimli_carpici.v \
+ $script_dir/../../verilog/rtl/tamsayi_carpma_birimi.v \
+ $script_dir/../../verilog/rtl/tamsayi_bolme_birimi.v \
+ $script_dir/../../verilog/rtl/axil_slave_gfa.v"
+
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(CLOCK_PORT) "clk_g"
+set ::env(CLOCK_NET) "clk_g"
+set ::env(CLOCK_PERIOD) "50"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 1300 1300"
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+#set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_TARGET_DENSITY) 0.19
+
+# Maximum layer used for routing is metal 4.
+# This is because this macro will be inserted in a top level (user_project_wrapper)
+# where the PDN is planned on metal 5. So, to avoid having shorts between routes
+# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.
+set ::env(RT_MAX_LAYER) {met4}
+
+# You can draw more power domains if you need to
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+# If you're going to use multiple power domains, then disable cvc run.
+set ::env(RUN_CVC) 1
+#set ::env(FP_PDN_CHECK_NODES) 0
+
+
+set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
+set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) 1
diff --git a/openlane/c0_system/pin_order.cfg b/openlane/c0_system/pin_order.cfg
new file mode 100644
index 0000000..8170762
--- /dev/null
+++ b/openlane/c0_system/pin_order.cfg
@@ -0,0 +1,12 @@
+#BUS_SORT
+
+#S
+clk_g
+rst_g
+tx
+rx
+io_.*
+
+#W
+vb_.*
+bb_.*
\ No newline at end of file
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
deleted file mode 100644
index c3de8af..0000000
--- a/openlane/user_proj_example/config.json
+++ /dev/null
@@ -1,21 +0,0 @@
-{
- "PDK" : "sky130A",
- "STD_CELL_LIBRARY" : "sky130_fd_sc_hd",
- "CARAVEL_ROOT" : "../../caravel",
- "CLOCK_NET" : "counter.clk",
- "CLOCK_PERIOD" : "10",
- "CLOCK_PORT" : "wb_clk_i",
- "DESIGN_IS_CORE" : "0",
- "DESIGN_NAME" : "user_proj_example",
- "DIE_AREA" : "0 0 900 600",
- "DIODE_INSERTION_STRATEGY" : "4",
- "FP_PIN_ORDER_CFG" : "pin_order.cfg",
- "FP_SIZING" : "absolute",
- "GLB_RT_MAXLAYER" : "5",
- "GND_NETS" : "vssd1",
- "PL_BASIC_PLACEMENT" : "1",
- "PL_TARGET_DENSITY" : "0.05",
- "RUN_CVC" : "1",
- "VDD_NETS" : "vccd1",
- "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v", "../../verilog/rtl/user_proj_example.v"]
-}
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
deleted file mode 100755
index c9266ee..0000000
--- a/openlane/user_proj_example/config.tcl
+++ /dev/null
@@ -1,56 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-set ::env(PDK) "sky130A"
-set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
-
-set script_dir [file dirname [file normalize [info script]]]
-
-set ::env(DESIGN_NAME) user_proj_example
-
-set ::env(VERILOG_FILES) "\
- $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj_example.v"
-
-set ::env(DESIGN_IS_CORE) 0
-
-set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_NET) "counter.clk"
-set ::env(CLOCK_PERIOD) "10"
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 900 600"
-
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-
-set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.05
-
-# Maximum layer used for routing is metal 4.
-# This is because this macro will be inserted in a top level (user_project_wrapper)
-# where the PDN is planned on metal 5. So, to avoid having shorts between routes
-# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.
-#
-# set ::env(GLB_RT_MAXLAYER) 5
-
-set ::env(RT_MAX_LAYER) {met4}
-
-# You can draw more power domains if you need to
-set ::env(VDD_NETS) [list {vccd1}]
-set ::env(GND_NETS) [list {vssd1}]
-
-set ::env(DIODE_INSERTION_STRATEGY) 4
-# If you're going to use multiple power domains, then disable cvc run.
-set ::env(RUN_CVC) 1
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg
deleted file mode 100644
index 2fda806..0000000
--- a/openlane/user_proj_example/pin_order.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#BUS_SORT
-
-#S
-wb_.*
-wbs_.*
-la_.*
-irq.*
-
-#N
-io_.*
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index f720e39..4b6a4bc 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -35,18 +35,25 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/sabitler.vh \
$script_dir/../../verilog/rtl/user_project_wrapper.v"
## Clock configurations
set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+set ::env(CLOCK_NET) "mprj.clk_g\
+ VB_SRAM.clk0\
+ VB_SRAM.clk1\
+ BB_SRAM.clk0\
+ BB_SRAM.clk1"
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "50"
## Internal Macros
### Macro PDN Connections
set ::env(FP_PDN_MACRO_HOOKS) "\
- mprj vccd1 vssd1"
+ mprj vccd1 vssd1\
+ BB_SRAM vccd1 vssd1 \
+ VB_SRAM vccd1 vssd1"
### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
@@ -54,13 +61,17 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj_example.v"
+ $script_dir/../../verilog/rtl/sabitler.vh \
+ $script_dir/../../verilog/rtl/c0_system.v \
+ $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v"
set ::env(EXTRA_LEFS) "\
- $script_dir/../../lef/user_proj_example.lef"
+ $script_dir/../../lef/c0_system.lef \
+ $script_dir/../../lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef"
set ::env(EXTRA_GDS_FILES) "\
- $script_dir/../../gds/user_proj_example.gds"
+ $script_dir/../../gds/c0_system.gds \
+ $script_dir/../../gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds"
# set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
@@ -69,6 +80,25 @@
# any issue with pdn connections will be flagged with LVS so it is not a critical check.
set ::env(FP_PDN_CHECK_NODES) 0
+
+#set ::env(VDD_NETS) "vccd1"
+#set ::env(GND_NETS) "vssd1"
+
+
+# Ataberk: yanked from mbist_ctrl
+# Add Blockage arond the SRAM to avoid Magic DRC &
+# add signal routing blockage for met5
+
+# SRAM Dimensions: X-479,78, Y-397,5
+# 2Kbyte Dim: X-683.1, Y-416.54
+set ::env(GLB_RT_OBS) " met1 250.00 1000.00 933.1 1416.54, \
+ met2 250.00 1000.00 933.1 1416.54, \
+ met3 250.00 1000.00 933.1 1416.54, \
+ met1 250.00 1900.00 933.1 2316.54, \
+ met2 250.00 1900.00 933.1 2316.54, \
+ met3 250.00 1900.00 933.1 2316.54, \
+ met5 0 0 2920 3520"
+
# The following is because there are no std cells in the example wrapper project.
set ::env(SYNTH_TOP_LEVEL) 1
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
@@ -84,3 +114,16 @@
set ::env(FILL_INSERTION) 0
set ::env(TAP_DECAP_INSERTION) 0
set ::env(CLOCK_TREE_SYNTH) 0
+
+# # Yanked from: https://github.com/dineshannayya/mbist_ctrl/blob/main/openlane/user_project_wrapper/config.tcl
+
+set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "0"
+set ::env(QUIT_ON_NEGATIVE_WNS) "0"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_TR_DRC) "0"
+
+# # Because OpenLANE takes up all memory trying to output DRC failures in KLAYOUT format
+set ::env(RUN_KLAYOUT_DRC) 0
+set ::env(MAGIC_DRC_USE_GDS) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..67c4ba1 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,4 @@
-mprj 1175 1690 N
+mprj 1200 700 N
+
+VB_SRAM 250 1000 N
+BB_SRAM 250 1900 N
