Turned off vccd1 and vssd1 rails
diff --git a/gds/flash_array_8x8.gds b/gds/flash_array_8x8.gds
index fba5caf..023c8b6 100644
--- a/gds/flash_array_8x8.gds
+++ b/gds/flash_array_8x8.gds
Binary files differ
diff --git a/lef/flash_array_8x8.lef b/lef/flash_array_8x8.lef
index fc8b0fe..4072aaa 100644
--- a/lef/flash_array_8x8.lef
+++ b/lef/flash_array_8x8.lef
@@ -607,7 +607,7 @@
RECT 8.450 -8.515 8.620 -8.345 ;
END
END SSL[1]
- PIN vssd1
+ PIN GND
ANTENNADIFFAREA 3.279200 ;
PORT
LAYER pwell ;
@@ -738,8 +738,8 @@
RECT 5.805 -22.460 6.035 -22.170 ;
RECT 7.245 -22.460 7.475 -22.170 ;
END
- END vssd1
- PIN vccd1
+ END GND
+ PIN VDD
ANTENNADIFFAREA 2.860800 ;
PORT
LAYER nwell ;
@@ -762,7 +762,7 @@
LAYER met1 ;
RECT 2.515 -18.305 8.275 -18.075 ;
END
- END vccd1
+ END VDD
PIN sen1
ANTENNAGATEAREA 0.504000 ;
PORT
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 56e0b4d..7640e47 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -42,8 +42,12 @@
## Internal Macros
### Macro PDN Connections
-set ::env(FP_PDN_MACRO_HOOKS) "\
- u_flash_array_8x8 vccd1 vssd1"
+# set ::env(FP_PDN_MACRO_HOOKS) "\
+# u_flash_array_8x8 vccd1 vssd1"
+
+set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
+set ::env(LVS_INSERT_POWER_PINS) 0
+
### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
@@ -61,6 +65,9 @@
set ::env(GLB_RT_MAXLAYER) 5
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
+
# disable pdn check nodes becuase it hangs with multiple power domains.
# any issue with pdn connections will be flagged with LVS so it is not a critical check.
set ::env(FP_PDN_CHECK_NODES) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 7d75456..03c1f13 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-u_flash_array_8x8 1175 1690 N
+u_flash_array_8x8 1152 1690 N
diff --git a/verilog/rtl/flash_array_8x8.v b/verilog/rtl/flash_array_8x8.v
index 0222f2a..960a575 100644
--- a/verilog/rtl/flash_array_8x8.v
+++ b/verilog/rtl/flash_array_8x8.v
@@ -2,9 +2,11 @@
`default_nettype none
module flash_array_8x8 (
-`ifdef USE_POWER_PINS
- inout vccd1, vssd1,
-`endif
+// `ifdef USE_POWER_PINS
+// inout vccd1, vssd1,
+// `endif
+
+ input VDD,GND,
// BL
inout [7:0] BL,
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index f8a36a9..9252820 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -76,18 +76,26 @@
// User maskable interrupt signals
output [2:0] user_irq
+
);
+ wire vdd,gnd;
+
+ assign vdd = vccd1;
+ assign gnd = vssd1;
+
/*--------------------------------------*/
/* User project is instantiated here */
/*--------------------------------------*/
flash_array_8x8 u_flash_array_8x8(
-`ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
-`endif
+// `ifdef USE_POWER_PINS
+// .vccd1(vccd1),
+// .vssd1(vssd1),
+// `endif
+ .VDD(io_in[2]),
+ .GND(io_in[3]),
.BL(analog_io[7:0]),
.SSL(analog_io[9:8]),
.GSL(analog_io[11:10]),
