Changed PSUB name to VBPW and extended dnwell in subcells
diff --git a/gds/flash_array_8x8.gds b/gds/flash_array_8x8.gds
index 023c8b6..ac3bde7 100644
--- a/gds/flash_array_8x8.gds
+++ b/gds/flash_array_8x8.gds
Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
index 28a545c..fa8e036 100644
--- a/gds/user_project_wrapper.gds
+++ b/gds/user_project_wrapper.gds
Binary files differ
diff --git a/lef/flash_array_8x8.lef b/lef/flash_array_8x8.lef
index 4072aaa..5bf6676 100644
--- a/lef/flash_array_8x8.lef
+++ b/lef/flash_array_8x8.lef
@@ -6,8 +6,8 @@
CLASS BLOCK ;
FOREIGN flash_array_8x8 ;
ORIGIN 0.000 0.000 ;
- SIZE 11.275 BY 25.530 ;
- PIN PSUB
+ SIZE 11.145 BY 25.490 ;
+ PIN VBPW
ANTENNADIFFAREA 8.916200 ;
PORT
LAYER pwell ;
@@ -100,7 +100,7 @@
RECT 1.620 -9.440 1.910 -9.210 ;
RECT 8.870 -9.440 9.160 -9.210 ;
END
- END PSUB
+ END VBPW
PIN BL[0]
ANTENNAGATEAREA 0.126000 ;
ANTENNADIFFAREA 0.273000 ;
diff --git a/verilog/rtl/flash_array_8x8.v b/verilog/rtl/flash_array_8x8.v
index 960a575..4e46110 100644
--- a/verilog/rtl/flash_array_8x8.v
+++ b/verilog/rtl/flash_array_8x8.v
@@ -21,7 +21,7 @@
// SL
input SL,
- input PSUB,
+ input VBPW,
// senseamp
input sen1,
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 9252820..90ba693 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -102,7 +102,7 @@
.WL0(analog_io[15:12]),
.WL1(analog_io[19:16]),
.SL(analog_io[20]),
- .PSUB(analog_io[21]),
+ .VBPW(analog_io[21]),
.sen1(io_in[0]),
.sen2(io_in[1]),
