commit 36dffbe21689840e2e8947e6fe6cce88fd3dc81c
author BrandonOng22 <brandonong22@gmail.com> Thu Jan 27 09:44:03 2022 -0600
committer BrandonOng22 <brandonong22@gmail.com> Thu Jan 27 09:44:03 2022 -0600
tree a083f9f2ead29ed679a56c2b85ca6b8811fba908
parent 00b6cd05068491f5d34f1c52e99369462383a48f

Attempting to connect to power rails

lef/flash_array_8x8.lef

diff --git a/lef/flash_array_8x8.lef b/lef/flash_array_8x8.lef
index f21d35d..72203d3 100644
--- a/lef/flash_array_8x8.lef
+++ b/lef/flash_array_8x8.lef
@@ -575,7 +575,8 @@
     END
   END SSL[1]
   PIN GND
-    ANTENNADIFFAREA 4.680000 ;
+    DIRECTION INOUT ;
+    USE GROUND ;
     PORT
       LAYER li1 ;
         RECT 3.365 -13.965 3.535 -13.905 ;
@@ -666,7 +667,8 @@
     END
   END GND
   PIN VDD
-    ANTENNADIFFAREA 2.860800 ;
+    DIRECTION INOUT ;
+    USE POWER ;
     PORT
       LAYER nwell ;
         RECT 2.335 -19.565 8.455 -16.815 ;

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 2c6a08d..dde22c6 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -38,18 +38,18 @@
 	$script_dir/../../verilog/rtl/user_project_wrapper.v"
 
 ## Clock configurations
-# set ::env(CLOCK_PORT) "user_clock2"
+set ::env(CLOCK_PORT) ""
 # set ::env(CLOCK_NET) "mprj.clk"
 
 # set ::env(CLOCK_PERIOD) "10"
 
 ## Internal Macros
 ### Macro PDN Connections
-# set ::env(FP_PDN_MACRO_HOOKS) "\
-# 	u_flash_array_8x8 vccd1 vssd1"
+set ::env(FP_PDN_MACRO_HOOKS) "\
+	u_flash_array_8x8 vccd1 vssd1"
 
-set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
-set ::env(LVS_INSERT_POWER_PINS) 0
+# set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
+# set ::env(LVS_INSERT_POWER_PINS) 0
 
 
 ### Macro Placement

verilog/rtl/flash_array_8x8.v

diff --git a/verilog/rtl/flash_array_8x8.v b/verilog/rtl/flash_array_8x8.v
index 4e46110..9a423f7 100644
--- a/verilog/rtl/flash_array_8x8.v
+++ b/verilog/rtl/flash_array_8x8.v
@@ -6,7 +6,9 @@
 //     inout vccd1, vssd1,
 // `endif
 
-    input VDD,GND,
+    `ifdef USE_POWER_PINS
+        inout VDD,GND,
+    `endif
 
     // BL
     inout [7:0] BL,

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 90ba693..e297245 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -94,8 +94,11 @@
 //     .vssd1(vssd1),
 // `endif
 
-    .VDD(io_in[2]),
-    .GND(io_in[3]),
+    `ifdef USE_POWER_PINS
+    .VDD(vccd1),
+    .GND(vssd1),
+    `endif
+
     .BL(analog_io[7:0]),
     .SSL(analog_io[9:8]),
     .GSL(analog_io[11:10]),