Merge branch 'flash' into main
diff --git a/.github/scripts/build/run-set-id.sh b/.github/scripts/build/run-set-id.sh
index b6e9cfb..9cb87f8 100644
--- a/.github/scripts/build/run-set-id.sh
+++ b/.github/scripts/build/run-set-id.sh
@@ -24,7 +24,7 @@
cd $UPRJ_ROOT
# Install full version of caravel
-git clone https://github.com/efabless/caravel --branch develop --depth 1 $CARAVEL_ROOT
+git clone https://github.com/efabless/caravel --depth 1 $CARAVEL_ROOT
LOG_FILE=out.log
docker run -v $UPRJ_ROOT:$UPRJ_ROOT -v $PDK_ROOT:$PDK_ROOT -v $CARAVEL_ROOT:$CARAVEL_ROOT -e UPRJ_ROOT=$UPRJ_ROOT -e PDK_ROOT=$PDK_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME bash -c "cd $CARAVEL_ROOT; make uncompress; cd $UPRJ_ROOT; export USER_ID=$USER_ID; make set_user_id | tee $LOG_FILE;"
@@ -35,4 +35,4 @@
exit 2;
fi
-exit 0
\ No newline at end of file
+exit 0
diff --git a/.github/scripts/build/run-ship.sh b/.github/scripts/build/run-ship.sh
index 0217dbc..d084c00 100644
--- a/.github/scripts/build/run-ship.sh
+++ b/.github/scripts/build/run-ship.sh
@@ -23,9 +23,11 @@
cd $UPRJ_ROOT
# Install full version of caravel
-git clone https://github.com/efabless/caravel --branch develop --depth 1 $CARAVEL_ROOT
+git clone https://github.com/efabless/caravel --depth 1 $CARAVEL_ROOT
-docker run -v $UPRJ_ROOT:$UPRJ_ROOT -v $PDK_ROOT:$PDK_ROOT -v $CARAVEL_ROOT:$CARAVEL_ROOT -e UPRJ_ROOT=$UPRJ_ROOT -e PDK_ROOT=$PDK_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME bash -c "cd $CARAVEL_ROOT; make uncompress; cd $UPRJ_ROOT; make ship;"
+make install_mcw
+
+docker run -v $UPRJ_ROOT:$UPRJ_ROOT -v $PDK_ROOT:$PDK_ROOT -v $CARAVEL_ROOT:$CARAVEL_ROOT -e UPRJ_ROOT=$UPRJ_ROOT -e PDK_ROOT=$PDK_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME bash -c "cd $CARAVEL_ROOT; make uncompress; cd $UPRJ_ROOT; make -f $CARAVEL_ROOT/Makefile ship;"
SHIP_FILE=$UPRJ_ROOT/gds/caravel.gds
diff --git a/.github/workflows/auto_update_submodule.yml b/.github/workflows/auto_update_submodule.yml
deleted file mode 100644
index 7219ddf..0000000
--- a/.github/workflows/auto_update_submodule.yml
+++ /dev/null
@@ -1,41 +0,0 @@
-
-name: 'Auto-update Submodules'
-
-on:
- workflow_dispatch:
- schedule:
- - cron: "0 0 * * *"
-
-jobs:
- sync:
- name: 'Auto-update Submodules'
- runs-on: ubuntu-latest
-
- # Use the Bash shell regardless whether the GitHub Actions runner is ubuntu-latest, macos-latest, or windows-latest
- defaults:
- run:
- shell: bash
-
- steps:
- # Checkout the repository to the GitHub Actions runner
- - name: Checkout
- uses: actions/checkout@v2
- with:
- submodules: true
-
- # Git config
- - name: Git Configurations
- run: |
- git config --global user.name 'Git bot'
- git config --global user.email 'bot@noreply.github.com'
-
- # Update references
- - name: Git Sumbodule Update
- run: |
- git submodule update --init --recursive
- git submodule update --remote --recursive
-
- - name: Commit update
- run: |
- git remote set-url origin https://x-access-token:${{ secrets.GITHUB_TOKEN }}@github.com/${{ github.repository }}
- git commit -am "Auto updated submodule references" && git push || echo "No changes to commit"
diff --git a/.github/workflows/caravel_build.yml b/.github/workflows/caravel_build.yml
index c615662..3978d7f 100644
--- a/.github/workflows/caravel_build.yml
+++ b/.github/workflows/caravel_build.yml
@@ -13,8 +13,6 @@
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
@@ -25,19 +23,17 @@
- name: Install The PDK
run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/pdkBuild.sh
env:
- OPENLANE_TAG: 2021.09.16_03.28.21
+ OPENLANE_TAG: 2021.12.17_05.07.41
- name: Run make ship
run: bash ${GITHUB_WORKSPACE}/.github/scripts/build/run-ship.sh
env:
- OPENLANE_TAG: 2021.09.16_03.28.21
+ OPENLANE_TAG: 2021.12.17_05.07.41
set_user_id:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
@@ -59,8 +55,6 @@
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/user_project_ci.yml
index 5b8ea91..9196114 100644
--- a/.github/workflows/user_project_ci.yml
+++ b/.github/workflows/user_project_ci.yml
@@ -14,8 +14,6 @@
timeout-minutes: 720
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
@@ -34,8 +32,6 @@
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
@@ -53,8 +49,6 @@
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
@@ -78,8 +72,6 @@
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
@@ -97,4 +89,4 @@
- name: Run DV tests
# Run test number 0,1,2,3,4 in one job <test-ids> <sim-mode>
- run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/run-dv-wrapper.sh 0,1,2,3,4 GL
\ No newline at end of file
+ run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/run-dv-wrapper.sh 0,1,2,3,4 GL
diff --git a/.gitmodules b/.gitmodules
deleted file mode 100644
index c73b442..0000000
--- a/.gitmodules
+++ /dev/null
@@ -1,3 +0,0 @@
-[submodule "caravel-lite"]
- path = caravel
- url = https://github.com/efabless/caravel-lite
diff --git a/Makefile b/Makefile
index 188e997..9fc63bd 100644
--- a/Makefile
+++ b/Makefile
@@ -24,15 +24,13 @@
ifeq ($(CARAVEL_LITE),1)
CARAVEL_NAME := caravel-lite
CARAVEL_REPO := https://github.com/efabless/caravel-lite
- CARAVEL_BRANCH := main
+ CARAVEL_TAG := 'rc-8'
else
CARAVEL_NAME := caravel
CARAVEL_REPO := https://github.com/efabless/caravel
- CARAVEL_BRANCH := master
+ CARAVEL_TAG := 'rc-8'
endif
-# Install caravel as submodule, (1): submodule, (0): clone
-SUBMODULE?=1
# Include Caravel Makefile Targets
.PHONY: % : check-caravel
@@ -72,19 +70,8 @@
# Install caravel
.PHONY: install
install:
-ifeq ($(SUBMODULE),1)
- @echo "Installing $(CARAVEL_NAME) as a submodule.."
-# Convert CARAVEL_ROOT to relative path because .gitmodules doesn't accept '/'
- $(eval CARAVEL_PATH := $(shell realpath --relative-to=$(shell pwd) $(CARAVEL_ROOT)))
- @if [ ! -d $(CARAVEL_ROOT) ]; then git submodule add --name $(CARAVEL_NAME) $(CARAVEL_REPO) $(CARAVEL_PATH); fi
- @git submodule update --init
- @cd $(CARAVEL_ROOT); git checkout $(CARAVEL_BRANCH)
- $(MAKE) simlink
-else
@echo "Installing $(CARAVEL_NAME).."
- @git clone $(CARAVEL_REPO) $(CARAVEL_ROOT)
- @cd $(CARAVEL_ROOT); git checkout $(CARAVEL_BRANCH)
-endif
+ @git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT)
# Create symbolic links to caravel's main files
.PHONY: simlink
@@ -102,30 +89,12 @@
# Update Caravel
.PHONY: update_caravel
update_caravel: check-caravel
-ifeq ($(SUBMODULE),1)
- @git submodule update --init --recursive
- cd $(CARAVEL_ROOT) && \
- git checkout $(CARAVEL_BRANCH) && \
- git pull
-else
- cd $(CARAVEL_ROOT)/ && \
- git checkout $(CARAVEL_BRANCH) && \
- git pull
-endif
+ cd $(CARAVEL_ROOT)/ && git checkout $(CARAVEL_TAG) && git pull
# Uninstall Caravel
.PHONY: uninstall
uninstall:
-ifeq ($(SUBMODULE),1)
- git config -f .gitmodules --remove-section "submodule.$(CARAVEL_NAME)"
- git add .gitmodules
- git submodule deinit -f $(CARAVEL_ROOT)
- git rm --cached $(CARAVEL_ROOT)
- rm -rf .git/modules/$(CARAVEL_NAME)
rm -rf $(CARAVEL_ROOT)
-else
- rm -rf $(CARAVEL_ROOT)
-endif
# Install Openlane
.PHONY: openlane
diff --git a/caravel b/caravel
index 0f16ba8..793bf63 160000
--- a/caravel
+++ b/caravel
@@ -1 +1 @@
-Subproject commit 0f16ba8eaae841a6f122fc0d5837005d3312fd2b
+Subproject commit 793bf634c2c1b1af90be95fcd85688e869bfb667
diff --git a/docs/source/_static/empty.png b/docs/source/_static/empty.png
new file mode 100644
index 0000000..4b7ae67
--- /dev/null
+++ b/docs/source/_static/empty.png
Binary files differ
diff --git a/docs/source/_static/layout.png b/docs/source/_static/layout.png
new file mode 100644
index 0000000..71ffad0
--- /dev/null
+++ b/docs/source/_static/layout.png
Binary files differ
diff --git a/docs/source/_static/option1.png b/docs/source/_static/option1.png
new file mode 100644
index 0000000..a88350b
--- /dev/null
+++ b/docs/source/_static/option1.png
Binary files differ
diff --git a/docs/source/_static/option2.png b/docs/source/_static/option2.png
new file mode 100644
index 0000000..5c604d6
--- /dev/null
+++ b/docs/source/_static/option2.png
Binary files differ
diff --git a/docs/source/_static/option3.png b/docs/source/_static/option3.png
new file mode 100644
index 0000000..7e346b3
--- /dev/null
+++ b/docs/source/_static/option3.png
Binary files differ
diff --git a/docs/source/_static/pitch.png b/docs/source/_static/pitch.png
new file mode 100644
index 0000000..2efc7a9
--- /dev/null
+++ b/docs/source/_static/pitch.png
Binary files differ
diff --git a/docs/source/index.rst b/docs/source/index.rst
index fa3f806..15a0a03 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -32,10 +32,12 @@
- `Repo Integration <#repo-integration>`__
- `Verilog Integration <#verilog-integration>`__
+ - `Layout Integration <#layout-integration>`__
- `Running Full Chip Simulation <#running-full-chip-simulation>`__
-- `Hardening the User Project Macro using
- Openlane <#hardening-the-user-project-macro-using-openlane>`__
+- `User Project Wrapper Requirements <#user-project-wrapper-requirements>`__
+- `Hardening the User Project using
+ Openlane <#hardening-the-user-project-using-openlane>`__
- `Checklist for Open-MPW
Submission <#checklist-for-open-mpw-submission>`__
@@ -101,7 +103,7 @@
Caravel files are kept separate from the user project by having caravel
as submodule. The submodule commit should point to the latest of
-caravel/caravel-lite master. The following files should have a symbolic
+caravel/caravel-lite master/main branch. The following files should have a symbolic
link to `caravel's <https://github.com/efabless/caravel.git>`__
corresponding files:
@@ -154,6 +156,21 @@
</p>
+
+Layout Integration
+-------------------
+
+The caravel layout is pre-designed with an empty golden wrapper in the user space. You only need to provide us with a valid ``user_project_wrapper`` GDS file. And, as part of the tapeout process, your hardened ``user_project_wrapper`` will be inserted into a vanilla caravel layout to get the final layout shipped for fabrication.
+
+.. raw:: html
+
+ <p align="center">
+ <img src="./_static/layout.png" width="80%" height="80%">
+ </p>
+
+To make sure that this integration process goes smoothly without having any DRC or LVS issues, your hardened ``user_project_wrapper`` must adhere to a number of requirements listed at `User Project Wrapper Requirements <#user-project-wrapper-requirements>`__ .
+
+
Building the PDK
================
@@ -162,7 +179,7 @@
- Build the pdk natively.
Make sure you have `Magic VLSI Layout Tool <http://opencircuitdesign.com/magic/index.html>`__ installed on your machine before building the pdk.
-The pdk build is tested with magic version `8.3.209`.
+The pdk build is tested with magic version ``8.3.209``.
.. code:: bash
@@ -199,7 +216,7 @@
This will pull a docker image with the needed tools installed.
-Then, run the RTL and GL simulation by
+Then, run the RTL simulation by
.. code:: bash
@@ -207,16 +224,69 @@
export CARAVEL_ROOT=$(pwd)/caravel
# specify simulation mode: RTL/GL
export SIM=RTL
- # Run IO ports testbench, make verify-io_ports
- make verify-<dv-pattern>
+ # Run RTL simulation on IO ports testbench, make verify-io_ports
+ make verify-<testbench-name>
-The verilog test-benches are under this directory
-`verilog/dv <https://github.com/efabless/caravel_user_project/tree/main/verilog/dv>`__. For more information on setting up the
+Once you have the physical implementation done and you have the gate-level netlists ready, it is crucial to run full gate-level simulations to make sure that your design works as intended after running the physical implementation.
+
+Run the gate-level simulation by:
+
+.. code:: bash
+
+ export PDK_ROOT=<pdk-installation-path>
+ export CARAVEL_ROOT=$(pwd)/caravel
+ # specify simulation mode: RTL/GL
+ export SIM=GL
+ # Run RTL simulation on IO ports testbench, make verify-io_ports
+ make verify-<testbench-name>
+
+
+This sample project comes with four example testbenches to test the IO port connection, wishbone interface, and logic analyzer. The test-benches are under the
+`verilog/dv <https://github.com/efabless/caravel_user_project/tree/main/verilog/dv>`__ directory. For more information on setting up the
simulation environment and the available testbenches for this sample
project, refer to `README <https://github.com/efabless/caravel_user_project/blob/main/verilog/dv/README.md>`__.
-Hardening the User Project Macro using Openlane
-===============================================
+
+User Project Wrapper Requirements
+=================================
+
+Your hardened ``user_project_wrapper`` must match the `golden user_project_wrapper <https://github.com/efabless/caravel/blob/master/gds/user_project_wrapper_empty.gds.gz>`__ in the following:
+
+- Area ``(2.920um x 3.520um)``
+- Top module name ``"user_project_wrapper"``
+- Pin Placement
+- Pin Sizes
+- Core Rings Width and Offset
+- PDN Vertical and Horizontal Straps Width
+
+
+.. raw:: html
+
+ <p align="center">
+ <img src="./_static/empty.png" width="40%" height="40%">
+ </p>
+
+
+These fixed configurations are specified `here <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl>`__ .
+
+However, you are allowed to change the following if you need to:
+
+- PDN Vertical and Horizontal Pitch & Offset
+
+.. raw:: html
+
+ <p align="center">
+ <img src="./_static/pitch.png" width="30%" height="30%">
+ </p>
+
+To make sure that you adhere to these requirements, we run an exclusive-or (XOR) check between your hardened ``user_project_wrapper`` GDS and the golden wrapper GDS after processing both layouts to include only the boundary (pins and core rings). This check is done as part of the `mpw-precheck <https://github.com/efabless/mpw_precheck>`__ tool.
+
+
+Hardening the User Project using OpenLane
+==========================================
+
+OpenLane Installation
+---------------------
You will need to install openlane by running the following
@@ -232,16 +302,45 @@
For detailed instructions on the openlane and the pdk installation refer
to
-`README <https://github.com/efabless/openlane/blob/master/README.md>`__.
+`README <https://github.com/The-OpenROAD-Project/OpenLane#setting-up-openlane>`__.
+
+Hardening Options
+-----------------
There are three options for hardening the user project macro using
openlane:
-1. Hardening the user macro, then embedding it in the wrapper
-2. Flattening the user macro with the wrapper.
-3. Placing multiple macros in the wrapper along with standard cells on the top level.
++--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
+| Option 1 | Option 2 | Option 3 |
++--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
+| Hardening the user macro(s) first, then inserting it in the | Flattening the user macro(s) with the | Placing multiple macros in the wrapper |
+| user project wrapper with no standard cells on the top level | user_project_wrapper | along with standard cells on the top level |
++==============================================================+============================================+============================================+
+| |pic1| | |pic2| | |pic3| |
+| | | |
++--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
+| ex: |link1| | | ex: |link2| |
++--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
-For more details on hardening the user project macro using openlane, refer to `README <https://github.com/efabless/caravel/blob/master/openlane/README.rst>`__.
+.. |link1| replace:: `caravel_user_project <https://github.com/efabless/caravel_user_project>`__
+
+.. |link2| replace:: `caravel_ibex <https://github.com/efabless/caravel_ibex>`__
+
+
+.. |pic1| image:: ./_static/option1.png
+ :width: 48%
+
+.. |pic2| image:: ./_static/option2.png
+ :width: 140%
+
+.. |pic3| image:: ./_static/option3.png
+ :width: 72%
+
+For more details on hardening macros using openlane, refer to `README <https://github.com/The-OpenROAD-Project/OpenLane/blob/master/docs/source/hardening_macros.md>`__.
+
+
+Running OpenLane
+-----------------
For this sample project, we went for the first option where the user
macro is hardened first, then it is inserted in the user project
@@ -250,13 +349,13 @@
.. raw:: html
<p align="center">
- <img src="./_static/wrapper.png" width="50%" height="50%">
+ <img src="./_static/wrapper.png" width="30%" height="30%">
</p>
.. raw:: html
</p>
-
+
To reproduce hardening this project, run the following:
.. code:: bash
@@ -267,10 +366,12 @@
make user_project_wrapper
+For more information on the openlane flow, check `README <https://github.com/The-OpenROAD-Project/OpenLane#readme>`__.
+
Running MPW Precheck Locally
=================================
-You can install the precheck by running
+You can install the `mpw-precheck <https://github.com/efabless/mpw_precheck>`__ by running
.. code:: bash
@@ -353,6 +454,7 @@
- ✔️ Top level macro is named ``user_project_wrapper``.
- ✔️ Full Chip Simulation passes for RTL and GL (gate-level)
- ✔️ The hardened Macros are LVS and DRC clean
+- ✔️ The project contains a gate-level netlist for ``user_project_wrapper`` at verilog/gl/user_project_wrapper.v
- ✔️ The hardened ``user_project_wrapper`` adheres to the same pin
order specified at
`pin\_order <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/pin_order.cfg>`__
diff --git a/info.yaml b/info.yaml
deleted file mode 100644
index bdd53ba..0000000
--- a/info.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
----
-project:
- description: "A template SoC for Google sponsored Open MPW shuttles for SKY130."
- foundry: "SkyWater"
- git_url: "https://github.com/efabless/caravel_project_example.git"
- organization: "Efabless"
- organization_url: "http://efabless.com"
- owner: "Tim Edwards"
- process: "SKY130"
- project_name: "Caravel"
- project_id: "00000000"
- tags:
- - "Open MPW"
- - "Test Harness"
- category: "Test Harness"
- top_level_netlist: "caravel/verilog/gl/caravel.v"
- user_level_netlist: "verilog/gl/user_project_wrapper.v"
- version: "1.00"
- cover_image: "docs/source/_static/caravel_harness.png"
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
new file mode 100644
index 0000000..c3de8af
--- /dev/null
+++ b/openlane/user_proj_example/config.json
@@ -0,0 +1,21 @@
+{
+ "PDK" : "sky130A",
+ "STD_CELL_LIBRARY" : "sky130_fd_sc_hd",
+ "CARAVEL_ROOT" : "../../caravel",
+ "CLOCK_NET" : "counter.clk",
+ "CLOCK_PERIOD" : "10",
+ "CLOCK_PORT" : "wb_clk_i",
+ "DESIGN_IS_CORE" : "0",
+ "DESIGN_NAME" : "user_proj_example",
+ "DIE_AREA" : "0 0 900 600",
+ "DIODE_INSERTION_STRATEGY" : "4",
+ "FP_PIN_ORDER_CFG" : "pin_order.cfg",
+ "FP_SIZING" : "absolute",
+ "GLB_RT_MAXLAYER" : "5",
+ "GND_NETS" : "vssd1",
+ "PL_BASIC_PLACEMENT" : "1",
+ "PL_TARGET_DENSITY" : "0.05",
+ "RUN_CVC" : "1",
+ "VDD_NETS" : "vccd1",
+ "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v", "../../verilog/rtl/user_proj_example.v"]
+}
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 2aa188c..94af8ba 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -13,6 +13,9 @@
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) user_proj_example
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
new file mode 100644
index 0000000..d83d5bb
--- /dev/null
+++ b/openlane/user_project_wrapper/config.json
@@ -0,0 +1,58 @@
+{
+ "PDK" : "sky130A",
+ "STD_CELL_LIBRARY" : "sky130_fd_sc_hd",
+ "CARAVEL_ROOT" : "../../caravel",
+ "CLOCK_NET" : "mprj.clk",
+ "CLOCK_PERIOD" : "10",
+ "CLOCK_PORT" : "user_clock2",
+ "CLOCK_TREE_SYNTH" : "0",
+ "DESIGN_NAME" : "user_project_wrapper",
+ "DIE_AREA" : "0 0 2920 3520",
+ "DIODE_INSERTION_STRATEGY" : "0",
+ "EXTRA_GDS_FILES" : "../../gds/user_proj_example.gds",
+ "EXTRA_LEFS" : "../../lef/user_proj_example.lef",
+ "FILL_INSERTION" : "0",
+ "FP_IO_HEXTEND" : "4.8",
+ "FP_IO_HLENGTH" : "2.4",
+ "FP_IO_HTHICKNESS_MULT" : "4",
+ "FP_IO_VEXTEND" : "4.8",
+ "FP_IO_VLENGTH" : "2.4",
+ "FP_IO_VTHICKNESS_MULT" : "4",
+ "FP_PDN_CHECK_NODES" : "0",
+ "FP_PDN_CORE_RING" : "1",
+ "FP_PDN_CORE_RING_HOFFSET" : "14",
+ "FP_PDN_CORE_RING_HSPACING" : "1.7",
+ "FP_PDN_CORE_RING_HWIDTH" : "3.1",
+ "FP_PDN_CORE_RING_VOFFSET" : "14",
+ "FP_PDN_CORE_RING_VSPACING" : "1.7",
+ "FP_PDN_CORE_RING_VWIDTH" : "3.1",
+ "FP_PDN_ENABLE_RAILS" : "0",
+ "FP_PDN_HOFFSET" : "5",
+ "FP_PDN_HPITCH" : "180",
+ "FP_PDN_HSPACING" : "15.5",
+ "FP_PDN_HWIDTH" : "3.1",
+ "FP_PDN_MACRO_HOOKS" : "mprj vccd1 vssd1",
+ "FP_PDN_VOFFSET" : "5",
+ "FP_PDN_VPITCH" : "180",
+ "FP_PDN_VSPACING" : "15.5",
+ "FP_PDN_VWIDTH" : "3.1",
+ "FP_PIN_ORDER_CFG" : "../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg",
+ "FP_SIZING" : "absolute",
+ "GLB_RT_MAXLAYER" : "5",
+ "GND_NETS" : "vssd1 vssd2 vssa1 vssa2",
+ "MACRO_PLACEMENT_CFG" : "macro.cfg",
+ "MAGIC_ZEROIZE_ORIGIN" : "0",
+ "PL_RANDOM_GLB_PLACEMENT" : "1",
+ "PL_RESIZER_BUFFER_INPUT_PORTS" : "0",
+ "PL_RESIZER_BUFFER_OUTPUT_PORTS" : "0",
+ "PL_RESIZER_DESIGN_OPTIMIZATIONS" : "0",
+ "PL_RESIZER_TIMING_OPTIMIZATIONS" : "0",
+ "RUN_CVC" : "0",
+ "SYNTH_TOP_LEVEL" : "1",
+ "SYNTH_USE_PG_PINS_DEFINES" : "USE_POWER_PINS",
+ "TAP_DECAP_INSERTION" : "0",
+ "VDD_NETS" : "vccd1 vccd2 vdda1 vdda2",
+ "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_project_wrapper.v"],
+ "VERILOG_FILES_BLACKBOX" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_proj_example.v"]
+}
+
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index c81d316..2c6a08d 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -16,6 +16,9 @@
# Base Configurations. Don't Touch
# section begin
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+
# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
index 3a73b99..b0e4051 100644
--- a/verilog/dv/mprj_stimulus/Makefile
+++ b/verilog/dv/mprj_stimulus/Makefile
@@ -25,6 +25,11 @@
CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+## Management SoC Pointers
+MGMT_SOC_PATH ?= ../../../../caravel_pico
+MGMT_SOC_VERILOG_PATH = $(MGMT_SOC_PATH)/verilog
+MGMT_SOC_RTL_PATH = $(MGMT_SOC_PATH)/verilog/rtl
+
## User Project Pointers
UPRJ_VERILOG_PATH ?= ../../../verilog
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
@@ -50,12 +55,12 @@
ifeq ($(SIM),RTL)
iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(MGMT_SOC_RTL_PATH) \
$< -o $@
else
iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) -I $(MGMT_SOC_VERILOG_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
index e4d0a2d..7d2c29a 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus.c
@@ -31,19 +31,21 @@
// designed to read the project count through the
// logic analyzer probes.
// I/O 6 is configured for the UART Tx line
+
uint32_t testval;
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2
+ reg_hkspi_disable = 1; // Shut off the housekeeping SPI,
+ // so we can use the pins.
reg_mprj_datal = 0x00000000;
reg_mprj_datah = 0x00000000;
- reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;;
- reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;;
- reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
- reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
- reg_mprj_io_33 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
- reg_mprj_io_32 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
@@ -71,18 +73,13 @@
reg_mprj_io_9 = GPIO_MODE_USER_STD_OUT_MONITORED;
reg_mprj_io_8 = GPIO_MODE_USER_STD_OUT_MONITORED;
reg_mprj_io_7 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
-
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Set UART clock to 64 kbaud (enable before I/O configuration)
- reg_uart_clkdiv = 625;
- reg_uart_enable = 1;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUT_MONITORED;
/* Apply configuration */
reg_mprj_xfer = 1;
@@ -116,17 +113,24 @@
// Test ability to force data on channel 37
// NOTE: Only the low 6 bits of reg_mprj_datah are meaningful
- reg_mprj_datah = 0xffffffca;
+
+ reg_mprj_datah = 0x0f0f0fc0;
+ reg_mprj_datah = 0x00000000;
+ reg_mprj_datah = 0x0f0f0fca;
+ reg_mprj_datah = 0x0000000a;
+ reg_mprj_datah = 0x0f0f0fc0;
reg_mprj_datah = 0x00000000;
reg_mprj_datah = 0x0f0f0fc5;
- reg_mprj_datah = 0x00000000;
+ reg_mprj_datah = 0x00000005;
// Test ability to read back data generated by the user project
// on the "monitored" outputs. Read from the lower 16 bits and
// copy the value to the upper 16 bits.
testval = reg_mprj_datal;
- reg_mprj_datal = ((testval & 0xff8) << 9) & 0xffff0000;
+ reg_mprj_datal = (testval << 16);
+ testval = reg_mprj_datal;
+ reg_mprj_datal = (testval << 16);
// Flag end of the test
reg_mprj_datal = 0xAB510000;
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
index 1409015..0ac0b42 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
@@ -28,17 +28,8 @@
reg RSTB;
reg CSB;
reg power1, power2;
- reg power3, power4;
-
- wire HIGH;
- wire LOW;
- wire TRI;
- assign HIGH = 1'b1;
- assign LOW = 1'b0;
- assign TRI = 1'bz;
wire gpio;
- wire uart_tx;
wire [37:0] mprj_io;
wire [15:0] checkbits;
wire [3:0] status;
@@ -46,8 +37,10 @@
// Signals Assignment
assign checkbits = mprj_io[31:16];
assign status = mprj_io[35:32];
- assign uart_tx = mprj_io[6];
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // Force CSB high until simulation is underway
+ // Note: The CSB GPIO pin default needs to be set to a pull-up. . .
+ assign mprj_io[3] = CSB;
always #12.5 clock <= (clock === 1'b0);
@@ -74,23 +67,29 @@
$display("Monitor: mprj_stimulus test started");
wait(status == 4'ha);
wait(status == 4'h5);
- // Value 0009 reflects copying user-controlled outputs to memory and back
- // to management-controlled outputs.
- wait(checkbits == 16'h0009);
+
+ // Values reflect copying user-controlled outputs to memory and back
+ // to management-controlled outputs. Note that there is a slight
+ // discrepancy in timing when using gate level simulation; either
+ // of the specified values is okay.
+
+ wait(checkbits == 16'h0840 || checkbits == 16'h0841);
+ wait(checkbits == 16'h0a00 || checkbits == 16'h0a01);
+
wait(checkbits == 16'hAB51);
$display("Monitor: mprj_stimulus test Passed");
#10000;
$finish;
end
- // Reset Operation
+ // Reset Operation
initial begin
RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
+ CSB <= 1'b1;
#2000;
- RSTB <= 1'b1; // Release reset
- #170000;
- CSB = 1'b0; // CSB can be released
+ RSTB <= 1'b1; // Release reset
+ #200000;
+ CSB <= 1'bz; // Stop driving CSB
end
initial begin // Power-up sequence
@@ -148,10 +147,5 @@
.io3() // not used
);
- // Testbench UART
- tbuart tbuart (
- .ser_rx(uart_tx)
- );
-
endmodule
`default_nettype wire
