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/root/junga_soc_mpw5/Makefile
/root/junga_soc_mpw5/docs/Makefile
/root/junga_soc_mpw5/docs/environment.yml
/root/junga_soc_mpw5/docs/source/conf.py
/root/junga_soc_mpw5/docs/source/index.rst
/root/junga_soc_mpw5/docs/source/roundtrip.rst
/root/junga_soc_mpw5/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
/root/junga_soc_mpw5/openlane/user_proj/config.tcl
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/root/junga_soc_mpw5/openlane/user_proj/src/simpleuart.v
/root/junga_soc_mpw5/openlane/user_proj/src/soc.v
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/root/junga_soc_mpw5/openlane/user_proj/src/wb_hyper.v
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/root/junga_soc_mpw5/openlane/user_proj/src/wb_led.v
/root/junga_soc_mpw5/openlane/user_proj/src/wb_mux.v
/root/junga_soc_mpw5/openlane/user_proj/src/wb_openram_wrapper.v
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/root/junga_soc_mpw5/openlane/user_project_wrapper/src/user_project_wrapper.v
/root/junga_soc_mpw5/verilog/dv/Makefile
/root/junga_soc_mpw5/verilog/dv/io_ports/Makefile
/root/junga_soc_mpw5/verilog/dv/io_ports/io_ports.c
/root/junga_soc_mpw5/verilog/dv/io_ports/io_ports_tb.v
/root/junga_soc_mpw5/verilog/dv/la_test1/Makefile
/root/junga_soc_mpw5/verilog/dv/la_test1/la_test1.c
/root/junga_soc_mpw5/verilog/dv/la_test1/la_test1_tb.v
/root/junga_soc_mpw5/verilog/dv/la_test2/Makefile
/root/junga_soc_mpw5/verilog/dv/la_test2/la_test2.c
/root/junga_soc_mpw5/verilog/dv/la_test2/la_test2_tb.v
/root/junga_soc_mpw5/verilog/dv/mprj_stimulus/Makefile
/root/junga_soc_mpw5/verilog/dv/mprj_stimulus/mprj_stimulus.c
/root/junga_soc_mpw5/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
/root/junga_soc_mpw5/verilog/dv/wb_leds/Makefile
/root/junga_soc_mpw5/verilog/dv/wb_leds/wb_leds.c
/root/junga_soc_mpw5/verilog/dv/wb_leds/wb_leds.gtkw
/root/junga_soc_mpw5/verilog/dv/wb_leds/wb_leds_tb.v
/root/junga_soc_mpw5/verilog/dv/wb_port/Makefile
/root/junga_soc_mpw5/verilog/dv/wb_port/wb_port.c
/root/junga_soc_mpw5/verilog/dv/wb_port/wb_port_tb.v
/root/junga_soc_mpw5/verilog/dv/wb_sram/Makefile
/root/junga_soc_mpw5/verilog/dv/wb_sram/wb_sram.c
/root/junga_soc_mpw5/verilog/dv/wb_sram/wb_sram_tb.v
/root/junga_soc_mpw5/verilog/rtl/uprj_netlists.v