Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-005
/
slot-025
/
04542fc6a35a5c9ad98d4b31a0396fad0f5cada0
commit
04542fc6a35a5c9ad98d4b31a0396fad0f5cada0
[
log
]
[
tgz
]
author
roman3017 <rbacik@hotmail.com>
Mon Feb 21 15:38:13 2022 -0800
committer
roman3017 <rbacik@hotmail.com>
Mon Feb 21 20:46:12 2022 -0800
tree
7ecaf593996e1f3f05fbf1d6b66369fec26cbde7
parent
d0d0edd0e335d3347be5cf8816a0a4a9aa47eefc
[
diff
]
add sram test
.github/workflows/caravel_build.yml
[
diff
]
.github/workflows/user_project_ci.yml
[
diff
]
openlane/user_proj/src/ram_1w_1rs.v
[
diff
]
openlane/user_proj/src/wb_led.v
[
diff
]
openlane/user_proj/src/wb_openram_wrapper.v
[
diff
]
verilog/dv/Makefile
[
diff
]
verilog/dv/wb_leds/wb_leds.c
[
diff
]
verilog/dv/wb_leds/wb_leds_tb.v
[
diff
]
verilog/dv/wb_sram/Makefile
[Added -
diff
]
verilog/dv/wb_sram/wb_sram.c
[Added -
diff
]
verilog/dv/wb_sram/wb_sram_tb.v
[Added -
diff
]
11 files changed
tree: 7ecaf593996e1f3f05fbf1d6b66369fec26cbde7
.github/
def/
docs/
gds/
lef/
lib/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
.gitignore
LICENSE
Makefile
README.md
README.md
RISC-V SoC
Vexriscv based SoC
See:
README
README
