add sram test
diff --git a/.github/workflows/caravel_build.yml b/.github/workflows/caravel_build.yml index a967ca3..346dd6d 100644 --- a/.github/workflows/caravel_build.yml +++ b/.github/workflows/caravel_build.yml
@@ -9,28 +9,22 @@ runs-on: ubuntu-latest env: OPENLANE_ROOT: /home/runner/work/caravel_mpw/openlane - PDK_ROOT: /home/runner/work/caravel_mpw/openlane/pdks - CARAVEL_ROOT: /home/runner/work/caravel_mpw/caravel_mpw/caravel - OPENLANE_IMAGE_NAME: efabless/openlane:2021.11.23_01.42.34 - OPENLANE_TAG: 2021.11.23_01.42.34 - CARAVEL_TAG: mpw-5a - MAGIC_VERSION: 8.3.265 - MCW: PICO + PDK_ROOT: /home/runner/work/caravel_mpw/pdks + CARAVEL_ROOT: /home/runner/work/caravel_mpw/caravel_mpw/caravel-lite + OPENLANE_IMAGE_NAME: efabless/openlane:2021.11.25_01.26.14 steps: - uses: actions/checkout@v2 - name: debug run: | echo ${{ github.event_name }} - - name: install deps - run: bash .github/scripts/build/run-install-magic.sh - - name: install caravel - run: | - make install - make install_mcw - make openlane - make pdk-with-sram + - name: Install Magic + run: bash ${GITHUB_WORKSPACE}/.github/scripts/install_magic.sh + - name: Build PDK + run: bash ${GITHUB_WORKSPACE}/.github/scripts/build_pdk.sh + - name: Install MCW + run: make install_mcw MCW=PICO - name: uncompress - run: make uncompress + run: make uncompress - name: build user gds run: | bash .github/scripts/build/build-user.sh \ @@ -46,7 +40,10 @@ || bash .github/scripts/build/build-wrapper.sh \ || bash .github/scripts/build/build-wrapper.sh - name: compress - run: make compress + run: | + make uninstall + make uninstall_mcw + make compress - name: push #if: github.event_name == 'workflow_dispatch' run: |
diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/user_project_ci.yml index 69cdb8b..e67b681 100644 --- a/.github/workflows/user_project_ci.yml +++ b/.github/workflows/user_project_ci.yml
@@ -6,80 +6,38 @@ types: - completed jobs: - precheck0: + precheck: timeout-minutes: 720 runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - - name: Set up QEMU uses: docker/setup-qemu-action@v1 - - name: Set up Docker Buildx uses: docker/setup-buildx-action@v1 - - name: Install Magic run: bash ${GITHUB_WORKSPACE}/.github/scripts/install_magic.sh - - name: Build PDK run: bash ${GITHUB_WORKSPACE}/.github/scripts/build_pdk.sh - - name: Install The Precheck run: git clone --depth=1 https://github.com/efabless/mpw_precheck.git ${GITHUB_WORKSPACE}/mpw_precheck - - name: Run The Precheck run: bash ${GITHUB_WORKSPACE}/.github/scripts/run_precheck.sh - precheck: - if: ${{ github.event.workflow_run.conclusion == 'success' }} - runs-on: ubuntu-latest - env: - OPENLANE_ROOT: /home/runner/work/caravel_mpw/openlane - PDK_ROOT: /home/runner/work/caravel_mpw/openlane/pdks - CARAVEL_ROOT: /home/runner/work/caravel_mpw/caravel_mpw/caravel - PRECHECK_IMAGE_NAME: efabless/mpw_precheck:latest - OPENLANE_TAG: 2021.11.23_01.42.34 - CARAVEL_TAG: mpw-5a - MAGIC_VERSION: 8.3.265 - MCW: PICO - steps: - - uses: actions/checkout@v2 - - name: install deps - run: bash .github/scripts/build/run-install-magic.sh - - name: install caravel - run: | - make install - make install_mcw - make openlane - make pdk-with-sram - - name: Install The Precheck - run: bash .github/scripts/precheck/precheckBuild.sh 1 - - name: Sanitize The Precheck - run: | - gzip -d -f gds/* - - name: Run The Precheck - run: bash .github/scripts/precheck/run-precheck.sh dv_rtl: if: ${{ github.event.workflow_run.conclusion == 'success' }} runs-on: ubuntu-latest env: OPENLANE_ROOT: /home/runner/work/caravel_mpw/openlane - PDK_ROOT: /home/runner/work/caravel_mpw/openlane/pdks - CARAVEL_ROOT: /home/runner/work/caravel_mpw/caravel_mpw/caravel - OPENLANE_IMAGE_NAME: efabless/openlane:2021.11.23_01.42.34 - OPENLANE_TAG: 2021.11.23_01.42.34 - CARAVEL_TAG: mpw-5a - MAGIC_VERSION: 8.3.265 - MCW: PICO + PDK_ROOT: /home/runner/work/caravel_mpw/pdks + CARAVEL_ROOT: /home/runner/work/caravel_mpw/caravel_mpw/caravel-lite steps: - uses: actions/checkout@v2 - - name: install deps - run: bash .github/scripts/build/run-install-magic.sh - - name: install caravel - run: | - make install - make install_mcw - make openlane - make pdk-with-sram + - name: Install Magic + run: bash ${GITHUB_WORKSPACE}/.github/scripts/install_magic.sh + - name: Build PDK + run: bash ${GITHUB_WORKSPACE}/.github/scripts/build_pdk.sh + - name: Install MCW + run: make install_mcw MCW=PICO - name: Run DV tests # Run test number 0,1,2,3,4 in one job <test-ids> <sim-mode> run: bash .github/scripts/dv/run-dv-tests.sh 4 RTL @@ -88,23 +46,16 @@ runs-on: ubuntu-latest env: OPENLANE_ROOT: /home/runner/work/caravel_mpw/openlane - PDK_ROOT: /home/runner/work/caravel_mpw/openlane/pdks - CARAVEL_ROOT: /home/runner/work/caravel_mpw/caravel_mpw/caravel - OPENLANE_IMAGE_NAME: efabless/openlane:2021.11.23_01.42.34 - OPENLANE_TAG: 2021.11.23_01.42.34 - CARAVEL_TAG: mpw-5a - MAGIC_VERSION: 8.3.265 - MCW: PICO + PDK_ROOT: /home/runner/work/caravel_mpw/pdks + CARAVEL_ROOT: /home/runner/work/caravel_mpw/caravel_mpw/caravel-lite steps: - uses: actions/checkout@v2 - - name: install deps - run: bash .github/scripts/build/run-install-magic.sh - - name: install caravel - run: | - make install - make install_mcw - make openlane - make pdk-with-sram + - name: Install Magic + run: bash ${GITHUB_WORKSPACE}/.github/scripts/install_magic.sh + - name: Build PDK + run: bash ${GITHUB_WORKSPACE}/.github/scripts/build_pdk.sh + - name: Install MCW + run: make install_mcw MCW=PICO - name: Run DV tests # Run test number 0,1,2,3,4 in one job <test-ids> <sim-mode> run: bash .github/scripts/dv/run-dv-tests.sh 4 GL
diff --git a/openlane/user_proj/src/ram_1w_1rs.v b/openlane/user_proj/src/ram_1w_1rs.v index 869742a..e0dbe07 100644 --- a/openlane/user_proj/src/ram_1w_1rs.v +++ b/openlane/user_proj/src/ram_1w_1rs.v
@@ -40,12 +40,12 @@ .csb0 (~wr_en), .web0 (~wr_en), .wmask0 (wr_mask0), - .addr0 (wr_addr), + .addr0 (wr_addr[7:0]), .din0 (wr_data), .dout0 (), .clk1 (rd_clk), .csb1 (~rd_en), - .addr1 (rd_addr), + .addr1 (rd_addr[7:0]), .dout1 (rd_data) ); endmodule
diff --git a/openlane/user_proj/src/wb_led.v b/openlane/user_proj/src/wb_led.v index b7a6c11..898eb7d 100644 --- a/openlane/user_proj/src/wb_led.v +++ b/openlane/user_proj/src/wb_led.v
@@ -46,22 +46,16 @@ o_wb_ack <= 0; data <= 0; end else begin - // Wishbone interface logic o_wb_ack <= 1'b0; - if (i_wb_cyc && i_wb_stb && !o_wb_ack) begin + if (i_wb_cyc & i_wb_stb & ~o_wb_ack) begin o_wb_ack <= 1'b1; - - // Register read case (register_index) - wb_r_DATA: o_wb_dat <= data; + wb_r_DATA: begin + o_wb_dat <= data; + if (i_wb_we) + data <= i_wb_dat; + end endcase - - // Register write - if (i_wb_we) begin - case (register_index) - wb_r_DATA: data <= i_wb_dat; - endcase - end end end end
diff --git a/openlane/user_proj/src/wb_openram_wrapper.v b/openlane/user_proj/src/wb_openram_wrapper.v index 3b40509..6eae76d 100644 --- a/openlane/user_proj/src/wb_openram_wrapper.v +++ b/openlane/user_proj/src/wb_openram_wrapper.v
@@ -15,7 +15,7 @@ `default_nettype none -module wb_openram_wrapper1 +module wb_openram_wrapper #( parameter BASE_ADDR = 32'h3000_0000, parameter ADDR_WIDTH = 9 @@ -60,14 +60,14 @@ end end -assign ram_csb0 = ~wbs_stb_i; +assign ram_csb0 = ~(wbs_cyc_i & wbs_stb_i); assign ram_web0 = ~wbs_we_i; assign ram_wmask0 = wbs_sel_i; assign ram_addr0 = wbs_adr_i[ADDR_WIDTH-1:0]; endmodule // wb_openram_wrapper -module wb_openram_wrapper +module wb_openram_wrapper1 #( parameter BASE_ADDR = 32'h3000_0000, parameter ADDR_WIDTH = 9 @@ -95,8 +95,8 @@ output ram_web0, output [3:0] ram_wmask0, output [ADDR_WIDTH-1:0] ram_addr0, - input [31:0] ram_dout0, - output [31:0] ram_din0 + output [31:0] ram_din0, + input [31:0] ram_dout0 ); wire valid;
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 9483154..cad0de5 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = wb_leds +PATTERNS = wb_leds wb_sram all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/wb_leds/wb_leds.c b/verilog/dv/wb_leds/wb_leds.c index 6501e1e..1f2d70a 100644 --- a/verilog/dv/wb_leds/wb_leds.c +++ b/verilog/dv/wb_leds/wb_leds.c
@@ -26,12 +26,9 @@ */ #define reg_wb_leds (*(volatile uint32_t*)0x30fffd00) -#define reg_sram (*(volatile uint32_t*)0x30000000) -#define reg_sram1 (*(volatile uint32_t*)0x30001000) void main() { - /* IO Control Registers | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | @@ -51,44 +48,34 @@ /* Set up the housekeeping SPI to be connected internally so */ /* that external pin changes don't affect it. */ - reg_spimaster_config = 0xa002; // Enable, prescaler = 2, - // connect to housekeeping SPI + // reg_spi_enable = 1; + // reg_spimaster_cs = 0x10001; + // reg_spimaster_control = 0x0801; + + // reg_spimaster_control = 0xa002; // Enable, prescaler = 2, + // connect to housekeeping SPI + // Connect the housekeeping SPI to the SPI master // so that the CSB line is not left floating. This allows // all of the GPIO pins to be used for user functions. - reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;//led - reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;//led - reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;//led - reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;//led - reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;//led - reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;//led - reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;//led - reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;//led - reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;//trstb - //reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;//srstb - - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;//led + reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;//led + reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;//led + reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;//led + reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;//led + reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;//led + reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;//led + reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;//led + //reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;//trstb + //reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;//srstb /* Apply configuration */ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); - //reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64] - - // Flag start of the test - reg_mprj_datal = 0x00060000; - // set the led, signalling the end of the test + reg_wb_leds = 0xaa; reg_wb_leds = 0xff; - reg_sram = 0x01234567; - reg_sram1 = 0xdeadbeef; - - if (reg_wb_leds == 0xff && reg_sram == 0x01234567 && reg_sram1 == 0xdeadbeef) { - reg_mprj_datal = 0x00070000; - } else { - reg_mprj_datal = 0x00060000; - } } +
diff --git a/verilog/dv/wb_leds/wb_leds_tb.v b/verilog/dv/wb_leds/wb_leds_tb.v index 502d7d0..9300e0b 100644 --- a/verilog/dv/wb_leds/wb_leds_tb.v +++ b/verilog/dv/wb_leds/wb_leds_tb.v
@@ -31,12 +31,11 @@ wire gpio; wire [37:0] mprj_io; wire [7:0] led; - wire [2:0] checkbits; - assign checkbits = mprj_io[18:16]; assign led = mprj_io[32:25]; -// assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; + assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; + // assign mprj_io[3] = 1'b1; // External clock is used by default. Make this artificially fast for the // simulation. Normally this would be a slow clock and the digital PLL @@ -53,7 +52,7 @@ $dumpvars(0, wb_leds_tb); // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (30) begin + repeat (25) begin repeat (1000) @(posedge clock); // $display("+1000 cycles"); end @@ -68,19 +67,15 @@ end initial begin - wait(checkbits == 3'h6); - $display("Monitor: checkbits=6"); - // wait for leds to get set wait(led == 8'h00); $display("Monitor: LED=0x00"); - wait(led == 8'hff); - $display("Monitor: LED=0xff"); + wait(led == 8'haa); + $display("Monitor: LED=0xaa"); - wait(checkbits == 3'h7); - $display("Monitor: checkbits=7"); - +// wait(led == 8'hff); +// $display("Monitor: LED=0xff"); `ifdef GL $display("Monitor: Test 1 Mega-Project IO (GL) Passed"); `else @@ -114,7 +109,7 @@ end always @(mprj_io) begin - #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); + #1 $display("MPRJ-IO state = %b ", mprj_io[32:25]); end wire flash_csb;
diff --git a/verilog/dv/wb_sram/Makefile b/verilog/dv/wb_sram/Makefile new file mode 100644 index 0000000..40bce85 --- /dev/null +++ b/verilog/dv/wb_sram/Makefile
@@ -0,0 +1,98 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + +## PDK +PDK_PATH = $(PDK_ROOT)/sky130A + +## Caravel Pointers +CARAVEL_ROOT ?= ../../../caravel +CARAVEL_PATH ?= $(CARAVEL_ROOT) +CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel +CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog +CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl +CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel + +## User Project Pointers +UPRJ_VERILOG_PATH ?= ../../../verilog +UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl +UPRJ_BEHAVIOURAL_MODELS = ../ + +## RISCV GCC +GCC_PATH?=/usr/bin +GCC_PREFIX?=riscv64-unknown-elf + +## Simulation mode: RTL/GL +SIM_DEFINES = -DFUNCTIONAL -DSIM +SIM?=RTL + +.SUFFIXES: + +PATTERN = wb_sram + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex +ifeq ($(SIM),RTL) + iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ + -I ../../../mgmt_core_wrapper/verilog/rtl \ + -I ../../../openlane/user_proj/src \ + $< -o $@ +else + iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ + $< -o $@ +endif + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env + ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +check-env: +ifndef PDK_ROOT + $(error PDK_ROOT is undefined, please export it before running make) +endif +ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) + $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) +endif +ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) + $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) +endif +# check for efabless style installation +ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) +SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE +endif + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all
diff --git a/verilog/dv/wb_sram/wb_sram.c b/verilog/dv/wb_sram/wb_sram.c new file mode 100644 index 0000000..6867c82 --- /dev/null +++ b/verilog/dv/wb_sram/wb_sram.c
@@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +// This include is relative to $CARAVEL_PATH (see Makefile) +#include "verilog/dv/caravel/defs.h" +#include "verilog/dv/caravel/stub.c" + +/* + Wishbone Test: + - Configures MPRJ lower 8-IO pins as outputs + - Checks led value through the wishbone port +*/ + +#define reg_srom (*(volatile uint32_t*)0x30000000) +#define reg_sram (*(volatile uint32_t*)0x30001000) + +void main() +{ + + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + /* Set up the housekeeping SPI to be connected internally so */ + /* that external pin changes don't affect it. */ + + //reg_spimaster_config = 0xa002; // Enable, prescaler = 2, + // connect to housekeeping SPI + // Connect the housekeeping SPI to the SPI master + // so that the CSB line is not left floating. This allows + // all of the GPIO pins to be used for user functions. + + //reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;//trstb + //reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;//srstb + + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + // Flag start of the test + reg_mprj_datal = 0x00050000; + + // set the sram, signalling the end of the test + if (reg_sram != 0x01234567) + reg_sram = 0x01234567; + + if (reg_sram == 0x01234567) + reg_mprj_datal = 0x00060000; +/* + if (reg_srom != 0xdeadbeef) + reg_srom = 0xdeadbeef; + + if (reg_srom == 0xdeadbeef) + reg_mprj_datal = 0x00070000; +*/ +}
diff --git a/verilog/dv/wb_sram/wb_sram_tb.v b/verilog/dv/wb_sram/wb_sram_tb.v new file mode 100644 index 0000000..03c8586 --- /dev/null +++ b/verilog/dv/wb_sram/wb_sram_tb.v
@@ -0,0 +1,163 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`timescale 1 ns / 1 ps + +`include "uprj_netlists.v" +`include "caravel_netlists.v" +`include "spiflash.v" + +module wb_sram_tb; + reg clock; + reg RSTB; + reg CSB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + wire [2:0] checkbits; + + assign checkbits = mprj_io[18:16]; + + assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; + // assign mprj_io[3] = 1'b1; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + initial begin + $dumpfile("wb_sram.vcd"); + $dumpvars(0, wb_sram_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (25) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + `ifdef GL + $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed"); + `else + $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); + `endif + $display("%c[0m",27); + $finish; + end + + initial begin + wait(checkbits == 3'h5); + $display("Monitor: checkbits=5"); + + wait(checkbits == 3'h6); + $display("Monitor: checkbits=6"); + +// wait(checkbits == 3'h7); +// $display("Monitor: checkbits=7"); + + `ifdef GL + $display("Monitor: Test 1 Mega-Project IO (GL) Passed"); + `else + $display("Monitor: Test 1 Mega-Project IO (RTL) Passed"); + `endif + $finish; + end + + initial begin + RSTB <= 1'b0; + CSB <= 1'b1; // Force CSB high + #2000; + RSTB <= 1'b1; // Release reset + #170000; + CSB = 1'b0; // CSB can be released + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #100; + power1 <= 1'b1; + #100; + power2 <= 1'b1; + #100; + power3 <= 1'b1; + #100; + power4 <= 1'b1; + end + + always @(mprj_io) begin + #1 $display("MPRJ-IO state = %b ", mprj_io[18:16]); + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3 = power1; + wire VDD1V8 = power2; + wire USER_VDD3V3 = power3; + wire USER_VDD1V8 = power4; + wire VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("wb_sram.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule +`default_nettype wire