commit: 4b231fc78b0df6e04c6f9872b57f4456ab464bfd
[log] [tgz]
author: Git bot <bot@noreply.github.com>
Sat Dec 25 00:49:01 2021 +0000
committer: gatecat <gatecat@ds0.me>
Tue Dec 28 22:03:51 2021 +0000
tree: cf231f38c7f93c6f9767e6c9831dfcf46387596e
parent: 19eb8caf2e8df2f7e755d64bf9d2ffff484a8708 [diff]

Auto updated submodule references

caravel[diff]

1 file changed

tree: cf231f38c7f93c6f9767e6c9831dfcf46387596e

README.md

nMigen+Coriolis Test SoC

This is a submission of a test SoC for MPW4 built from https://github.com/ChipFlow/mpw4

It contains:

Minerva RV32IM CPU
512 bytes SRAM
(Q)SPI flash for code and data memory using spimemio from picosoc
HyperRAM for RAM extension using a derivative of litehyperbus
8-bit GPIO
UART, timer, and interrupt controller

Built using:

nMigen
Yosys+ABC
Coriolis for PnR; with PDKMaster and flexcell used in place of the standard sky130 cells.