qf105: harden-c configs
diff --git a/openlane/mkLanaiCPU/config.tcl b/openlane/mkLanaiCPU/config.tcl index a73a8f9..ddd69c0 100755 --- a/openlane/mkLanaiCPU/config.tcl +++ b/openlane/mkLanaiCPU/config.tcl
@@ -26,14 +26,14 @@ set ::env(CLOCK_PORT) "CLK" set ::env(CLOCK_NET) "CLK" -set ::env(CLOCK_PERIOD) "40" +set ::env(CLOCK_PERIOD) "25" set ::env(CLOCK_BUFFER_FANOUT) "8" set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" set ::env(CTS_SINK_CLUSTERING_SIZE) "16" set ::env(FP_SIZING) relative -set ::env(FP_CORE_UTIL) "25" +set ::env(FP_CORE_UTIL) "30" set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(FP_PDN_CORE_RING) 0 @@ -41,7 +41,7 @@ set ::env(SYNTH_STRATEGY) "AREA 0" set ::env(PL_BASIC_PLACEMENT) 0 -set ::env(PL_TARGET_DENSITY) 0.27 +set ::env(PL_TARGET_DENSITY) 0.35 set ::env(PL_TIME_DRIVEN) 1 #set ::env(PL_ROUTABILITY_DRIVEN) 1 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) "1"
diff --git a/openlane/mkLanaiFrontend/config.tcl b/openlane/mkLanaiFrontend/config.tcl new file mode 100755 index 0000000..cba6fa4 --- /dev/null +++ b/openlane/mkLanaiFrontend/config.tcl
@@ -0,0 +1,63 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +set ::env(PDK) "sky130A" +set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" + +set script_dir [file dirname [file normalize [info script]]] + +set ::env(DESIGN_NAME) mkLanaiFrontend + +set ::env(VERILOG_FILES) "\ + $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/mkLanaiFrontend.v" + +set ::env(DESIGN_IS_CORE) 0 + +set ::env(CLOCK_PORT) "CLK" +set ::env(CLOCK_NET) "CLK" +set ::env(CLOCK_PERIOD) "20" + +#set ::env(FP_SIZING) absolute +#set ::env(DIE_AREA) "0 0 500 300" + +set ::env(FP_SIZING) relative +set ::env(FP_CORE_UTIL) "30" + +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg + +set ::env(PL_BASIC_PLACEMENT) 0 +set ::env(PL_TARGET_DENSITY) 0.35 +#set ::env(PL_ROUTABILITY_DRIVEN) 1 +#set ::env(PL_SKIP_INITIAL_PLACEMENT) 1 +set ::env(SYNTH_STRATEGY) "DELAY 0" + +# Maximum layer used for routing is metal 4. +# This is because this macro will be inserted in a top level (user_project_wrapper) +# where the PDN is planned on metal 5. So, to avoid having shorts between routes +# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. +# +# set ::env(GLB_RT_MAXLAYER) 5 + +set ::env(RT_MAX_LAYER) {met4} + +# You can draw more power domains if you need to +set ::env(VDD_NETS) [list {vccd1}] +set ::env(GND_NETS) [list {vssd1}] + +set ::env(DIODE_INSERTION_STRATEGY) 4 +set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +# If you're going to use multiple power domains, then disable cvc run. +set ::env(RUN_CVC) 1
diff --git a/openlane/mkLanaiFrontend/pin_order.cfg b/openlane/mkLanaiFrontend/pin_order.cfg new file mode 100644 index 0000000..25b860d --- /dev/null +++ b/openlane/mkLanaiFrontend/pin_order.cfg
@@ -0,0 +1,15 @@ +#BUS_SORT + +#W +CLK +RST_N +cpu.* + +#S +.*core.* + +#N +.*ram.* + +#E +.*fmc.*
diff --git a/openlane/mkQF100Fabric/config.tcl b/openlane/mkQF100Fabric/config.tcl index 5430103..e675048 100755 --- a/openlane/mkQF100Fabric/config.tcl +++ b/openlane/mkQF100Fabric/config.tcl
@@ -31,7 +31,7 @@ set ::env(CLOCK_PERIOD) "20" set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 500 300" +set ::env(DIE_AREA) "0 0 800 300" #set ::env(FP_SIZING) relative #set ::env(FP_CORE_UTIL) "30"
diff --git a/openlane/mkQF100Fabric/pin_order.cfg b/openlane/mkQF100Fabric/pin_order.cfg index f4d4fee..ad6cfe3 100644 --- a/openlane/mkQF100Fabric/pin_order.cfg +++ b/openlane/mkQF100Fabric/pin_order.cfg
@@ -8,3 +8,4 @@ #N spi.* gpio.* +ksc.*
diff --git a/openlane/mkQF100FlashController/config.tcl b/openlane/mkQF100FlashController/config.tcl new file mode 100755 index 0000000..41c799e --- /dev/null +++ b/openlane/mkQF100FlashController/config.tcl
@@ -0,0 +1,63 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +set ::env(PDK) "sky130A" +set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" + +set script_dir [file dirname [file normalize [info script]]] + +set ::env(DESIGN_NAME) mkQF100FlashController + +set ::env(VERILOG_FILES) "\ + $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/mkQF100FlashController.v" + +set ::env(DESIGN_IS_CORE) 0 + +set ::env(CLOCK_PORT) "CLK" +set ::env(CLOCK_NET) "CLK" +set ::env(CLOCK_PERIOD) "20" + +#set ::env(FP_SIZING) absolute +#set ::env(DIE_AREA) "0 0 500 300" + +set ::env(FP_SIZING) relative +set ::env(FP_CORE_UTIL) "20" + +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg + +set ::env(PL_BASIC_PLACEMENT) 0 +set ::env(PL_TARGET_DENSITY) 0.25 +#set ::env(PL_ROUTABILITY_DRIVEN) 1 +#set ::env(PL_SKIP_INITIAL_PLACEMENT) 1 +set ::env(SYNTH_STRATEGY) "AREA 0" + +# Maximum layer used for routing is metal 4. +# This is because this macro will be inserted in a top level (user_project_wrapper) +# where the PDN is planned on metal 5. So, to avoid having shorts between routes +# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. +# +# set ::env(GLB_RT_MAXLAYER) 5 + +set ::env(RT_MAX_LAYER) {met4} + +# You can draw more power domains if you need to +set ::env(VDD_NETS) [list {vccd1}] +set ::env(GND_NETS) [list {vssd1}] + +set ::env(DIODE_INSERTION_STRATEGY) 4 +set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +# If you're going to use multiple power domains, then disable cvc run. +set ::env(RUN_CVC) 1
diff --git a/openlane/mkQF100FlashController/pin_order.cfg b/openlane/mkQF100FlashController/pin_order.cfg new file mode 100644 index 0000000..b3bbe60 --- /dev/null +++ b/openlane/mkQF100FlashController/pin_order.cfg
@@ -0,0 +1,12 @@ +#BUS_SORT + +#W +CLK +RST_N +spi.* + +#S +.*serverA.* + +#E +.*serverB.*
diff --git a/openlane/mkQF100KSC/config.tcl b/openlane/mkQF100KSC/config.tcl new file mode 100755 index 0000000..271c3e0 --- /dev/null +++ b/openlane/mkQF100KSC/config.tcl
@@ -0,0 +1,62 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +set ::env(PDK) "sky130A" +set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" + +set script_dir [file dirname [file normalize [info script]]] + +set ::env(DESIGN_NAME) mkQF100KSC + +set ::env(VERILOG_FILES) "\ + $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/mkQF100KSC.v" + +set ::env(DESIGN_IS_CORE) 0 + +set ::env(CLOCK_PORT) "CLK" +set ::env(CLOCK_NET) "CLK" +set ::env(CLOCK_PERIOD) "10" + +#set ::env(FP_SIZING) relative +#set ::env(FP_CORE_UTIL) "50" +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 200 250" + +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg + +set ::env(PL_BASIC_PLACEMENT) 0 +set ::env(PL_TARGET_DENSITY) 0.55 +#set ::env(PL_ROUTABILITY_DRIVEN) 1 +#set ::env(PL_SKIP_INITIAL_PLACEMENT) 1 +#set ::env(SYNTH_STRATEGY) "DELAY 1" + +# Maximum layer used for routing is metal 4. +# This is because this macro will be inserted in a top level (user_project_wrapper) +# where the PDN is planned on metal 5. So, to avoid having shorts between routes +# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. +# +# set ::env(GLB_RT_MAXLAYER) 5 + +set ::env(RT_MAX_LAYER) {met4} + +# You can draw more power domains if you need to +set ::env(VDD_NETS) [list {vccd1}] +set ::env(GND_NETS) [list {vssd1}] + +#set ::env(DIODE_INSERTION_STRATEGY) 2 +#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 2 +# If you're going to use multiple power domains, then disable cvc run. +set ::env(RUN_CVC) 1
diff --git a/openlane/mkQF100KSC/pin_order.cfg b/openlane/mkQF100KSC/pin_order.cfg new file mode 100644 index 0000000..0580837 --- /dev/null +++ b/openlane/mkQF100KSC/pin_order.cfg
@@ -0,0 +1,16 @@ +#BUS_SORT + +#S +CLK +RST_N +slave_cyc_.* +slave_stb_.* +slave_sel_.* +slave_ack_.* +slave_err_.* +slave_rty_.* +slave_adr_.* +slave_dat_.* + +#N +spiMaster_.*
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index fcb4c41..a907dda 100755 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -36,6 +36,7 @@ set ::env(VERILOG_FILES) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ $script_dir/../../verilog/rtl/user_project_wrapper.v \ + $script_dir/../../verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8_wrapper.v \ $script_dir/../../verilog/rtl/mkQF105.v" ## Clock configurations @@ -55,24 +56,33 @@ ### Black-box verilog and views set ::env(VERILOG_FILES_BLACKBOX) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ + $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \ $script_dir/../../verilog/rtl/mkLanaiCPU.v \ + $script_dir/../../verilog/rtl/mkLanaiFrontend.v \ $script_dir/../../verilog/rtl/mkQF100Fabric.v \ - $script_dir/../../verilog/rtl/mkQF100Memory.v \ + $script_dir/../../verilog/rtl/mkQF100FlashController.v \ $script_dir/../../verilog/rtl/mkQF100GPIO.v \ + $script_dir/../../verilog/rtl/mkQF100KSC.v \ $script_dir/../../verilog/rtl/mkQF100SPI.v" set ::env(EXTRA_LEFS) "\ + $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \ $script_dir/../../lef/mkLanaiCPU.lef \ + $script_dir/../../lef/mkLanaiFrontend.lef \ $script_dir/../../lef/mkQF100Fabric.lef \ - $script_dir/../../lef/mkQF100Memory.lef \ + $script_dir/../../lef/mkQF100FlashController.lef \ $script_dir/../../lef/mkQF100GPIO.lef \ + $script_dir/../../lef/mkQF100KSC.lef \ $script_dir/../../lef/mkQF100SPI.lef" set ::env(EXTRA_GDS_FILES) "\ + $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \ $script_dir/../../gds/mkLanaiCPU.gds \ + $script_dir/../../gds/mkLanaiFrontend.gds \ $script_dir/../../gds/mkQF100Fabric.gds \ - $script_dir/../../gds/mkQF100Memory.gds \ + $script_dir/../../gds/mkQF100FlashController.gds \ $script_dir/../../gds/mkQF100GPIO.gds \ + $script_dir/../../gds/mkQF100KSC.gds \ $script_dir/../../gds/mkQF100SPI.gds" # set ::env(GLB_RT_MAXLAYER) 5 @@ -82,7 +92,7 @@ # any issue with pdn connections will be flagged with LVS so it is not a critical check. set ::env(FP_PDN_CHECK_NODES) 0 -set ::env(PL_TARGET_DENSITY) "0.10" +set ::env(PL_TARGET_DENSITY) "0.05" # The following is because there are no std cells in the example wrapper project. #set ::env(SYNTH_TOP_LEVEL) 1 @@ -102,7 +112,7 @@ set ::env(CLOCK_PORT) "wb_clk_i" set ::env(CLOCK_NET) "wb_clk_i" -set ::env(CLOCK_PERIOD) "30" +set ::env(CLOCK_PERIOD) "20" set ::env(DECAP_CELL) "\ sky130_fd_sc_hd__decap_3 \
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index a61adab..dd197f0 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,5 +1,12 @@ -qf105.res_cpu 500 500 N # 962x973 -qf105.res_mem 500 1600 N # 348x359 -qf105.res_fabric 2000 500 N # 500x300 -qf105.res_spi 2000 1600 N # 200x250 -qf105.res_gpio 2400 1600 N # 200x250 +qf105.qf100_sram_core.inner 500 2800 N # 683x417 +qf105.qf100_qf100_frontend 500 2000 N # 273x283 +qf105.qf100_qf100_cpu 500 500 N # 840x851 + +qf105.qf100_qf100_fmc 1500 2600 N # 617x628 + +qf105.qf100_qf100_spiCtrl 2000 1600 N # 200x250 +qf105.qf100_qf100_fabric 2000 500 N # 800x300 + +qf105.qf100_qf100_ksCtrl 2300 1600 N # 200x250 + +qf105.qf100_qf100_gpioCtrl 2600 1600 N # 200x250