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foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-021 / 957638349c2b20e7fa991826342c34ed9e841f32 / verilog / dv / Makefile
  1. 0f93045 added includes directory by Marwan Abbas · 3 years, 1 month ago
  2. 51e6c1c cleanup by Marwan Abbas · 3 years, 1 month ago
  3. 96d63c5 litex integration iteration - only wb_port not working by Marwan Abbas · 3 years, 1 month ago
  4. 51a1096 initial commit to integrating litex tb with caravel_user_project mprj by Marwan Abbas · 3 years, 1 month ago
  5. 340cc4a Update full chip simulation to run from root by manarabdelaty · 3 years, 11 months ago
  6. b41301c Added top level makefile by manarabdelaty · 4 years ago
  7. 8dbabc1 Update DV Makefiles by manarabdelaty · 4 years ago
  8. 69bd326 Updated DV tests by manarabdelaty · 4 years ago[Renamed from verilog/dv/user_proj_example/Makefile]
  9. d4ec2f0 Example of a full run of user_project_wrapper by Ahmed Ghazy · 4 years ago