commit	c73d4bc516f3390b5fe970bd0b10841f762016f3	[log] [tgz]
author	Rameen Anwar <ramianwer1996@gmail.com>	Fri Mar 18 05:52:58 2022 -0700
committer	Rameen Anwar <ramianwer1996@gmail.com>	Fri Mar 18 05:52:58 2022 -0700
tree	f64789a14c3472f7e77cd13190bbcb112a74e3c6
parent	b11f954a531d1862f760dc8131e71eff07fabe13 [diff]

Added updated GDS without analog pins

gds/azadi_soc_top_caravel.gds.gz[diff]

1 file changed

tree: f64789a14c3472f7e77cd13190bbcb112a74e3c6

.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
sdc/
sdf/
signoff/
spef/
spi/
verilog/
.gitignore
LICENSE
Makefile
README.md

README.md

Azadi-III

Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, QSPI and timer.