commit	79a8347352831b86ce0fd36ace40a8d9f0cc197d	[log] [tgz]
author	Rameen Anwar <ramianwer1996@gmail.com>	Fri Mar 18 06:05:14 2022 -0700
committer	Rameen Anwar <ramianwer1996@gmail.com>	Fri Mar 18 06:05:14 2022 -0700
tree	2ae11d2dbad05c9d458e6e1dd477f8c461dd1a1e
parent	83b81260aaa86f7efbc1691d6c194552f4c77780 [diff]

Added uncompressed def file for Azadi SoC

def/azadi_soc_top_caravel.def[Added - diff]

1 file changed

tree: 2ae11d2dbad05c9d458e6e1dd477f8c461dd1a1e

.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
sdc/
sdf/
signoff/
spef/
spi/
verilog/
.gitignore
LICENSE
Makefile
README.md

README.md

Azadi-III

Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, QSPI and timer.