commit | 527bb1900fa9c3e7bae613366fcbfca739c5e6a0 | [log] [tgz] |
---|---|---|
author | Ryan Wans <37909218+ryanrocket@users.noreply.github.com> | Wed Jan 26 11:25:47 2022 -0500 |
committer | GitHub <noreply@github.com> | Wed Jan 26 11:25:47 2022 -0500 |
tree | 8b7eb10d5332875021571649621209f2434078e5 | |
parent | e0335e2d12b898838f5c718d6be3ef78cf50eca4 [diff] |
Update user_analog_proj_example.v
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v index 94412da..fedd7aa 100644 --- a/verilog/rtl/user_analog_proj_example.v +++ b/verilog/rtl/user_analog_proj_example.v
@@ -90,7 +90,7 @@ inout vssd2, // User area 2 digital ground `endif - // Wishbone Slave ports (WB MI A) + // Wishbone Follower ports (WB MI A) input wb_clk_i, input wb_rst_i, input wbs_stb_i,