Update user_analog_proj_example.v

verilog/rtl/user_analog_proj_example.v

diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v
index 94412da..fedd7aa 100644
--- a/verilog/rtl/user_analog_proj_example.v
+++ b/verilog/rtl/user_analog_proj_example.v
@@ -90,7 +90,7 @@
     inout vssd2,	// User area 2 digital ground
 `endif
 
-    // Wishbone Slave ports (WB MI A)
+    // Wishbone Follower ports (WB MI A)
     input wb_clk_i,
     input wb_rst_i,
     input wbs_stb_i,