New LVDT empty verilog file

verilog/rtl/LVDT.v

diff --git a/verilog/rtl/LVDT.v b/verilog/rtl/LVDT.v
index ea4046b..c6821e6 100644
--- a/verilog/rtl/LVDT.v
+++ b/verilog/rtl/LVDT.v
@@ -1,8 +1,8 @@
 module LVDT(
 
 `ifdef USE_POWER_PINS
-    inout vdda1,	
-    inout vssa1,	
+    inout vdd,	
+    inout vss,	
 `endif
 input Iin,
 input va,