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foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-018 / de2760e9e7a652b5e12debcdd00b0d1ba16b4353
commitde2760e9e7a652b5e12debcdd00b0d1ba16b4353[log] [tgz]
authorbaburaj2000 <88964390+baburaj2000@users.noreply.github.com>Sat Oct 23 06:53:57 2021 +0530
committerGitHub <noreply@github.com>Sat Oct 23 06:53:57 2021 +0530
tree633a785ea1cde7fb76cf9c7c0659950ac0d07002
parent5b43c7117436091b188dbc0f6f8937c0537f0923 [diff]
Update README.md
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tree: 633a785ea1cde7fb76cf9c7c0659950ac0d07002
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. caravel
  13. .gitmodules
  14. info.yaml
  15. LICENSE
  16. Makefile
  17. README.md
README.md

Caravel User Project

Table of contents

  • Overview
  • RTL Implementation
  • RTL Verification
  • ASIC Implementation

Overview

In this proposal, the entire GPS baseband functionality is realized using a combination of custom designed logic functionality GPS Engine (ASIC portion) and the on chip RISCV microprocessor to provide the complete position fix starting from the digitized IF input bits. The signal processing operations in the baseband comprise of dispreading and data demodulation performed on six identical channels followed by psuedo range, and position fix computation. The major part of the signal processing operations for the six channels are carried out in the GPS Engine and the low frequency control tasks and position fix computation tasks are carried out in the RISCV processor.

RTL Implementation

caravel_based_img

The Caravel user_proj_example.v has eight instanciation of GPS channel and a I2C Master . The GPS Channel < write the functionality of gps channel> and the I2C Master is used to configure the GPS RF Front End chipset .

The following block diagram shows the internal blocks of single gps channel gps_single_channel

  • wb_interface : Provides interface between 32-bit wiishbone bus and internal blocks . Through this wishbone interface , software can write and read memory mapped registers . The details of the wishbone registers is mentioned below .
  • adc2to3bit :
  • signmul_bhv :
  • clk_gen_gps_new :
  • signmag_twocomp :
  • codecontrollogic :
  • threshold :
  • threshold_ctl :
  • track_intganddump :

Wishbone Registers

image image

Pin Description

image

Verification Environment

The verification environment is shown in the following block diagram . A wishbone bus function model is used to create wishbone write and read transactions . tb_img