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commitafd64e30edfdb8436d7bab62c211ff403f5ffda6[log] [tgz]
authorbaburaj2000 <88964390+baburaj2000@users.noreply.github.com>Sat Oct 23 10:00:55 2021 +0530
committerGitHub <noreply@github.com>Sat Oct 23 10:00:55 2021 +0530
tree671f834eefee9cb041b891ecaaee6946e502f8cf
parent8bf1a9f0feb17df749b93b4a35a0737102648ba5 [diff]
Update README.md
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tree: 671f834eefee9cb041b891ecaaee6946e502f8cf
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. caravel
  13. .gitmodules
  14. info.yaml
  15. LICENSE
  16. Makefile
  17. README.md
README.md

GPS Baseband Chip

Table of contents

  • Overview
  • RTL Implementation
  • RTL Verification
  • ASIC Implementation

Overview

In this proposal, the entire GPS baseband functionality is realized using a combination of custom designed logic functionality GPS Engine (ASIC portion) and the on chip RISCV microprocessor to provide the complete position fix starting from the digitized IF input bits. The signal processing operations in the baseband comprise of dispreading and data demodulation performed on six identical channels followed by psuedo range, and position fix computation. The major part of the signal processing operations for the six channels are carried out in the GPS Engine and the low frequency control tasks and position fix computation tasks are carried out in the RISCV processor.

RTL Implementation

caravel_based_img

The Caravel user_proj_example.v has eight instanciation of GPS channel and a I2C Master . The GPS Channel < write the functionality of gps channel> and the I2C Master is used to configure the GPS RF Front End chipset .

The following block diagram shows the internal blocks of single gps channel gps_single_channel

  1. accumulator.v - 20 bit accumulator
  2. adc2to3bit.v - Two to three bit mapping of the input data
  3. clk_gen_gps_new.v - Module containing NCO for Carrier Generation and code clock generation
  4. codectrllogic.v- Topmost module for generation of three versions of Goldcodes (Early,Late,Prompt)
  5. codegen.v - Goldcode instantiation module
  6. goldcode.v- Goldcode generation module based on the Satellite ID
  7. gps_multichannel.v - Topmost Module containing 8 single channels and address decoding
  8. gps_single_channel.v - Single channel module containing all module instantiations and Wishbone Interface
  9. signmag_twocomp_vv.v - Sign Magnitude to Two's complement Conversion
  10. signmul.v - 3 bit Sign Magnitude Number multiplier
  11. thresh_control.v - Threshold check block to generate Carrier change pulse to invoke Doppler
  12. threshold.v - Threshold check block to check whether the satellite is acquired or not
  13. track_intganddump.v - Gold code multiplication with Integrate and dumping of 6 signals(3 - i and 3 - q)
  14. wb_interface.v - Provides interface between 32-bit wiishbone bus and internal blocks . Through this wishbone interface , software can write and read memory mapped registers . The details of the wishbone registers is mentioned below .

Wishbone Registers

image image

Pin Description

image

Verification Environment

The verification environment is shown in the following block diagram . A wishbone bus function model is used to create wishbone write and read transactions . The gps raw data is stored to a txt file and being used in the simulation environment .

tb_img

Test Case Description

The following test cases were created and used to verify the gps channel at block level and system level

  • wb_bfm_carrier_part_test :
  • wb_bfm_goldcode_test :

The testcase can be simulated by executing the following command

.. code:: bash

 cd verilog/dv/wb_bfm_goldcode_test/
 chmod +x verify_gold.sh
 ./verify_gold.sh

ASIC Implementation

The Physical implementation of single gps channel is carried out using openlane tool flow with the timing constraint of 50MHz .

user_proj_example gds