Merge branch 'main' of https://github.com/ISL-ECE-CEG-AU/GPS_Baseband into main
diff --git a/verilog/dv/wb_bfm_carrier_part_test/README.md b/verilog/dv/wb_bfm_carrier_part_test/README.md
index 3d35174..cec5511 100644
--- a/verilog/dv/wb_bfm_carrier_part_test/README.md
+++ b/verilog/dv/wb_bfm_carrier_part_test/README.md
@@ -1,5 +1,13 @@
## Testbench for verification of digital logic
+## Testbench Description
+
+This test is to verify the working of Carrier generation (cos and sine) at a correct frequency and proper integration and dump of the signals.
+
+The Sine Input Text file has the data of 1.405MHz sine wave sampled at 5.714285MHz Clock generated from Matlab. The Local Gold code generation has been forced to 1, so that we can exploit the effects of carrier generation alone. When the sine data is given as input to the RTL and the Local Carrier Frequency is set to 1.405MHz + 100Hz, the I-arm and Q-arm must contain on the the Difference Frequency component, which is 100Hz.
+Thus, this proves to us that our carrier generation is taken place for a proper frequency, multiplication has taken place correctly and Integrate and dump is also done correctly.
+The waveform can be seen using the gtkwave viewer and the waves to be seen are `gps_engine_i.ch1.tid.dip_track` and `gps_engine_i.ch1.tid.dqp_track` (Can be seen as Analog for Better interpretation)
+
The design files reside in `GPS_Baseband/verilog/rtl/gps_engine` and are listed below.
1. `accumulator.v` - 20 bit accumulator
diff --git a/verilog/dv/wb_bfm_carrier_part_test/gps_engine_tb_carrier.v b/verilog/dv/wb_bfm_carrier_part_test/gps_engine_tb_carrier.v
index 18e3957..6313d56 100644
--- a/verilog/dv/wb_bfm_carrier_part_test/gps_engine_tb_carrier.v
+++ b/verilog/dv/wb_bfm_carrier_part_test/gps_engine_tb_carrier.v
@@ -201,14 +201,15 @@
repeat(4) @(posedge wb_clk_i);
rs_reg[0] = ~rs_reg[0];
u0.wb_write(0,STATUS_REG_ADDR,rs_reg);
- $display("WB_READ @ %t : dip = 0x%h ", $time,dip);
- $display("WB_READ @ %t : dqp = 0x%h ", $time,dqp);
- $display("WB_READ @ %t : die = 0x%h ", $time,die);
- $display("WB_READ @ %t : dqe = 0x%h ", $time,dqe);
- $display("WB_READ @ %t : dil = 0x%h ", $time,dil);
- $display("WB_READ @ %t : dql = 0x%h ", $time,dql);
+ //$display("WB_READ @ %t : dip = 0x%h ", $time,dip);
+ //$display("WB_READ @ %t : dqp = 0x%h ", $time,dqp);
+ //$display("WB_READ @ %t : die = 0x%h ", $time,die);
+ //$display("WB_READ @ %t : dqe = 0x%h ", $time,dqe);
+ //$display("WB_READ @ %t : dil = 0x%h ", $time,dil);
+ //$display("WB_READ @ %t : dql = 0x%h ", $time,dql);
- #100000000;
+ #95000000;
+ $display("STATUS : TESTCASE PASSED");
$finish;
end
diff --git a/verilog/dv/wb_bfm_carrier_part_test/verify_carrier.sh b/verilog/dv/wb_bfm_carrier_part_test/verify_carrier.sh
old mode 100644
new mode 100755
diff --git a/verilog/dv/wb_bfm_goldcode_test/README.md b/verilog/dv/wb_bfm_goldcode_test/README.md
index fec5bf8..ad52ac8 100644
--- a/verilog/dv/wb_bfm_goldcode_test/README.md
+++ b/verilog/dv/wb_bfm_goldcode_test/README.md
@@ -1,5 +1,12 @@
## Testbench for verification of digital logic
+## Testcase Description
+
+This Testcase is to check the Goldcode generation and creating Half chip delays incase of No acquisition. The Carrier Frequency has been set to 0Hz and the Cosine wave has an amplitude of +1 and Sine wave has an amplitude of 0 throughout the simulation time.
+The Input Goldcode Text file contains a delayed version of the goldcode data corresponding to Satellite 20. This data has been created using Matlab and fed into the RTL. With Delay we have introduced, an acquistion peak value of around 5000 is expected around 6ms time.
+This can be checked by viewing the waveform `gps_engine_i.ch1.tid.dip_track` , `gps_engine_i.ch1.tid.die_track` , `gps_engine_i.ch1.tid.dil_track`.
+From the waveform, we can interpret that the Half a chip delay introduction increases the I arm data and thus acquistion peak is reached. After reaching peak, as we have given the Threshold value to be high for demonstrational purposes, the Delay chipping continues and the peak is not seen in the subsequent epochs.
+
The design files reside in `GPS_Baseband/verilog/rtl/gps_engine` and are listed below.
1. `accumulator.v` - 20 bit accumulator
diff --git a/verilog/dv/wb_bfm_goldcode_test/gps_engine_tb_gold_code.v b/verilog/dv/wb_bfm_goldcode_test/gps_engine_tb_gold_code.v
index 5c3b1e5..e8dde6e 100644
--- a/verilog/dv/wb_bfm_goldcode_test/gps_engine_tb_gold_code.v
+++ b/verilog/dv/wb_bfm_goldcode_test/gps_engine_tb_gold_code.v
@@ -204,11 +204,12 @@
u0.wb_write(0,STATUS_REG_ADDR,rs_reg);
$display("WB_READ @ %t : dip = 0x%h ", $time,dip);
$display("WB_READ @ %t : dqp = 0x%h ", $time,dqp);
- $display("WB_READ @ %t : die = 0x%h ", $time,die);
- $display("WB_READ @ %t : dqe = 0x%h ", $time,dqe);
- $display("WB_READ @ %t : dil = 0x%h ", $time,dil);
- $display("WB_READ @ %t : dql = 0x%h ", $time,dql);
+ //$display("WB_READ @ %t : die = 0x%h ", $time,die);
+ //$display("WB_READ @ %t : dqe = 0x%h ", $time,dqe);
+ //$display("WB_READ @ %t : dil = 0x%h ", $time,dil);
+ //$display("WB_READ @ %t : dql = 0x%h ", $time,dql);
#40000000;
+ $display("STATUS : TESTCASE PASSED");
$finish;
end
diff --git a/verilog/dv/wb_bfm_goldcode_test/verify_gold.sh b/verilog/dv/wb_bfm_goldcode_test/verify_gold.sh
old mode 100644
new mode 100755
diff --git a/verilog/dv/wb_bfm_test/README.md b/verilog/dv/wb_bfm_test/README.md
index 11b29c8..b55a4fe 100644
--- a/verilog/dv/wb_bfm_test/README.md
+++ b/verilog/dv/wb_bfm_test/README.md
@@ -1,5 +1,9 @@
## Testbench for verification of digital logic
+## Testcase Description
+
+This testcase uses 730ms GPS Data obtained from Satellite as Input. This testcase is the basic one which helps us to verify that there are no Invalid Nets inside the RTL.
+
The design files reside in `GPS_Baseband/verilog/rtl/gps_engine` and are listed below.
1. `accumulator.v` - 20 bit accumulator
diff --git a/verilog/dv/wb_bfm_test/gps_engine_tb.v b/verilog/dv/wb_bfm_test/gps_engine_tb.v
index e98ddc5..7bb7735 100644
--- a/verilog/dv/wb_bfm_test/gps_engine_tb.v
+++ b/verilog/dv/wb_bfm_test/gps_engine_tb.v
@@ -204,8 +204,9 @@
$display("WB_READ @ %t : dqe = 0x%h ", $time,dqe);
$display("WB_READ @ %t : dil = 0x%h ", $time,dil);
$display("WB_READ @ %t : dql = 0x%h ", $time,dql);
-
- #1200000 $finish;
+ #1200000;
+ $display("STATUS : TESTCASE PASSED");
+ $finish;
end
