buffers
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds index 4a541b7..b1f75a0 100644 --- a/gds/user_analog_project_wrapper.gds +++ b/gds/user_analog_project_wrapper.gds Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag index d4e18df..fabd439 100644 --- a/mag/user_analog_project_wrapper.mag +++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@ magic tech sky130A -timestamp 1642944651 +timestamp 1643022782 << locali >> rect 247445 329554 247576 329570 rect 247445 329454 247459 329554 @@ -1098,46 +1098,110 @@ rect -50 0 0 352000 rect 292000 0 292050 352000 rect -50 -50 292050 0 +use divbuf divbuf_19 +timestamp 1641017053 +transform 1 0 27511 0 1 45357 +box -460 -1085 31200 495 use filter filter_1 timestamp 1640983258 transform 1 0 38025 0 1 41313 box -1800 -11005 6240 390 +use divbuf divbuf_25 +timestamp 1641017053 +transform 1 0 237817 0 1 138431 +box -460 -1085 31200 495 +use divbuf divbuf_24 +timestamp 1641017053 +transform 1 0 237896 0 1 140897 +box -460 -1085 31200 495 +use divbuf divbuf_23 +timestamp 1641017053 +transform 1 0 237976 0 1 143283 +box -460 -1085 31200 495 use divider divider_0 -timestamp 1642911854 +timestamp 1643022782 transform 1 0 246803 0 1 129340 box -490 -235 4690 2150 -use pd pd_1 -timestamp 1642911854 -transform 1 0 43920 0 1 171288 +use divbuf divbuf_18 +timestamp 1641017053 +transform 1 0 30445 0 1 186973 +box -460 -1085 31200 495 +use divbuf divbuf_17 +timestamp 1641017053 +transform 1 0 30365 0 1 184587 +box -460 -1085 31200 495 +use divbuf divbuf_16 +timestamp 1641017053 +transform 1 0 30286 0 1 182121 +box -460 -1085 31200 495 +use divbuf divbuf_15 +timestamp 1641017053 +transform 1 0 30286 0 1 179927 +box -460 -1085 31200 495 +use pd pd_5 +timestamp 1643022782 +transform 1 0 38673 0 1 170517 box -215 -855 1685 810 -use divider divider_3 -timestamp 1642911854 -transform 1 0 31863 0 1 169542 -box -490 -235 4690 2150 use pd pd_4 -timestamp 1642911854 +timestamp 1643022782 transform 1 0 36668 0 1 222858 box -215 -855 1685 810 -use cp cp_0 -timestamp 1640911461 -transform 1 0 37991 0 1 261137 -box -415 -1715 4690 2035 +use divider divider_3 +timestamp 1643022782 +transform 1 0 31863 0 1 169542 +box -490 -235 4690 2150 +use divbuf divbuf_14 +timestamp 1641017053 +transform 1 0 31964 0 1 233669 +box -460 -1085 31200 495 +use divbuf divbuf_13 +timestamp 1641017053 +transform 1 0 31964 0 1 235863 +box -460 -1085 31200 495 +use divbuf divbuf_12 +timestamp 1641017053 +transform 1 0 32043 0 1 238329 +box -460 -1085 31200 495 +use divbuf divbuf_11 +timestamp 1641017053 +transform 1 0 32123 0 1 240715 +box -460 -1085 31200 495 +use divbuf divbuf_10 +timestamp 1641017053 +transform 1 0 28832 0 1 268030 +box -460 -1085 31200 495 +use divbuf divbuf_9 +timestamp 1641017053 +transform 1 0 28752 0 1 265644 +box -460 -1085 31200 495 +use divbuf divbuf_8 +timestamp 1641017053 +transform 1 0 28673 0 1 263178 +box -460 -1085 31200 495 +use divbuf divbuf_22 +timestamp 1641017053 +transform 1 0 234947 0 1 265819 +box -460 -1085 31200 495 +use divbuf divbuf_21 +timestamp 1641017053 +transform 1 0 234867 0 1 263433 +box -460 -1085 31200 495 +use divbuf divbuf_20 +timestamp 1641017053 +transform 1 0 234788 0 1 260967 +box -460 -1085 31200 495 use ro_complete ro_complete_0 -timestamp 1642943789 +timestamp 1643022782 transform -1 0 245567 0 -1 235887 box -57 -5330 4455 1440 use divider divider_2 -timestamp 1642911854 +timestamp 1643022782 transform 1 0 260331 0 1 239350 box -490 -235 4690 2150 use pll_full pll_full_1 -timestamp 1642911854 +timestamp 1643022782 transform 1 0 31292 0 1 318138 box -5415 -2690 26430 12835 -use ro_complete ro_complete_1 -timestamp 1642943789 -transform 1 0 247313 0 1 328719 -box -57 -5330 4455 1440 use divbuf divbuf_7 timestamp 1641017053 transform 1 0 245779 0 1 306691 @@ -1170,6 +1234,14 @@ timestamp 1641017053 transform 1 0 244347 0 1 337471 box -460 -1085 31200 495 +use ro_complete ro_complete_1 +timestamp 1643022782 +transform 1 0 247313 0 1 328719 +box -57 -5330 4455 1440 +use cp cp_0 +timestamp 1640911461 +transform 1 0 21911 0 1 264642 +box -415 -1715 4690 2035 << labels >> flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0] port 0 nsew signal bidirectional
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice index 2d7071c..9ea1472 100644 --- a/netgen/user_analog_project_wrapper.spice +++ b/netgen/user_analog_project_wrapper.spice
@@ -106,1604 +106,1856 @@ + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] + wbs_stb_i wbs_we_i -C0 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C1 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C2 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C3 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF -C4 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.32fF -C5 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C6 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF -C7 divider_1/tspc_0/Q divider_1/tspc_1/Z3 0.45fF -C8 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a4 0.12fF -C9 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF -C10 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF -C11 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF -C12 divider_1/tspc_2/Z3 divider_1/Out 0.05fF -C13 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF -C14 divider_2/tspc_0/Z2 divider_2/prescaler_0/Out 0.11fF -C15 divider_2/and_0/OUT divider_2/prescaler_0/tspc_0/Q 0.04fF -C16 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF -C17 divider_2/nor_0/Z1 gnd 0.01fF -C18 io_clamp_high[2] io_analog[6] 0.53fF -C19 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF -C20 divider_1/nor_0/Z1 divider_1/nor_1/B 0.18fF -C21 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF -C22 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z4 0.14fF -C23 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF -C24 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C25 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C26 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF -C27 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF -C28 gnd pll_full_0/divider_0/tspc_0/Z2 0.16fF -C29 divider_2/nor_1/A divider_2/and_0/A 0.01fF -C30 divider_2/nor_1/Z1 divider_2/nor_1/B 0.06fF -C31 divider_1/tspc_0/Z2 divider_1/prescaler_0/Out 0.11fF -C32 divider_1/tspc_0/Z1 divider_1/nor_1/A 0.03fF -C33 divider_1/prescaler_0/tspc_1/Z4 divider_1/prescaler_0/tspc_2/a_740_n680# 0.01fF -C34 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF -C35 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF -C36 divider_2/nor_1/B divider_2/tspc_1/Z2 0.30fF -C37 divider_2/tspc_0/Z3 divider_2/tspc_0/Q 0.05fF -C38 divider_1/and_0/A divider_1/and_0/B 0.18fF -C39 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF -C40 divider_2/tspc_2/a_630_n680# divider_2/nor_0/B 0.35fF -C41 divider_0/tspc_0/a_630_n680# gnd 0.62fF -C42 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF -C43 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C44 divider_1/prescaler_0/nand_1/z1 gnd 0.16fF -C45 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF -C46 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z2 0.01fF -C47 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF -C48 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF -C49 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF -C50 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF -C51 pd_1/tspc_r_1/Qbar pd_1/tspc_r_1/Qbar1 0.01fF -C52 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF -C53 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/A 0.35fF -C54 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C55 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C56 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C57 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF -C58 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF -C59 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF -C60 divider_2/tspc_1/Z2 divider_2/tspc_1/a_630_n680# 0.01fF -C61 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF -C62 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF -C63 divider_1/and_0/Z1 gnd 0.41fF -C64 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF -C65 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF -C66 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF -C67 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF -C68 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF -C69 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C70 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/Out 0.08fF -C71 pll_full_0/divider_0/nor_1/A gnd 1.05fF -C72 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF -C73 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF -C74 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF -C75 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/DIV 0.19fF -C76 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF -C77 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/switch_5/vin 0.20fF -C78 divider_1/and_0/OUT gnd 0.28fF -C79 divider_1/nor_1/Z1 gnd 0.01fF -C80 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C81 divider_2/prescaler_0/tspc_0/D gnd 0.05fF -C82 divider_0/nor_1/B divider_0/and_0/B 0.31fF -C83 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF -C84 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF -C85 pd_0/R pd_0/and_pd_0/Out1 0.33fF -C86 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF -C87 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF -C88 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF -C89 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF -C90 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C91 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C92 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/v 1.30fF -C93 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.64fF -C94 divider_2/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF -C95 divider_1/tspc_0/Z3 gnd 0.27fF -C96 divbuf_6/OUT4 divbuf_6/OUT 1.11fF -C97 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C98 divider_2/and_0/out1 gnd 0.23fF -C99 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF -C100 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/Z1 1.07fF -C101 divider_1/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.01fF -C102 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.01fF -C103 divider_0/and_0/OUT divider_0/clk 0.04fF -C104 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF -C105 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C106 divider_1/nor_1/A divider_1/tspc_0/Z3 0.38fF -C107 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF -C108 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF -C109 divbuf_0/OUT5 divbuf_0/OUT 43.38fF -C110 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF -C111 divider_2/nor_1/B divider_2/tspc_1/Z4 0.21fF -C112 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF -C113 ro_complete_1/a0 ro_complete_1/cbank_2/switch_5/vin 0.09fF -C114 divider_0/and_0/OUT gnd 0.28fF -C115 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C116 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF -C117 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF -C118 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF -C119 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF -C120 divider_1/nor_0/Z1 divider_1/and_0/B 0.78fF -C121 cp_0/a_1710_0# cp_0/down 0.32fF -C122 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF -C123 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Z1 0.02fF -C124 pd_1/REF pd_1/tspc_r_1/Qbar1 0.12fF -C125 pll_full_0/divider_0/tspc_1/Z2 gnd 0.16fF -C126 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF -C127 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF -C128 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF -C129 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF -C130 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF -C131 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF -C132 divider_2/and_0/B divider_2/and_0/Z1 0.07fF -C133 divider_1/prescaler_0/tspc_0/Z3 gnd 0.27fF -C134 pd_0/R pd_0/tspc_r_1/Z2 0.21fF -C135 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF -C136 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C137 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF -C138 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF -C139 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF -C140 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF -C141 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C142 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.04fF -C143 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF -C144 ro_complete_1/a4 ro_complete_1/cbank_1/v 0.05fF -C145 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C146 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF -C147 io_clamp_low[1] io_analog[5] 0.53fF -C148 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF -C149 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF -C150 divider_1/tspc_1/Z2 gnd 0.16fF -C151 divider_2/tspc_2/a_630_n680# gnd 0.61fF -C152 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF -C153 pd_1/DOWN pd_1/tspc_r_1/Qbar 0.02fF -C154 pd_0/UP pd_0/and_pd_0/Z1 0.06fF -C155 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C156 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.61fF -C157 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF -C158 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF -C159 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Q 0.20fF -C160 divider_1/tspc_1/Z2 divider_1/nor_1/A 0.15fF -C161 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF -C162 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF -C163 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF -C164 divider_2/nor_1/B divider_2/tspc_1/Q 0.51fF -C165 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF -C166 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF -C167 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF -C168 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF -C169 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF -C170 divider_1/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF -C171 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF -C172 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF -C173 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C174 divider_0/nor_1/B divider_0/tspc_0/a_630_n680# 0.01fF -C175 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF -C176 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF -C177 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF -C178 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/Out 0.12fF -C179 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C180 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C181 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF -C182 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF -C183 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF -C184 divider_0/tspc_2/Z3 divider_0/Out 0.05fF -C185 divbuf_0/OUT5 divbuf_0/IN 0.00fF -C186 divbuf_0/OUT2 divbuf_0/OUT3 1.37fF -C187 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C188 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Z3 0.03fF -C189 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF -C190 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.03fF -C191 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF -C192 divider_2/tspc_1/Q divider_2/tspc_1/a_630_n680# 0.04fF -C193 divider_2/mc2 divider_2/nor_0/B 0.15fF -C194 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF -C195 divbuf_4/IN divbuf_4/OUT5 0.00fF -C196 ro_complete_1/cbank_1/v ro_complete_1/cbank_2/v 1.36fF -C197 divider_2/and_0/out1 divider_2/and_0/A 0.01fF -C198 divider_1/tspc_0/Z2 gnd 0.16fF -C199 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_1/A 0.01fF -C200 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C201 divider_2/prescaler_0/tspc_1/Z3 gnd 0.27fF -C202 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF -C203 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF -C204 pd_1/UP pd_1/and_pd_0/Out1 0.33fF -C205 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF -C206 pll_full_0/divider_0/tspc_1/Z4 gnd 0.44fF -C207 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/Out 0.11fF -C208 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF -C209 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF -C210 divider_1/mc2 divider_1/and_0/out1 0.06fF -C211 divider_1/tspc_0/Z2 divider_1/nor_1/A 0.23fF -C212 divider_0/and_0/A divider_0/and_0/B 0.18fF -C213 divider_1/tspc_2/a_630_n680# divider_1/nor_0/B 0.35fF -C214 divider_2/nor_1/B divider_2/and_0/B 0.31fF -C215 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF -C216 divider_1/prescaler_0/tspc_0/D gnd 0.05fF -C217 ro_complete_1/a5 ro_complete_1/cbank_1/switch_0/vin 0.09fF -C218 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/v 1.30fF -C219 divbuf_5/IN divbuf_5/OUT5 0.00fF -C220 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF -C221 divider_2/prescaler_0/nand_0/z1 gnd 0.16fF -C222 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF -C223 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF -C224 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C225 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF -C226 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF -C227 gnd pll_full_0/divider_0/tspc_2/Z3 0.27fF -C228 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF -C229 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z2 0.01fF -C230 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF -C231 divider_1/nor_1/Z1 divider_1/nor_1/B 0.06fF -C232 ro_complete_1/a2 ro_complete_1/cbank_0/switch_3/vin 0.09fF -C233 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF -C234 ro_complete_1/cbank_1/switch_2/vin ro_complete_1/cbank_1/v 1.30fF -C235 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF -C236 divider_2/clk gnd 0.07fF -C237 pd_1/tspc_r_1/Qbar pd_1/R 0.03fF -C238 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF -C239 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF -C240 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF -C241 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF -C242 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF -C243 divbuf_2/OUT5 divbuf_2/a_492_n240# 0.01fF -C244 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/v 1.30fF -C245 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF -C246 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF -C247 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C248 divider_0/prescaler_0/tspc_0/D gnd 0.05fF -C249 ro_complete_1/a0 ro_complete_1/cbank_2/v 0.05fF -C250 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF -C251 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF -C252 divider_1/prescaler_0/Out gnd 0.46fF -C253 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF -C254 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF -C255 pd_1/tspc_r_1/Z3 pd_1/UP 0.03fF -C256 pll_full_0/divider_0/tspc_1/Q gnd 0.33fF -C257 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C258 divider_1/nor_1/A divider_1/prescaler_0/Out 0.15fF -C259 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.14fF -C260 divbuf_2/OUT3 divbuf_2/OUT 0.26fF -C261 divider_2/nor_1/B divider_2/tspc_2/Z4 0.02fF -C262 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF -C263 divider_1/tspc_0/a_630_n680# gnd 0.62fF -C264 divider_0/and_0/out1 gnd 0.23fF -C265 divider_2/prescaler_0/tspc_2/Z3 gnd 0.27fF -C266 divider_1/tspc_0/a_630_n680# divider_1/nor_1/A 0.35fF -C267 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF -C268 pd_1/DIV pd_1/tspc_r_0/Z3 0.65fF -C269 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF -C270 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/a_630_n680# 0.19fF -C271 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C272 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF -C273 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF -C274 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a5 0.09fF -C275 divbuf_3/OUT2 divbuf_3/a_492_n240# 0.42fF -C276 divider_0/prescaler_0/tspc_0/Z3 gnd 0.27fF -C277 divider_1/tspc_1/Q gnd 0.33fF -C278 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF -C279 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C280 divider_2/nor_0/B gnd 1.08fF -C281 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C282 divider_1/tspc_1/Z2 divider_1/nor_1/B 0.30fF -C283 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF -C284 gnd pll_full_0/divider_0/and_0/B 0.66fF -C285 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF -C286 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF -C287 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF -C288 divider_1/and_0/B divider_1/and_0/Z1 0.07fF -C289 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF -C290 ro_complete_1/a3 ro_complete_1/cbank_2/v 0.05fF -C291 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF -C292 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF -C293 divider_2/tspc_2/a_630_n680# divider_2/Out 0.04fF -C294 divider_2/nor_0/B divider_2/tspc_2/Z2 0.40fF -C295 divider_2/prescaler_0/tspc_0/Q divider_2/clk 0.05fF -C296 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C297 divider_2/mc2 gnd 1.36fF -C298 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF -C299 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF -C300 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z3 0.27fF -C301 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF -C302 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF -C303 divider_2/nor_1/A divider_2/tspc_0/a_630_n680# 0.35fF -C304 divider_1/and_0/OUT divider_1/and_0/B 0.01fF -C305 cp_0/a_1710_n2840# cp_0/upbar 0.29fF -C306 pd_1/R pd_1/REF 0.61fF -C307 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF -C308 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF -C309 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/Z3 0.05fF -C310 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C311 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C312 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.01fF -C313 divider_1/tspc_1/Q divider_1/tspc_2/Z1 0.01fF -C314 divider_1/nor_1/Z1 divider_1/and_0/B 0.18fF -C315 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF -C316 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF -C317 divbuf_1/OUT divbuf_1/OUT3 0.26fF -C318 ro_complete_1/a4 ro_complete_1/cbank_1/switch_1/vin 0.09fF -C319 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF -C320 divider_2/tspc_1/Z2 divider_2/tspc_0/Q 0.14fF -C321 divbuf_4/OUT2 divbuf_4/OUT 0.06fF -C322 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF -C323 divider_0/tspc_2/a_630_n680# gnd 0.61fF -C324 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF -C325 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF -C326 divider_2/prescaler_0/tspc_1/Z4 gnd 0.44fF -C327 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z3 0.09fF -C328 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF -C329 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/B 0.22fF -C330 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C331 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_0/D 0.16fF -C332 cp_0/upbar cp_0/down 0.02fF -C333 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/Out 0.28fF -C334 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF -C335 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF -C336 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF -C337 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF -C338 ro_complete_1/a3 ro_complete_1/cbank_1/switch_2/vin 0.09fF -C339 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF -C340 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.03fF -C341 divider_2/prescaler_0/tspc_0/Z2 gnd 0.16fF -C342 divbuf_5/OUT2 divbuf_5/OUT 0.06fF -C343 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF -C344 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C345 divider_2/prescaler_0/tspc_1/Q gnd 0.83fF -C346 pd_0/UP pd_0/tspc_r_1/z5 0.03fF -C347 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Q 0.20fF -C348 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF -C349 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF -C350 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/A 0.21fF -C351 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Q 0.04fF -C352 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF -C353 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF -C354 gnd pll_full_0/divider_0/tspc_2/Z4 0.44fF -C355 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/Out 0.91fF -C356 divider_2/tspc_0/Z3 divider_2/tspc_0/Z1 0.06fF -C357 divider_1/and_0/out1 divider_1/and_0/A 0.01fF -C358 ro_complete_1/a2 ro_complete_1/cbank_2/switch_3/vin 0.09fF -C359 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF -C360 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/switch_5/vin 0.20fF -C361 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C362 divider_0/prescaler_0/tspc_1/Z3 gnd 0.27fF -C363 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C364 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF -C365 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C366 divider_2/nor_1/A divider_2/nor_1/B 1.21fF -C367 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF -C368 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF -C369 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF -C370 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z3 0.45fF -C371 divider_0/prescaler_0/nand_0/z1 gnd 0.16fF -C372 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF -C373 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF -C374 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF -C375 divider_1/tspc_1/Z4 divider_1/tspc_0/Q 0.15fF -C376 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF -C377 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF -C378 pd_1/REF pd_1/tspc_r_1/z5 0.04fF -C379 pll_full_0/divider_0/tspc_0/a_630_n680# gnd 0.62fF -C380 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF -C381 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C382 divider_1/mc2 divider_1/nor_0/B 0.15fF -C383 divider_0/prescaler_0/Out divider_0/tspc_0/Z2 0.11fF -C384 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF -C385 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF -C386 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/REF 0.12fF -C387 divider_2/mc2 divider_2/and_0/A 0.16fF -C388 divider_2/tspc_0/Q divider_2/tspc_1/Z4 0.15fF -C389 divider_2/tspc_0/Z4 gnd 0.44fF -C390 divbuf_2/OUT5 divbuf_2/OUT 43.38fF -C391 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF -C392 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF -C393 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF -C394 divider_0/clk gnd 0.07fF -C395 divider_2/prescaler_0/tspc_2/Z4 gnd 0.44fF -C396 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF -C397 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF -C398 divider_1/tspc_0/a_630_n680# divider_1/nor_1/B 0.01fF -C399 divider_1/tspc_1/Z4 divider_1/tspc_1/Z3 0.65fF -C400 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF -C401 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF -C402 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C403 divider_1/tspc_0/Q divider_1/tspc_1/Z1 0.01fF -C404 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF -C405 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/Q 0.19fF -C406 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.14fF -C407 divider_0/prescaler_0/tspc_0/Z4 gnd 0.44fF -C408 ro_complete_1/a5 ro_complete_1/cbank_1/v 0.10fF -C409 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/cbank_0/v 1.30fF -C410 io_clamp_high[0] io_analog[4] 0.53fF -C411 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF -C412 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF -C413 divider_1/nor_1/A gnd 1.02fF -C414 divider_0/mc2 divider_0/nor_1/A 0.04fF -C415 divider_2/tspc_2/Z2 gnd 0.16fF -C416 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF -C417 pd_1/DOWN pd_1/tspc_r_0/Qbar1 0.11fF -C418 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF -C419 pll_full_0/divider_0/nor_1/Z1 gnd 0.01fF -C420 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.01fF -C421 divider_2/nor_1/A divider_2/tspc_0/Z3 0.38fF -C422 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z3 0.65fF -C423 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF -C424 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF -C425 divider_1/tspc_1/Z3 divider_1/tspc_1/Z1 0.06fF -C426 divider_1/tspc_1/Q divider_1/nor_1/B 0.51fF -C427 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF -C428 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF -C429 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF -C430 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF -C431 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF -C432 divider_2/nor_0/B divider_2/Out 0.22fF -C433 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.29fF -C434 divider_0/prescaler_0/tspc_2/Z3 gnd 0.27fF -C435 divbuf_7/OUT3 divbuf_7/OUT 0.26fF -C436 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF -C437 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C438 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C439 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF -C440 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF -C441 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF -C442 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF -C443 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF -C444 pd_1/R pd_1/tspc_r_1/Qbar1 0.30fF -C445 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C446 divider_2/nor_0/Z1 divider_2/nor_1/B 0.18fF -C447 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF -C448 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF -C449 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C450 divider_1/tspc_1/Q divider_1/tspc_2/Z3 0.45fF -C451 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF -C452 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/Out 0.08fF -C453 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF -C454 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF -C455 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF -C456 ro_complete_1/a2 ro_complete_1/cbank_1/v 0.05fF -C457 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF -C458 divider_0/nor_0/B gnd 1.08fF -C459 divbuf_4/OUT4 divbuf_4/OUT 1.11fF -C460 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z3 0.65fF -C461 divider_2/tspc_1/Z3 gnd 0.27fF -C462 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z4 0.12fF -C463 divider_0/tspc_0/Z4 divider_0/prescaler_0/Out 0.12fF -C464 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF -C465 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF -C466 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF -C467 pll_full_0/divider_0/and_0/OUT gnd 0.32fF -C468 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF -C469 divider_0/and_0/B divider_0/and_0/Z1 0.07fF -C470 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF -C471 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF -C472 divider_1/tspc_2/a_630_n680# divider_1/Out 0.04fF -C473 divider_1/nor_0/B divider_1/tspc_2/Z2 0.40fF -C474 divider_1/prescaler_0/tspc_0/Q divider_1/clk 0.05fF -C475 divider_2/tspc_1/Q divider_2/tspc_2/Z1 0.01fF -C476 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF -C477 divider_0/tspc_0/Q gnd 0.33fF -C478 ro_complete_1/a3 ro_complete_1/cbank_2/switch_1/vin 0.13fF -C479 divider_1/tspc_1/a_630_n680# gnd 0.62fF -C480 divbuf_5/OUT4 divbuf_5/OUT 1.11fF -C481 divider_0/tspc_0/Z4 divider_0/tspc_0/Z1 0.00fF -C482 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF -C483 divider_2/prescaler_0/tspc_0/Q gnd 0.35fF -C484 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z3 0.11fF -C485 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF -C486 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z3 0.25fF -C487 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF -C488 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF -C489 filter_0/a_4216_n2998# filter_0/v 0.31fF -C490 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF -C491 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF -C492 divider_2/nor_1/A divider_2/prescaler_0/Out 0.15fF -C493 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF -C494 ro_complete_1/a2 ro_complete_1/cbank_0/switch_2/vin 0.14fF -C495 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a4 0.09fF -C496 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF -C497 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF -C498 divider_0/prescaler_0/tspc_1/Z4 gnd 0.44fF -C499 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/v 1.30fF -C500 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/tspc_0/Z4 0.11fF -C501 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C502 divider_2/and_0/A gnd 0.53fF -C503 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z4 0.04fF -C504 pll_full_0/pd_0/R pll_full_0/pd_0/DIV 0.51fF -C505 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF -C506 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF -C507 pd_1/tspc_r_0/Qbar1 pd_1/R 0.01fF -C508 divbuf_0/OUT divbuf_0/OUT2 0.06fF -C509 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF -C510 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF -C511 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF -C512 divider_2/tspc_0/Z2 divider_2/tspc_0/Z1 1.07fF -C513 divider_2/prescaler_0/tspc_1/Z4 divider_2/prescaler_0/tspc_2/a_740_n680# 0.01fF -C514 divider_0/prescaler_0/tspc_1/Q gnd 0.83fF -C515 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF -C516 ro_complete_1/cbank_2/switch_2/vin ro_complete_1/cbank_2/v 1.30fF -C517 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF -C518 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF -C519 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C520 pd_1/DIV pd_1/tspc_r_0/Z2 0.19fF -C521 pd_0/DOWN pd_0/R 0.36fF -C522 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF -C523 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF -C524 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF -C525 divider_1/and_0/OUT divider_1/prescaler_0/tspc_0/Z2 0.05fF -C526 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF -C527 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF -C528 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF -C529 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF -C530 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/DIV 0.17fF -C531 divider_0/and_0/out1 divider_0/and_0/A 0.01fF -C532 pd_1/R pd_1/and_pd_0/Z1 0.02fF -C533 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF -C534 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C535 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C536 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/Out 0.11fF -C537 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF -C538 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF -C539 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF -C540 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.06fF -C541 divider_0/nor_0/Z1 gnd 0.01fF -C542 divider_0/tspc_0/Z3 gnd 0.27fF -C543 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF -C544 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF -C545 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF -C546 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF -C547 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF -C548 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z3 0.38fF -C549 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF -C550 divider_2/nor_1/Z1 divider_2/and_0/B 0.18fF -C551 divider_2/nor_1/B divider_2/tspc_1/Z1 0.03fF -C552 divbuf_3/IN divbuf_3/OUT5 0.00fF -C553 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/D 0.32fF -C554 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF -C555 divider_0/nor_1/B gnd 1.10fF -C556 divider_1/nor_1/B gnd 1.10fF -C557 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF -C558 divider_2/Out gnd 0.29fF -C559 pd_1/DOWN pd_1/R 0.36fF -C560 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF -C561 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF -C562 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C563 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.20fF -C564 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_1/A 1.21fF -C565 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar1 0.11fF -C566 divider_1/nor_1/A divider_1/nor_1/B 1.21fF -C567 divbuf_3/OUT4 divbuf_3/OUT 1.11fF -C568 ro_complete_1/a1 ro_complete_1/cbank_2/v 0.05fF -C569 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF -C570 divider_0/prescaler_0/tspc_2/Z4 gnd 0.44fF -C571 divider_1/tspc_2/Z3 gnd 0.27fF -C572 divbuf_7/OUT5 divbuf_7/OUT 43.38fF -C573 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF -C574 divider_2/nor_1/A divider_2/tspc_0/Z2 0.23fF -C575 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF -C576 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF -C577 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z3 0.16fF -C578 divider_1/tspc_1/Q divider_1/tspc_2/Z4 0.15fF -C579 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/Q 0.19fF -C580 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/Out 0.11fF -C581 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF -C582 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF -C583 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF -C584 divider_0/tspc_2/Z2 gnd 0.16fF -C585 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C586 divider_2/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF -C587 pd_0/R pd_0/tspc_r_1/Z3 0.29fF -C588 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF -C589 divider_0/nor_1/B divider_0/nor_0/B 0.47fF -C590 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF -C591 divider_0/tspc_0/Q divider_0/tspc_0/Z3 0.05fF -C592 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF -C593 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF -C594 cp_0/a_10_n50# cp_0/vbias 0.19fF -C595 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar1 0.11fF -C596 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF -C597 divider_1/mc2 divider_1/and_0/A 0.16fF -C598 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF -C599 pll_full_0/divider_0/prescaler_0/tspc_0/D gnd 0.05fF -C600 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF -C601 divider_1/nor_0/B divider_1/Out 0.22fF -C602 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.29fF -C603 divbuf_2/OUT2 divbuf_2/a_492_n240# 0.42fF -C604 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF -C605 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF -C606 divider_2/tspc_1/Q divider_2/tspc_2/Z3 0.45fF -C607 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF -C608 divider_0/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF -C609 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF -C610 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF -C611 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF -C612 divider_2/prescaler_0/tspc_2/D gnd 0.05fF -C613 pd_1/tspc_r_0/Qbar pd_1/tspc_r_0/Qbar1 0.01fF -C614 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z2 0.30fF -C615 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C616 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF -C617 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z2 0.01fF -C618 filter_0/a_4216_n5230# filter_0/v 0.19fF -C619 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF -C620 divider_1/tspc_1/a_630_n680# divider_1/nor_1/B 0.35fF -C621 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_2/a_740_n680# 0.01fF -C622 gnd pll_full_0/divider_0/and_0/out1 0.29fF -C623 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF -C624 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF -C625 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF -C626 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF -C627 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF -C628 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/v 1.45fF -C629 divider_0/tspc_1/Z3 gnd 0.27fF -C630 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF -C631 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF -C632 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF -C633 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C634 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z3 0.09fF -C635 pd_1/tspc_r_1/Z2 pd_1/REF 0.19fF -C636 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/z5 0.11fF -C637 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 gnd 0.27fF -C638 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF -C639 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF -C640 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF -C641 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF -C642 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF -C643 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF -C644 divbuf_0/OUT divbuf_0/OUT3 0.26fF -C645 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF -C646 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF -C647 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/switch_5/vin 0.20fF -C648 divider_0/prescaler_0/tspc_0/Q gnd 0.35fF -C649 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF -C650 divider_1/and_0/B gnd 0.45fF -C651 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/tspc_0/Z2 0.09fF -C652 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF -C653 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF -C654 divider_0/mc2 divider_0/and_0/B 0.20fF -C655 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF -C656 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF -C657 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C658 cp_0/a_1710_n2840# cp_0/out 0.61fF -C659 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF -C660 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C661 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C662 divider_2/nor_1/A divider_2/tspc_0/Q 0.55fF -C663 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF -C664 divider_1/nor_1/A divider_1/and_0/B 0.08fF -C665 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/Out 0.05fF -C666 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF -C667 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF -C668 divider_2/prescaler_0/m1_2700_2190# gnd 0.22fF -C669 divbuf_1/OUT5 divbuf_1/IN 0.00fF -C670 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF -C671 divider_0/and_0/A gnd 0.53fF -C672 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF -C673 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C674 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF -C675 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF -C676 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF -C677 pd_1/DIV pd_1/tspc_r_0/z5 0.04fF -C678 pd_1/tspc_r_0/Qbar pd_1/DOWN 0.21fF -C679 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF -C680 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF -C681 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z1 0.03fF -C682 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF -C683 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF -C684 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF -C685 gnd pll_full_0/divider_0/tspc_2/a_630_n680# 0.61fF -C686 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF -C687 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DIV 0.04fF -C688 divider_1/tspc_0/Q divider_1/tspc_0/Z3 0.05fF -C689 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF -C690 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF -C691 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF -C692 divider_2/prescaler_0/tspc_0/Q divider_2/prescaler_0/tspc_2/D 0.04fF -C693 divider_0/prescaler_0/m1_2700_2190# gnd 0.22fF -C694 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF -C695 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF -C696 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF -C697 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF -C698 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C699 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_1/A 0.01fF -C700 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF -C701 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF -C702 pll_full_0/divider_0/tspc_0/Z4 gnd 0.44fF -C703 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.15fF -C704 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF -C705 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF -C706 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF -C707 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF -C708 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF -C709 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF -C710 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF -C711 divider_1/prescaler_0/tspc_0/Z4 gnd 0.44fF -C712 ro_complete_1/cbank_1/switch_5/vin ro_complete_1/cbank_1/v 1.30fF -C713 divider_1/tspc_2/Z4 gnd 0.44fF -C714 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z3 0.33fF -C715 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF -C716 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF -C717 divider_2/nor_1/A divider_2/tspc_1/Z2 0.15fF -C718 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF -C719 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_630_n680# 0.05fF -C720 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Out1 0.05fF -C721 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 gnd 0.27fF -C722 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF -C723 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/D 0.32fF -C724 divider_1/prescaler_0/tspc_1/Z4 divider_1/prescaler_0/Out 0.28fF -C725 divbuf_1/OUT4 divbuf_1/OUT3 5.16fF -C726 divider_2/nor_1/B divider_2/nor_0/B 0.47fF -C727 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF -C728 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF -C729 divider_0/Out gnd 0.29fF -C730 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C731 divider_2/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF -C732 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF -C733 divider_1/and_0/OUT divider_1/prescaler_0/m1_2700_2190# 0.14fF -C734 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF -C735 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF -C736 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF -C737 pd_0/R pd_0/UP 0.45fF -C738 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C739 pll_full_0/divider_0/nor_0/Z1 gnd 0.01fF -C740 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF -C741 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF -C742 divider_1/tspc_0/Q divider_1/tspc_1/Z2 0.14fF -C743 pll_full_0/divider_0/prescaler_0/nand_0/z1 gnd 0.16fF -C744 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF -C745 divider_2/mc2 divider_2/nor_1/B 0.06fF -C746 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF -C747 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.00fF -C748 divider_2/tspc_1/Q divider_2/tspc_2/Z4 0.15fF -C749 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/Out 0.11fF -C750 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF -C751 divider_0/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF -C752 io_clamp_low[2] io_analog[6] 0.53fF -C753 divider_1/prescaler_0/tspc_1/Z3 gnd 0.27fF -C754 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF -C755 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C756 divider_2/prescaler_0/nand_1/z1 gnd 0.16fF -C757 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF -C758 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF -C759 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF -C760 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF -C761 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF -C762 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF -C763 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF -C764 pd_0/UP pd_0/and_pd_0/Out1 0.33fF -C765 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF -C766 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF -C767 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF -C768 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF -C769 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF -C770 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF -C771 gnd pll_full_0/divider_0/clk 0.08fF -C772 divbuf_2/OUT2 divbuf_2/OUT 0.06fF -C773 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF -C774 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF -C775 ro_complete_1/a0 ro_complete_1/cbank_1/switch_5/vin 0.09fF -C776 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF -C777 divider_0/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF -C778 divider_2/and_0/Z1 gnd 0.41fF -C779 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF -C780 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF -C781 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF -C782 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF -C783 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF -C784 divider_2/tspc_0/Z4 divider_2/tspc_0/a_630_n680# 0.12fF -C785 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_630_n680# 0.12fF -C786 divider_1/and_0/OUT divider_1/clk 0.04fF -C787 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z3 0.06fF -C788 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF -C789 divider_0/nor_0/B divider_0/Out 0.22fF -C790 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF -C791 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF -C792 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF -C793 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C794 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 gnd 0.44fF -C795 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF -C796 divbuf_0/OUT divbuf_0/OUT4 1.11fF -C797 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF -C798 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF -C799 ro_complete_1/a2 ro_complete_1/cbank_2/switch_2/vin 0.14fF -C800 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/REF 0.19fF -C801 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF -C802 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/v 1.30fF -C803 divider_2/prescaler_0/Out divider_2/clk 0.51fF -C804 divider_0/prescaler_0/tspc_2/D gnd 0.05fF -C805 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C806 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C807 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF -C808 divider_2/tspc_0/a_630_n680# gnd 0.62fF -C809 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF -C810 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF -C811 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF -C812 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF -C813 divider_2/nor_1/A divider_2/tspc_1/Z4 0.02fF -C814 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF -C815 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF -C816 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF -C817 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C818 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 gnd 0.27fF -C819 divider_1/nor_1/B divider_1/and_0/B 0.31fF -C820 divbuf_2/IN divbuf_2/OUT5 0.00fF -C821 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C822 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_0/vin 0.19fF -C823 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Z3 0.38fF -C824 divider_2/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF -C825 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C826 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF -C827 divider_1/tspc_1/Z4 divider_1/tspc_1/Z1 0.00fF -C828 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF -C829 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF -C830 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF -C831 divider_0/nor_1/B divider_0/and_0/A 0.26fF -C832 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.05fF -C833 gnd pll_full_0/divider_0/nor_0/B 1.23fF -C834 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF -C835 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF -C836 divider_2/prescaler_0/tspc_0/Q divider_2/prescaler_0/nand_1/z1 0.01fF -C837 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/Out 0.05fF -C838 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF -C839 divider_0/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF -C840 divbuf_6/OUT3 divbuf_6/OUT 0.26fF -C841 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF -C842 divider_1/prescaler_0/tspc_2/Z3 gnd 0.27fF -C843 divider_0/mc2 divider_0/and_0/OUT 0.05fF -C844 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF -C845 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C846 divider_0/nor_1/A divider_0/and_0/B 0.08fF -C847 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF -C848 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.45fF -C849 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/tspc_r_1/Qbar1 0.01fF -C850 divider_2/tspc_1/Z1 divider_2/tspc_0/Q 0.01fF -C851 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF -C852 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF -C853 ro_complete_1/cbank_0/v ro_complete_1/cbank_2/v 0.04fF -C854 divider_2/nor_1/B gnd 1.10fF -C855 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF -C856 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Q 0.04fF -C857 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/tspc_0/Z1 0.15fF -C858 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF -C859 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C860 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF -C861 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF -C862 pd_1/REF pd_1/tspc_r_1/Z3 0.65fF -C863 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF -C864 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 gnd 0.44fF -C865 divider_1/nor_1/B divider_1/tspc_2/Z4 0.02fF -C866 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF -C867 divider_1/prescaler_0/tspc_0/Q divider_1/prescaler_0/tspc_2/D 0.04fF -C868 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF -C869 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF -C870 divider_2/nor_1/B divider_2/tspc_2/Z2 0.20fF -C871 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF -C872 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF -C873 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF -C874 divider_1/prescaler_0/tspc_0/Z2 gnd 0.16fF -C875 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C876 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C877 divider_2/tspc_1/a_630_n680# gnd 0.62fF -C878 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C879 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF -C880 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/m1_2700_2190# 0.16fF -C881 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF -C882 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF -C883 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF -C884 pll_full_0/divider_0/prescaler_0/tspc_1/Q gnd 0.83fF -C885 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF -C886 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF -C887 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF -C888 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF -C889 divider_2/prescaler_0/tspc_1/Z4 divider_2/prescaler_0/Out 0.28fF -C890 divider_0/tspc_1/a_630_n680# gnd 0.62fF -C891 ro_complete_1/a4 ro_complete_1/cbank_2/switch_0/vin 0.12fF -C892 divider_1/prescaler_0/tspc_1/Z4 gnd 0.44fF -C893 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_740_n680# 0.33fF -C894 divider_1/and_0/OUT divider_1/mc2 0.05fF -C895 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF -C896 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF -C897 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C898 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C899 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C900 divider_2/tspc_0/Z4 divider_2/tspc_0/Z3 0.65fF -C901 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_0/z1 0.24fF -C902 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF -C903 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF -C904 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF -C905 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF -C906 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divbuf_0/IN 0.05fF -C907 gnd pll_full_0/divider_0/tspc_0/Z3 0.27fF -C908 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C909 divider_2/nor_1/A divider_2/and_0/B 0.08fF -C910 divider_1/tspc_1/Z3 divider_1/tspc_1/Q 0.05fF -C911 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF -C912 divider_2/nor_1/B divider_2/tspc_1/Z3 0.38fF -C913 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF -C914 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF -C915 divider_2/and_0/OUT divider_2/and_0/B 0.01fF -C916 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/Out 0.91fF -C917 divider_0/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF -C918 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF -C919 ro_complete_1/a0 ro_complete_1/cbank_1/v 0.05fF -C920 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF -C921 divider_2/tspc_0/Z3 gnd 0.27fF -C922 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF -C923 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF -C924 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C925 pd_1/tspc_r_1/Qbar pd_1/UP 0.21fF -C926 pll_full_0/divider_0/nor_1/B gnd 1.17fF -C927 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF -C928 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Qbar1 0.20fF -C929 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.26fF -C930 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF -C931 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF -C932 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF -C933 divider_1/tspc_1/Q divider_1/tspc_2/a_630_n680# 0.01fF -C934 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/Out 0.11fF -C935 divider_2/tspc_1/Z3 divider_2/tspc_1/a_630_n680# 0.05fF -C936 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF -C937 divbuf_1/OUT divbuf_1/OUT4 1.11fF -C938 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF -C939 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_4/vin 0.20fF -C940 divider_0/prescaler_0/nand_1/z1 gnd 0.16fF -C941 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF -C942 ro_complete_1/cbank_2/switch_0/vin ro_complete_1/cbank_2/v 1.44fF -C943 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C944 divider_2/prescaler_0/tspc_1/Z2 gnd 0.17fF -C945 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF -C946 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF -C947 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF -C948 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF -C949 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF -C950 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF -C951 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C952 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 gnd 0.44fF -C953 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/Out 0.19fF -C954 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF -C955 ro_complete_1/a2 ro_complete_1/cbank_1/switch_3/vin 0.09fF -C956 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF -C957 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C958 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF -C959 divider_2/nor_1/B divider_2/and_0/A 0.26fF -C960 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF -C961 divider_0/and_0/Z1 gnd 0.41fF -C962 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF -C963 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_740_n680# 0.08fF -C964 divider_0/tspc_0/Q divider_0/tspc_1/a_630_n680# 0.01fF -C965 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C966 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C967 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF -C968 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF -C969 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF -C970 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF -C971 pd_0/REF pd_0/tspc_r_1/z5 0.04fF -C972 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF -C973 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF -C974 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF -C975 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF -C976 gnd pll_full_0/divider_0/tspc_2/Z2 0.16fF -C977 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.26fF -C978 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DIV 0.65fF -C979 divider_2/tspc_0/Z4 divider_2/prescaler_0/Out 0.12fF -C980 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF -C981 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF -C982 divider_1/prescaler_0/Out divider_1/clk 0.51fF -C983 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_1/z1 0.21fF -C984 divbuf_3/OUT2 divbuf_3/OUT 0.06fF -C985 ro_complete_1/a3 ro_complete_1/cbank_1/v 0.05fF -C986 divider_1/prescaler_0/tspc_2/Z4 gnd 0.44fF -C987 divbuf_6/OUT5 divbuf_6/OUT 43.38fF -C988 divider_0/tspc_0/Z4 divider_0/tspc_0/a_630_n680# 0.12fF -C989 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C990 divider_2/prescaler_0/Out gnd 0.46fF -C991 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z1 0.06fF -C992 pd_1/tspc_r_1/Z2 pd_1/R 0.21fF -C993 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C994 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF -C995 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/DIV 0.02fF -C996 divider_2/nor_0/Z1 divider_2/and_0/B 0.78fF -C997 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_4/vin 0.20fF -C998 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF -C999 divider_1/and_0/out1 gnd 0.23fF -C1000 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF -C1001 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF -C1002 divider_1/mc2 divider_1/prescaler_0/tspc_0/a_630_n680# 0.33fF -C1003 divider_0/mc2 divider_0/and_0/out1 0.06fF -C1004 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF -C1005 divider_2/nor_1/A divider_2/tspc_0/Z1 0.03fF -C1006 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF -C1007 pll_full_0/divider_0/tspc_1/Z3 gnd 0.27fF -C1008 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.45fF -C1009 divider_1/prescaler_0/tspc_0/Q divider_1/prescaler_0/nand_1/z1 0.01fF -C1010 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/Out 0.21fF -C1011 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a1 0.14fF -C1012 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/a3 0.09fF -C1013 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF -C1014 divider_1/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF -C1015 ro_complete_1/cbank_2/switch_5/vin ro_complete_1/cbank_2/v 1.30fF -C1016 divider_1/tspc_0/Q gnd 0.33fF -C1017 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF -C1018 divider_2/prescaler_0/tspc_2/Z2 gnd 0.16fF -C1019 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF -C1020 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF -C1021 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C1022 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.32fF -C1023 divider_1/tspc_0/Q divider_1/nor_1/A 0.55fF -C1024 pd_1/and_pd_0/Out1 pd_1/and_pd_0/Z1 0.18fF -C1025 pll_full_0/divider_0/prescaler_0/tspc_0/Q gnd 0.35fF -C1026 io_clamp_low[2] io_clamp_high[2] 0.53fF -C1027 divbuf_3/IN divbuf_3/a_492_n240# 0.13fF -C1028 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/v 1.30fF -C1029 divider_0/prescaler_0/tspc_0/Z2 gnd 0.16fF -C1030 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF -C1031 io_clamp_high[1] io_analog[5] 0.53fF -C1032 divider_1/tspc_1/Z3 gnd 0.27fF -C1033 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF -C1034 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF -C1035 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF -C1036 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z2 0.21fF -C1037 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z1 0.00fF -C1038 divider_1/and_0/OUT divider_1/prescaler_0/tspc_0/Q 0.04fF -C1039 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF -C1040 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF -C1041 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF -C1042 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C1043 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF -C1044 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.45fF -C1045 gnd pll_full_0/divider_0/and_0/A 0.69fF -C1046 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF -C1047 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF -C1048 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF -C1049 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF -C1050 divider_2/nor_0/B divider_2/tspc_2/Z1 0.03fF -C1051 divbuf_7/IN divbuf_7/OUT5 0.00fF -C1052 divider_1/tspc_2/a_630_n680# gnd 0.61fF -C1053 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C1054 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF -C1055 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF -C1056 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF -C1057 divider_2/tspc_0/Z4 divider_2/tspc_0/Z2 0.36fF -C1058 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF -C1059 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C1060 pll_full_0/divider_0/prescaler_0/m1_2700_2190# gnd 0.22fF -C1061 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF -C1062 divider_1/tspc_1/Q divider_1/nor_0/B 0.22fF -C1063 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF -C1064 divider_1/nor_1/Z1 divider_1/and_0/A 0.80fF -C1065 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/switch_1/vin 0.19fF -C1066 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF -C1067 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF -C1068 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF -C1069 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF -C1070 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF -C1071 divider_2/and_0/out1 divider_2/and_0/B 0.18fF -C1072 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF -C1073 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C1074 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1075 divider_2/tspc_0/Z2 gnd 0.16fF -C1076 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF -C1077 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF -C1078 divider_1/tspc_0/Q divider_1/tspc_1/a_630_n680# 0.01fF -C1079 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C1080 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF -C1081 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/Out 0.91fF -C1082 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF -C1083 divider_2/tspc_1/Q divider_2/tspc_2/a_630_n680# 0.01fF -C1084 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/Out 0.08fF -C1085 divider_0/nor_1/Z1 gnd 0.01fF -C1086 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF -C1087 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF -C1088 divider_1/prescaler_0/m1_2700_2190# gnd 0.22fF -C1089 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1090 pd_0/R pd_0/and_pd_0/Z1 0.02fF -C1091 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF -C1092 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF -C1093 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/A 0.55fF -C1094 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF -C1095 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF -C1096 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF -C1097 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF -C1098 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_1/A 0.01fF -C1099 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z3 0.05fF -C1100 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF -C1101 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Q 0.05fF -C1102 gnd pll_full_0/divbuf_0/IN 3.72fF -C1103 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF -C1104 ro_complete_1/a4 ro_complete_1/cbank_2/v 0.05fF -C1105 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_0/vin 0.19fF -C1106 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF -C1107 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C1108 divider_0/prescaler_0/tspc_1/Z2 gnd 0.17fF -C1109 divider_1/prescaler_0/nand_0/z1 gnd 0.16fF -C1110 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF -C1111 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C1112 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Qbar1 0.38fF -C1113 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF -C1114 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF -C1115 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# gnd 0.94fF -C1116 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF -C1117 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z2 0.11fF -C1118 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_2/a_740_n680# 0.01fF -C1119 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF -C1120 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF -C1121 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C1122 divider_1/clk gnd 0.07fF -C1123 pd_0/DIV pd_0/R 0.51fF -C1124 pd_1/R pd_1/and_pd_0/Out1 0.33fF -C1125 pd_1/REF pd_1/tspc_r_1/Z4 0.02fF -C1126 pd_1/tspc_r_1/Qbar1 pd_1/UP 0.11fF -C1127 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF -C1128 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF -C1129 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF -C1130 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Q 0.04fF -C1131 divider_0/prescaler_0/Out divider_0/clk 0.51fF -C1132 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF -C1133 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_1/z1 0.21fF -C1134 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/Out 0.04fF -C1135 divider_0/mc2 gnd 1.36fF -C1136 divbuf_2/OUT4 divbuf_2/OUT 1.11fF -C1137 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a1 0.14fF -C1138 divider_0/prescaler_0/Out gnd 0.46fF -C1139 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF -C1140 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/Z3 0.16fF -C1141 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C1142 divider_2/tspc_0/Q gnd 0.33fF -C1143 divider_1/tspc_1/Z4 divider_1/tspc_1/Z2 0.36fF -C1144 divider_1/and_0/OUT divider_1/prescaler_0/tspc_1/Z2 0.06fF -C1145 pd_1/DIV pd_1/tspc_r_0/Qbar1 0.12fF -C1146 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF -C1147 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF -C1148 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF -C1149 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/Out 0.15fF -C1150 pll_full_0/divider_0/prescaler_0/tspc_2/D gnd 0.05fF -C1151 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.64fF -C1152 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF -C1153 divider_1/tspc_0/Q divider_1/nor_1/B 0.22fF -C1154 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF -C1155 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/Out 0.21fF -C1156 ro_complete_1/a5 ro_complete_1/cbank_2/switch_0/vin 0.09fF -C1157 io_clamp_low[0] io_analog[4] 0.53fF -C1158 divider_1/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF -C1159 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF -C1160 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C1161 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z2 0.36fF -C1162 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF -C1163 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF -C1164 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF -C1165 pd_1/DOWN pd_1/tspc_r_0/Z3 0.03fF -C1166 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/A 0.03fF -C1167 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C1168 divider_1/tspc_1/Z2 divider_1/tspc_1/Z1 1.07fF -C1169 divider_1/tspc_1/Z3 divider_1/nor_1/B 0.38fF -C1170 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF -C1171 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF -C1172 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF -C1173 divider_2/nor_0/B divider_2/tspc_2/Z3 0.38fF -C1174 divider_0/prescaler_0/tspc_2/Z2 gnd 0.16fF -C1175 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF -C1176 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF -C1177 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C1178 divider_1/nor_0/B gnd 1.08fF -C1179 divbuf_7/OUT2 divbuf_7/OUT 0.06fF -C1180 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF -C1181 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF -C1182 divider_0/mc2 divider_0/nor_0/B 0.15fF -C1183 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1184 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF -C1185 divider_1/tspc_0/Z4 divider_1/tspc_0/Z1 0.00fF -C1186 pd_1/R pd_1/tspc_r_1/Z3 0.29fF -C1187 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z3 0.65fF -C1188 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C1189 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF -C1190 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C1191 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF -C1192 divider_1/tspc_1/Q divider_1/tspc_2/Z2 0.14fF -C1193 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF -C1194 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z3 0.25fF -C1195 divider_2/tspc_1/Z3 divider_2/tspc_0/Q 0.45fF -C1196 divider_2/nor_1/Z1 gnd 0.01fF -C1197 divbuf_4/OUT3 divbuf_4/OUT 0.26fF -C1198 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF -C1199 divider_2/tspc_1/Z2 gnd 0.16fF -C1200 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z2 0.36fF -C1201 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C1202 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF -C1203 pd_0/DOWN pd_0/UP 0.46fF -C1204 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF -C1205 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF -C1206 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/a_630_n680# 0.19fF -C1207 pd_1/UP pd_1/and_pd_0/Z1 0.06fF -C1208 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF -C1209 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF -C1210 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF -C1211 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF -C1212 divider_1/nor_0/B divider_1/tspc_2/Z1 0.03fF -C1213 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/a0 0.13fF -C1214 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF -C1215 divider_2/tspc_1/Q divider_2/nor_0/B 0.22fF -C1216 divider_2/and_0/OUT divider_2/prescaler_0/tspc_0/D 0.03fF -C1217 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF -C1218 divider_2/prescaler_0/tspc_0/Z3 gnd 0.27fF -C1219 divider_1/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF -C1220 divbuf_5/OUT3 divbuf_5/OUT 0.26fF -C1221 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF -C1222 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF -C1223 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/Z2 0.06fF -C1224 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF -C1225 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z3 0.09fF -C1226 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF -C1227 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/Out 0.11fF -C1228 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF -C1229 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF -C1230 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF -C1231 divbuf_1/OUT5 divbuf_1/OUT 43.38fF -C1232 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF -C1233 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF -C1234 divider_2/nor_1/B divider_2/tspc_0/a_630_n680# 0.01fF -C1235 divider_1/and_0/out1 divider_1/and_0/B 0.18fF -C1236 ro_complete_1/a1 ro_complete_1/cbank_1/v 0.05fF -C1237 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF -C1238 pll_full_0/cp_0/down pll_full_0/cp_0/upbar 0.02fF -C1239 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF -C1240 divider_1/mc2 gnd 1.36fF -C1241 divider_1/prescaler_0/tspc_1/Q gnd 0.83fF -C1242 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF -C1243 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF -C1244 divider_1/mc2 divider_1/nor_1/A 0.04fF -C1245 divider_0/and_0/OUT divider_0/and_0/B 0.01fF -C1246 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF -C1247 pd_1/DOWN pd_1/UP 0.46fF -C1248 pd_1/tspc_r_0/Z3 pd_1/R 0.27fF -C1249 pll_full_0/divider_0/tspc_1/a_630_n680# gnd 0.62fF -C1250 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_0/D 0.16fF -C1251 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.05fF -C1252 divider_1/nor_1/A divider_1/prescaler_0/tspc_1/Q 0.03fF -C1253 divider_1/tspc_1/a_630_n680# divider_1/nor_0/B 0.00fF -C1254 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF -C1255 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF -C1256 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF -C1257 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF -C1258 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF -C1259 divider_2/nor_0/B divider_2/and_0/B 0.29fF -C1260 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF -C1261 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF -C1262 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1263 pd_1/DIV pd_1/tspc_r_0/Z1 0.17fF -C1264 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF -C1265 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF -C1266 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF -C1267 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C1268 divider_1/tspc_0/Z4 divider_1/tspc_0/Z3 0.65fF -C1269 divider_0/prescaler_0/Out divider_0/tspc_0/Z3 0.45fF -C1270 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF -C1271 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C1272 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF -C1273 ro_complete_1/a4 ro_complete_1/cbank_2/switch_1/vin 0.09fF -C1274 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/v 1.30fF -C1275 divider_2/prescaler_0/tspc_0/Z4 gnd 0.44fF -C1276 divider_2/mc2 divider_2/and_0/B 0.20fF -C1277 divider_0/tspc_0/Z2 gnd 0.16fF -C1278 divider_2/tspc_1/Z4 gnd 0.44fF -C1279 divider_0/mc2 divider_0/nor_1/B 0.06fF -C1280 pd_1/DIV pd_1/R 0.51fF -C1281 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF -C1282 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF -C1283 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C1284 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Q 0.05fF -C1285 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z2 0.23fF -C1286 gnd pll_full_0/divider_0/prescaler_0/nand_1/z1 0.16fF -C1287 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF -C1288 io_clamp_low[1] io_clamp_high[1] 0.53fF -C1289 divider_2/tspc_0/Z3 divider_2/tspc_0/a_630_n680# 0.05fF -C1290 divider_2/nor_1/Z1 divider_2/and_0/A 0.80fF -C1291 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF -C1292 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF -C1293 ro_complete_1/a3 ro_complete_1/cbank_2/switch_2/vin 0.09fF -C1294 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/Out 0.04fF -C1295 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF -C1296 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF -C1297 divider_1/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF -C1298 divider_2/tspc_2/Z3 gnd 0.27fF -C1299 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z4 0.08fF -C1300 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF -C1301 divider_1/tspc_0/Z1 divider_1/tspc_0/Z3 0.06fF -C1302 gnd pll_full_0/divider_0/and_0/Z1 0.32fF -C1303 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF -C1304 divider_2/nor_1/B divider_2/tspc_1/a_630_n680# 0.35fF -C1305 divbuf_1/OUT2 divbuf_1/OUT 0.06fF -C1306 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a3 0.13fF -C1307 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF -C1308 divbuf_3/OUT3 divbuf_3/OUT 0.26fF -C1309 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/v 1.30fF -C1310 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF -C1311 divider_2/nor_0/B divider_2/tspc_2/Z4 0.22fF -C1312 divider_0/nor_1/A gnd 1.02fF -C1313 divbuf_7/OUT4 divbuf_7/OUT 1.11fF -C1314 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF -C1315 divider_1/tspc_2/Z2 gnd 0.16fF -C1316 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.44fF -C1317 pd_1/R pd_1/UP 0.45fF -C1318 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF -C1319 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C1320 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF -C1321 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF -C1322 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF -C1323 divider_1/nor_1/B divider_1/nor_0/B 0.47fF -C1324 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/Out 0.19fF -C1325 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF -C1326 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF -C1327 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/v 1.30fF -C1328 divbuf_4/OUT5 divbuf_4/OUT 43.38fF -C1329 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C1330 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1331 divider_2/tspc_1/Q gnd 0.33fF -C1332 pd_0/R pd_0/REF 0.61fF -C1333 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF -C1334 pll_full_0/pd_0/R pll_full_0/pd_0/DOWN 0.36fF -C1335 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF -C1336 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF -C1337 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF -C1338 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF -C1339 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF -C1340 divider_1/nor_0/B divider_1/tspc_2/Z3 0.38fF -C1341 divbuf_2/IN divbuf_2/a_492_n240# 0.13fF -C1342 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF -C1343 divider_2/tspc_1/Q divider_2/tspc_2/Z2 0.14fF -C1344 divider_2/tspc_0/a_630_n680# divider_2/prescaler_0/Out 0.01fF -C1345 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF -C1346 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF -C1347 divider_0/tspc_0/Z4 gnd 0.44fF -C1348 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_4/vin 0.20fF -C1349 divbuf_5/OUT5 divbuf_5/OUT 43.38fF -C1350 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF -C1351 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C1352 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF -C1353 divider_1/tspc_0/Z4 divider_1/tspc_0/Z2 0.36fF -C1354 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z1 0.00fF -C1355 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF -C1356 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF -C1357 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF -C1358 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/clk 0.05fF -C1359 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/v 1.30fF -C1360 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF -C1361 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF -C1362 divider_2/and_0/OUT divider_2/clk 0.04fF -C1363 divider_0/tspc_1/Z2 gnd 0.16fF -C1364 ro_complete_1/a5 ro_complete_1/cbank_2/v 0.08fF -C1365 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF -C1366 divider_1/prescaler_0/tspc_0/Q gnd 0.35fF -C1367 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF -C1368 divider_2/and_0/B gnd 0.45fF -C1369 pd_1/tspc_r_1/Z1 pd_1/REF 0.17fF -C1370 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Z4 0.20fF -C1371 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/A 0.15fF -C1372 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C1373 pll_full_0/pd_0/UP pll_full_0/pd_0/DOWN 4.58fF -C1374 divider_1/mc2 divider_1/nor_1/B 0.06fF -C1375 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF -C1376 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF -C1377 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF -C1378 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DIV 0.12fF -C1379 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF -C1380 divider_2/tspc_1/Z3 divider_2/tspc_1/Q 0.05fF -C1381 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF -C1382 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF -C1383 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF -C1384 divider_1/and_0/A gnd 0.53fF -C1385 divider_0/mc2 divider_0/and_0/A 0.16fF -C1386 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF -C1387 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1388 pd_1/UP pd_1/tspc_r_1/z5 0.03fF -C1389 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C1390 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C1391 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF -C1392 divider_1/tspc_0/Z2 divider_1/tspc_0/Z1 1.07fF -C1393 divider_0/and_0/out1 divider_0/and_0/B 0.18fF -C1394 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF -C1395 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF -C1396 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF -C1397 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF -C1398 divider_1/nor_1/A divider_1/and_0/A 0.01fF -C1399 ro_complete_1/a2 ro_complete_1/cbank_2/v 0.05fF -C1400 divider_1/tspc_1/Z4 gnd 0.44fF -C1401 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF -C1402 divider_1/tspc_1/Z4 divider_1/nor_1/A 0.02fF -C1403 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF -C1404 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF -C1405 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF -C1406 pd_1/DIV pd_1/tspc_r_0/Z4 0.02fF -C1407 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF -C1408 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF -C1409 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF -C1410 divider_1/tspc_0/Z4 divider_1/prescaler_0/Out 0.12fF -C1411 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF -C1412 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF -C1413 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF -C1414 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF -C1415 divider_2/mc2 divider_2/prescaler_0/tspc_0/a_630_n680# 0.33fF -C1416 divider_1/nor_0/B divider_1/and_0/B 0.29fF -C1417 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF -C1418 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/a0 0.09fF -C1419 divbuf_6/IN divbuf_6/OUT5 0.00fF -C1420 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z4 0.12fF -C1421 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF -C1422 divider_2/tspc_2/Z4 gnd 0.44fF -C1423 divider_2/nor_1/A divider_2/mc2 0.04fF -C1424 divider_0/nor_1/A divider_0/tspc_0/Z3 0.38fF -C1425 pll_full_0/divider_0/tspc_0/Q gnd 0.33fF -C1426 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF -C1427 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C1428 divider_2/mc2 divider_2/and_0/OUT 0.05fF -C1429 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z2 0.01fF -C1430 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.15fF -C1431 divbuf_3/OUT5 divbuf_3/OUT 43.38fF -C1432 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF -C1433 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF -C1434 divider_2/tspc_2/Z3 divider_2/Out 0.05fF -C1435 divider_0/tspc_1/Z4 gnd 0.44fF -C1436 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF -C1437 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C1438 divider_1/Out gnd 0.29fF -C1439 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF -C1440 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C1441 divider_0/nor_1/B divider_0/nor_1/A 1.21fF -C1442 divider_2/tspc_0/Z4 divider_2/tspc_0/Z1 0.00fF -C1443 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/a_630_n680# 0.01fF -C1444 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF -C1445 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF -C1446 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 gnd 0.17fF -C1447 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C1448 divider_1/nor_1/B divider_1/tspc_2/Z2 0.20fF -C1449 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF -C1450 divider_2/tspc_0/Z3 divider_2/prescaler_0/Out 0.45fF -C1451 divider_2/and_0/A divider_2/and_0/B 0.18fF -C1452 divider_0/tspc_2/Z3 gnd 0.27fF -C1453 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C1454 divider_1/and_0/OUT divider_1/prescaler_0/tspc_0/D 0.03fF -C1455 divider_0/mc2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF -C1456 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z2 0.71fF -C1457 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF -C1458 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF -C1459 divider_1/tspc_1/Z4 divider_1/tspc_1/a_630_n680# 0.12fF -C1460 divider_0/tspc_0/Z4 divider_0/tspc_0/Z3 0.65fF -C1461 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C1462 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C1463 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF -C1464 divider_2/nor_1/A divider_2/prescaler_0/tspc_1/Q 0.03fF -C1465 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.05fF -C1466 divider_1/tspc_0/Z2 divider_1/tspc_0/Z3 0.16fF -C1467 divider_1/mc2 divider_1/and_0/B 0.20fF -C1468 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.01fF -C1469 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.19fF -C1470 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.14fF -C1471 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF -C1472 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF -C1473 divider_1/nor_0/B divider_1/tspc_2/Z4 0.22fF -C1474 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF -C1475 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1476 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z1 0.71fF -C1477 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_0/z1 0.24fF -C1478 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/Out 0.19fF -C1479 divider_1/nor_0/Z1 gnd 0.01fF -C1480 divider_1/prescaler_0/tspc_1/Z2 gnd 0.17fF -C1481 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C1482 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1483 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF -C1484 pd_1/tspc_r_0/Z2 pd_1/R 0.21fF -C1485 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z3 0.05fF -C1486 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF -C1487 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF -C1488 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z3 0.38fF -C1489 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C1490 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C1491 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/Z2 0.14fF -C1492 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF -C1493 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF -C1494 pll_full_0/divider_0/nor_0/B pll_full_0/divbuf_0/IN 0.29fF -C1495 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.29fF -C1496 gnd pll_full_0/divider_0/prescaler_0/Out 0.46fF -C1497 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF -C1498 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF -C1499 ro_complete_1/a0 ro_complete_1/cbank_2/switch_4/vin 0.13fF -C1500 ro_complete_1/cbank_0/v ro_complete_1/cbank_1/v 1.27fF -C1501 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF -C1502 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.26fF -C1503 divider_0/tspc_1/Q gnd 0.33fF -C1504 divider_1/prescaler_0/tspc_2/D gnd 0.05fF -C1505 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF -C1506 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF -C1507 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF -C1508 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1509 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z3 0.25fF -C1510 pd_1/tspc_r_0/Qbar1 pd_1/tspc_r_0/z5 0.20fF -C1511 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DOWN 0.03fF -C1512 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF -C1513 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF -C1514 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF -C1515 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF -C1516 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF -C1517 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C1518 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C1519 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C1520 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.01fF -C1521 divbuf_0/OUT5 divbuf_0/OUT4 20.26fF -C1522 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF -C1523 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Q 0.04fF -C1524 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF -C1525 divider_2/tspc_0/Z4 divider_2/nor_1/A 0.21fF -C1526 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF -C1527 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C1528 divider_2/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF -C1529 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF -C1530 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF -C1531 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/tspc_0/Z3 0.05fF -C1532 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF -C1533 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF -C1534 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 gnd 0.16fF -C1535 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C1536 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C1537 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF -C1538 divider_1/tspc_0/Z3 divider_1/prescaler_0/Out 0.45fF -C1539 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.64fF -C1540 divider_1/nor_1/B divider_1/and_0/A 0.26fF -C1541 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF -C1542 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF -C1543 divider_2/nor_1/A gnd 1.02fF -C1544 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/cbank_0/v 1.30fF -C1545 divider_0/and_0/B gnd 0.45fF -C1546 divider_2/and_0/OUT gnd 0.28fF -C1547 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF -C1548 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF -C1549 divider_1/tspc_1/Z4 divider_1/nor_1/B 0.21fF -C1550 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z3 0.05fF -C1551 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF -C1552 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF -C1553 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF -C1554 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF -C1555 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF -C1556 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF -C1557 io_clamp_low[0] io_clamp_high[0] 0.53fF -C1558 divider_2/tspc_0/Z3 divider_2/tspc_0/Z2 0.16fF -C1559 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF -C1560 divbuf_6/OUT2 divbuf_6/OUT 0.06fF -C1561 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF -C1562 divider_1/prescaler_0/tspc_2/Z2 gnd 0.16fF -C1563 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF -C1564 pd_1/DOWN pd_1/tspc_r_0/z5 0.03fF -C1565 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF -C1566 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C1567 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF -C1568 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C1569 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF -C1570 divider_0/nor_1/A divider_0/and_0/A 0.01fF -C1571 divider_1/nor_1/B divider_1/tspc_1/Z1 0.03fF -C1572 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF -C1573 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF -C1574 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF -C1575 divider_2/nor_1/B divider_2/tspc_0/Q 0.22fF -C1576 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF -C1577 divider_1/tspc_0/Z4 gnd 0.44fF -C1578 pll_full_0/pd_0/DIV gnd 0.01fF -C1579 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT2 1.37fF -C1580 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF -C1581 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF -C1582 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF -C1583 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF -C1584 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF -C1585 cp_0/a_1710_0# cp_0/out 0.84fF -C1586 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF -C1587 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C1588 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C1589 divider_1/tspc_0/Z4 divider_1/nor_1/A 0.21fF -C1590 divider_0/nor_0/B divider_0/and_0/B 0.29fF -C1591 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF -C1592 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF -C1593 divider_2/mc2 divider_2/and_0/out1 0.06fF -C1594 divider_2/tspc_1/a_630_n680# divider_2/tspc_0/Q 0.01fF -C1595 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF -C1596 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Q 0.04fF -C1597 divider_0/tspc_2/Z4 gnd 0.44fF +C0 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF +C1 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF +C2 divider_0/prescaler_0/Out gnd 0.46fF +C3 divider_0/mc2 divider_0/and_0/A 0.16fF +C4 ro_complete_1/a2 ro_complete_1/cbank_2/switch_3/vin 0.09fF +C5 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF +C6 divider_2/tspc_0/Z4 gnd 0.44fF +C7 divider_0/and_0/out1 divider_0/and_0/B 0.18fF +C8 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF +C9 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/switch_5/vin 0.20fF +C10 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C11 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C12 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C13 divider_1/tspc_1/Z3 divider_1/tspc_1/Z4 0.65fF +C14 divbuf_11/OUT2 divbuf_11/OUT5 0.02fF +C15 divbuf_11/OUT3 divbuf_11/OUT4 5.16fF +C16 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/Out 0.05fF +C17 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF +C18 divider_1/prescaler_0/Out divider_1/clk 0.51fF +C19 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF +C20 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divbuf_0/IN 0.05fF +C21 gnd pll_full_0/divider_0/tspc_0/Z3 0.27fF +C22 divbuf_18/OUT2 divbuf_18/OUT 0.06fF +C23 divider_2/tspc_0/Z1 divider_2/tspc_0/Z2 1.07fF +C24 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF +C25 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF +C26 divbuf_13/a_492_n240# divbuf_13/OUT2 0.42fF +C27 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF +C28 divider_1/tspc_0/Q gnd 0.33fF +C29 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/a_740_n680# 0.08fF +C30 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF +C31 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF +C32 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF +C33 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT4 20.26fF +C34 divider_2/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF +C35 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C36 pll_full_0/divider_0/nor_1/B gnd 1.17fF +C37 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/a_630_n680# 0.19fF +C38 divider_1/tspc_1/Q divider_1/tspc_2/Z2 0.14fF +C39 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF +C40 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF +C41 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z2 1.07fF +C42 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF +C43 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF +C44 pd_1/REF pd_1/tspc_r_1/z5 0.04fF +C45 divider_2/and_0/OUT divider_2/clk 0.04fF +C46 divider_0/prescaler_0/tspc_2/Z2 gnd 0.16fF +C47 divbuf_9/IN divbuf_9/OUT5 0.00fF +C48 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF +C49 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C50 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF +C51 divider_0/nor_1/A divider_0/tspc_0/Z3 0.38fF +C52 divbuf_2/OUT5 divbuf_2/OUT 43.38fF +C53 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF +C54 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF +C55 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C56 divider_2/prescaler_0/tspc_1/Q gnd 0.83fF +C57 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF +C58 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF +C59 divbuf_21/OUT2 divbuf_21/OUT 0.06fF +C60 divbuf_21/OUT3 divbuf_21/OUT5 0.01fF +C61 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C62 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 gnd 0.44fF +C63 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/Out 0.19fF +C64 divider_1/prescaler_0/tspc_0/Q divider_1/prescaler_0/nand_1/z1 0.01fF +C65 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/Out 0.05fF +C66 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF +C67 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF +C68 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF +C69 divider_2/nor_1/B divider_2/tspc_1/Z3 0.38fF +C70 divider_2/tspc_0/Z1 divider_2/nor_1/A 0.03fF +C71 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF +C72 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF +C73 pll_full_0/pd_0/DIV pll_full_0/pd_0/R 0.51fF +C74 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF +C75 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT 0.06fF +C76 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT5 0.01fF +C77 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C78 divider_0/nor_1/B divider_0/nor_1/A 1.21fF +C79 divbuf_15/OUT4 divbuf_15/OUT 1.11fF +C80 ro_complete_1/a5 ro_complete_1/cbank_1/v 0.10fF +C81 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/cbank_0/v 1.30fF +C82 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C83 divider_2/tspc_0/Z3 gnd 0.27fF +C84 divider_1/tspc_1/Z3 divider_1/tspc_1/Z1 0.06fF +C85 divider_1/tspc_1/Q divider_1/nor_1/B 0.51fF +C86 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF +C87 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF +C88 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF +C89 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF +C90 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF +C91 gnd pll_full_0/divider_0/tspc_2/Z2 0.16fF +C92 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.26fF +C93 divbuf_18/a_492_n240# divbuf_18/OUT2 0.42fF +C94 divbuf_23/OUT2 divbuf_23/OUT5 0.02fF +C95 divbuf_23/OUT3 divbuf_23/OUT4 5.16fF +C96 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF +C97 pd_1/DOWN pd_1/tspc_r_0/Qbar1 0.11fF +C98 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF +C99 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF +C100 divider_2/tspc_0/a_630_n680# gnd 0.62fF +C101 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/a_630_n680# 0.19fF +C102 divider_0/mc2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF +C103 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF +C104 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF +C105 divider_2/tspc_1/a_630_n680# gnd 0.62fF +C106 divider_0/tspc_0/Z4 divider_0/tspc_0/Z3 0.65fF +C107 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C108 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF +C109 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF +C110 divbuf_10/OUT3 divbuf_10/OUT 0.26fF +C111 divbuf_10/OUT4 divbuf_10/OUT5 20.26fF +C112 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C113 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF +C114 pd_1/R pd_1/tspc_r_1/Qbar1 0.30fF +C115 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF +C116 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF +C117 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C118 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF +C119 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C120 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C121 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF +C122 divider_1/prescaler_0/tspc_1/Z2 gnd 0.17fF +C123 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF +C124 ro_complete_1/a2 ro_complete_1/cbank_1/v 0.05fF +C125 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF +C126 divider_2/prescaler_0/tspc_2/Z4 gnd 0.44fF +C127 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Q 0.04fF +C128 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF +C129 divbuf_4/OUT4 divbuf_4/OUT 1.11fF +C130 divider_2/mc2 divider_2/nor_1/B 0.06fF +C131 divider_1/prescaler_0/tspc_1/Z4 divider_1/prescaler_0/Out 0.28fF +C132 pll_full_0/divider_0/tspc_1/Z3 gnd 0.27fF +C133 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.45fF +C134 divbuf_12/OUT2 divbuf_12/OUT 0.06fF +C135 divbuf_12/OUT3 divbuf_12/OUT5 0.01fF +C136 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.01fF +C137 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF +C138 divider_2/tspc_2/Z3 divider_2/Out 0.05fF +C139 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF +C140 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF +C141 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF +C142 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF +C143 ro_complete_1/a3 ro_complete_1/cbank_2/switch_1/vin 0.13fF +C144 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF +C145 divider_2/tspc_2/Z2 gnd 0.16fF +C146 divider_1/prescaler_0/m1_2700_2190# divider_1/and_0/OUT 0.14fF +C147 divbuf_15/OUT2 divbuf_15/OUT5 0.02fF +C148 divbuf_15/OUT3 divbuf_15/OUT4 5.16fF +C149 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF +C150 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF +C151 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF +C152 divbuf_18/OUT5 divbuf_18/OUT2 0.02fF +C153 divider_1/tspc_0/Q divider_1/nor_1/B 0.22fF +C154 divbuf_5/OUT4 divbuf_5/OUT 1.11fF +C155 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C156 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.32fF +C157 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF +C158 divider_1/and_0/OUT divider_1/and_0/B 0.01fF +C159 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/Out 0.91fF +C160 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF +C161 pll_full_0/divider_0/prescaler_0/tspc_0/Q gnd 0.35fF +C162 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z3 0.25fF +C163 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF +C164 io_clamp_low[2] io_clamp_high[2] 0.53fF +C165 divbuf_19/OUT2 divbuf_19/a_492_n240# 0.42fF +C166 divider_2/prescaler_0/tspc_1/Z4 divider_2/prescaler_0/tspc_2/a_740_n680# 0.01fF +C167 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_0/D 0.16fF +C168 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Q 0.05fF +C169 filter_0/a_4216_n2998# filter_0/v 0.31fF +C170 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF +C171 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF +C172 divider_2/and_0/A divider_2/and_0/B 0.18fF +C173 divider_0/tspc_0/Z2 gnd 0.16fF +C174 ro_complete_1/a2 ro_complete_1/cbank_0/switch_2/vin 0.14fF +C175 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a4 0.09fF +C176 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF +C177 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF +C178 io_clamp_high[1] io_analog[5] 0.53fF +C179 divider_1/prescaler_0/Out gnd 0.46fF +C180 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/v 1.30fF +C181 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF +C182 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF +C183 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/D 0.15fF +C184 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF +C185 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C186 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF +C187 divider_2/mc2 divider_2/and_0/out1 0.06fF +C188 divider_1/prescaler_0/Out divider_1/tspc_0/Z2 0.11fF +C189 divbuf_11/OUT3 divbuf_11/OUT 0.26fF +C190 divbuf_11/OUT4 divbuf_11/OUT5 20.26fF +C191 gnd pll_full_0/divider_0/and_0/A 0.69fF +C192 pd_1/tspc_r_0/Qbar1 pd_1/R 0.01fF +C193 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_0/z1 0.24fF +C194 divbuf_0/OUT divbuf_0/OUT2 0.06fF +C195 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF +C196 divider_1/tspc_1/a_630_n680# divider_1/tspc_0/Q 0.01fF +C197 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/a_630_n680# 0.12fF +C198 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF +C199 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF +C200 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF +C201 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF +C202 ro_complete_1/cbank_2/switch_2/vin ro_complete_1/cbank_2/v 1.30fF +C203 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C204 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF +C205 divbuf_20/a_492_n240# divbuf_20/OUT 0.00fF +C206 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C207 pll_full_0/divider_0/prescaler_0/m1_2700_2190# gnd 0.22fF +C208 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF +C209 pd_1/DIV pd_1/tspc_r_0/Z2 0.19fF +C210 pd_0/DOWN pd_0/R 0.36fF +C211 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF +C212 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF +C213 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF +C214 divbuf_18/a_492_n240# divbuf_18/IN 0.13fF +C215 divider_2/tspc_0/Q divider_2/tspc_1/Z2 0.14fF +C216 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/Z3 0.16fF +C217 pd_1/R pd_1/and_pd_0/Z1 0.02fF +C218 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF +C219 divbuf_9/OUT2 divbuf_9/OUT 0.06fF +C220 divbuf_9/OUT3 divbuf_9/OUT5 0.01fF +C221 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.26fF +C222 divider_0/nor_1/A gnd 1.02fF +C223 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF +C224 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF +C225 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF +C226 divider_1/prescaler_0/tspc_2/Z2 gnd 0.16fF +C227 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C228 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C229 divider_2/prescaler_0/tspc_0/Q gnd 0.35fF +C230 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF +C231 divider_0/nor_1/A divider_0/and_0/A 0.01fF +C232 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF +C233 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_1/z1 0.21fF +C234 divbuf_21/OUT4 divbuf_21/OUT 1.11fF +C235 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF +C236 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF +C237 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF +C238 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF +C239 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF +C240 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF +C241 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF +C242 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF +C243 divbuf_8/a_492_n240# divbuf_8/OUT5 0.01fF +C244 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF +C245 divbuf_15/a_492_n240# divbuf_15/OUT 0.00fF +C246 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF +C247 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF +C248 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF +C249 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF +C250 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF +C251 pll_full_0/divbuf_1/OUT4 pll_full_0/divbuf_1/OUT 1.11fF +C252 divbuf_3/IN divbuf_3/OUT5 0.00fF +C253 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C254 divider_2/and_0/A gnd 0.53fF +C255 divider_0/nor_0/B divider_0/and_0/B 0.29fF +C256 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF +C257 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF +C258 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/A 0.55fF +C259 divbuf_17/OUT5 divbuf_17/OUT3 0.01fF +C260 divider_2/mc2 divider_2/prescaler_0/tspc_0/a_630_n680# 0.33fF +C261 divider_2/nor_1/Z1 divider_2/and_0/A 0.80fF +C262 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF +C263 gnd pll_full_0/divbuf_0/IN 3.72fF +C264 pd_1/DOWN pd_1/R 0.36fF +C265 divider_2/nor_1/B divider_2/nor_0/B 0.47fF +C266 divider_0/tspc_0/Z4 gnd 0.44fF +C267 divbuf_23/OUT3 divbuf_23/OUT 0.26fF +C268 divbuf_23/OUT4 divbuf_23/OUT5 20.26fF +C269 divbuf_25/OUT5 divbuf_25/a_492_n240# 0.01fF +C270 divider_2/prescaler_0/tspc_0/Z2 gnd 0.16fF +C271 divbuf_3/OUT4 divbuf_3/OUT 1.11fF +C272 ro_complete_1/a1 ro_complete_1/cbank_2/v 0.05fF +C273 divbuf_10/OUT5 divbuf_10/OUT 43.38fF +C274 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF +C275 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# gnd 0.94fF +C276 divbuf_18/OUT5 divbuf_18/IN 0.00fF +C277 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF +C278 divider_1/nor_0/Z1 divider_1/and_0/B 0.78fF +C279 divbuf_22/a_492_n240# divbuf_22/OUT 0.00fF +C280 divider_2/tspc_0/Q divider_2/tspc_1/Z1 0.01fF +C281 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z2 0.11fF +C282 divbuf_17/OUT2 divbuf_17/OUT3 1.37fF +C283 divider_0/tspc_1/Z2 gnd 0.16fF +C284 divbuf_15/a_492_n240# divbuf_15/IN 0.13fF +C285 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF +C286 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF +C287 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF +C288 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF +C289 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C290 divbuf_21/a_492_n240# divbuf_21/IN 0.13fF +C291 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF +C292 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF +C293 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF +C294 divbuf_12/OUT4 divbuf_12/OUT 1.11fF +C295 pd_0/R pd_0/tspc_r_1/Z3 0.29fF +C296 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF +C297 cp_0/a_10_n50# cp_0/vbias 0.19fF +C298 divbuf_24/a_492_n240# divbuf_24/OUT5 0.01fF +C299 divbuf_2/OUT2 divbuf_2/a_492_n240# 0.42fF +C300 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF +C301 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF +C302 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF +C303 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF +C304 divbuf_16/OUT divbuf_16/OUT3 0.26fF +C305 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_0/D 0.16fF +C306 divbuf_15/OUT3 divbuf_15/OUT 0.26fF +C307 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF +C308 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF +C309 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C310 divider_2/Out gnd 0.29fF +C311 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF +C312 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF +C313 divider_1/tspc_0/Z3 divider_1/tspc_0/a_630_n680# 0.05fF +C314 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF +C315 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/Out 0.15fF +C316 pll_full_0/divider_0/prescaler_0/tspc_2/D gnd 0.05fF +C317 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.64fF +C318 divider_1/nor_0/B divider_1/tspc_2/Z1 0.03fF +C319 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF +C320 pd_1/tspc_r_0/Qbar pd_1/tspc_r_0/Qbar1 0.01fF +C321 divider_2/tspc_1/Z2 divider_2/nor_1/A 0.15fF +C322 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF +C323 divider_1/prescaler_0/tspc_0/Z4 gnd 0.44fF +C324 filter_0/a_4216_n5230# filter_0/v 0.19fF +C325 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF +C326 io_clamp_low[0] io_analog[4] 0.53fF +C327 divbuf_25/OUT5 divbuf_25/OUT2 0.02fF +C328 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF +C329 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF +C330 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF +C331 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/v 1.45fF +C332 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF +C333 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C334 divbuf_10/a_492_n240# divbuf_10/OUT2 0.42fF +C335 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/A 0.03fF +C336 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C337 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z4 0.12fF +C338 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/D 0.05fF +C339 divbuf_11/OUT5 divbuf_11/OUT 43.38fF +C340 divider_1/and_0/out1 divider_1/and_0/B 0.18fF +C341 divider_1/tspc_0/Z1 divider_1/tspc_0/Z2 1.07fF +C342 divbuf_13/a_492_n240# divbuf_13/OUT 0.00fF +C343 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z3 0.09fF +C344 pd_1/tspc_r_1/Z2 pd_1/REF 0.19fF +C345 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/z5 0.11fF +C346 divider_2/and_0/OUT divider_2/prescaler_0/tspc_0/Q 0.04fF +C347 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF +C348 divbuf_0/OUT divbuf_0/OUT3 0.26fF +C349 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF +C350 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF +C351 divbuf_25/OUT5 divbuf_25/OUT3 0.01fF +C352 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF +C353 divider_0/nor_1/B divider_0/and_0/B 0.31fF +C354 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF +C355 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF +C356 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/OUT3 1.37fF +C357 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C358 divider_2/prescaler_0/tspc_1/Z2 gnd 0.17fF +C359 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF +C360 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/switch_5/vin 0.20fF +C361 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C362 divbuf_20/IN divbuf_20/OUT5 0.00fF +C363 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z3 0.65fF +C364 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C365 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF +C366 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C367 divider_2/tspc_0/a_630_n680# divider_2/nor_1/B 0.01fF +C368 divider_1/nor_1/A divider_1/prescaler_0/tspc_1/Q 0.03fF +C369 divbuf_12/a_492_n240# divbuf_12/IN 0.13fF +C370 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF +C371 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF +C372 divider_2/tspc_1/a_630_n680# divider_2/nor_1/B 0.35fF +C373 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/Z4 0.36fF +C374 divbuf_9/OUT4 divbuf_9/OUT 1.11fF +C375 cp_0/a_1710_n2840# cp_0/out 0.61fF +C376 divbuf_17/OUT4 divbuf_17/OUT3 5.16fF +C377 divider_2/tspc_2/a_630_n680# divider_2/nor_0/B 0.35fF +C378 divider_0/tspc_1/Z4 gnd 0.44fF +C379 divider_1/nor_1/A gnd 1.02fF +C380 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF +C381 divbuf_1/OUT5 divbuf_1/IN 0.00fF +C382 divbuf_16/OUT divbuf_16/a_492_n240# 0.00fF +C383 divider_0/and_0/OUT divider_0/clk 0.04fF +C384 divider_2/prescaler_0/tspc_2/D gnd 0.05fF +C385 divbuf_19/OUT3 divbuf_19/OUT4 5.16fF +C386 divider_1/tspc_0/Q divider_1/tspc_1/Z2 0.14fF +C387 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z3 0.33fF +C388 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF +C389 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF +C390 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF +C391 divider_1/nor_1/A divider_1/tspc_0/Z2 0.23fF +C392 divbuf_8/OUT2 divbuf_8/OUT3 1.37fF +C393 pd_1/DIV pd_1/tspc_r_0/z5 0.04fF +C394 pd_1/tspc_r_0/Qbar pd_1/DOWN 0.21fF +C395 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF +C396 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF +C397 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.05fF +C398 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF +C399 divider_2/prescaler_0/Out divider_2/tspc_0/Z2 0.11fF +C400 divider_0/tspc_2/Z3 gnd 0.27fF +C401 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF +C402 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF +C403 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF +C404 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF +C405 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_2/a_740_n680# 0.01fF +C406 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF +C407 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF +C408 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF +C409 divbuf_19/OUT2 divbuf_19/OUT5 0.02fF +C410 divider_2/mc2 divider_2/nor_0/B 0.15fF +C411 divbuf_11/a_492_n240# divbuf_11/OUT2 0.42fF +C412 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF +C413 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF +C414 divbuf_23/OUT5 divbuf_23/OUT 43.38fF +C415 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF +C416 divider_2/nor_1/B divider_2/tspc_2/Z2 0.20fF +C417 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF +C418 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF +C419 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF +C420 ro_complete_1/cbank_1/switch_5/vin ro_complete_1/cbank_1/v 1.30fF +C421 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF +C422 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF +C423 pll_full_0/divider_0/tspc_1/a_630_n680# gnd 0.62fF +C424 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_0/D 0.16fF +C425 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.05fF +C426 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF +C427 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Q 0.20fF +C428 divbuf_22/IN divbuf_22/OUT5 0.00fF +C429 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF +C430 divbuf_9/a_492_n240# divbuf_9/IN 0.13fF +C431 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Out1 0.05fF +C432 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z3 0.09fF +C433 divider_2/nor_1/A divider_2/prescaler_0/Out 0.15fF +C434 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.14fF +C435 divider_0/tspc_1/Q gnd 0.33fF +C436 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF +C437 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF +C438 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF +C439 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF +C440 divbuf_1/OUT4 divbuf_1/OUT3 5.16fF +C441 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C442 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF +C443 divbuf_14/OUT2 divbuf_14/a_492_n240# 0.42fF +C444 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF +C445 divbuf_18/OUT4 divbuf_18/OUT 1.11fF +C446 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/Out 0.21fF +C447 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C448 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF +C449 pd_0/R pd_0/UP 0.45fF +C450 divbuf_17/OUT divbuf_17/OUT3 0.26fF +C451 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z3 0.05fF +C452 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF +C453 divbuf_24/OUT2 divbuf_24/OUT3 1.37fF +C454 divider_0/nor_1/B divider_0/tspc_0/a_630_n680# 0.01fF +C455 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF +C456 divbuf_16/OUT divbuf_16/OUT5 43.38fF +C457 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF +C458 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF +C459 divider_0/tspc_2/Z3 divider_0/Out 0.05fF +C460 divider_1/tspc_0/Z3 divider_1/tspc_0/Z4 0.65fF +C461 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF +C462 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF +C463 divider_1/nor_0/B divider_1/tspc_2/Z3 0.38fF +C464 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF +C465 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF +C466 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF +C467 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z2 0.23fF +C468 gnd pll_full_0/divider_0/prescaler_0/nand_1/z1 0.16fF +C469 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF +C470 pd_0/UP pd_0/and_pd_0/Out1 0.33fF +C471 io_clamp_low[1] io_clamp_high[1] 0.53fF +C472 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF +C473 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF +C474 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF +C475 divbuf_23/a_492_n240# divbuf_23/OUT2 0.42fF +C476 divider_2/and_0/B divider_2/and_0/Z1 0.07fF +C477 divider_0/and_0/B gnd 0.45fF +C478 divbuf_2/OUT2 divbuf_2/OUT 0.06fF +C479 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF +C480 ro_complete_1/a0 ro_complete_1/cbank_1/switch_5/vin 0.09fF +C481 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF +C482 divider_0/and_0/A divider_0/and_0/B 0.18fF +C483 divider_1/nor_1/B divider_1/nor_1/A 1.21fF +C484 gnd pll_full_0/divider_0/and_0/Z1 0.32fF +C485 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF +C486 divider_2/tspc_1/Q divider_2/tspc_2/Z1 0.01fF +C487 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF +C488 divider_2/nor_1/B divider_2/and_0/A 0.26fF +C489 divbuf_13/IN divbuf_13/OUT5 0.00fF +C490 divbuf_25/OUT divbuf_25/OUT4 1.11fF +C491 divbuf_0/OUT divbuf_0/OUT4 1.11fF +C492 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF +C493 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF +C494 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF +C495 divbuf_16/OUT divbuf_16/OUT4 1.11fF +C496 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z2 0.36fF +C497 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF +C498 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF +C499 ro_complete_1/a2 ro_complete_1/cbank_2/switch_2/vin 0.14fF +C500 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF +C501 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/v 1.30fF +C502 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.44fF +C503 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF +C504 divbuf_20/OUT2 divbuf_20/OUT 0.06fF +C505 divbuf_20/OUT3 divbuf_20/OUT5 0.01fF +C506 divider_1/and_0/OUT divider_1/prescaler_0/tspc_0/D 0.03fF +C507 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF +C508 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.45fF +C509 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF +C510 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C511 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF +C512 divider_2/tspc_0/Q divider_2/nor_1/A 0.55fF +C513 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF +C514 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF +C515 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF +C516 divbuf_2/IN divbuf_2/OUT5 0.00fF +C517 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C518 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF +C519 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF +C520 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C521 divider_1/tspc_1/Z4 gnd 0.44fF +C522 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF +C523 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_0/vin 0.19fF +C524 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C525 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C526 divider_2/prescaler_0/nand_1/z1 gnd 0.16fF +C527 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF +C528 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z3 0.05fF +C529 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF +C530 divider_1/nor_1/A divider_1/and_0/A 0.01fF +C531 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF +C532 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF +C533 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF +C534 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF +C535 divbuf_8/OUT2 divbuf_8/OUT5 0.02fF +C536 divbuf_8/OUT3 divbuf_8/OUT4 5.16fF +C537 divider_2/and_0/out1 divider_2/and_0/A 0.01fF +C538 divider_0/tspc_2/Z4 gnd 0.44fF +C539 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF +C540 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF +C541 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF +C542 divider_1/tspc_2/Z3 gnd 0.27fF +C543 divider_2/and_0/Z1 gnd 0.41fF +C544 divbuf_6/OUT3 divbuf_6/OUT 0.26fF +C545 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF +C546 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C547 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF +C548 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF +C549 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF +C550 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF +C551 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/clk 0.05fF +C552 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/Out 0.04fF +C553 divider_1/nor_0/B divider_1/and_0/B 0.29fF +C554 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF +C555 divider_2/prescaler_0/tspc_2/Z3 gnd 0.27fF +C556 divbuf_18/OUT4 divbuf_18/OUT5 20.26fF +C557 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF +C558 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF +C559 divider_1/mc2 divider_1/nor_1/A 0.04fF +C560 ro_complete_1/cbank_0/v ro_complete_1/cbank_2/v 0.04fF +C561 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/A 0.15fF +C562 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C563 divbuf_22/OUT2 divbuf_22/OUT 0.06fF +C564 divbuf_22/OUT3 divbuf_22/OUT5 0.01fF +C565 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF +C566 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Q 0.04fF +C567 pd_1/REF pd_1/tspc_r_1/Z3 0.65fF +C568 divider_2/nor_1/A divider_2/tspc_0/Z2 0.23fF +C569 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF +C570 divider_0/tspc_0/a_630_n680# gnd 0.62fF +C571 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF +C572 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF +C573 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF +C574 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF +C575 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF +C576 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF +C577 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF +C578 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C579 divbuf_21/a_492_n240# divbuf_21/OUT5 0.01fF +C580 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C581 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C582 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF +C583 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/Out 0.04fF +C584 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF +C585 divbuf_24/OUT2 divbuf_24/OUT5 0.02fF +C586 divbuf_24/OUT3 divbuf_24/OUT4 5.16fF +C587 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF +C588 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF +C589 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF +C590 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF +C591 ro_complete_1/a4 ro_complete_1/cbank_2/switch_0/vin 0.12fF +C592 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF +C593 divbuf_7/OUT3 divbuf_7/OUT 0.26fF +C594 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF +C595 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z2 0.01fF +C596 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF +C597 divider_1/nor_0/B divider_1/tspc_2/Z4 0.22fF +C598 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.00fF +C599 divider_2/tspc_0/Z4 divider_2/tspc_0/Z3 0.65fF +C600 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF +C601 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF +C602 divider_1/prescaler_0/m1_2700_2190# gnd 0.22fF +C603 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF +C604 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF +C605 divider_1/and_0/B gnd 0.45fF +C606 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF +C607 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF +C608 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF +C609 ro_complete_1/a0 ro_complete_1/cbank_1/v 0.05fF +C610 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z4 0.12fF +C611 divider_1/nor_1/B divider_1/tspc_1/Z4 0.21fF +C612 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF +C613 divbuf_10/a_492_n240# divbuf_10/OUT 0.00fF +C614 pll_full_0/divider_0/tspc_0/Q gnd 0.33fF +C615 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF +C616 divider_2/mc2 divider_2/and_0/A 0.16fF +C617 divbuf_13/OUT2 divbuf_13/OUT 0.06fF +C618 divbuf_13/OUT3 divbuf_13/OUT5 0.01fF +C619 pd_1/tspc_r_1/Qbar pd_1/UP 0.21fF +C620 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/DIV 0.17fF +C621 divider_2/tspc_1/Q divider_2/tspc_2/Z3 0.45fF +C622 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/Out 0.08fF +C623 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF +C624 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C625 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF +C626 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF +C627 divider_1/prescaler_0/tspc_0/Z3 gnd 0.27fF +C628 divbuf_1/OUT divbuf_1/OUT4 1.11fF +C629 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF +C630 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_4/vin 0.20fF +C631 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF +C632 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C633 divider_2/tspc_1/Z2 gnd 0.16fF +C634 divbuf_14/OUT2 divbuf_14/OUT 0.06fF +C635 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF +C636 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF +C637 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF +C638 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF +C639 ro_complete_1/cbank_2/switch_0/vin ro_complete_1/cbank_2/v 1.44fF +C640 divbuf_19/OUT3 divbuf_19/OUT5 0.01fF +C641 divbuf_16/OUT3 divbuf_16/OUT5 0.01fF +C642 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF +C643 divbuf_20/OUT4 divbuf_20/OUT 1.11fF +C644 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF +C645 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF +C646 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 gnd 0.17fF +C647 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C648 divbuf_12/a_492_n240# divbuf_12/OUT5 0.01fF +C649 divider_2/tspc_0/Q divider_2/tspc_1/Z4 0.15fF +C650 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF +C651 divider_2/nor_0/B divider_2/tspc_2/Z2 0.40fF +C652 divider_2/tspc_2/a_630_n680# divider_2/Out 0.04fF +C653 divider_2/prescaler_0/tspc_0/Q divider_2/clk 0.05fF +C654 divider_0/and_0/OUT gnd 0.28fF +C655 ro_complete_1/a2 ro_complete_1/cbank_1/switch_3/vin 0.09fF +C656 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF +C657 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF +C658 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF +C659 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF +C660 pll_full_0/pd_0/DIV gnd 0.01fF +C661 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C662 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z4 0.12fF +C663 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF +C664 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF +C665 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF +C666 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C667 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C668 divider_1/and_0/OUT divider_1/clk 0.04fF +C669 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.01fF +C670 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.19fF +C671 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.14fF +C672 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF +C673 pd_0/REF pd_0/tspc_r_1/z5 0.04fF +C674 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF +C675 divbuf_8/OUT3 divbuf_8/OUT 0.26fF +C676 divbuf_8/OUT4 divbuf_8/OUT5 20.26fF +C677 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF +C678 divider_1/tspc_2/Z4 gnd 0.44fF +C679 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF +C680 divbuf_3/OUT2 divbuf_3/OUT 0.06fF +C681 ro_complete_1/a3 ro_complete_1/cbank_1/v 0.05fF +C682 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C683 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C684 divider_0/prescaler_0/Out divider_0/tspc_0/Z2 0.11fF +C685 divbuf_6/OUT5 divbuf_6/OUT 43.38fF +C686 divbuf_16/OUT4 divbuf_16/OUT3 5.16fF +C687 divider_1/tspc_1/Z2 divider_1/nor_1/A 0.15fF +C688 divider_1/nor_1/B divider_1/tspc_1/Z1 0.03fF +C689 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF +C690 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z3 0.38fF +C691 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C692 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C693 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z3 0.05fF +C694 divider_2/nor_0/Z1 divider_2/and_0/B 0.78fF +C695 divbuf_11/a_492_n240# divbuf_11/OUT 0.00fF +C696 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF +C697 pll_full_0/divider_0/nor_0/B pll_full_0/divbuf_0/IN 0.29fF +C698 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.29fF +C699 gnd pll_full_0/divider_0/prescaler_0/Out 0.46fF +C700 pd_1/tspc_r_1/Z2 pd_1/R 0.21fF +C701 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF +C702 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF +C703 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF +C704 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF +C705 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_4/vin 0.20fF +C706 divbuf_25/a_492_n240# divbuf_25/IN 0.13fF +C707 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF +C708 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF +C709 divbuf_20/a_492_n240# divbuf_20/IN 0.13fF +C710 divbuf_16/a_492_n240# divbuf_16/OUT5 0.01fF +C711 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF +C712 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C713 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C714 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C715 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF +C716 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF +C717 divbuf_22/OUT4 divbuf_22/OUT 1.11fF +C718 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF +C719 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF +C720 divbuf_9/a_492_n240# divbuf_9/OUT5 0.01fF +C721 divider_0/mc2 divider_0/nor_1/A 0.04fF +C722 divider_1/tspc_0/a_630_n680# gnd 0.62fF +C723 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a1 0.14fF +C724 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/a3 0.09fF +C725 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF +C726 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C727 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF +C728 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF +C729 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF +C730 ro_complete_1/cbank_2/switch_5/vin ro_complete_1/cbank_2/v 1.30fF +C731 divbuf_21/OUT2 divbuf_21/OUT3 1.37fF +C732 divider_1/nor_1/B divider_1/and_0/B 0.31fF +C733 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z2 0.01fF +C734 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF +C735 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C736 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 gnd 0.16fF +C737 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C738 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF +C739 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF +C740 pd_1/and_pd_0/Out1 pd_1/and_pd_0/Z1 0.18fF +C741 divbuf_24/OUT3 divbuf_24/OUT 0.26fF +C742 divbuf_24/OUT4 divbuf_24/OUT5 20.26fF +C743 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF +C744 divbuf_14/OUT3 divbuf_14/OUT2 1.37fF +C745 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF +C746 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF +C747 divbuf_3/IN divbuf_3/a_492_n240# 0.13fF +C748 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/v 1.30fF +C749 divider_2/prescaler_0/Out gnd 0.46fF +C750 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF +C751 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF +C752 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF +C753 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF +C754 divbuf_7/OUT5 divbuf_7/OUT 43.38fF +C755 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF +C756 divider_1/tspc_2/Z3 divider_1/Out 0.05fF +C757 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF +C758 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF +C759 io_clamp_low[0] io_clamp_high[0] 0.53fF +C760 divider_2/nor_1/A divider_2/tspc_1/Z4 0.02fF +C761 divider_1/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF +C762 divbuf_23/a_492_n240# divbuf_23/OUT 0.00fF +C763 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF +C764 divider_2/nor_0/Z1 gnd 0.01fF +C765 divider_0/tspc_0/Z4 divider_0/prescaler_0/Out 0.12fF +C766 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF +C767 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF +C768 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF +C769 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF +C770 divbuf_16/OUT divbuf_16/OUT2 0.06fF +C771 divider_0/and_0/B divider_0/and_0/Z1 0.07fF +C772 divbuf_10/IN divbuf_10/OUT5 0.00fF +C773 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF +C774 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C775 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF +C776 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C777 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Q 0.05fF +C778 divbuf_22/a_492_n240# divbuf_22/IN 0.13fF +C779 divider_1/and_0/A divider_1/and_0/B 0.18fF +C780 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF +C781 divider_2/tspc_1/Q divider_2/tspc_2/Z4 0.15fF +C782 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/Q 0.19fF +C783 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/Out 0.11fF +C784 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF +C785 divbuf_13/OUT4 divbuf_13/OUT 1.11fF +C786 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/switch_1/vin 0.19fF +C787 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF +C788 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF +C789 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF +C790 divider_0/tspc_0/Z4 divider_0/tspc_0/Z1 0.00fF +C791 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF +C792 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF +C793 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF +C794 divider_1/tspc_1/Z3 gnd 0.27fF +C795 divbuf_14/OUT4 divbuf_14/OUT 1.11fF +C796 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF +C797 divider_2/tspc_1/Q gnd 0.33fF +C798 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF +C799 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF +C800 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C801 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C802 divbuf_19/OUT4 divbuf_19/OUT 1.11fF +C803 divider_1/nor_1/B divider_1/tspc_2/Z4 0.02fF +C804 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_0/z1 0.24fF +C805 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/Out 0.19fF +C806 divbuf_12/OUT2 divbuf_12/OUT3 1.37fF +C807 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF +C808 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF +C809 divider_2/nor_0/B divider_2/Out 0.22fF +C810 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.29fF +C811 divider_0/prescaler_0/tspc_0/D gnd 0.05fF +C812 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF +C813 divider_1/and_0/OUT gnd 0.28fF +C814 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF +C815 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF +C816 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF +C817 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C818 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C819 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z3 0.16fF +C820 divider_1/mc2 divider_1/and_0/B 0.20fF +C821 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF +C822 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF +C823 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C824 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF +C825 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF +C826 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.32fF +C827 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C828 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.26fF +C829 divbuf_8/OUT5 divbuf_8/OUT 43.38fF +C830 pd_0/R pd_0/and_pd_0/Z1 0.02fF +C831 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF +C832 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_2/a_740_n680# 0.01fF +C833 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/R 0.01fF +C834 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF +C835 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF +C836 divider_0/and_0/out1 gnd 0.23fF +C837 io_clamp_high[2] io_analog[6] 0.53fF +C838 divbuf_14/OUT5 divbuf_14/OUT2 0.02fF +C839 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF +C840 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF +C841 divider_2/tspc_0/Q gnd 0.33fF +C842 divbuf_17/OUT5 divbuf_17/a_492_n240# 0.01fF +C843 divider_0/and_0/out1 divider_0/and_0/A 0.01fF +C844 ro_complete_1/a4 ro_complete_1/cbank_2/v 0.05fF +C845 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_0/vin 0.19fF +C846 divbuf_16/OUT4 divbuf_16/OUT5 20.26fF +C847 divbuf_16/IN divbuf_16/a_492_n240# 0.13fF +C848 divider_1/nor_1/B divider_1/tspc_0/a_630_n680# 0.01fF +C849 divider_1/tspc_1/Z2 divider_1/tspc_1/Z4 0.36fF +C850 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF +C851 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C852 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C853 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF +C854 divbuf_11/IN divbuf_11/OUT5 0.00fF +C855 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF +C856 gnd pll_full_0/divider_0/tspc_0/Z2 0.16fF +C857 divbuf_18/OUT3 divbuf_18/OUT 0.26fF +C858 divbuf_13/a_492_n240# divbuf_13/IN 0.13fF +C859 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Qbar1 0.38fF +C860 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF +C861 divbuf_19/OUT divbuf_19/a_492_n240# 0.00fF +C862 divider_0/prescaler_0/tspc_0/Z3 gnd 0.27fF +C863 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF +C864 divider_1/tspc_0/Z3 gnd 0.27fF +C865 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF +C866 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF +C867 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF +C868 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C869 divider_1/tspc_1/Q divider_1/tspc_2/Z1 0.01fF +C870 divider_1/nor_1/Z1 divider_1/and_0/B 0.18fF +C871 divider_1/tspc_0/Z3 divider_1/tspc_0/Z2 0.16fF +C872 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.01fF +C873 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF +C874 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/A 0.35fF +C875 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C876 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C877 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C878 pd_0/DIV pd_0/R 0.51fF +C879 divbuf_17/a_492_n240# divbuf_17/OUT2 0.42fF +C880 divbuf_9/OUT2 divbuf_9/OUT3 1.37fF +C881 pd_1/R pd_1/and_pd_0/Out1 0.33fF +C882 pd_1/tspc_r_1/Qbar1 pd_1/UP 0.11fF +C883 pd_1/REF pd_1/tspc_r_1/Z4 0.02fF +C884 divider_2/nor_1/A divider_2/and_0/B 0.08fF +C885 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF +C886 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C887 divider_1/tspc_0/Z4 gnd 0.44fF +C888 divbuf_2/OUT4 divbuf_2/OUT 1.11fF +C889 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a1 0.14fF +C890 divbuf_14/OUT divbuf_14/a_492_n240# 0.00fF +C891 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF +C892 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF +C893 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF +C894 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF +C895 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF +C896 divider_1/tspc_0/Z4 divider_1/tspc_0/Z2 0.36fF +C897 divbuf_21/OUT2 divbuf_21/OUT5 0.02fF +C898 divbuf_21/OUT3 divbuf_21/OUT4 5.16fF +C899 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF +C900 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C901 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/Out 0.08fF +C902 pll_full_0/divider_0/nor_1/A gnd 1.05fF +C903 divbuf_8/a_492_n240# divbuf_8/OUT2 0.42fF +C904 pd_1/DIV pd_1/tspc_r_0/Qbar1 0.12fF +C905 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF +C906 divider_2/nor_1/B divider_2/tspc_1/Z2 0.30fF +C907 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF +C908 divbuf_24/OUT5 divbuf_24/OUT 43.38fF +C909 divider_0/tspc_2/a_630_n680# gnd 0.61fF +C910 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT5 0.02fF +C911 divbuf_14/OUT3 divbuf_14/OUT4 5.16fF +C912 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF +C913 ro_complete_1/a5 ro_complete_1/cbank_2/switch_0/vin 0.09fF +C914 divbuf_15/OUT4 divbuf_15/OUT5 20.26fF +C915 divbuf_14/a_492_n240# divbuf_14/IN 0.13fF +C916 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C917 divider_2/tspc_0/Z2 gnd 0.16fF +C918 divider_1/tspc_1/Z2 divider_1/tspc_1/Z1 1.07fF +C919 divider_1/tspc_1/Z3 divider_1/nor_1/B 0.38fF +C920 divider_1/tspc_0/Q divider_1/nor_1/A 0.55fF +C921 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF +C922 divbuf_23/IN divbuf_23/OUT5 0.00fF +C923 pd_1/DOWN pd_1/tspc_r_0/Z3 0.03fF +C924 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF +C925 divider_1/nor_0/Z1 gnd 0.01fF +C926 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF +C927 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF +C928 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF +C929 divider_0/nor_1/B divider_0/nor_0/B 0.47fF +C930 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF +C931 divider_0/tspc_0/Q divider_0/tspc_0/Z3 0.05fF +C932 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF +C933 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF +C934 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF +C935 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C936 divbuf_19/OUT3 divbuf_19/OUT2 1.37fF +C937 divbuf_16/IN divbuf_16/OUT5 0.00fF +C938 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF +C939 divbuf_10/OUT2 divbuf_10/OUT 0.06fF +C940 divbuf_10/OUT3 divbuf_10/OUT5 0.01fF +C941 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF +C942 divider_2/tspc_0/Z4 divider_2/tspc_0/Z1 0.00fF +C943 pd_1/R pd_1/tspc_r_1/Z3 0.29fF +C944 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/D 0.32fF +C945 divider_2/prescaler_0/tspc_1/Z4 divider_2/prescaler_0/Out 0.28fF +C946 divider_0/prescaler_0/tspc_1/Z3 gnd 0.27fF +C947 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF +C948 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF +C949 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF +C950 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF +C951 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF +C952 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C953 divider_2/nor_1/A gnd 1.02fF +C954 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z3 0.05fF +C955 divbuf_4/OUT3 divbuf_4/OUT 0.26fF +C956 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF +C957 divider_1/and_0/OUT divider_1/prescaler_0/tspc_0/Q 0.04fF +C958 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF +C959 pll_full_0/divider_0/tspc_1/Z2 gnd 0.16fF +C960 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF +C961 pd_0/DOWN pd_0/UP 0.46fF +C962 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF +C963 divider_2/nor_1/B divider_2/tspc_1/Z1 0.03fF +C964 divbuf_12/OUT2 divbuf_12/OUT5 0.02fF +C965 divbuf_12/OUT3 divbuf_12/OUT4 5.16fF +C966 divbuf_24/a_492_n240# divbuf_24/OUT2 0.42fF +C967 pd_1/UP pd_1/and_pd_0/Z1 0.06fF +C968 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF +C969 divider_0/prescaler_0/nand_0/z1 gnd 0.16fF +C970 divbuf_25/OUT3 divbuf_25/OUT4 5.16fF +C971 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF +C972 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF +C973 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF +C974 divider_1/prescaler_0/tspc_0/D gnd 0.05fF +C975 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/a0 0.13fF +C976 divbuf_18/OUT5 divbuf_18/OUT3 0.01fF +C977 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF +C978 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF +C979 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF +C980 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF +C981 divbuf_5/OUT3 divbuf_5/OUT 0.26fF +C982 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF +C983 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF +C984 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C985 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF +C986 divbuf_16/OUT3 divbuf_16/OUT2 1.37fF +C987 divider_1/tspc_2/a_630_n680# divider_1/nor_0/B 0.35fF +C988 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.04fF +C989 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C990 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z3 0.09fF +C991 divbuf_19/IN divbuf_19/a_492_n240# 0.13fF +C992 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF +C993 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF +C994 divider_0/clk gnd 0.07fF +C995 io_clamp_low[1] io_analog[5] 0.53fF +C996 divbuf_14/OUT5 divbuf_14/OUT4 20.26fF +C997 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF +C998 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF +C999 divider_0/mc2 divider_0/and_0/B 0.20fF +C1000 divbuf_1/OUT5 divbuf_1/OUT 43.38fF +C1001 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF +C1002 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF +C1003 divider_1/and_0/out1 gnd 0.23fF +C1004 ro_complete_1/a1 ro_complete_1/cbank_1/v 0.05fF +C1005 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C1006 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.61fF +C1007 divider_1/prescaler_0/tspc_0/Z2 divider_1/and_0/OUT 0.05fF +C1008 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.64fF +C1009 divbuf_11/OUT2 divbuf_11/OUT 0.06fF +C1010 divbuf_11/OUT3 divbuf_11/OUT5 0.01fF +C1011 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF +C1012 pd_1/DOWN pd_1/UP 0.46fF +C1013 pd_1/tspc_r_0/Z3 pd_1/R 0.27fF +C1014 divider_2/tspc_0/Z1 divider_2/tspc_0/Z3 0.06fF +C1015 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF +C1016 divider_0/prescaler_0/tspc_0/Z4 gnd 0.44fF +C1017 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF +C1018 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF +C1019 divider_1/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF +C1020 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF +C1021 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF +C1022 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF +C1023 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF +C1024 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF +C1025 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C1026 divider_1/mc2 divider_1/and_0/OUT 0.05fF +C1027 divbuf_20/a_492_n240# divbuf_20/OUT5 0.01fF +C1028 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/Out 0.12fF +C1029 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C1030 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C1031 divider_2/nor_0/Z1 divider_2/nor_1/B 0.18fF +C1032 divider_1/tspc_1/Q divider_1/tspc_2/Z3 0.45fF +C1033 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF +C1034 pd_1/DIV pd_1/tspc_r_0/Z1 0.17fF +C1035 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF +C1036 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF +C1037 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF +C1038 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z3 0.06fF +C1039 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF +C1040 divider_0/prescaler_0/tspc_2/Z3 gnd 0.27fF +C1041 divbuf_9/OUT2 divbuf_9/OUT5 0.02fF +C1042 divbuf_9/OUT3 divbuf_9/OUT4 5.16fF +C1043 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF +C1044 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF +C1045 ro_complete_1/a4 ro_complete_1/cbank_2/switch_1/vin 0.09fF +C1046 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/v 1.30fF +C1047 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1048 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF +C1049 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF +C1050 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF +C1051 divider_1/nor_0/Z1 divider_1/nor_1/B 0.18fF +C1052 divbuf_21/OUT3 divbuf_21/OUT 0.26fF +C1053 divbuf_21/OUT4 divbuf_21/OUT5 20.26fF +C1054 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF +C1055 pll_full_0/divider_0/tspc_1/Z4 gnd 0.44fF +C1056 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/Out 0.11fF +C1057 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF +C1058 divbuf_17/OUT divbuf_17/a_492_n240# 0.00fF +C1059 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF +C1060 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/a_740_n680# 0.33fF +C1061 divbuf_16/a_492_n240# divbuf_16/OUT2 0.42fF +C1062 divider_1/nor_1/A divider_1/prescaler_0/Out 0.15fF +C1063 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.64fF +C1064 pd_1/DIV pd_1/R 0.51fF +C1065 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF +C1066 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF +C1067 divider_2/nor_1/B divider_2/tspc_1/Q 0.51fF +C1068 divider_0/nor_0/B gnd 1.08fF +C1069 divbuf_15/a_492_n240# divbuf_15/OUT5 0.01fF +C1070 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF +C1071 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF +C1072 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT 0.26fF +C1073 pll_full_0/divbuf_1/OUT4 pll_full_0/divbuf_1/OUT5 20.26fF +C1074 divider_1/tspc_2/a_630_n680# gnd 0.61fF +C1075 divbuf_15/OUT5 divbuf_15/OUT 43.38fF +C1076 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF +C1077 ro_complete_1/a3 ro_complete_1/cbank_2/switch_2/vin 0.09fF +C1078 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF +C1079 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF +C1080 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF +C1081 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF +C1082 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1083 divider_1/tspc_0/Q divider_1/tspc_1/Z4 0.15fF +C1084 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF +C1085 gnd pll_full_0/divider_0/tspc_2/Z3 0.27fF +C1086 divider_0/tspc_0/Q gnd 0.33fF +C1087 divbuf_23/OUT2 divbuf_23/OUT 0.06fF +C1088 divbuf_23/OUT3 divbuf_23/OUT5 0.01fF +C1089 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF +C1090 divider_2/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF +C1091 divbuf_14/OUT5 divbuf_14/a_492_n240# 0.01fF +C1092 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF +C1093 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF +C1094 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF +C1095 divbuf_1/OUT2 divbuf_1/OUT 0.06fF +C1096 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a3 0.13fF +C1097 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF +C1098 divbuf_3/OUT3 divbuf_3/OUT 0.26fF +C1099 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/v 1.30fF +C1100 divbuf_10/OUT4 divbuf_10/OUT 1.11fF +C1101 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF +C1102 divbuf_17/IN divbuf_17/a_492_n240# 0.13fF +C1103 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF +C1104 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF +C1105 divbuf_22/a_492_n240# divbuf_22/OUT5 0.01fF +C1106 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF +C1107 divbuf_19/OUT5 divbuf_19/OUT 43.38fF +C1108 divider_2/tspc_0/Q divider_2/nor_1/B 0.22fF +C1109 divider_1/and_0/B divider_1/and_0/Z1 0.07fF +C1110 pd_1/R pd_1/UP 0.45fF +C1111 divider_2/prescaler_0/tspc_0/Q divider_2/prescaler_0/tspc_2/D 0.04fF +C1112 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF +C1113 divider_0/prescaler_0/tspc_1/Z4 gnd 0.44fF +C1114 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF +C1115 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C1116 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF +C1117 divider_1/prescaler_0/tspc_1/Z3 gnd 0.27fF +C1118 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF +C1119 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF +C1120 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/v 1.30fF +C1121 divbuf_15/IN divbuf_15/OUT5 0.00fF +C1122 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF +C1123 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF +C1124 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF +C1125 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF +C1126 divider_2/tspc_1/Z4 gnd 0.44fF +C1127 divbuf_4/OUT5 divbuf_4/OUT 43.38fF +C1128 pll_full_0/divider_0/tspc_1/Q gnd 0.33fF +C1129 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF +C1130 divbuf_12/OUT3 divbuf_12/OUT 0.26fF +C1131 divbuf_12/OUT4 divbuf_12/OUT5 20.26fF +C1132 pd_0/R pd_0/REF 0.61fF +C1133 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF +C1134 divider_0/prescaler_0/tspc_1/Q gnd 0.83fF +C1135 divbuf_2/IN divbuf_2/a_492_n240# 0.13fF +C1136 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF +C1137 divider_1/prescaler_0/nand_0/z1 gnd 0.16fF +C1138 divbuf_15/a_492_n240# divbuf_15/OUT2 0.42fF +C1139 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF +C1140 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF +C1141 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF +C1142 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF +C1143 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_4/vin 0.20fF +C1144 divbuf_15/OUT2 divbuf_15/OUT 0.06fF +C1145 divbuf_15/OUT3 divbuf_15/OUT5 0.01fF +C1146 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF +C1147 divider_0/nor_0/B divider_0/Out 0.22fF +C1148 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF +C1149 divider_2/tspc_2/Z3 gnd 0.27fF +C1150 divider_1/tspc_0/Q divider_1/tspc_1/Z1 0.01fF +C1151 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF +C1152 divbuf_5/OUT5 divbuf_5/OUT 43.38fF +C1153 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF +C1154 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C1155 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF +C1156 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF +C1157 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF +C1158 divbuf_16/OUT5 divbuf_16/OUT2 0.02fF +C1159 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF +C1160 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF +C1161 divider_2/tspc_1/Z3 divider_2/tspc_1/Q 0.05fF +C1162 divider_0/nor_0/Z1 gnd 0.01fF +C1163 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF +C1164 divider_0/tspc_0/Z3 gnd 0.27fF +C1165 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/v 1.30fF +C1166 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF +C1167 divider_1/clk gnd 0.07fF +C1168 divbuf_25/OUT5 divbuf_25/IN 0.00fF +C1169 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF +C1170 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF +C1171 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF +C1172 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF +C1173 ro_complete_1/a5 ro_complete_1/cbank_2/v 0.08fF +C1174 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF +C1175 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C1176 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Q 0.20fF +C1177 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/D 0.09fF +C1178 divbuf_10/a_492_n240# divbuf_10/IN 0.13fF +C1179 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C1180 divbuf_11/OUT4 divbuf_11/OUT 1.11fF +C1181 gnd pll_full_0/divider_0/and_0/B 0.66fF +C1182 divider_1/and_0/out1 divider_1/and_0/A 0.01fF +C1183 divbuf_13/a_492_n240# divbuf_13/OUT5 0.01fF +C1184 pd_1/tspc_r_1/Z1 pd_1/REF 0.17fF +C1185 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Z4 0.20fF +C1186 divider_2/tspc_1/Q divider_2/tspc_2/a_630_n680# 0.01fF +C1187 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/Out 0.11fF +C1188 divider_0/nor_1/B gnd 1.10fF +C1189 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF +C1190 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF +C1191 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF +C1192 divider_1/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF +C1193 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C1194 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF +C1195 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF +C1196 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF +C1197 divider_0/nor_1/B divider_0/and_0/A 0.26fF +C1198 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF +C1199 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF +C1200 divider_1/tspc_1/Q divider_1/tspc_2/Z4 0.15fF +C1201 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF +C1202 divbuf_20/OUT2 divbuf_20/OUT3 1.37fF +C1203 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF +C1204 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF +C1205 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/Z3 0.05fF +C1206 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1207 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C1208 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.01fF +C1209 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF +C1210 divider_2/tspc_0/Q divider_2/tspc_1/Z3 0.45fF +C1211 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z4 0.00fF +C1212 divbuf_9/OUT3 divbuf_9/OUT 0.26fF +C1213 divbuf_9/OUT4 divbuf_9/OUT5 20.26fF +C1214 pd_1/UP pd_1/tspc_r_1/z5 0.03fF +C1215 divider_0/prescaler_0/tspc_2/Z4 gnd 0.44fF +C1216 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF +C1217 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF +C1218 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF +C1219 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF +C1220 divider_1/prescaler_0/tspc_2/Z3 gnd 0.27fF +C1221 divider_0/mc2 divider_0/and_0/OUT 0.05fF +C1222 ro_complete_1/a2 ro_complete_1/cbank_2/v 0.05fF +C1223 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C1224 divbuf_15/OUT2 divbuf_15/OUT3 1.37fF +C1225 divider_0/nor_1/A divider_0/and_0/B 0.08fF +C1226 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF +C1227 divider_1/mc2 divider_1/and_0/out1 0.06fF +C1228 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/B 0.22fF +C1229 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C1230 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF +C1231 divider_1/nor_1/A divider_1/tspc_0/Z1 0.03fF +C1232 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF +C1233 divbuf_21/OUT5 divbuf_21/OUT 43.38fF +C1234 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/Out 0.28fF +C1235 pd_1/DIV pd_1/tspc_r_0/Z4 0.02fF +C1236 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF +C1237 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF +C1238 divbuf_8/a_492_n240# divbuf_8/OUT 0.00fF +C1239 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF +C1240 divider_2/nor_1/B divider_2/nor_1/A 1.21fF +C1241 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C1242 divider_2/prescaler_0/Out divider_2/clk 0.51fF +C1243 divider_0/tspc_2/Z2 gnd 0.16fF +C1244 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF +C1245 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF +C1246 divider_1/nor_0/B gnd 1.08fF +C1247 divbuf_14/OUT3 divbuf_14/OUT 0.26fF +C1248 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF +C1249 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C1250 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF +C1251 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF +C1252 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF +C1253 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/a0 0.09fF +C1254 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1255 divider_2/and_0/B gnd 0.45fF +C1256 divbuf_6/IN divbuf_6/OUT5 0.00fF +C1257 divider_2/nor_1/Z1 divider_2/and_0/B 0.18fF +C1258 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/A 0.21fF +C1259 divbuf_19/IN divbuf_19/OUT5 0.00fF +C1260 divbuf_11/a_492_n240# divbuf_11/IN 0.13fF +C1261 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF +C1262 gnd pll_full_0/divider_0/tspc_2/Z4 0.44fF +C1263 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/Out 0.91fF +C1264 divbuf_23/OUT4 divbuf_23/OUT 1.11fF +C1265 divider_0/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF +C1266 divbuf_25/OUT divbuf_25/a_492_n240# 0.00fF +C1267 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF +C1268 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF +C1269 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C1270 divider_2/prescaler_0/tspc_0/Z3 gnd 0.27fF +C1271 divbuf_3/OUT5 divbuf_3/OUT 43.38fF +C1272 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF +C1273 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C1274 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF +C1275 divbuf_22/OUT2 divbuf_22/OUT3 1.37fF +C1276 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z3 0.45fF +C1277 divider_2/prescaler_0/tspc_0/Q divider_2/prescaler_0/nand_1/z1 0.01fF +C1278 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/Out 0.21fF +C1279 divider_0/tspc_1/Z3 gnd 0.27fF +C1280 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF +C1281 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C1282 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF +C1283 divider_1/prescaler_0/tspc_1/Z4 gnd 0.44fF +C1284 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF +C1285 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF +C1286 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF +C1287 divbuf_21/a_492_n240# divbuf_21/OUT2 0.42fF +C1288 pll_full_0/divider_0/tspc_0/a_630_n680# gnd 0.62fF +C1289 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF +C1290 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1291 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z2 0.71fF +C1292 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF +C1293 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF +C1294 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z2 0.01fF +C1295 divbuf_12/OUT5 divbuf_12/OUT 43.38fF +C1296 divbuf_24/a_492_n240# divbuf_24/OUT 0.00fF +C1297 divider_0/prescaler_0/tspc_0/Q gnd 0.35fF +C1298 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF +C1299 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF +C1300 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF +C1301 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1302 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF +C1303 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF +C1304 divider_1/prescaler_0/tspc_1/Q gnd 0.83fF +C1305 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF +C1306 divider_2/tspc_2/Z4 gnd 0.44fF +C1307 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF +C1308 divider_1/tspc_1/Z3 divider_1/tspc_1/Q 0.05fF +C1309 divider_1/tspc_0/Q divider_1/tspc_0/a_630_n680# 0.04fF +C1310 divbuf_7/IN divbuf_7/OUT5 0.00fF +C1311 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.03fF +C1312 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF +C1313 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF +C1314 divider_1/nor_0/B divider_1/tspc_2/Z2 0.40fF +C1315 divider_1/tspc_2/a_630_n680# divider_1/Out 0.04fF +C1316 divider_1/prescaler_0/tspc_0/Q divider_1/clk 0.05fF +C1317 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C1318 pd_1/tspc_r_0/Z2 pd_1/R 0.21fF +C1319 divider_2/tspc_0/Z4 divider_2/prescaler_0/Out 0.12fF +C1320 divider_2/nor_1/Z1 gnd 0.01fF +C1321 divbuf_23/a_492_n240# divbuf_23/IN 0.13fF +C1322 divider_0/and_0/A gnd 0.53fF +C1323 io_clamp_high[0] io_analog[4] 0.53fF +C1324 divbuf_25/OUT divbuf_25/OUT2 0.06fF +C1325 divbuf_14/OUT5 divbuf_14/OUT 43.38fF +C1326 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF +C1327 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF +C1328 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF +C1329 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF +C1330 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF +C1331 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF +C1332 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF +C1333 divider_1/tspc_0/Z2 gnd 0.16fF +C1334 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/Out 0.11fF +C1335 ro_complete_1/a0 ro_complete_1/cbank_2/switch_4/vin 0.13fF +C1336 ro_complete_1/cbank_0/v ro_complete_1/cbank_1/v 1.27fF +C1337 pll_full_0/divider_0/nor_1/Z1 gnd 0.01fF +C1338 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.01fF +C1339 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Q 0.04fF +C1340 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z3 0.25fF +C1341 pd_1/tspc_r_0/Qbar1 pd_1/tspc_r_0/z5 0.20fF +C1342 divider_2/tspc_1/Q divider_2/nor_0/B 0.22fF +C1343 divider_0/prescaler_0/m1_2700_2190# gnd 0.22fF +C1344 divbuf_13/OUT2 divbuf_13/OUT3 1.37fF +C1345 divbuf_0/OUT5 divbuf_0/OUT4 20.26fF +C1346 divbuf_25/OUT divbuf_25/OUT3 0.26fF +C1347 divbuf_25/OUT5 divbuf_25/OUT4 20.26fF +C1348 divider_0/tspc_0/Q divider_0/tspc_1/a_630_n680# 0.01fF +C1349 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C1350 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF +C1351 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z1 0.00fF +C1352 divbuf_14/OUT5 divbuf_14/IN 0.00fF +C1353 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF +C1354 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF +C1355 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF +C1356 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF +C1357 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C1358 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF +C1359 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF +C1360 divider_2/prescaler_0/tspc_1/Z3 gnd 0.27fF +C1361 divbuf_20/OUT2 divbuf_20/OUT5 0.02fF +C1362 divbuf_20/OUT3 divbuf_20/OUT4 5.16fF +C1363 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C1364 divider_1/nor_1/B divider_1/nor_0/B 0.47fF +C1365 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF +C1366 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.03fF +C1367 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF +C1368 divbuf_12/a_492_n240# divbuf_12/OUT2 0.42fF +C1369 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF +C1370 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF +C1371 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z4 0.65fF +C1372 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF +C1373 divider_2/and_0/OUT divider_2/and_0/B 0.01fF +C1374 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/Out 0.91fF +C1375 divbuf_9/OUT5 divbuf_9/OUT 43.38fF +C1376 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF +C1377 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF +C1378 divider_0/tspc_0/Z4 divider_0/tspc_0/a_630_n680# 0.12fF +C1379 divider_1/prescaler_0/tspc_2/Z4 gnd 0.44fF +C1380 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/cbank_0/v 1.30fF +C1381 divider_1/tspc_0/Q divider_1/tspc_1/Z3 0.45fF +C1382 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z2 0.01fF +C1383 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF +C1384 pll_full_0/divider_0/and_0/OUT gnd 0.32fF +C1385 divider_2/mc2 divider_2/nor_1/A 0.04fF +C1386 divbuf_8/IN divbuf_8/OUT5 0.00fF +C1387 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF +C1388 divbuf_18/a_492_n240# divbuf_18/OUT 0.00fF +C1389 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_1/A 0.01fF +C1390 divider_2/nor_1/B divider_2/tspc_1/Z4 0.21fF +C1391 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF +C1392 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.15fF +C1393 divider_2/prescaler_0/Out divider_2/tspc_0/Z3 0.45fF +C1394 divider_0/Out gnd 0.29fF +C1395 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF +C1396 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/a_492_n240# 0.42fF +C1397 divider_1/tspc_2/Z2 gnd 0.16fF +C1398 divider_0/mc2 divider_0/and_0/out1 0.06fF +C1399 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF +C1400 divider_1/tspc_1/a_630_n680# divider_1/nor_0/B 0.00fF +C1401 divider_1/mc2 divider_1/prescaler_0/tspc_0/a_630_n680# 0.33fF +C1402 divbuf_6/OUT2 divbuf_6/OUT 0.06fF +C1403 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF +C1404 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF +C1405 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF +C1406 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF +C1407 divbuf_19/OUT2 divbuf_19/OUT 0.06fF +C1408 divider_2/tspc_0/a_630_n680# divider_2/prescaler_0/Out 0.01fF +C1409 pd_1/DOWN pd_1/tspc_r_0/z5 0.03fF +C1410 divider_0/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF +C1411 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C1412 divider_2/prescaler_0/tspc_2/Z2 gnd 0.16fF +C1413 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF +C1414 divider_2/prescaler_0/tspc_0/Z4 gnd 0.44fF +C1415 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF +C1416 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C1417 divbuf_18/OUT3 divbuf_18/OUT2 1.37fF +C1418 divider_1/nor_1/A divider_1/tspc_1/Z4 0.02fF +C1419 divbuf_22/OUT2 divbuf_22/OUT5 0.02fF +C1420 divbuf_22/OUT3 divbuf_22/OUT4 5.16fF +C1421 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF +C1422 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF +C1423 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF +C1424 divbuf_9/a_492_n240# divbuf_9/OUT2 0.42fF +C1425 cp_0/a_1710_0# cp_0/out 0.84fF +C1426 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF +C1427 pll_full_0/cp_0/a_1710_0# pll_full_0/pd_0/DOWN 0.04fF +C1428 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z3 0.25fF +C1429 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_1/z1 0.21fF +C1430 divider_0/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF +C1431 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF +C1432 divider_1/nor_1/B gnd 1.10fF +C1433 divbuf_14/OUT3 divbuf_14/OUT5 0.01fF +C1434 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF +C1435 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF +C1436 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1437 divider_2/and_0/OUT gnd 0.28fF +C1438 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF +C1439 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF +C1440 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF +C1441 divider_1/tspc_0/Z3 divider_1/tspc_0/Q 0.05fF +C1442 divider_1/mc2 divider_1/nor_0/B 0.15fF +C1443 divbuf_18/OUT5 divbuf_18/OUT 43.38fF +C1444 divider_1/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.01fF +C1445 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/Q 0.19fF +C1446 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.14fF +C1447 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C1448 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C1449 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/Out 0.11fF +C1450 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Q 0.04fF +C1451 divbuf_24/IN divbuf_24/OUT5 0.00fF +C1452 divider_0/prescaler_0/tspc_2/D gnd 0.05fF +C1453 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a4 0.12fF +C1454 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF +C1455 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF +C1456 divider_1/prescaler_0/tspc_0/Q gnd 0.35fF +C1457 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF +C1458 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF +C1459 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF +C1460 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF +C1461 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z3 0.33fF +C1462 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF +C1463 divider_1/nor_0/B divider_1/Out 0.22fF +C1464 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.29fF +C1465 divbuf_7/OUT2 divbuf_7/OUT 0.06fF +C1466 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF +C1467 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z3 0.38fF +C1468 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z4 0.14fF +C1469 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF +C1470 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF +C1471 divider_2/tspc_0/Z4 divider_2/tspc_0/Z2 0.36fF +C1472 divider_2/tspc_0/Q divider_2/tspc_0/Z3 0.05fF +C1473 divider_1/tspc_1/a_630_n680# gnd 0.62fF +C1474 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF +C1475 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF +C1476 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF +C1477 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF +C1478 divider_1/and_0/A gnd 0.53fF +C1479 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF +C1480 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF +C1481 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Q 0.04fF +C1482 divider_1/prescaler_0/tspc_1/Z2 divider_1/and_0/OUT 0.06fF +C1483 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF +C1484 divbuf_10/a_492_n240# divbuf_10/OUT5 0.01fF +C1485 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C1486 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.20fF +C1487 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_1/A 1.21fF +C1488 divider_2/tspc_0/Q divider_2/tspc_1/a_630_n680# 0.01fF +C1489 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF +C1490 divbuf_13/OUT2 divbuf_13/OUT5 0.02fF +C1491 divbuf_13/OUT3 divbuf_13/OUT4 5.16fF +C1492 pd_1/tspc_r_1/Qbar pd_1/tspc_r_1/Qbar1 0.01fF +C1493 divider_2/nor_1/B divider_2/and_0/B 0.31fF +C1494 divider_2/tspc_1/Q divider_2/tspc_2/Z2 0.14fF +C1495 divider_0/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF +C1496 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF +C1497 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF +C1498 divider_1/prescaler_0/tspc_0/Z2 gnd 0.16fF +C1499 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF +C1500 divider_2/prescaler_0/tspc_1/Z4 gnd 0.44fF +C1501 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z3 0.65fF +C1502 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF +C1503 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF +C1504 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF +C1505 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF +C1506 divbuf_18/OUT5 divbuf_18/a_492_n240# 0.01fF +C1507 divbuf_17/OUT5 divbuf_17/OUT2 0.02fF +C1508 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF +C1509 divider_1/nor_1/B divider_1/tspc_2/Z2 0.20fF +C1510 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF +C1511 divbuf_20/OUT3 divbuf_20/OUT 0.26fF +C1512 divbuf_20/OUT4 divbuf_20/OUT5 20.26fF +C1513 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF +C1514 divider_2/tspc_0/Z4 divider_2/nor_1/A 0.21fF +C1515 divider_2/nor_0/B divider_2/tspc_2/Z1 0.03fF +C1516 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF +C1517 divider_1/mc2 gnd 1.36fF +C1518 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF +C1519 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1520 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF +C1521 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF +C1522 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF +C1523 divider_2/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF +C1524 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/switch_5/vin 0.20fF +C1525 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C1526 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_1/A 0.01fF +C1527 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.06fF +C1528 divider_1/nor_1/A divider_1/and_0/B 0.08fF +C1529 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF +C1530 pll_full_0/divider_0/prescaler_0/tspc_0/D gnd 0.05fF +C1531 pd_0/R pd_0/and_pd_0/Out1 0.33fF +C1532 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF +C1533 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF +C1534 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF +C1535 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF +C1536 divbuf_8/OUT2 divbuf_8/OUT 0.06fF +C1537 divbuf_8/OUT3 divbuf_8/OUT5 0.01fF +C1538 divider_2/and_0/out1 divider_2/and_0/B 0.18fF +C1539 divider_2/tspc_0/Z2 divider_2/tspc_0/Z3 0.16fF +C1540 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1541 divider_1/Out gnd 0.29fF +C1542 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/v 1.30fF +C1543 divider_0/prescaler_0/Out divider_0/clk 0.51fF +C1544 divbuf_6/OUT4 divbuf_6/OUT 1.11fF +C1545 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z2 0.30fF +C1546 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1547 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF +C1548 divider_1/prescaler_0/tspc_1/Z4 divider_1/prescaler_0/tspc_2/a_740_n680# 0.01fF +C1549 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z2 0.01fF +C1550 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF +C1551 divbuf_11/a_492_n240# divbuf_11/OUT5 0.01fF +C1552 gnd pll_full_0/divider_0/and_0/out1 0.29fF +C1553 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF +C1554 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF +C1555 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF +C1556 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF +C1557 divider_2/nor_1/A divider_2/prescaler_0/tspc_1/Q 0.03fF +C1558 divider_2/nor_1/B divider_2/tspc_2/Z4 0.02fF +C1559 divider_0/tspc_1/a_630_n680# gnd 0.62fF +C1560 divbuf_0/OUT5 divbuf_0/OUT 43.38fF +C1561 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF +C1562 divider_1/nor_1/Z1 gnd 0.01fF +C1563 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF +C1564 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF +C1565 divider_2/nor_1/B gnd 1.10fF +C1566 ro_complete_1/a0 ro_complete_1/cbank_2/switch_5/vin 0.09fF +C1567 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1568 divider_2/nor_1/Z1 divider_2/nor_1/B 0.06fF +C1569 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 gnd 0.27fF +C1570 divider_1/tspc_1/Q divider_1/tspc_2/a_630_n680# 0.01fF +C1571 divider_1/tspc_0/Z3 divider_1/prescaler_0/Out 0.45fF +C1572 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF +C1573 divider_1/prescaler_0/tspc_2/Z2 divider_1/and_0/OUT 0.06fF +C1574 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF +C1575 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF +C1576 divbuf_22/OUT3 divbuf_22/OUT 0.26fF +C1577 divbuf_22/OUT4 divbuf_22/OUT5 20.26fF +C1578 cp_0/a_1710_0# cp_0/down 0.32fF +C1579 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF +C1580 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Z1 0.02fF +C1581 pd_1/REF pd_1/tspc_r_1/Qbar1 0.12fF +C1582 divider_2/nor_1/A divider_2/tspc_0/Z3 0.38fF +C1583 divider_0/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF +C1584 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF +C1585 divider_1/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF +C1586 divider_1/tspc_1/a_630_n680# divider_1/nor_1/B 0.35fF +C1587 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF +C1588 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF +C1589 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF +C1590 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF +C1591 divider_2/prescaler_0/tspc_0/D gnd 0.05fF +C1592 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C1593 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C1594 divbuf_17/OUT5 divbuf_17/OUT4 20.26fF +C1595 divbuf_21/a_492_n240# divbuf_21/OUT 0.00fF +C1596 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF +C1597 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C1598 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C1599 divider_2/tspc_0/a_630_n680# divider_2/nor_1/A 0.35fF +C1600 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/a_740_n680# 0.19fF +C1601 divider_1/tspc_0/Z4 divider_1/prescaler_0/Out 0.12fF +C1602 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/D 0.32fF +C1603 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF +C1604 divider_1/nor_1/B divider_1/and_0/A 0.26fF +C1605 pd_0/R pd_0/tspc_r_1/Z2 0.21fF +C1606 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF +C1607 divider_0/prescaler_0/nand_1/z1 gnd 0.16fF +C1608 divbuf_24/OUT2 divbuf_24/OUT 0.06fF +C1609 divbuf_24/OUT3 divbuf_24/OUT5 0.01fF +C1610 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF +C1611 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF +C1612 divider_0/mc2 divider_0/nor_0/B 0.15fF +C1613 divider_1/prescaler_0/tspc_2/D gnd 0.05fF +C1614 ro_complete_1/a4 ro_complete_1/cbank_1/v 0.05fF +C1615 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C1616 divider_2/and_0/out1 gnd 0.23fF +C1617 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF +C1618 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z1 0.03fF +C1619 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF +C1620 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF +C1621 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF +C1622 divbuf_7/OUT4 divbuf_7/OUT 1.11fF +C1623 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF +C1624 gnd pll_full_0/divider_0/tspc_2/a_630_n680# 0.61fF +C1625 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF +C1626 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z4 0.08fF +C1627 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z3 0.05fF +C1628 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF +C1629 pd_1/DOWN pd_1/tspc_r_1/Qbar 0.02fF +C1630 pd_0/UP pd_0/and_pd_0/Z1 0.06fF +C1631 divbuf_23/a_492_n240# divbuf_23/OUT5 0.01fF +C1632 divider_0/and_0/Z1 gnd 0.41fF +C1633 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF +C1634 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF +C1635 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C1636 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF +C1637 divider_1/mc2 divider_1/nor_1/B 0.06fF +C1638 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF +C1639 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1640 divbuf_10/OUT2 divbuf_10/OUT3 1.37fF +C1641 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_1/A 0.01fF +C1642 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF +C1643 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF +C1644 pll_full_0/divider_0/tspc_0/Z4 gnd 0.44fF +C1645 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.15fF +C1646 divider_1/tspc_1/Z1 divider_1/tspc_1/Z4 0.00fF +C1647 divider_1/tspc_0/a_630_n680# divider_1/nor_1/A 0.35fF +C1648 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF +C1649 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF +C1650 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF +C1651 divider_2/mc2 divider_2/and_0/B 0.20fF +C1652 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF +C1653 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF +C1654 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/DIV 0.19fF +C1655 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/Out 0.19fF +C1656 divbuf_13/OUT3 divbuf_13/OUT 0.26fF +C1657 divbuf_13/OUT4 divbuf_13/OUT5 20.26fF +C1658 divbuf_0/OUT5 divbuf_0/IN 0.00fF +C1659 divbuf_0/OUT2 divbuf_0/OUT3 1.37fF +C1660 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C1661 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF +C1662 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF +C1663 divider_1/tspc_1/Z2 gnd 0.16fF +C1664 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF +C1665 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF +C1666 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF +C1667 divider_2/tspc_1/Z3 gnd 0.27fF +C1668 divbuf_4/IN divbuf_4/OUT5 0.00fF +C1669 ro_complete_1/cbank_1/v ro_complete_1/cbank_2/v 1.36fF +C1670 divbuf_20/OUT5 divbuf_20/OUT 43.38fF +C1671 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 gnd 0.27fF +C1672 divbuf_19/OUT3 divbuf_19/OUT 0.26fF +C1673 divbuf_19/OUT4 divbuf_19/OUT5 20.26fF +C1674 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF +C1675 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/Out 0.08fF +C1676 divbuf_12/a_492_n240# divbuf_12/OUT 0.00fF +C1677 pd_1/UP pd_1/and_pd_0/Out1 0.33fF +C1678 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF +C1679 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF +C1680 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF +C1681 divider_2/nor_0/B divider_2/tspc_2/Z3 0.38fF +C1682 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF +C1683 divider_2/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF +C1684 ro_complete_1/a5 ro_complete_1/cbank_1/switch_0/vin 0.09fF +C1685 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/v 1.30fF +C1686 divbuf_17/OUT5 divbuf_17/OUT 43.38fF +C1687 divider_0/and_0/OUT divider_0/and_0/B 0.01fF +C1688 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF +C1689 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF +C1690 divider_2/tspc_2/a_630_n680# gnd 0.61fF +C1691 divider_1/mc2 divider_1/and_0/A 0.16fF +C1692 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z3 0.06fF +C1693 divider_1/nor_1/Z1 divider_1/nor_1/B 0.06fF +C1694 divbuf_5/IN divbuf_5/OUT5 0.00fF +C1695 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C1696 pll_full_0/divider_0/nor_0/Z1 gnd 0.01fF +C1697 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF +C1698 pll_full_0/divider_0/prescaler_0/nand_0/z1 gnd 0.16fF +C1699 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF +C1700 divbuf_8/OUT4 divbuf_8/OUT 1.11fF +C1701 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF +C1702 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF +C1703 divbuf_25/OUT5 divbuf_25/OUT 43.38fF +C1704 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/R 0.27fF +C1705 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF +C1706 ro_complete_1/a2 ro_complete_1/cbank_0/switch_3/vin 0.09fF +C1707 io_clamp_low[2] io_analog[6] 0.53fF +C1708 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C1709 ro_complete_1/cbank_1/switch_2/vin ro_complete_1/cbank_1/v 1.30fF +C1710 divider_0/prescaler_0/Out divider_0/tspc_0/Z3 0.45fF +C1711 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C1712 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF +C1713 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF +C1714 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF +C1715 divbuf_11/OUT2 divbuf_11/OUT3 1.37fF +C1716 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF +C1717 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF +C1718 gnd pll_full_0/divider_0/clk 0.08fF +C1719 divbuf_17/OUT divbuf_17/OUT2 0.06fF +C1720 pd_1/tspc_r_1/Qbar pd_1/R 0.03fF +C1721 divbuf_19/OUT5 divbuf_19/a_492_n240# 0.01fF +C1722 divider_2/and_0/OUT divider_2/prescaler_0/tspc_0/D 0.03fF +C1723 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.45fF +C1724 divider_0/prescaler_0/tspc_0/Z2 gnd 0.16fF +C1725 divider_0/mc2 divider_0/nor_1/B 0.06fF +C1726 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF +C1727 divider_2/mc2 gnd 1.36fF +C1728 divbuf_2/OUT5 divbuf_2/a_492_n240# 0.01fF +C1729 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/v 1.30fF +C1730 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF +C1731 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT3 0.01fF +C1732 divbuf_17/OUT5 divbuf_17/IN 0.00fF +C1733 divider_2/prescaler_0/m1_2700_2190# gnd 0.22fF +C1734 divbuf_25/a_492_n240# divbuf_25/OUT2 0.42fF +C1735 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF +C1736 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C1737 ro_complete_1/a0 ro_complete_1/cbank_2/v 0.05fF +C1738 divider_1/tspc_1/Q divider_1/nor_0/B 0.22fF +C1739 divider_1/tspc_0/Z3 divider_1/tspc_0/Z1 0.06fF +C1740 divider_1/nor_1/Z1 divider_1/and_0/A 0.80fF +C1741 divbuf_20/a_492_n240# divbuf_20/OUT2 0.42fF +C1742 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF +C1743 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C1744 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 gnd 0.44fF +C1745 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF +C1746 divbuf_22/OUT5 divbuf_22/OUT 43.38fF +C1747 divbuf_9/a_492_n240# divbuf_9/OUT 0.00fF +C1748 pd_1/tspc_r_1/Z3 pd_1/UP 0.03fF +C1749 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF +C1750 divider_2/nor_1/A divider_2/and_0/A 0.01fF +C1751 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1752 divider_1/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF +C1753 divbuf_2/OUT3 divbuf_2/OUT 0.26fF +C1754 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C1755 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1756 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF +C1757 divider_2/prescaler_0/nand_0/z1 gnd 0.16fF +C1758 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF +C1759 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF +C1760 divider_1/tspc_0/Z4 divider_1/tspc_0/Z1 0.00fF +C1761 divider_1/prescaler_0/tspc_0/Q divider_1/prescaler_0/tspc_2/D 0.04fF +C1762 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF +C1763 divbuf_21/IN divbuf_21/OUT5 0.00fF +C1764 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF +C1765 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF +C1766 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C1767 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 gnd 0.27fF +C1768 pd_1/DIV pd_1/tspc_r_0/Z3 0.65fF +C1769 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF +C1770 divbuf_8/a_492_n240# divbuf_8/IN 0.13fF +C1771 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF +C1772 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF +C1773 divbuf_24/OUT4 divbuf_24/OUT 1.11fF +C1774 divider_2/nor_0/B divider_2/and_0/B 0.29fF +C1775 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a5 0.09fF +C1776 divider_1/prescaler_0/nand_1/z1 gnd 0.16fF +C1777 divbuf_3/OUT2 divbuf_3/a_492_n240# 0.42fF +C1778 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1779 divider_2/clk gnd 0.07fF +C1780 divider_1/tspc_1/Z2 divider_1/nor_1/B 0.30fF +C1781 divider_1/tspc_0/Z3 divider_1/nor_1/A 0.38fF +C1782 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF +C1783 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z4 0.12fF +C1784 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF +C1785 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.05fF +C1786 gnd pll_full_0/divider_0/nor_0/B 1.23fF +C1787 divbuf_23/OUT2 divbuf_23/OUT3 1.37fF +C1788 divider_0/nor_1/Z1 gnd 0.01fF +C1789 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF +C1790 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF +C1791 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF +C1792 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF +C1793 divider_1/and_0/Z1 gnd 0.41fF +C1794 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF +C1795 ro_complete_1/a3 ro_complete_1/cbank_2/v 0.05fF +C1796 divbuf_10/OUT2 divbuf_10/OUT5 0.02fF +C1797 divbuf_10/OUT3 divbuf_10/OUT4 5.16fF +C1798 divider_1/tspc_0/Z4 divider_1/nor_1/A 0.21fF +C1799 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF +C1800 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF +C1801 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF +C1802 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C1803 divbuf_17/OUT divbuf_17/OUT4 1.11fF +C1804 divbuf_22/a_492_n240# divbuf_22/OUT2 0.42fF +C1805 cp_0/a_1710_n2840# cp_0/upbar 0.29fF +C1806 pd_1/R pd_1/REF 0.61fF +C1807 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF +C1808 divider_0/prescaler_0/tspc_1/Z2 gnd 0.17fF +C1809 divbuf_13/OUT5 divbuf_13/OUT 43.38fF +C1810 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF +C1811 divider_1/tspc_1/Q gnd 0.33fF +C1812 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z2 0.01fF +C1813 divbuf_25/OUT3 divbuf_25/OUT2 1.37fF +C1814 divbuf_1/OUT divbuf_1/OUT3 0.26fF +C1815 ro_complete_1/a4 ro_complete_1/cbank_1/switch_1/vin 0.09fF +C1816 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF +C1817 divider_2/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF +C1818 divbuf_4/OUT2 divbuf_4/OUT 0.06fF +C1819 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF +C1820 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/Out 0.11fF +C1821 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF +C1822 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF +C1823 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 gnd 0.44fF +C1824 divbuf_12/IN divbuf_12/OUT5 0.00fF +C1825 cp_0/upbar cp_0/down 0.02fF +C1826 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF +C1827 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF +C1828 divider_2/nor_0/B divider_2/tspc_2/Z4 0.22fF +C1829 divbuf_24/a_492_n240# divbuf_24/IN 0.13fF +C1830 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF +C1831 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF +C1832 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF +C1833 divbuf_18/OUT4 divbuf_18/OUT3 5.16fF +C1834 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/D 0.11fF +C1835 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF +C1836 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF +C1837 ro_complete_1/a3 ro_complete_1/cbank_1/switch_2/vin 0.09fF +C1838 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C1839 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1840 divider_2/nor_0/B gnd 1.08fF +C1841 divbuf_5/OUT2 divbuf_5/OUT 0.06fF +C1842 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF +C1843 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C1844 divider_2/mc2 divider_2/and_0/OUT 0.05fF +C1845 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF +C1846 pll_full_0/divider_0/prescaler_0/tspc_1/Q gnd 0.83fF +C1847 pd_0/UP pd_0/tspc_r_1/z5 0.03fF +C1848 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF +C1849 divider_0/mc2 gnd 1.36fF Xpd_0 VDD vssa1 pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd Xpd_1 VDD vssa1 pd_1/REF pd_1/DIV pd_1/UP pd_1/DOWN pd_1/R pd Xcp_0 cp_0/vbias vdd vssa1 cp_0/out cp_0/down cp_0/upbar cp @@ -1726,1130 +1978,1292 @@ + divbuf_5/OUT5 vssa1 divbuf Xdivbuf_6 vdda1 divbuf_6/IN divbuf_6/OUT divbuf_6/OUT2 divbuf_6/OUT3 divbuf_6/OUT4 + divbuf_6/OUT5 vssa1 divbuf +Xdivbuf_10 VDD divbuf_10/IN divbuf_10/OUT divbuf_10/OUT2 divbuf_10/OUT3 divbuf_10/OUT4 ++ divbuf_10/OUT5 vssa1 divbuf +Xdivbuf_20 VDD divbuf_20/IN divbuf_20/OUT divbuf_20/OUT2 divbuf_20/OUT3 divbuf_20/OUT4 ++ divbuf_20/OUT5 vssa1 divbuf +Xdivbuf_21 VDD divbuf_21/IN divbuf_21/OUT divbuf_21/OUT2 divbuf_21/OUT3 divbuf_21/OUT4 ++ divbuf_21/OUT5 vssa1 divbuf Xdivbuf_7 vdda1 divbuf_7/IN divbuf_7/OUT divbuf_7/OUT2 divbuf_7/OUT3 divbuf_7/OUT4 + divbuf_7/OUT5 vssa1 divbuf +Xdivbuf_11 VDD divbuf_11/IN divbuf_11/OUT divbuf_11/OUT2 divbuf_11/OUT3 divbuf_11/OUT4 ++ divbuf_11/OUT5 vssa1 divbuf +Xdivbuf_22 VDD divbuf_22/IN divbuf_22/OUT divbuf_22/OUT2 divbuf_22/OUT3 divbuf_22/OUT4 ++ divbuf_22/OUT5 vssa1 divbuf +Xdivbuf_12 VDD divbuf_12/IN divbuf_12/OUT divbuf_12/OUT2 divbuf_12/OUT3 divbuf_12/OUT4 ++ divbuf_12/OUT5 vssa1 divbuf +Xdivbuf_8 VDD divbuf_8/IN divbuf_8/OUT divbuf_8/OUT2 divbuf_8/OUT3 divbuf_8/OUT4 divbuf_8/OUT5 ++ vssa1 divbuf +Xdivbuf_23 VDD divbuf_23/IN divbuf_23/OUT divbuf_23/OUT2 divbuf_23/OUT3 divbuf_23/OUT4 ++ divbuf_23/OUT5 vssa1 divbuf +Xdivbuf_13 VDD divbuf_13/IN divbuf_13/OUT divbuf_13/OUT2 divbuf_13/OUT3 divbuf_13/OUT4 ++ divbuf_13/OUT5 vssa1 divbuf +Xdivbuf_9 VDD divbuf_9/IN divbuf_9/OUT divbuf_9/OUT2 divbuf_9/OUT3 divbuf_9/OUT4 divbuf_9/OUT5 ++ vssa1 divbuf +Xdivbuf_24 VDD divbuf_24/IN divbuf_24/OUT divbuf_24/OUT2 divbuf_24/OUT3 divbuf_24/OUT4 ++ divbuf_24/OUT5 vssa1 divbuf Xdivider_0 gnd vdd divider_0/Out divider_0/clk divider_0/mc2 divider +Xdivbuf_14 VDD divbuf_14/IN divbuf_14/OUT divbuf_14/OUT2 divbuf_14/OUT3 divbuf_14/OUT4 ++ divbuf_14/OUT5 vssa1 divbuf +Xdivbuf_25 VDD divbuf_25/IN divbuf_25/OUT divbuf_25/OUT2 divbuf_25/OUT3 divbuf_25/OUT4 ++ divbuf_25/OUT5 vssa1 divbuf +Xdivbuf_15 VDD divbuf_15/IN divbuf_15/OUT divbuf_15/OUT2 divbuf_15/OUT3 divbuf_15/OUT4 ++ divbuf_15/OUT5 vssa1 divbuf Xdivider_1 gnd vdd divider_1/Out divider_1/clk divider_1/mc2 divider +Xdivbuf_16 VDD divbuf_16/IN divbuf_16/OUT divbuf_16/OUT2 divbuf_16/OUT3 divbuf_16/OUT4 ++ divbuf_16/OUT5 vssa1 divbuf Xdivider_2 gnd vdd divider_2/Out divider_2/clk divider_2/mc2 divider +Xdivbuf_17 VDD divbuf_17/IN divbuf_17/OUT divbuf_17/OUT2 divbuf_17/OUT3 divbuf_17/OUT4 ++ divbuf_17/OUT5 vssa1 divbuf +Xdivbuf_18 VDD divbuf_18/IN divbuf_18/OUT divbuf_18/OUT2 divbuf_18/OUT3 divbuf_18/OUT4 ++ divbuf_18/OUT5 vssa1 divbuf +Xdivbuf_19 VDD divbuf_19/IN divbuf_19/OUT divbuf_19/OUT2 divbuf_19/OUT3 divbuf_19/OUT4 ++ divbuf_19/OUT5 vssa1 divbuf Xpll_full_0 vdd pll_full -C1598 io_analog[4] vdd 43.96fF -C1599 io_analog[5] vdd 44.13fF -C1600 io_analog[6] vdd 43.46fF -C1601 io_in_3v3[0] vdd 0.61fF -C1602 io_oeb[26] vdd 0.61fF -C1603 io_in[0] vdd 0.61fF -C1604 io_out[26] vdd 0.61fF -C1605 io_out[0] vdd 0.61fF -C1606 io_in[26] vdd 0.61fF -C1607 io_oeb[0] vdd 0.61fF -C1608 io_in_3v3[26] vdd 0.61fF -C1609 io_in_3v3[1] vdd 0.61fF -C1610 io_oeb[25] vdd 0.61fF -C1611 io_in[1] vdd 0.61fF -C1612 io_out[25] vdd 0.61fF -C1613 io_out[1] vdd 0.61fF -C1614 io_in[25] vdd 0.61fF -C1615 io_oeb[1] vdd 0.61fF -C1616 io_in_3v3[25] vdd 0.61fF -C1617 io_in_3v3[2] vdd 0.61fF -C1618 io_oeb[24] vdd 0.61fF -C1619 io_in[2] vdd 0.61fF -C1620 io_out[24] vdd 0.61fF -C1621 io_out[2] vdd 0.61fF -C1622 io_in[24] vdd 0.61fF -C1623 io_oeb[2] vdd 0.61fF -C1624 io_in_3v3[24] vdd 0.61fF -C1625 io_in_3v3[3] vdd 0.61fF -C1626 gpio_noesd[17] vdd 2.32fF -C1627 io_in[3] vdd 0.61fF -C1628 gpio_analog[17] vdd 2.30fF -C1629 io_out[3] vdd 0.61fF -C1630 io_oeb[3] vdd 0.61fF -C1631 io_in_3v3[4] vdd 0.61fF -C1632 io_in[4] vdd 0.61fF -C1633 io_out[4] vdd 0.61fF -C1634 io_oeb[4] vdd 0.61fF -C1635 io_oeb[23] vdd 0.61fF -C1636 io_out[23] vdd 0.61fF -C1637 io_in[23] vdd 0.61fF -C1638 io_in_3v3[23] vdd 0.61fF -C1639 gpio_noesd[16] vdd 2.30fF -C1640 gpio_analog[16] vdd 2.30fF -C1641 io_in_3v3[5] vdd 0.61fF -C1642 io_in[5] vdd 0.61fF -C1643 io_out[5] vdd 0.61fF -C1644 io_oeb[5] vdd 0.61fF -C1645 io_oeb[22] vdd 0.61fF -C1646 io_out[22] vdd 0.61fF -C1647 io_in[22] vdd 0.61fF -C1648 io_in_3v3[22] vdd 0.61fF -C1649 gpio_noesd[15] vdd 2.31fF -C1650 gpio_analog[15] vdd 2.30fF -C1651 io_in_3v3[6] vdd 0.61fF -C1652 io_in[6] vdd 0.61fF -C1653 io_out[6] vdd 0.61fF -C1654 io_oeb[6] vdd 0.61fF -C1655 io_oeb[21] vdd 0.61fF -C1656 io_out[21] vdd 0.61fF -C1657 io_in[21] vdd 0.61fF -C1658 io_in_3v3[21] vdd 0.61fF -C1659 gpio_noesd[14] vdd 2.30fF -C1660 gpio_analog[14] vdd 2.29fF -C1661 vssd2 vdd 38.54fF -C1662 vssd1 vdd 13.04fF -C1663 vdda2 vdd 38.30fF -C1664 io_oeb[20] vdd 0.61fF -C1665 io_out[20] vdd 0.61fF -C1666 io_in[20] vdd 0.61fF -C1667 io_in_3v3[20] vdd 0.61fF -C1668 gpio_noesd[13] vdd 2.31fF -C1669 gpio_analog[13] vdd 2.30fF -C1670 gpio_analog[0] vdd 0.61fF -C1671 gpio_noesd[0] vdd 0.61fF -C1672 io_in_3v3[7] vdd 0.61fF -C1673 io_in[7] vdd 0.61fF -C1674 io_out[7] vdd 0.61fF -C1675 io_oeb[7] vdd 0.61fF -C1676 io_oeb[19] vdd 0.61fF -C1677 io_out[19] vdd 0.61fF -C1678 io_in[19] vdd 0.61fF -C1679 io_in_3v3[19] vdd 0.61fF -C1680 gpio_noesd[12] vdd 2.32fF -C1681 gpio_analog[12] vdd 2.30fF -C1682 gpio_analog[1] vdd 0.61fF -C1683 gpio_noesd[1] vdd 0.61fF -C1684 io_in_3v3[8] vdd 0.61fF -C1685 io_in[8] vdd 0.61fF -C1686 io_out[8] vdd 0.61fF -C1687 io_oeb[8] vdd 0.61fF -C1688 io_oeb[18] vdd 0.61fF -C1689 io_out[18] vdd 0.61fF -C1690 io_in[18] vdd 0.61fF -C1691 io_in_3v3[18] vdd 0.61fF -C1692 gpio_noesd[11] vdd 2.30fF -C1693 gpio_analog[11] vdd 2.29fF -C1694 gpio_analog[2] vdd 0.61fF -C1695 gpio_noesd[2] vdd 0.61fF -C1696 io_in_3v3[9] vdd 0.61fF -C1697 io_in[9] vdd 0.61fF -C1698 io_out[9] vdd 0.61fF -C1699 io_oeb[9] vdd 0.61fF -C1700 io_oeb[17] vdd 0.61fF -C1701 io_out[17] vdd 0.61fF -C1702 io_in[17] vdd 0.61fF -C1703 io_in_3v3[17] vdd 0.61fF -C1704 gpio_noesd[10] vdd 2.31fF -C1705 gpio_analog[10] vdd 2.29fF -C1706 gpio_analog[3] vdd 0.61fF -C1707 gpio_noesd[3] vdd 0.61fF -C1708 io_in_3v3[10] vdd 0.61fF -C1709 io_in[10] vdd 0.61fF -C1710 io_out[10] vdd 0.61fF -C1711 io_oeb[10] vdd 0.61fF -C1712 io_oeb[16] vdd 0.61fF -C1713 io_out[16] vdd 0.61fF -C1714 io_in[16] vdd 0.61fF -C1715 io_in_3v3[16] vdd 0.61fF -C1716 gpio_noesd[9] vdd 2.28fF -C1717 gpio_analog[9] vdd 2.28fF -C1718 gpio_analog[4] vdd 0.61fF -C1719 gpio_noesd[4] vdd 0.61fF -C1720 io_in_3v3[11] vdd 0.61fF -C1721 io_in[11] vdd 0.61fF -C1722 io_out[11] vdd 0.61fF -C1723 io_oeb[11] vdd 0.61fF -C1724 io_oeb[15] vdd 0.61fF -C1725 io_out[15] vdd 0.61fF -C1726 io_in[15] vdd 0.61fF -C1727 io_in_3v3[15] vdd 0.61fF -C1728 gpio_noesd[8] vdd 2.28fF -C1729 gpio_analog[8] vdd 2.26fF -C1730 gpio_analog[5] vdd 0.61fF -C1731 gpio_noesd[5] vdd 0.61fF -C1732 io_in_3v3[12] vdd 0.61fF -C1733 io_in[12] vdd 0.61fF -C1734 io_out[12] vdd 0.61fF -C1735 io_oeb[12] vdd 0.61fF -C1736 io_oeb[14] vdd 0.61fF -C1737 io_out[14] vdd 0.61fF -C1738 io_in[14] vdd 0.61fF -C1739 io_in_3v3[14] vdd 0.61fF -C1740 gpio_noesd[7] vdd 2.30fF -C1741 gpio_analog[7] vdd 2.28fF -C1742 vssa2 vdd 38.35fF -C1743 gpio_analog[6] vdd 5.71fF -C1744 gpio_noesd[6] vdd 5.70fF -C1745 io_in_3v3[13] vdd 0.61fF -C1746 io_in[13] vdd 0.61fF -C1747 io_out[13] vdd 0.61fF -C1748 io_oeb[13] vdd 0.61fF -C1749 vccd1 vdd 39.84fF -C1750 vccd2 vdd 38.46fF -C1751 io_analog[0] vdd 19.99fF -C1752 io_analog[10] vdd 19.36fF -C1753 io_analog[1] vdd 13.17fF -C1754 io_analog[2] vdd 12.57fF -C1755 io_analog[3] vdd 12.83fF -C1756 io_clamp_high[0] vdd 3.58fF -C1757 io_clamp_low[0] vdd 3.58fF -C1758 io_clamp_high[1] vdd 3.58fF -C1759 io_clamp_low[1] vdd 3.58fF -C1760 io_clamp_high[2] vdd 3.58fF -C1761 io_clamp_low[2] vdd 3.58fF -C1762 io_analog[7] vdd 12.74fF -C1763 io_analog[8] vdd 13.08fF -C1764 io_analog[9] vdd 13.08fF -C1765 user_irq[2] vdd 0.63fF -C1766 user_irq[1] vdd 0.63fF -C1767 user_irq[0] vdd 0.63fF -C1768 user_clock2 vdd 0.63fF -C1769 la_oenb[127] vdd 0.63fF -C1770 la_data_out[127] vdd 0.63fF -C1771 la_data_in[127] vdd 0.63fF -C1772 la_oenb[126] vdd 0.63fF -C1773 la_data_out[126] vdd 0.63fF -C1774 la_data_in[126] vdd 0.63fF -C1775 la_oenb[125] vdd 0.63fF -C1776 la_data_out[125] vdd 0.63fF -C1777 la_data_in[125] vdd 0.63fF -C1778 la_oenb[124] vdd 0.63fF -C1779 la_data_out[124] vdd 0.63fF -C1780 la_data_in[124] vdd 0.63fF -C1781 la_oenb[123] vdd 0.63fF -C1782 la_data_out[123] vdd 0.63fF -C1783 la_data_in[123] vdd 0.63fF -C1784 la_oenb[122] vdd 0.63fF -C1785 la_data_out[122] vdd 0.63fF -C1786 la_data_in[122] vdd 0.63fF -C1787 la_oenb[121] vdd 0.63fF -C1788 la_data_out[121] vdd 0.63fF -C1789 la_data_in[121] vdd 0.63fF -C1790 la_oenb[120] vdd 0.63fF -C1791 la_data_out[120] vdd 0.63fF -C1792 la_data_in[120] vdd 0.63fF -C1793 la_oenb[119] vdd 0.63fF -C1794 la_data_out[119] vdd 0.63fF -C1795 la_data_in[119] vdd 0.63fF -C1796 la_oenb[118] vdd 0.63fF -C1797 la_data_out[118] vdd 0.63fF -C1798 la_data_in[118] vdd 0.63fF -C1799 la_oenb[117] vdd 0.63fF -C1800 la_data_out[117] vdd 0.63fF -C1801 la_data_in[117] vdd 0.63fF -C1802 la_oenb[116] vdd 0.63fF -C1803 la_data_out[116] vdd 0.63fF -C1804 la_data_in[116] vdd 0.63fF -C1805 la_oenb[115] vdd 0.63fF -C1806 la_data_out[115] vdd 0.63fF -C1807 la_data_in[115] vdd 0.63fF -C1808 la_oenb[114] vdd 0.63fF -C1809 la_data_out[114] vdd 0.63fF -C1810 la_data_in[114] vdd 0.63fF -C1811 la_oenb[113] vdd 0.63fF -C1812 la_data_out[113] vdd 0.63fF -C1813 la_data_in[113] vdd 0.63fF -C1814 la_oenb[112] vdd 0.63fF -C1815 la_data_out[112] vdd 0.63fF -C1816 la_data_in[112] vdd 0.63fF -C1817 la_oenb[111] vdd 0.63fF -C1818 la_data_out[111] vdd 0.63fF -C1819 la_data_in[111] vdd 0.63fF -C1820 la_oenb[110] vdd 0.63fF -C1821 la_data_out[110] vdd 0.63fF -C1822 la_data_in[110] vdd 0.63fF -C1823 la_oenb[109] vdd 0.63fF -C1824 la_data_out[109] vdd 0.63fF -C1825 la_data_in[109] vdd 0.63fF -C1826 la_oenb[108] vdd 0.63fF -C1827 la_data_out[108] vdd 0.63fF -C1828 la_data_in[108] vdd 0.63fF -C1829 la_oenb[107] vdd 0.63fF -C1830 la_data_out[107] vdd 0.63fF -C1831 la_data_in[107] vdd 0.63fF -C1832 la_oenb[106] vdd 0.63fF -C1833 la_data_out[106] vdd 0.63fF -C1834 la_data_in[106] vdd 0.63fF -C1835 la_oenb[105] vdd 0.63fF -C1836 la_data_out[105] vdd 0.63fF -C1837 la_data_in[105] vdd 0.63fF -C1838 la_oenb[104] vdd 0.63fF -C1839 la_data_out[104] vdd 0.63fF -C1840 la_data_in[104] vdd 0.63fF -C1841 la_oenb[103] vdd 0.63fF -C1842 la_data_out[103] vdd 0.63fF -C1843 la_data_in[103] vdd 0.63fF -C1844 la_oenb[102] vdd 0.63fF -C1845 la_data_out[102] vdd 0.63fF -C1846 la_data_in[102] vdd 0.63fF -C1847 la_oenb[101] vdd 0.63fF -C1848 la_data_out[101] vdd 0.63fF -C1849 la_data_in[101] vdd 0.63fF -C1850 la_oenb[100] vdd 0.63fF -C1851 la_data_out[100] vdd 0.63fF -C1852 la_data_in[100] vdd 0.63fF -C1853 la_oenb[99] vdd 0.63fF -C1854 la_data_out[99] vdd 0.63fF -C1855 la_data_in[99] vdd 0.63fF -C1856 la_oenb[98] vdd 0.63fF -C1857 la_data_out[98] vdd 0.63fF -C1858 la_data_in[98] vdd 0.63fF -C1859 la_oenb[97] vdd 0.63fF -C1860 la_data_out[97] vdd 0.63fF -C1861 la_data_in[97] vdd 0.63fF -C1862 la_oenb[96] vdd 0.63fF -C1863 la_data_out[96] vdd 0.63fF -C1864 la_data_in[96] vdd 0.63fF -C1865 la_oenb[95] vdd 0.63fF -C1866 la_data_out[95] vdd 0.63fF -C1867 la_data_in[95] vdd 0.63fF -C1868 la_oenb[94] vdd 0.63fF -C1869 la_data_out[94] vdd 0.63fF -C1870 la_data_in[94] vdd 0.63fF -C1871 la_oenb[93] vdd 0.63fF -C1872 la_data_out[93] vdd 0.63fF -C1873 la_data_in[93] vdd 0.63fF -C1874 la_oenb[92] vdd 0.63fF -C1875 la_data_out[92] vdd 0.63fF -C1876 la_data_in[92] vdd 0.63fF -C1877 la_oenb[91] vdd 0.63fF -C1878 la_data_out[91] vdd 0.63fF -C1879 la_data_in[91] vdd 0.63fF -C1880 la_oenb[90] vdd 0.63fF -C1881 la_data_out[90] vdd 0.63fF -C1882 la_data_in[90] vdd 0.63fF -C1883 la_oenb[89] vdd 0.63fF -C1884 la_data_out[89] vdd 0.63fF -C1885 la_data_in[89] vdd 0.63fF -C1886 la_oenb[88] vdd 0.63fF -C1887 la_data_out[88] vdd 0.63fF -C1888 la_data_in[88] vdd 0.63fF -C1889 la_oenb[87] vdd 0.63fF -C1890 la_data_out[87] vdd 0.63fF -C1891 la_data_in[87] vdd 0.63fF -C1892 la_oenb[86] vdd 0.63fF -C1893 la_data_out[86] vdd 0.63fF -C1894 la_data_in[86] vdd 0.63fF -C1895 la_oenb[85] vdd 0.63fF -C1896 la_data_out[85] vdd 0.63fF -C1897 la_data_in[85] vdd 0.63fF -C1898 la_oenb[84] vdd 0.63fF -C1899 la_data_out[84] vdd 0.63fF -C1900 la_data_in[84] vdd 0.63fF -C1901 la_oenb[83] vdd 0.63fF -C1902 la_data_out[83] vdd 0.63fF -C1903 la_data_in[83] vdd 0.63fF -C1904 la_oenb[82] vdd 0.63fF -C1905 la_data_out[82] vdd 0.63fF -C1906 la_data_in[82] vdd 0.63fF -C1907 la_oenb[81] vdd 0.63fF -C1908 la_data_out[81] vdd 0.63fF -C1909 la_data_in[81] vdd 0.63fF -C1910 la_oenb[80] vdd 0.63fF -C1911 la_data_out[80] vdd 0.63fF -C1912 la_data_in[80] vdd 0.63fF -C1913 la_oenb[79] vdd 0.63fF -C1914 la_data_out[79] vdd 0.63fF -C1915 la_data_in[79] vdd 0.63fF -C1916 la_oenb[78] vdd 0.63fF -C1917 la_data_out[78] vdd 0.63fF -C1918 la_data_in[78] vdd 0.63fF -C1919 la_oenb[77] vdd 0.63fF -C1920 la_data_out[77] vdd 0.63fF -C1921 la_data_in[77] vdd 0.63fF -C1922 la_oenb[76] vdd 0.63fF -C1923 la_data_out[76] vdd 0.63fF -C1924 la_data_in[76] vdd 0.63fF -C1925 la_oenb[75] vdd 0.63fF -C1926 la_data_out[75] vdd 0.63fF -C1927 la_data_in[75] vdd 0.63fF -C1928 la_oenb[74] vdd 0.63fF -C1929 la_data_out[74] vdd 0.63fF -C1930 la_data_in[74] vdd 0.63fF -C1931 la_oenb[73] vdd 0.63fF -C1932 la_data_out[73] vdd 0.63fF -C1933 la_data_in[73] vdd 0.63fF -C1934 la_oenb[72] vdd 0.63fF -C1935 la_data_out[72] vdd 0.63fF -C1936 la_data_in[72] vdd 0.63fF -C1937 la_oenb[71] vdd 0.63fF -C1938 la_data_out[71] vdd 0.63fF -C1939 la_data_in[71] vdd 0.63fF -C1940 la_oenb[70] vdd 0.63fF -C1941 la_data_out[70] vdd 0.63fF -C1942 la_data_in[70] vdd 0.63fF -C1943 la_oenb[69] vdd 0.63fF -C1944 la_data_out[69] vdd 0.63fF -C1945 la_data_in[69] vdd 0.63fF -C1946 la_oenb[68] vdd 0.63fF -C1947 la_data_out[68] vdd 0.63fF -C1948 la_data_in[68] vdd 0.63fF -C1949 la_oenb[67] vdd 0.63fF -C1950 la_data_out[67] vdd 0.63fF -C1951 la_data_in[67] vdd 0.63fF -C1952 la_oenb[66] vdd 0.63fF -C1953 la_data_out[66] vdd 0.63fF -C1954 la_data_in[66] vdd 0.63fF -C1955 la_oenb[65] vdd 0.63fF -C1956 la_data_out[65] vdd 0.63fF -C1957 la_data_in[65] vdd 0.63fF -C1958 la_oenb[64] vdd 0.63fF -C1959 la_data_out[64] vdd 0.63fF -C1960 la_data_in[64] vdd 0.63fF -C1961 la_oenb[63] vdd 0.63fF -C1962 la_data_out[63] vdd 0.63fF -C1963 la_data_in[63] vdd 0.63fF -C1964 la_oenb[62] vdd 0.63fF -C1965 la_data_out[62] vdd 0.63fF -C1966 la_data_in[62] vdd 0.63fF -C1967 la_oenb[61] vdd 0.63fF -C1968 la_data_out[61] vdd 0.63fF -C1969 la_data_in[61] vdd 0.63fF -C1970 la_oenb[60] vdd 0.63fF -C1971 la_data_out[60] vdd 0.63fF -C1972 la_data_in[60] vdd 0.63fF -C1973 la_oenb[59] vdd 0.63fF -C1974 la_data_out[59] vdd 0.63fF -C1975 la_data_in[59] vdd 0.63fF -C1976 la_oenb[58] vdd 0.63fF -C1977 la_data_out[58] vdd 0.63fF -C1978 la_data_in[58] vdd 0.63fF -C1979 la_oenb[57] vdd 0.63fF -C1980 la_data_out[57] vdd 0.63fF -C1981 la_data_in[57] vdd 0.63fF -C1982 la_oenb[56] vdd 0.63fF -C1983 la_data_out[56] vdd 0.63fF -C1984 la_data_in[56] vdd 0.63fF -C1985 la_oenb[55] vdd 0.63fF -C1986 la_data_out[55] vdd 0.63fF -C1987 la_data_in[55] vdd 0.63fF -C1988 la_oenb[54] vdd 0.63fF -C1989 la_data_out[54] vdd 0.63fF -C1990 la_data_in[54] vdd 0.63fF -C1991 la_oenb[53] vdd 0.63fF -C1992 la_data_out[53] vdd 0.63fF -C1993 la_data_in[53] vdd 0.63fF -C1994 la_oenb[52] vdd 0.63fF -C1995 la_data_out[52] vdd 0.63fF -C1996 la_data_in[52] vdd 0.63fF -C1997 la_oenb[51] vdd 0.63fF -C1998 la_data_out[51] vdd 0.63fF -C1999 la_data_in[51] vdd 0.63fF -C2000 la_oenb[50] vdd 0.63fF -C2001 la_data_out[50] vdd 0.63fF -C2002 la_data_in[50] vdd 0.63fF -C2003 la_oenb[49] vdd 0.63fF -C2004 la_data_out[49] vdd 0.63fF -C2005 la_data_in[49] vdd 0.63fF -C2006 la_oenb[48] vdd 0.63fF -C2007 la_data_out[48] vdd 0.63fF -C2008 la_data_in[48] vdd 0.63fF -C2009 la_oenb[47] vdd 0.63fF -C2010 la_data_out[47] vdd 0.63fF -C2011 la_data_in[47] vdd 0.63fF -C2012 la_oenb[46] vdd 0.63fF -C2013 la_data_out[46] vdd 0.63fF -C2014 la_data_in[46] vdd 0.63fF -C2015 la_oenb[45] vdd 0.63fF -C2016 la_data_out[45] vdd 0.63fF -C2017 la_data_in[45] vdd 0.63fF -C2018 la_oenb[44] vdd 0.63fF -C2019 la_data_out[44] vdd 0.63fF -C2020 la_data_in[44] vdd 0.63fF -C2021 la_oenb[43] vdd 0.63fF -C2022 la_data_out[43] vdd 0.63fF -C2023 la_data_in[43] vdd 0.63fF -C2024 la_oenb[42] vdd 0.63fF -C2025 la_data_out[42] vdd 0.63fF -C2026 la_data_in[42] vdd 0.63fF -C2027 la_oenb[41] vdd 0.63fF -C2028 la_data_out[41] vdd 0.63fF -C2029 la_data_in[41] vdd 0.63fF -C2030 la_oenb[40] vdd 0.63fF -C2031 la_data_out[40] vdd 0.63fF -C2032 la_data_in[40] vdd 0.63fF -C2033 la_oenb[39] vdd 0.63fF -C2034 la_data_out[39] vdd 0.63fF -C2035 la_data_in[39] vdd 0.63fF -C2036 la_oenb[38] vdd 0.63fF -C2037 la_data_out[38] vdd 0.63fF -C2038 la_data_in[38] vdd 0.63fF -C2039 la_oenb[37] vdd 0.63fF -C2040 la_data_out[37] vdd 0.63fF -C2041 la_data_in[37] vdd 0.63fF -C2042 la_oenb[36] vdd 0.63fF -C2043 la_data_out[36] vdd 0.63fF -C2044 la_data_in[36] vdd 0.63fF -C2045 la_oenb[35] vdd 0.63fF -C2046 la_data_out[35] vdd 0.63fF -C2047 la_data_in[35] vdd 0.63fF -C2048 la_oenb[34] vdd 0.63fF -C2049 la_data_out[34] vdd 0.63fF -C2050 la_data_in[34] vdd 0.63fF -C2051 la_oenb[33] vdd 0.63fF -C2052 la_data_out[33] vdd 0.63fF -C2053 la_data_in[33] vdd 0.63fF -C2054 la_oenb[32] vdd 0.63fF -C2055 la_data_out[32] vdd 0.63fF -C2056 la_data_in[32] vdd 0.63fF -C2057 la_oenb[31] vdd 0.63fF -C2058 la_data_out[31] vdd 0.63fF -C2059 la_data_in[31] vdd 0.63fF -C2060 la_oenb[30] vdd 0.63fF -C2061 la_data_out[30] vdd 0.63fF -C2062 la_data_in[30] vdd 0.63fF -C2063 la_oenb[29] vdd 0.63fF -C2064 la_data_out[29] vdd 0.63fF -C2065 la_data_in[29] vdd 0.63fF -C2066 la_oenb[28] vdd 0.63fF -C2067 la_data_out[28] vdd 0.63fF -C2068 la_data_in[28] vdd 0.63fF -C2069 la_oenb[27] vdd 0.63fF -C2070 la_data_out[27] vdd 0.63fF -C2071 la_data_in[27] vdd 0.63fF -C2072 la_oenb[26] vdd 0.63fF -C2073 la_data_out[26] vdd 0.63fF -C2074 la_data_in[26] vdd 0.63fF -C2075 la_oenb[25] vdd 0.63fF -C2076 la_data_out[25] vdd 0.63fF -C2077 la_data_in[25] vdd 0.63fF -C2078 la_oenb[24] vdd 0.63fF -C2079 la_data_out[24] vdd 0.63fF -C2080 la_data_in[24] vdd 0.63fF -C2081 la_oenb[23] vdd 0.63fF -C2082 la_data_out[23] vdd 0.63fF -C2083 la_data_in[23] vdd 0.63fF -C2084 la_oenb[22] vdd 0.63fF -C2085 la_data_out[22] vdd 0.63fF -C2086 la_data_in[22] vdd 0.63fF -C2087 la_oenb[21] vdd 0.63fF -C2088 la_data_out[21] vdd 0.63fF -C2089 la_data_in[21] vdd 0.63fF -C2090 la_oenb[20] vdd 0.63fF -C2091 la_data_out[20] vdd 0.63fF -C2092 la_data_in[20] vdd 0.63fF -C2093 la_oenb[19] vdd 0.63fF -C2094 la_data_out[19] vdd 0.63fF -C2095 la_data_in[19] vdd 0.63fF -C2096 la_oenb[18] vdd 0.63fF -C2097 la_data_out[18] vdd 0.63fF -C2098 la_data_in[18] vdd 0.63fF -C2099 la_oenb[17] vdd 0.63fF -C2100 la_data_out[17] vdd 0.63fF -C2101 la_data_in[17] vdd 0.63fF -C2102 la_oenb[16] vdd 0.63fF -C2103 la_data_out[16] vdd 0.63fF -C2104 la_data_in[16] vdd 0.63fF -C2105 la_oenb[15] vdd 0.63fF -C2106 la_data_out[15] vdd 0.63fF -C2107 la_data_in[15] vdd 0.63fF -C2108 la_oenb[14] vdd 0.63fF -C2109 la_data_out[14] vdd 0.63fF -C2110 la_data_in[14] vdd 0.63fF -C2111 la_oenb[13] vdd 0.63fF -C2112 la_data_out[13] vdd 0.63fF -C2113 la_data_in[13] vdd 0.63fF -C2114 la_oenb[12] vdd 0.63fF -C2115 la_data_out[12] vdd 0.63fF -C2116 la_data_in[12] vdd 0.63fF -C2117 la_oenb[11] vdd 0.63fF -C2118 la_data_out[11] vdd 0.63fF -C2119 la_data_in[11] vdd 0.63fF -C2120 la_oenb[10] vdd 0.63fF -C2121 la_data_out[10] vdd 0.63fF -C2122 la_data_in[10] vdd 0.63fF -C2123 la_oenb[9] vdd 0.63fF -C2124 la_data_out[9] vdd 0.63fF -C2125 la_data_in[9] vdd 0.63fF -C2126 la_oenb[8] vdd 0.63fF -C2127 la_data_out[8] vdd 0.63fF -C2128 la_data_in[8] vdd 0.63fF -C2129 la_oenb[7] vdd 0.63fF -C2130 la_data_out[7] vdd 0.63fF -C2131 la_data_in[7] vdd 0.63fF -C2132 la_oenb[6] vdd 0.63fF -C2133 la_data_out[6] vdd 0.63fF -C2134 la_data_in[6] vdd 0.63fF -C2135 la_oenb[5] vdd 0.63fF -C2136 la_data_out[5] vdd 0.63fF -C2137 la_data_in[5] vdd 0.63fF -C2138 la_oenb[4] vdd 0.63fF -C2139 la_data_out[4] vdd 0.63fF -C2140 la_data_in[4] vdd 0.63fF -C2141 la_oenb[3] vdd 0.63fF -C2142 la_data_out[3] vdd 0.63fF -C2143 la_data_in[3] vdd 0.63fF -C2144 la_oenb[2] vdd 0.63fF -C2145 la_data_out[2] vdd 0.63fF -C2146 la_data_in[2] vdd 0.63fF -C2147 la_oenb[1] vdd 0.63fF -C2148 la_data_out[1] vdd 0.63fF -C2149 la_data_in[1] vdd 0.63fF -C2150 la_oenb[0] vdd 0.63fF -C2151 la_data_out[0] vdd 0.63fF -C2152 la_data_in[0] vdd 0.63fF -C2153 wbs_dat_o[31] vdd 0.63fF -C2154 wbs_dat_i[31] vdd 0.63fF -C2155 wbs_adr_i[31] vdd 0.63fF -C2156 wbs_dat_o[30] vdd 0.63fF -C2157 wbs_dat_i[30] vdd 0.63fF -C2158 wbs_adr_i[30] vdd 0.63fF -C2159 wbs_dat_o[29] vdd 0.63fF -C2160 wbs_dat_i[29] vdd 0.63fF -C2161 wbs_adr_i[29] vdd 0.63fF -C2162 wbs_dat_o[28] vdd 0.63fF -C2163 wbs_dat_i[28] vdd 0.63fF -C2164 wbs_adr_i[28] vdd 0.63fF -C2165 wbs_dat_o[27] vdd 0.63fF -C2166 wbs_dat_i[27] vdd 0.63fF -C2167 wbs_adr_i[27] vdd 0.63fF -C2168 wbs_dat_o[26] vdd 0.63fF -C2169 wbs_dat_i[26] vdd 0.63fF -C2170 wbs_adr_i[26] vdd 0.63fF -C2171 wbs_dat_o[25] vdd 0.63fF -C2172 wbs_dat_i[25] vdd 0.63fF -C2173 wbs_adr_i[25] vdd 0.63fF -C2174 wbs_dat_o[24] vdd 0.63fF -C2175 wbs_dat_i[24] vdd 0.63fF -C2176 wbs_adr_i[24] vdd 0.63fF -C2177 wbs_dat_o[23] vdd 0.63fF -C2178 wbs_dat_i[23] vdd 0.63fF -C2179 wbs_adr_i[23] vdd 0.63fF -C2180 wbs_dat_o[22] vdd 0.63fF -C2181 wbs_dat_i[22] vdd 0.63fF -C2182 wbs_adr_i[22] vdd 0.63fF -C2183 wbs_dat_o[21] vdd 0.63fF -C2184 wbs_dat_i[21] vdd 0.63fF -C2185 wbs_adr_i[21] vdd 0.63fF -C2186 wbs_dat_o[20] vdd 0.63fF -C2187 wbs_dat_i[20] vdd 0.63fF -C2188 wbs_adr_i[20] vdd 0.63fF -C2189 wbs_dat_o[19] vdd 0.63fF -C2190 wbs_dat_i[19] vdd 0.63fF -C2191 wbs_adr_i[19] vdd 0.63fF -C2192 wbs_dat_o[18] vdd 0.63fF -C2193 wbs_dat_i[18] vdd 0.63fF -C2194 wbs_adr_i[18] vdd 0.63fF -C2195 wbs_dat_o[17] vdd 0.63fF -C2196 wbs_dat_i[17] vdd 0.63fF -C2197 wbs_adr_i[17] vdd 0.63fF -C2198 wbs_dat_o[16] vdd 0.63fF -C2199 wbs_dat_i[16] vdd 0.63fF -C2200 wbs_adr_i[16] vdd 0.63fF -C2201 wbs_dat_o[15] vdd 0.63fF -C2202 wbs_dat_i[15] vdd 0.63fF -C2203 wbs_adr_i[15] vdd 0.63fF -C2204 wbs_dat_o[14] vdd 0.63fF -C2205 wbs_dat_i[14] vdd 0.63fF -C2206 wbs_adr_i[14] vdd 0.63fF -C2207 wbs_dat_o[13] vdd 0.63fF -C2208 wbs_dat_i[13] vdd 0.63fF -C2209 wbs_adr_i[13] vdd 0.63fF -C2210 wbs_dat_o[12] vdd 0.63fF -C2211 wbs_dat_i[12] vdd 0.63fF -C2212 wbs_adr_i[12] vdd 0.63fF -C2213 wbs_dat_o[11] vdd 0.63fF -C2214 wbs_dat_i[11] vdd 0.63fF -C2215 wbs_adr_i[11] vdd 0.63fF -C2216 wbs_dat_o[10] vdd 0.63fF -C2217 wbs_dat_i[10] vdd 0.63fF -C2218 wbs_adr_i[10] vdd 0.63fF -C2219 wbs_dat_o[9] vdd 0.63fF -C2220 wbs_dat_i[9] vdd 0.63fF -C2221 wbs_adr_i[9] vdd 0.63fF -C2222 wbs_dat_o[8] vdd 0.63fF -C2223 wbs_dat_i[8] vdd 0.63fF -C2224 wbs_adr_i[8] vdd 0.63fF -C2225 wbs_dat_o[7] vdd 0.63fF -C2226 wbs_dat_i[7] vdd 0.63fF -C2227 wbs_adr_i[7] vdd 0.63fF -C2228 wbs_dat_o[6] vdd 0.63fF -C2229 wbs_dat_i[6] vdd 0.63fF -C2230 wbs_adr_i[6] vdd 0.63fF -C2231 wbs_dat_o[5] vdd 0.63fF -C2232 wbs_dat_i[5] vdd 0.63fF -C2233 wbs_adr_i[5] vdd 0.63fF -C2234 wbs_dat_o[4] vdd 0.63fF -C2235 wbs_dat_i[4] vdd 0.63fF -C2236 wbs_adr_i[4] vdd 0.63fF -C2237 wbs_sel_i[3] vdd 0.63fF -C2238 wbs_dat_o[3] vdd 0.63fF -C2239 wbs_dat_i[3] vdd 0.63fF -C2240 wbs_adr_i[3] vdd 0.63fF -C2241 wbs_sel_i[2] vdd 0.63fF -C2242 wbs_dat_o[2] vdd 0.63fF -C2243 wbs_dat_i[2] vdd 0.63fF -C2244 wbs_adr_i[2] vdd 0.63fF -C2245 wbs_sel_i[1] vdd 0.63fF -C2246 wbs_dat_o[1] vdd 0.63fF -C2247 wbs_dat_i[1] vdd 0.63fF -C2248 wbs_adr_i[1] vdd 0.63fF -C2249 wbs_sel_i[0] vdd 0.63fF -C2250 wbs_dat_o[0] vdd 0.63fF -C2251 wbs_dat_i[0] vdd 0.63fF -C2252 wbs_adr_i[0] vdd 0.63fF -C2253 wbs_we_i vdd 0.63fF -C2254 wbs_stb_i vdd 0.63fF -C2255 wbs_cyc_i vdd 0.63fF -C2256 wbs_ack_o vdd 0.63fF -C2257 wb_rst_i vdd 0.63fF -C2258 wb_clk_i vdd 0.63fF -C2259 m2_494098_659718# vdd 0.80fF **FLOATING -C2260 pll_full_0/divider_0/and_0/Z1 vdd 0.33fF -C2261 pll_full_0/divider_0/and_0/B vdd 1.79fF -C2262 pll_full_0/divider_0/and_0/A vdd 1.66fF -C2263 pll_full_0/divider_0/and_0/out1 vdd 2.71fF -C2264 pll_full_0/divider_0/tspc_2/Z4 vdd 0.42fF -C2265 pll_full_0/divbuf_0/IN vdd 6.23fF -C2266 pll_full_0/divider_0/tspc_2/Z3 vdd 2.00fF -C2267 pll_full_0/divider_0/tspc_2/Z2 vdd 1.29fF -C2268 pll_full_0/divider_0/tspc_2/Z1 vdd 0.99fF -C2269 pll_full_0/divider_0/nor_0/B vdd 5.25fF -C2270 pll_full_0/divider_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING -C2271 pll_full_0/divider_0/tspc_1/Z4 vdd 0.42fF -C2272 pll_full_0/divider_0/tspc_1/Q vdd 2.79fF -C2273 pll_full_0/divider_0/tspc_1/Z3 vdd 2.00fF -C2274 pll_full_0/divider_0/tspc_1/Z2 vdd 1.29fF -C2275 pll_full_0/divider_0/tspc_1/Z1 vdd 0.99fF -C2276 pll_full_0/divider_0/nor_1/B vdd 5.95fF -C2277 pll_full_0/divider_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING -C2278 pll_full_0/divider_0/tspc_0/Z4 vdd 0.42fF -C2279 pll_full_0/divider_0/tspc_0/Q vdd 2.81fF -C2280 pll_full_0/divider_0/tspc_0/Z3 vdd 2.00fF -C2281 pll_full_0/divider_0/tspc_0/Z2 vdd 1.30fF -C2282 pll_full_0/divider_0/tspc_0/Z1 vdd 0.99fF -C2283 pll_full_0/divider_0/nor_1/A vdd 6.02fF -C2284 pll_full_0/divider_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING -C2285 pll_full_0/divider_0/clk vdd 31.77fF -C2286 pll_full_0/divider_0/prescaler_0/Out vdd 4.13fF -C2287 pll_full_0/divider_0/prescaler_0/nand_1/z1 vdd 0.20fF -C2288 gnd vdd 91.98fF -C2289 pll_full_0/divider_0/prescaler_0/tspc_2/D vdd 2.59fF -C2290 pll_full_0/divider_0/prescaler_0/tspc_0/Q vdd 3.30fF -C2291 pll_full_0/divider_0/prescaler_0/tspc_1/Q vdd 2.78fF -C2292 pll_full_0/divider_0/prescaler_0/nand_0/z1 vdd 0.20fF -C2293 pll_full_0/divider_0/prescaler_0/tspc_0/D vdd 3.07fF -C2294 pll_full_0/divider_0/and_0/OUT vdd 5.35fF -C2295 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 vdd 0.42fF -C2296 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 vdd 2.00fF -C2297 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 vdd 1.30fF -C2298 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF -C2299 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING -C2300 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# vdd 1.89fF **FLOATING -C2301 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 vdd 0.42fF -C2302 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 vdd 2.00fF -C2303 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 vdd 1.31fF -C2304 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF -C2305 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING -C2306 pll_full_0/divider_0/prescaler_0/m1_2700_2190# vdd 3.99fF **FLOATING -C2307 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 vdd 0.42fF -C2308 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 vdd 2.00fF -C2309 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 vdd 1.30fF -C2310 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF -C2311 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING -C2312 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# vdd 1.89fF **FLOATING -C2313 pll_full_0/divider_0/nor_1/Z1 vdd 1.33fF -C2314 pll_full_0/divider_0/nor_0/Z1 vdd 1.33fF -C2315 pll_full_0/divbuf_1/OUT vdd 363.82fF -C2316 pll_full_0/divbuf_1/OUT5 vdd 350.37fF -C2317 pll_full_0/divbuf_1/OUT4 vdd 133.72fF -C2318 pll_full_0/divbuf_1/OUT3 vdd 34.03fF -C2319 pll_full_0/divbuf_1/OUT2 vdd 8.71fF -C2320 pll_full_0/divbuf_1/a_492_n240# vdd 2.46fF **FLOATING -C2321 pll_full_0/divbuf_0/OUT5 vdd 350.37fF -C2322 pll_full_0/divbuf_0/OUT4 vdd 133.72fF -C2323 pll_full_0/divbuf_0/OUT3 vdd 34.03fF -C2324 pll_full_0/divbuf_0/OUT2 vdd 8.71fF -C2325 pll_full_0/divbuf_0/a_492_n240# vdd 2.46fF **FLOATING -C2326 pll_full_0/ro_complete_0/cbank_2/v vdd 17.88fF -C2327 pll_full_0/ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF -C2328 pll_full_0/ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF -C2329 pll_full_0/ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF -C2330 pll_full_0/ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF -C2331 pll_full_0/ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF -C2332 pll_full_0/ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF -C2333 pll_full_0/ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF -C2334 pll_full_0/ro_complete_0/a0 vdd 7.88fF -C2335 pll_full_0/ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF -C2336 pll_full_0/ro_complete_0/a1 vdd 5.39fF -C2337 pll_full_0/ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF -C2338 pll_full_0/ro_complete_0/a3 vdd 6.85fF -C2339 pll_full_0/ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF -C2340 pll_full_0/ro_complete_0/a2 vdd 5.48fF -C2341 pll_full_0/ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF -C2342 pll_full_0/ro_complete_0/a4 vdd 5.36fF -C2343 pll_full_0/ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF -C2344 pll_full_0/ro_complete_0/a5 vdd 5.19fF -C2345 pll_full_0/ro_complete_0/cbank_0/v vdd 15.02fF -C2346 pll_full_0/ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF -C2347 pll_full_0/ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF -C2348 pll_full_0/ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF -C2349 pll_full_0/ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF -C2350 pll_full_0/ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF -C2351 pll_full_0/ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF -C2352 pll_full_0/ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF -C2353 pll_full_0/filter_0/a_4216_n5230# vdd 419.25fF **FLOATING -C2354 pll_full_0/filter_0/a_4216_n2998# vdd 1.39fF **FLOATING -C2355 pll_full_0/cp_0/down vdd 1.54fF -C2356 pll_full_0/cp_0/upbar vdd 1.79fF -C2357 pll_full_0/cp_0/a_7110_n2840# vdd 0.17fF **FLOATING -C2358 pll_full_0/cp_0/a_3060_n2840# vdd 1.71fF **FLOATING -C2359 pll_full_0/cp_0/a_7110_0# vdd 0.17fF **FLOATING -C2360 pll_full_0/cp_0/a_6370_0# vdd 0.40fF **FLOATING -C2361 pll_full_0/cp_0/a_3060_0# vdd 2.49fF **FLOATING -C2362 pll_full_0/cp_0/a_1710_0# vdd 7.47fF **FLOATING -C2363 pll_full_0/pd_0/and_pd_0/Z1 vdd 0.39fF -C2364 pll_full_0/pd_0/and_pd_0/Out1 vdd 2.22fF -C2365 pll_full_0/pd_0/tspc_r_1/z5 vdd 1.10fF -C2366 pll_full_0/pd_0/tspc_r_1/Z4 vdd 1.07fF -C2367 pll_full_0/pd_0/tspc_r_1/Qbar vdd 0.88fF -C2368 pll_full_0/pd_0/tspc_r_1/Z2 vdd 1.22fF -C2369 pll_full_0/pd_0/tspc_r_1/Z1 vdd 0.67fF -C2370 pll_full_0/pd_0/UP vdd 6.61fF -C2371 pll_full_0/pd_0/tspc_r_1/Qbar1 vdd 1.34fF -C2372 pll_full_0/pd_0/tspc_r_1/Z3 vdd 2.12fF -C2373 pll_full_0/pd_0/REF vdd 6.44fF -C2374 pll_full_0/pd_0/tspc_r_0/z5 vdd 1.10fF -C2375 pll_full_0/pd_0/tspc_r_0/Z4 vdd 1.07fF -C2376 pll_full_0/pd_0/R vdd 3.05fF -C2377 pll_full_0/pd_0/tspc_r_0/Qbar vdd 0.79fF -C2378 pll_full_0/pd_0/tspc_r_0/Z2 vdd 1.22fF -C2379 pll_full_0/pd_0/tspc_r_0/Z1 vdd 0.67fF -C2380 pll_full_0/pd_0/DOWN vdd 7.24fF -C2381 pll_full_0/pd_0/tspc_r_0/Qbar1 vdd 1.34fF -C2382 pll_full_0/pd_0/tspc_r_0/Z3 vdd 2.12fF -C2383 pll_full_0/pd_0/DIV vdd 371.86fF -C2384 divider_2/and_0/Z1 vdd 0.33fF -C2385 divider_2/and_0/B vdd 1.79fF -C2386 divider_2/and_0/A vdd 1.66fF -C2387 divider_2/and_0/out1 vdd 2.71fF -C2388 divider_2/tspc_2/Z4 vdd 0.42fF -C2389 divider_2/Out vdd 1.31fF -C2390 divider_2/tspc_2/Z3 vdd 2.00fF -C2391 divider_2/tspc_2/Z2 vdd 1.29fF -C2392 divider_2/tspc_2/Z1 vdd 0.99fF -C2393 divider_2/nor_0/B vdd 5.25fF -C2394 divider_2/tspc_2/a_630_n680# vdd 0.53fF **FLOATING -C2395 divider_2/tspc_1/Z4 vdd 0.42fF -C2396 divider_2/tspc_1/Q vdd 2.79fF -C2397 divider_2/tspc_1/Z3 vdd 2.00fF -C2398 divider_2/tspc_1/Z2 vdd 1.29fF -C2399 divider_2/tspc_1/Z1 vdd 0.99fF -C2400 divider_2/nor_1/B vdd 5.95fF -C2401 divider_2/tspc_1/a_630_n680# vdd 0.53fF **FLOATING -C2402 divider_2/tspc_0/Z4 vdd 0.42fF -C2403 divider_2/tspc_0/Q vdd 2.81fF -C2404 divider_2/tspc_0/Z3 vdd 2.00fF -C2405 divider_2/tspc_0/Z2 vdd 1.30fF -C2406 divider_2/tspc_0/Z1 vdd 0.99fF -C2407 divider_2/nor_1/A vdd 6.02fF -C2408 divider_2/tspc_0/a_630_n680# vdd 0.53fF **FLOATING -C2409 divider_2/clk vdd 5.56fF -C2410 divider_2/prescaler_0/Out vdd 4.13fF -C2411 divider_2/prescaler_0/nand_1/z1 vdd 0.20fF -C2412 divider_2/prescaler_0/tspc_2/D vdd 2.59fF -C2413 divider_2/prescaler_0/tspc_0/Q vdd 3.30fF -C2414 divider_2/prescaler_0/tspc_1/Q vdd 2.78fF -C2415 divider_2/prescaler_0/nand_0/z1 vdd 0.20fF -C2416 divider_2/prescaler_0/tspc_0/D vdd 3.07fF -C2417 divider_2/and_0/OUT vdd 5.35fF -C2418 divider_2/prescaler_0/tspc_2/Z4 vdd 0.42fF -C2419 divider_2/prescaler_0/tspc_2/Z3 vdd 2.00fF -C2420 divider_2/prescaler_0/tspc_2/Z2 vdd 1.30fF -C2421 divider_2/prescaler_0/tspc_2/Z1 vdd 0.99fF -C2422 divider_2/prescaler_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING -C2423 divider_2/prescaler_0/tspc_2/a_740_n680# vdd 1.89fF **FLOATING -C2424 divider_2/prescaler_0/tspc_1/Z4 vdd 0.42fF -C2425 divider_2/prescaler_0/tspc_1/Z3 vdd 2.00fF -C2426 divider_2/prescaler_0/tspc_1/Z2 vdd 1.31fF -C2427 divider_2/prescaler_0/tspc_1/Z1 vdd 0.99fF -C2428 divider_2/prescaler_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING -C2429 divider_2/prescaler_0/m1_2700_2190# vdd 3.99fF **FLOATING -C2430 divider_2/prescaler_0/tspc_0/Z4 vdd 0.42fF -C2431 divider_2/prescaler_0/tspc_0/Z3 vdd 2.00fF -C2432 divider_2/prescaler_0/tspc_0/Z2 vdd 1.30fF -C2433 divider_2/prescaler_0/tspc_0/Z1 vdd 0.99fF -C2434 divider_2/prescaler_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING -C2435 divider_2/prescaler_0/tspc_0/a_740_n680# vdd 1.89fF **FLOATING -C2436 divider_2/nor_1/Z1 vdd 1.33fF -C2437 divider_2/nor_0/Z1 vdd 1.33fF -C2438 divider_2/mc2 vdd 3.93fF -C2439 divider_1/and_0/Z1 vdd 0.33fF -C2440 divider_1/and_0/B vdd 1.79fF -C2441 divider_1/and_0/A vdd 1.66fF -C2442 divider_1/and_0/out1 vdd 2.71fF -C2443 divider_1/tspc_2/Z4 vdd 0.42fF -C2444 divider_1/Out vdd 1.31fF -C2445 divider_1/tspc_2/Z3 vdd 2.00fF -C2446 divider_1/tspc_2/Z2 vdd 1.29fF -C2447 divider_1/tspc_2/Z1 vdd 0.99fF -C2448 divider_1/nor_0/B vdd 5.25fF -C2449 divider_1/tspc_2/a_630_n680# vdd 0.53fF **FLOATING -C2450 divider_1/tspc_1/Z4 vdd 0.42fF -C2451 divider_1/tspc_1/Q vdd 2.79fF -C2452 divider_1/tspc_1/Z3 vdd 2.00fF -C2453 divider_1/tspc_1/Z2 vdd 1.29fF -C2454 divider_1/tspc_1/Z1 vdd 0.99fF -C2455 divider_1/nor_1/B vdd 5.95fF -C2456 divider_1/tspc_1/a_630_n680# vdd 0.53fF **FLOATING -C2457 divider_1/tspc_0/Z4 vdd 0.42fF -C2458 divider_1/tspc_0/Q vdd 2.81fF -C2459 divider_1/tspc_0/Z3 vdd 2.00fF -C2460 divider_1/tspc_0/Z2 vdd 1.30fF -C2461 divider_1/tspc_0/Z1 vdd 0.99fF -C2462 divider_1/nor_1/A vdd 6.02fF -C2463 divider_1/tspc_0/a_630_n680# vdd 0.53fF **FLOATING -C2464 divider_1/clk vdd 5.56fF -C2465 divider_1/prescaler_0/Out vdd 4.13fF -C2466 divider_1/prescaler_0/nand_1/z1 vdd 0.20fF -C2467 divider_1/prescaler_0/tspc_2/D vdd 2.59fF -C2468 divider_1/prescaler_0/tspc_0/Q vdd 3.30fF -C2469 divider_1/prescaler_0/tspc_1/Q vdd 2.78fF -C2470 divider_1/prescaler_0/nand_0/z1 vdd 0.20fF -C2471 divider_1/prescaler_0/tspc_0/D vdd 3.07fF -C2472 divider_1/and_0/OUT vdd 5.35fF -C2473 divider_1/prescaler_0/tspc_2/Z4 vdd 0.42fF -C2474 divider_1/prescaler_0/tspc_2/Z3 vdd 2.00fF -C2475 divider_1/prescaler_0/tspc_2/Z2 vdd 1.30fF -C2476 divider_1/prescaler_0/tspc_2/Z1 vdd 0.99fF -C2477 divider_1/prescaler_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING -C2478 divider_1/prescaler_0/tspc_2/a_740_n680# vdd 1.89fF **FLOATING -C2479 divider_1/prescaler_0/tspc_1/Z4 vdd 0.42fF -C2480 divider_1/prescaler_0/tspc_1/Z3 vdd 2.00fF -C2481 divider_1/prescaler_0/tspc_1/Z2 vdd 1.31fF -C2482 divider_1/prescaler_0/tspc_1/Z1 vdd 0.99fF -C2483 divider_1/prescaler_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING -C2484 divider_1/prescaler_0/m1_2700_2190# vdd 3.99fF **FLOATING -C2485 divider_1/prescaler_0/tspc_0/Z4 vdd 0.42fF -C2486 divider_1/prescaler_0/tspc_0/Z3 vdd 2.00fF -C2487 divider_1/prescaler_0/tspc_0/Z2 vdd 1.30fF -C2488 divider_1/prescaler_0/tspc_0/Z1 vdd 0.99fF -C2489 divider_1/prescaler_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING -C2490 divider_1/prescaler_0/tspc_0/a_740_n680# vdd 1.89fF **FLOATING -C2491 divider_1/nor_1/Z1 vdd 1.33fF -C2492 divider_1/nor_0/Z1 vdd 1.33fF -C2493 divider_1/mc2 vdd 3.93fF -C2494 divider_0/and_0/Z1 vdd 0.33fF -C2495 divider_0/and_0/B vdd 1.79fF -C2496 divider_0/and_0/A vdd 1.66fF -C2497 divider_0/and_0/out1 vdd 2.71fF -C2498 divider_0/tspc_2/Z4 vdd 0.42fF -C2499 divider_0/Out vdd 1.31fF -C2500 divider_0/tspc_2/Z3 vdd 2.00fF -C2501 divider_0/tspc_2/Z2 vdd 1.29fF -C2502 divider_0/tspc_2/Z1 vdd 0.99fF -C2503 divider_0/nor_0/B vdd 5.25fF -C2504 divider_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING -C2505 divider_0/tspc_1/Z4 vdd 0.42fF -C2506 divider_0/tspc_1/Q vdd 2.79fF -C2507 divider_0/tspc_1/Z3 vdd 2.00fF -C2508 divider_0/tspc_1/Z2 vdd 1.29fF -C2509 divider_0/tspc_1/Z1 vdd 0.99fF -C2510 divider_0/nor_1/B vdd 5.95fF -C2511 divider_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING -C2512 divider_0/tspc_0/Z4 vdd 0.42fF -C2513 divider_0/tspc_0/Q vdd 2.81fF -C2514 divider_0/tspc_0/Z3 vdd 2.00fF -C2515 divider_0/tspc_0/Z2 vdd 1.30fF -C2516 divider_0/tspc_0/Z1 vdd 0.99fF -C2517 divider_0/nor_1/A vdd 6.02fF -C2518 divider_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING -C2519 divider_0/clk vdd 5.56fF -C2520 divider_0/prescaler_0/Out vdd 4.13fF -C2521 divider_0/prescaler_0/nand_1/z1 vdd 0.20fF -C2522 divider_0/prescaler_0/tspc_2/D vdd 2.59fF -C2523 divider_0/prescaler_0/tspc_0/Q vdd 3.30fF -C2524 divider_0/prescaler_0/tspc_1/Q vdd 2.78fF -C2525 divider_0/prescaler_0/nand_0/z1 vdd 0.20fF -C2526 divider_0/prescaler_0/tspc_0/D vdd 3.07fF -C2527 divider_0/and_0/OUT vdd 5.35fF -C2528 divider_0/prescaler_0/tspc_2/Z4 vdd 0.42fF -C2529 divider_0/prescaler_0/tspc_2/Z3 vdd 2.00fF -C2530 divider_0/prescaler_0/tspc_2/Z2 vdd 1.30fF -C2531 divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF -C2532 divider_0/prescaler_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING -C2533 divider_0/prescaler_0/tspc_2/a_740_n680# vdd 1.89fF **FLOATING -C2534 divider_0/prescaler_0/tspc_1/Z4 vdd 0.42fF -C2535 divider_0/prescaler_0/tspc_1/Z3 vdd 2.00fF -C2536 divider_0/prescaler_0/tspc_1/Z2 vdd 1.31fF -C2537 divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF -C2538 divider_0/prescaler_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING -C2539 divider_0/prescaler_0/m1_2700_2190# vdd 3.99fF **FLOATING -C2540 divider_0/prescaler_0/tspc_0/Z4 vdd 0.42fF -C2541 divider_0/prescaler_0/tspc_0/Z3 vdd 2.00fF -C2542 divider_0/prescaler_0/tspc_0/Z2 vdd 1.30fF -C2543 divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF -C2544 divider_0/prescaler_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING -C2545 divider_0/prescaler_0/tspc_0/a_740_n680# vdd 1.89fF **FLOATING -C2546 divider_0/nor_1/Z1 vdd 1.33fF -C2547 divider_0/nor_0/Z1 vdd 1.33fF -C2548 divider_0/mc2 vdd 3.93fF -C2549 divbuf_7/OUT vdd 363.82fF -C2550 divbuf_7/OUT5 vdd 350.37fF -C2551 divbuf_7/OUT4 vdd 133.72fF -C2552 divbuf_7/OUT3 vdd 34.03fF -C2553 divbuf_7/OUT2 vdd 8.71fF -C2554 divbuf_7/IN vdd 0.89fF -C2555 divbuf_7/a_492_n240# vdd 2.46fF **FLOATING -C2556 divbuf_6/OUT vdd 363.82fF -C2557 divbuf_6/OUT5 vdd 350.37fF -C2558 divbuf_6/OUT4 vdd 133.72fF -C2559 divbuf_6/OUT3 vdd 34.03fF -C2560 divbuf_6/OUT2 vdd 8.71fF -C2561 divbuf_6/IN vdd 0.89fF -C2562 divbuf_6/a_492_n240# vdd 2.46fF **FLOATING -C2563 divbuf_5/OUT vdd 363.82fF -C2564 divbuf_5/OUT5 vdd 350.37fF -C2565 divbuf_5/OUT4 vdd 133.72fF -C2566 divbuf_5/OUT3 vdd 34.03fF -C2567 divbuf_5/OUT2 vdd 8.71fF -C2568 divbuf_5/IN vdd 0.89fF -C2569 divbuf_5/a_492_n240# vdd 2.46fF **FLOATING -C2570 divbuf_4/OUT vdd 363.82fF -C2571 divbuf_4/OUT5 vdd 350.37fF -C2572 divbuf_4/OUT4 vdd 133.72fF -C2573 divbuf_4/OUT3 vdd 34.03fF -C2574 divbuf_4/OUT2 vdd 8.71fF -C2575 divbuf_4/IN vdd 0.89fF -C2576 divbuf_4/a_492_n240# vdd 2.46fF **FLOATING -C2577 divbuf_3/OUT vdd 363.82fF -C2578 divbuf_3/OUT5 vdd 350.37fF -C2579 divbuf_3/OUT4 vdd 133.72fF -C2580 divbuf_3/OUT3 vdd 34.03fF -C2581 divbuf_3/OUT2 vdd 8.71fF -C2582 divbuf_3/IN vdd 0.89fF -C2583 divbuf_3/a_492_n240# vdd 2.46fF **FLOATING -C2584 divbuf_2/OUT vdd 363.82fF -C2585 divbuf_2/OUT5 vdd 350.37fF -C2586 divbuf_2/OUT4 vdd 133.72fF -C2587 divbuf_2/OUT3 vdd 34.03fF -C2588 divbuf_2/OUT2 vdd 8.71fF -C2589 divbuf_2/IN vdd 0.89fF -C2590 divbuf_2/a_492_n240# vdd 2.46fF **FLOATING -C2591 divbuf_1/OUT vdd 363.82fF -C2592 divbuf_1/OUT5 vdd 350.37fF -C2593 divbuf_1/OUT4 vdd 133.72fF -C2594 divbuf_1/OUT3 vdd 34.03fF -C2595 divbuf_1/OUT2 vdd 8.71fF -C2596 divbuf_1/IN vdd 0.89fF -C2597 divbuf_1/a_492_n240# vdd 2.46fF **FLOATING -C2598 ro_complete_1/cbank_2/v vdd 17.84fF -C2599 ro_complete_1/cbank_2/switch_5/vin vdd 0.78fF -C2600 ro_complete_1/cbank_2/switch_4/vin vdd 1.50fF -C2601 ro_complete_1/cbank_2/switch_2/vin vdd 1.30fF -C2602 ro_complete_1/cbank_2/switch_3/vin vdd 0.56fF -C2603 ro_complete_1/cbank_2/switch_1/vin vdd 1.14fF -C2604 ro_complete_1/cbank_2/switch_0/vin vdd 1.02fF -C2605 ro_complete_1/cbank_1/v vdd 16.34fF -C2606 ro_complete_1/cbank_1/switch_5/vin vdd 0.78fF -C2607 ro_complete_1/a0 vdd 7.88fF -C2608 ro_complete_1/cbank_1/switch_4/vin vdd 1.50fF -C2609 ro_complete_1/a1 vdd 5.39fF -C2610 ro_complete_1/cbank_1/switch_2/vin vdd 1.30fF -C2611 ro_complete_1/a3 vdd 6.85fF -C2612 ro_complete_1/cbank_1/switch_3/vin vdd 0.56fF -C2613 ro_complete_1/a2 vdd 5.48fF -C2614 ro_complete_1/cbank_1/switch_1/vin vdd 1.14fF -C2615 ro_complete_1/a4 vdd 5.36fF -C2616 ro_complete_1/cbank_1/switch_0/vin vdd 1.02fF -C2617 ro_complete_1/a5 vdd 5.19fF -C2618 ro_complete_1/cbank_0/v vdd 14.98fF -C2619 ro_complete_1/cbank_0/switch_5/vin vdd 0.78fF -C2620 ro_complete_1/cbank_0/switch_4/vin vdd 1.50fF -C2621 ro_complete_1/cbank_0/switch_2/vin vdd 1.30fF -C2622 ro_complete_1/cbank_0/switch_3/vin vdd 0.56fF -C2623 ro_complete_1/cbank_0/switch_1/vin vdd 1.14fF -C2624 ro_complete_1/cbank_0/switch_0/vin vdd 1.02fF -C2625 ro_complete_1/ro_var_extend_0/vcont vdd 0.27fF -C2626 divbuf_0/OUT vdd 363.82fF -C2627 divbuf_0/OUT5 vdd 350.37fF -C2628 divbuf_0/OUT4 vdd 133.72fF -C2629 divbuf_0/OUT3 vdd 34.03fF -C2630 divbuf_0/OUT2 vdd 8.71fF -C2631 divbuf_0/IN vdd 0.89fF -C2632 divbuf_0/a_492_n240# vdd 2.46fF **FLOATING -C2633 ro_complete_0/cbank_2/v vdd 17.84fF -C2634 ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF -C2635 ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF -C2636 ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF -C2637 ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF -C2638 ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF -C2639 ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF -C2640 ro_complete_0/cbank_1/v vdd 16.38fF -C2641 ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF -C2642 ro_complete_0/a0 vdd 7.88fF -C2643 ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF -C2644 ro_complete_0/a1 vdd 5.39fF -C2645 ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF -C2646 ro_complete_0/a3 vdd 6.85fF -C2647 ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF -C2648 ro_complete_0/a2 vdd 5.48fF -C2649 ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF -C2650 ro_complete_0/a4 vdd 5.36fF -C2651 ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF -C2652 ro_complete_0/a5 vdd 5.19fF -C2653 ro_complete_0/cbank_0/v vdd 14.98fF -C2654 ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF -C2655 ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF -C2656 ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF -C2657 ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF -C2658 ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF -C2659 ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF -C2660 ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF -C2661 filter_0/v vdd 85.69fF -C2662 filter_0/a_4216_n5230# vdd 418.47fF **FLOATING -C2663 filter_0/a_4216_n2998# vdd 1.03fF **FLOATING -C2664 cp_0/down vdd 1.54fF -C2665 cp_0/vbias vdd 2.41fF -C2666 cp_0/out vdd 5.26fF -C2667 cp_0/upbar vdd 1.50fF -C2668 cp_0/a_7110_n2840# vdd 0.17fF **FLOATING -C2669 cp_0/a_3060_n2840# vdd 1.71fF **FLOATING -C2670 cp_0/a_7110_0# vdd 0.17fF **FLOATING -C2671 cp_0/a_6370_0# vdd 0.40fF **FLOATING -C2672 cp_0/a_3060_0# vdd 1.65fF **FLOATING -C2673 cp_0/a_1710_0# vdd 5.76fF **FLOATING -C2674 cp_0/a_1710_n2840# vdd 4.89fF **FLOATING -C2675 cp_0/a_10_n50# vdd 2.96fF **FLOATING -C2676 pd_1/and_pd_0/Z1 vdd 0.39fF -C2677 pd_1/and_pd_0/Out1 vdd 2.22fF -C2678 pd_1/tspc_r_1/z5 vdd 1.10fF -C2679 pd_1/tspc_r_1/Z4 vdd 1.07fF -C2680 pd_1/tspc_r_1/Qbar vdd 0.88fF -C2681 pd_1/tspc_r_1/Z2 vdd 1.22fF -C2682 pd_1/tspc_r_1/Z1 vdd 0.67fF -C2683 pd_1/UP vdd 2.21fF -C2684 pd_1/tspc_r_1/Qbar1 vdd 1.34fF -C2685 pd_1/tspc_r_1/Z3 vdd 2.12fF -C2686 pd_1/REF vdd 1.80fF -C2687 pd_1/tspc_r_0/z5 vdd 1.10fF -C2688 pd_1/tspc_r_0/Z4 vdd 1.07fF -C2689 pd_1/R vdd 3.05fF -C2690 pd_1/tspc_r_0/Qbar vdd 0.79fF -C2691 pd_1/tspc_r_0/Z2 vdd 1.22fF -C2692 pd_1/tspc_r_0/Z1 vdd 0.67fF -C2693 pd_1/DOWN vdd 3.08fF -C2694 pd_1/tspc_r_0/Qbar1 vdd 1.34fF -C2695 pd_1/tspc_r_0/Z3 vdd 2.12fF -C2696 pd_1/DIV vdd 1.82fF -C2697 pd_0/and_pd_0/Z1 vdd 0.39fF -C2698 pd_0/and_pd_0/Out1 vdd 2.22fF -C2699 pd_0/tspc_r_1/z5 vdd 1.10fF -C2700 pd_0/tspc_r_1/Z4 vdd 1.07fF -C2701 pd_0/tspc_r_1/Qbar vdd 0.88fF -C2702 pd_0/tspc_r_1/Z2 vdd 1.22fF -C2703 pd_0/tspc_r_1/Z1 vdd 0.67fF -C2704 pd_0/UP vdd 2.21fF -C2705 pd_0/tspc_r_1/Qbar1 vdd 1.34fF -C2706 pd_0/tspc_r_1/Z3 vdd 2.12fF -C2707 pd_0/REF vdd 1.80fF -C2708 pd_0/tspc_r_0/z5 vdd 1.10fF -C2709 pd_0/tspc_r_0/Z4 vdd 1.07fF -C2710 pd_0/R vdd 3.05fF -C2711 pd_0/tspc_r_0/Qbar vdd 0.79fF -C2712 pd_0/tspc_r_0/Z2 vdd 1.22fF -C2713 pd_0/tspc_r_0/Z1 vdd 0.67fF -C2714 pd_0/DOWN vdd 3.08fF -C2715 pd_0/tspc_r_0/Qbar1 vdd 1.34fF -C2716 pd_0/tspc_r_0/Z3 vdd 2.12fF -C2717 pd_0/DIV vdd 1.82fF +C1850 io_analog[4] vdd 43.96fF +C1851 io_analog[5] vdd 44.13fF +C1852 io_analog[6] vdd 43.46fF +C1853 io_in_3v3[0] vdd 0.61fF +C1854 io_oeb[26] vdd 0.61fF +C1855 io_in[0] vdd 0.61fF +C1856 io_out[26] vdd 0.61fF +C1857 io_out[0] vdd 0.61fF +C1858 io_in[26] vdd 0.61fF +C1859 io_oeb[0] vdd 0.61fF +C1860 io_in_3v3[26] vdd 0.61fF +C1861 io_in_3v3[1] vdd 0.61fF +C1862 io_oeb[25] vdd 0.61fF +C1863 io_in[1] vdd 0.61fF +C1864 io_out[25] vdd 0.61fF +C1865 io_out[1] vdd 0.61fF +C1866 io_in[25] vdd 0.61fF +C1867 io_oeb[1] vdd 0.61fF +C1868 io_in_3v3[25] vdd 0.61fF +C1869 io_in_3v3[2] vdd 0.61fF +C1870 io_oeb[24] vdd 0.61fF +C1871 io_in[2] vdd 0.61fF +C1872 io_out[24] vdd 0.61fF +C1873 io_out[2] vdd 0.61fF +C1874 io_in[24] vdd 0.61fF +C1875 io_oeb[2] vdd 0.61fF +C1876 io_in_3v3[24] vdd 0.61fF +C1877 io_in_3v3[3] vdd 0.61fF +C1878 gpio_noesd[17] vdd 2.32fF +C1879 io_in[3] vdd 0.61fF +C1880 gpio_analog[17] vdd 2.30fF +C1881 io_out[3] vdd 0.61fF +C1882 io_oeb[3] vdd 0.61fF +C1883 io_in_3v3[4] vdd 0.61fF +C1884 io_in[4] vdd 0.61fF +C1885 io_out[4] vdd 0.61fF +C1886 io_oeb[4] vdd 0.61fF +C1887 io_oeb[23] vdd 0.61fF +C1888 io_out[23] vdd 0.61fF +C1889 io_in[23] vdd 0.61fF +C1890 io_in_3v3[23] vdd 0.61fF +C1891 gpio_noesd[16] vdd 2.30fF +C1892 gpio_analog[16] vdd 2.30fF +C1893 io_in_3v3[5] vdd 0.61fF +C1894 io_in[5] vdd 0.61fF +C1895 io_out[5] vdd 0.61fF +C1896 io_oeb[5] vdd 0.61fF +C1897 io_oeb[22] vdd 0.61fF +C1898 io_out[22] vdd 0.61fF +C1899 io_in[22] vdd 0.61fF +C1900 io_in_3v3[22] vdd 0.61fF +C1901 gpio_noesd[15] vdd 2.31fF +C1902 gpio_analog[15] vdd 2.30fF +C1903 io_in_3v3[6] vdd 0.61fF +C1904 io_in[6] vdd 0.61fF +C1905 io_out[6] vdd 0.61fF +C1906 io_oeb[6] vdd 0.61fF +C1907 io_oeb[21] vdd 0.61fF +C1908 io_out[21] vdd 0.61fF +C1909 io_in[21] vdd 0.61fF +C1910 io_in_3v3[21] vdd 0.61fF +C1911 gpio_noesd[14] vdd 2.30fF +C1912 gpio_analog[14] vdd 2.29fF +C1913 vssd2 vdd 38.54fF +C1914 vssd1 vdd 13.04fF +C1915 vdda2 vdd 38.30fF +C1916 io_oeb[20] vdd 0.61fF +C1917 io_out[20] vdd 0.61fF +C1918 io_in[20] vdd 0.61fF +C1919 io_in_3v3[20] vdd 0.61fF +C1920 gpio_noesd[13] vdd 2.31fF +C1921 gpio_analog[13] vdd 2.30fF +C1922 gpio_analog[0] vdd 0.61fF +C1923 gpio_noesd[0] vdd 0.61fF +C1924 io_in_3v3[7] vdd 0.61fF +C1925 io_in[7] vdd 0.61fF +C1926 io_out[7] vdd 0.61fF +C1927 io_oeb[7] vdd 0.61fF +C1928 io_oeb[19] vdd 0.61fF +C1929 io_out[19] vdd 0.61fF +C1930 io_in[19] vdd 0.61fF +C1931 io_in_3v3[19] vdd 0.61fF +C1932 gpio_noesd[12] vdd 2.32fF +C1933 gpio_analog[12] vdd 2.30fF +C1934 gpio_analog[1] vdd 0.61fF +C1935 gpio_noesd[1] vdd 0.61fF +C1936 io_in_3v3[8] vdd 0.61fF +C1937 io_in[8] vdd 0.61fF +C1938 io_out[8] vdd 0.61fF +C1939 io_oeb[8] vdd 0.61fF +C1940 io_oeb[18] vdd 0.61fF +C1941 io_out[18] vdd 0.61fF +C1942 io_in[18] vdd 0.61fF +C1943 io_in_3v3[18] vdd 0.61fF +C1944 gpio_noesd[11] vdd 2.30fF +C1945 gpio_analog[11] vdd 2.29fF +C1946 gpio_analog[2] vdd 0.61fF +C1947 gpio_noesd[2] vdd 0.61fF +C1948 io_in_3v3[9] vdd 0.61fF +C1949 io_in[9] vdd 0.61fF +C1950 io_out[9] vdd 0.61fF +C1951 io_oeb[9] vdd 0.61fF +C1952 io_oeb[17] vdd 0.61fF +C1953 io_out[17] vdd 0.61fF +C1954 io_in[17] vdd 0.61fF +C1955 io_in_3v3[17] vdd 0.61fF +C1956 gpio_noesd[10] vdd 2.31fF +C1957 gpio_analog[10] vdd 2.29fF +C1958 gpio_analog[3] vdd 0.61fF +C1959 gpio_noesd[3] vdd 0.61fF +C1960 io_in_3v3[10] vdd 0.61fF +C1961 io_in[10] vdd 0.61fF +C1962 io_out[10] vdd 0.61fF +C1963 io_oeb[10] vdd 0.61fF +C1964 io_oeb[16] vdd 0.61fF +C1965 io_out[16] vdd 0.61fF +C1966 io_in[16] vdd 0.61fF +C1967 io_in_3v3[16] vdd 0.61fF +C1968 gpio_noesd[9] vdd 2.28fF +C1969 gpio_analog[9] vdd 2.28fF +C1970 gpio_analog[4] vdd 0.61fF +C1971 gpio_noesd[4] vdd 0.61fF +C1972 io_in_3v3[11] vdd 0.61fF +C1973 io_in[11] vdd 0.61fF +C1974 io_out[11] vdd 0.61fF +C1975 io_oeb[11] vdd 0.61fF +C1976 io_oeb[15] vdd 0.61fF +C1977 io_out[15] vdd 0.61fF +C1978 io_in[15] vdd 0.61fF +C1979 io_in_3v3[15] vdd 0.61fF +C1980 gpio_noesd[8] vdd 2.28fF +C1981 gpio_analog[8] vdd 2.26fF +C1982 gpio_analog[5] vdd 0.61fF +C1983 gpio_noesd[5] vdd 0.61fF +C1984 io_in_3v3[12] vdd 0.61fF +C1985 io_in[12] vdd 0.61fF +C1986 io_out[12] vdd 0.61fF +C1987 io_oeb[12] vdd 0.61fF +C1988 io_oeb[14] vdd 0.61fF +C1989 io_out[14] vdd 0.61fF +C1990 io_in[14] vdd 0.61fF +C1991 io_in_3v3[14] vdd 0.61fF +C1992 gpio_noesd[7] vdd 2.30fF +C1993 gpio_analog[7] vdd 2.28fF +C1994 vssa2 vdd 38.35fF +C1995 gpio_analog[6] vdd 5.71fF +C1996 gpio_noesd[6] vdd 5.70fF +C1997 io_in_3v3[13] vdd 0.61fF +C1998 io_in[13] vdd 0.61fF +C1999 io_out[13] vdd 0.61fF +C2000 io_oeb[13] vdd 0.61fF +C2001 vccd1 vdd 39.84fF +C2002 vccd2 vdd 38.46fF +C2003 io_analog[0] vdd 19.99fF +C2004 io_analog[10] vdd 19.36fF +C2005 io_analog[1] vdd 13.17fF +C2006 io_analog[2] vdd 12.57fF +C2007 io_analog[3] vdd 12.83fF +C2008 io_clamp_high[0] vdd 3.58fF +C2009 io_clamp_low[0] vdd 3.58fF +C2010 io_clamp_high[1] vdd 3.58fF +C2011 io_clamp_low[1] vdd 3.58fF +C2012 io_clamp_high[2] vdd 3.58fF +C2013 io_clamp_low[2] vdd 3.58fF +C2014 io_analog[7] vdd 12.74fF +C2015 io_analog[8] vdd 13.08fF +C2016 io_analog[9] vdd 13.08fF +C2017 user_irq[2] vdd 0.63fF +C2018 user_irq[1] vdd 0.63fF +C2019 user_irq[0] vdd 0.63fF +C2020 user_clock2 vdd 0.63fF +C2021 la_oenb[127] vdd 0.63fF +C2022 la_data_out[127] vdd 0.63fF +C2023 la_data_in[127] vdd 0.63fF +C2024 la_oenb[126] vdd 0.63fF +C2025 la_data_out[126] vdd 0.63fF +C2026 la_data_in[126] vdd 0.63fF +C2027 la_oenb[125] vdd 0.63fF +C2028 la_data_out[125] vdd 0.63fF +C2029 la_data_in[125] vdd 0.63fF +C2030 la_oenb[124] vdd 0.63fF +C2031 la_data_out[124] vdd 0.63fF +C2032 la_data_in[124] vdd 0.63fF +C2033 la_oenb[123] vdd 0.63fF +C2034 la_data_out[123] vdd 0.63fF +C2035 la_data_in[123] vdd 0.63fF +C2036 la_oenb[122] vdd 0.63fF +C2037 la_data_out[122] vdd 0.63fF +C2038 la_data_in[122] vdd 0.63fF +C2039 la_oenb[121] vdd 0.63fF +C2040 la_data_out[121] vdd 0.63fF +C2041 la_data_in[121] vdd 0.63fF +C2042 la_oenb[120] vdd 0.63fF +C2043 la_data_out[120] vdd 0.63fF +C2044 la_data_in[120] vdd 0.63fF +C2045 la_oenb[119] vdd 0.63fF +C2046 la_data_out[119] vdd 0.63fF +C2047 la_data_in[119] vdd 0.63fF +C2048 la_oenb[118] vdd 0.63fF +C2049 la_data_out[118] vdd 0.63fF +C2050 la_data_in[118] vdd 0.63fF +C2051 la_oenb[117] vdd 0.63fF +C2052 la_data_out[117] vdd 0.63fF +C2053 la_data_in[117] vdd 0.63fF +C2054 la_oenb[116] vdd 0.63fF +C2055 la_data_out[116] vdd 0.63fF +C2056 la_data_in[116] vdd 0.63fF +C2057 la_oenb[115] vdd 0.63fF +C2058 la_data_out[115] vdd 0.63fF +C2059 la_data_in[115] vdd 0.63fF +C2060 la_oenb[114] vdd 0.63fF +C2061 la_data_out[114] vdd 0.63fF +C2062 la_data_in[114] vdd 0.63fF +C2063 la_oenb[113] vdd 0.63fF +C2064 la_data_out[113] vdd 0.63fF +C2065 la_data_in[113] vdd 0.63fF +C2066 la_oenb[112] vdd 0.63fF +C2067 la_data_out[112] vdd 0.63fF +C2068 la_data_in[112] vdd 0.63fF +C2069 la_oenb[111] vdd 0.63fF +C2070 la_data_out[111] vdd 0.63fF +C2071 la_data_in[111] vdd 0.63fF +C2072 la_oenb[110] vdd 0.63fF +C2073 la_data_out[110] vdd 0.63fF +C2074 la_data_in[110] vdd 0.63fF +C2075 la_oenb[109] vdd 0.63fF +C2076 la_data_out[109] vdd 0.63fF +C2077 la_data_in[109] vdd 0.63fF +C2078 la_oenb[108] vdd 0.63fF +C2079 la_data_out[108] vdd 0.63fF +C2080 la_data_in[108] vdd 0.63fF +C2081 la_oenb[107] vdd 0.63fF +C2082 la_data_out[107] vdd 0.63fF +C2083 la_data_in[107] vdd 0.63fF +C2084 la_oenb[106] vdd 0.63fF +C2085 la_data_out[106] vdd 0.63fF +C2086 la_data_in[106] vdd 0.63fF +C2087 la_oenb[105] vdd 0.63fF +C2088 la_data_out[105] vdd 0.63fF +C2089 la_data_in[105] vdd 0.63fF +C2090 la_oenb[104] vdd 0.63fF +C2091 la_data_out[104] vdd 0.63fF +C2092 la_data_in[104] vdd 0.63fF +C2093 la_oenb[103] vdd 0.63fF +C2094 la_data_out[103] vdd 0.63fF +C2095 la_data_in[103] vdd 0.63fF +C2096 la_oenb[102] vdd 0.63fF +C2097 la_data_out[102] vdd 0.63fF +C2098 la_data_in[102] vdd 0.63fF +C2099 la_oenb[101] vdd 0.63fF +C2100 la_data_out[101] vdd 0.63fF +C2101 la_data_in[101] vdd 0.63fF +C2102 la_oenb[100] vdd 0.63fF +C2103 la_data_out[100] vdd 0.63fF +C2104 la_data_in[100] vdd 0.63fF +C2105 la_oenb[99] vdd 0.63fF +C2106 la_data_out[99] vdd 0.63fF +C2107 la_data_in[99] vdd 0.63fF +C2108 la_oenb[98] vdd 0.63fF +C2109 la_data_out[98] vdd 0.63fF +C2110 la_data_in[98] vdd 0.63fF +C2111 la_oenb[97] vdd 0.63fF +C2112 la_data_out[97] vdd 0.63fF +C2113 la_data_in[97] vdd 0.63fF +C2114 la_oenb[96] vdd 0.63fF +C2115 la_data_out[96] vdd 0.63fF +C2116 la_data_in[96] vdd 0.63fF +C2117 la_oenb[95] vdd 0.63fF +C2118 la_data_out[95] vdd 0.63fF +C2119 la_data_in[95] vdd 0.63fF +C2120 la_oenb[94] vdd 0.63fF +C2121 la_data_out[94] vdd 0.63fF +C2122 la_data_in[94] vdd 0.63fF +C2123 la_oenb[93] vdd 0.63fF +C2124 la_data_out[93] vdd 0.63fF +C2125 la_data_in[93] vdd 0.63fF +C2126 la_oenb[92] vdd 0.63fF +C2127 la_data_out[92] vdd 0.63fF +C2128 la_data_in[92] vdd 0.63fF +C2129 la_oenb[91] vdd 0.63fF +C2130 la_data_out[91] vdd 0.63fF +C2131 la_data_in[91] vdd 0.63fF +C2132 la_oenb[90] vdd 0.63fF +C2133 la_data_out[90] vdd 0.63fF +C2134 la_data_in[90] vdd 0.63fF +C2135 la_oenb[89] vdd 0.63fF +C2136 la_data_out[89] vdd 0.63fF +C2137 la_data_in[89] vdd 0.63fF +C2138 la_oenb[88] vdd 0.63fF +C2139 la_data_out[88] vdd 0.63fF +C2140 la_data_in[88] vdd 0.63fF +C2141 la_oenb[87] vdd 0.63fF +C2142 la_data_out[87] vdd 0.63fF +C2143 la_data_in[87] vdd 0.63fF +C2144 la_oenb[86] vdd 0.63fF +C2145 la_data_out[86] vdd 0.63fF +C2146 la_data_in[86] vdd 0.63fF +C2147 la_oenb[85] vdd 0.63fF +C2148 la_data_out[85] vdd 0.63fF +C2149 la_data_in[85] vdd 0.63fF +C2150 la_oenb[84] vdd 0.63fF +C2151 la_data_out[84] vdd 0.63fF +C2152 la_data_in[84] vdd 0.63fF +C2153 la_oenb[83] vdd 0.63fF +C2154 la_data_out[83] vdd 0.63fF +C2155 la_data_in[83] vdd 0.63fF +C2156 la_oenb[82] vdd 0.63fF +C2157 la_data_out[82] vdd 0.63fF +C2158 la_data_in[82] vdd 0.63fF +C2159 la_oenb[81] vdd 0.63fF +C2160 la_data_out[81] vdd 0.63fF +C2161 la_data_in[81] vdd 0.63fF +C2162 la_oenb[80] vdd 0.63fF +C2163 la_data_out[80] vdd 0.63fF +C2164 la_data_in[80] vdd 0.63fF +C2165 la_oenb[79] vdd 0.63fF +C2166 la_data_out[79] vdd 0.63fF +C2167 la_data_in[79] vdd 0.63fF +C2168 la_oenb[78] vdd 0.63fF +C2169 la_data_out[78] vdd 0.63fF +C2170 la_data_in[78] vdd 0.63fF +C2171 la_oenb[77] vdd 0.63fF +C2172 la_data_out[77] vdd 0.63fF +C2173 la_data_in[77] vdd 0.63fF +C2174 la_oenb[76] vdd 0.63fF +C2175 la_data_out[76] vdd 0.63fF +C2176 la_data_in[76] vdd 0.63fF +C2177 la_oenb[75] vdd 0.63fF +C2178 la_data_out[75] vdd 0.63fF +C2179 la_data_in[75] vdd 0.63fF +C2180 la_oenb[74] vdd 0.63fF +C2181 la_data_out[74] vdd 0.63fF +C2182 la_data_in[74] vdd 0.63fF +C2183 la_oenb[73] vdd 0.63fF +C2184 la_data_out[73] vdd 0.63fF +C2185 la_data_in[73] vdd 0.63fF +C2186 la_oenb[72] vdd 0.63fF +C2187 la_data_out[72] vdd 0.63fF +C2188 la_data_in[72] vdd 0.63fF +C2189 la_oenb[71] vdd 0.63fF +C2190 la_data_out[71] vdd 0.63fF +C2191 la_data_in[71] vdd 0.63fF +C2192 la_oenb[70] vdd 0.63fF +C2193 la_data_out[70] vdd 0.63fF +C2194 la_data_in[70] vdd 0.63fF +C2195 la_oenb[69] vdd 0.63fF +C2196 la_data_out[69] vdd 0.63fF +C2197 la_data_in[69] vdd 0.63fF +C2198 la_oenb[68] vdd 0.63fF +C2199 la_data_out[68] vdd 0.63fF +C2200 la_data_in[68] vdd 0.63fF +C2201 la_oenb[67] vdd 0.63fF +C2202 la_data_out[67] vdd 0.63fF +C2203 la_data_in[67] vdd 0.63fF +C2204 la_oenb[66] vdd 0.63fF +C2205 la_data_out[66] vdd 0.63fF +C2206 la_data_in[66] vdd 0.63fF +C2207 la_oenb[65] vdd 0.63fF +C2208 la_data_out[65] vdd 0.63fF +C2209 la_data_in[65] vdd 0.63fF +C2210 la_oenb[64] vdd 0.63fF +C2211 la_data_out[64] vdd 0.63fF +C2212 la_data_in[64] vdd 0.63fF +C2213 la_oenb[63] vdd 0.63fF +C2214 la_data_out[63] vdd 0.63fF +C2215 la_data_in[63] vdd 0.63fF +C2216 la_oenb[62] vdd 0.63fF +C2217 la_data_out[62] vdd 0.63fF +C2218 la_data_in[62] vdd 0.63fF +C2219 la_oenb[61] vdd 0.63fF +C2220 la_data_out[61] vdd 0.63fF +C2221 la_data_in[61] vdd 0.63fF +C2222 la_oenb[60] vdd 0.63fF +C2223 la_data_out[60] vdd 0.63fF +C2224 la_data_in[60] vdd 0.63fF +C2225 la_oenb[59] vdd 0.63fF +C2226 la_data_out[59] vdd 0.63fF +C2227 la_data_in[59] vdd 0.63fF +C2228 la_oenb[58] vdd 0.63fF +C2229 la_data_out[58] vdd 0.63fF +C2230 la_data_in[58] vdd 0.63fF +C2231 la_oenb[57] vdd 0.63fF +C2232 la_data_out[57] vdd 0.63fF +C2233 la_data_in[57] vdd 0.63fF +C2234 la_oenb[56] vdd 0.63fF +C2235 la_data_out[56] vdd 0.63fF +C2236 la_data_in[56] vdd 0.63fF +C2237 la_oenb[55] vdd 0.63fF +C2238 la_data_out[55] vdd 0.63fF +C2239 la_data_in[55] vdd 0.63fF +C2240 la_oenb[54] vdd 0.63fF +C2241 la_data_out[54] vdd 0.63fF +C2242 la_data_in[54] vdd 0.63fF +C2243 la_oenb[53] vdd 0.63fF +C2244 la_data_out[53] vdd 0.63fF +C2245 la_data_in[53] vdd 0.63fF +C2246 la_oenb[52] vdd 0.63fF +C2247 la_data_out[52] vdd 0.63fF +C2248 la_data_in[52] vdd 0.63fF +C2249 la_oenb[51] vdd 0.63fF +C2250 la_data_out[51] vdd 0.63fF +C2251 la_data_in[51] vdd 0.63fF +C2252 la_oenb[50] vdd 0.63fF +C2253 la_data_out[50] vdd 0.63fF +C2254 la_data_in[50] vdd 0.63fF +C2255 la_oenb[49] vdd 0.63fF +C2256 la_data_out[49] vdd 0.63fF +C2257 la_data_in[49] vdd 0.63fF +C2258 la_oenb[48] vdd 0.63fF +C2259 la_data_out[48] vdd 0.63fF +C2260 la_data_in[48] vdd 0.63fF +C2261 la_oenb[47] vdd 0.63fF +C2262 la_data_out[47] vdd 0.63fF +C2263 la_data_in[47] vdd 0.63fF +C2264 la_oenb[46] vdd 0.63fF +C2265 la_data_out[46] vdd 0.63fF +C2266 la_data_in[46] vdd 0.63fF +C2267 la_oenb[45] vdd 0.63fF +C2268 la_data_out[45] vdd 0.63fF +C2269 la_data_in[45] vdd 0.63fF +C2270 la_oenb[44] vdd 0.63fF +C2271 la_data_out[44] vdd 0.63fF +C2272 la_data_in[44] vdd 0.63fF +C2273 la_oenb[43] vdd 0.63fF +C2274 la_data_out[43] vdd 0.63fF +C2275 la_data_in[43] vdd 0.63fF +C2276 la_oenb[42] vdd 0.63fF +C2277 la_data_out[42] vdd 0.63fF +C2278 la_data_in[42] vdd 0.63fF +C2279 la_oenb[41] vdd 0.63fF +C2280 la_data_out[41] vdd 0.63fF +C2281 la_data_in[41] vdd 0.63fF +C2282 la_oenb[40] vdd 0.63fF +C2283 la_data_out[40] vdd 0.63fF +C2284 la_data_in[40] vdd 0.63fF +C2285 la_oenb[39] vdd 0.63fF +C2286 la_data_out[39] vdd 0.63fF +C2287 la_data_in[39] vdd 0.63fF +C2288 la_oenb[38] vdd 0.63fF +C2289 la_data_out[38] vdd 0.63fF +C2290 la_data_in[38] vdd 0.63fF +C2291 la_oenb[37] vdd 0.63fF +C2292 la_data_out[37] vdd 0.63fF +C2293 la_data_in[37] vdd 0.63fF +C2294 la_oenb[36] vdd 0.63fF +C2295 la_data_out[36] vdd 0.63fF +C2296 la_data_in[36] vdd 0.63fF +C2297 la_oenb[35] vdd 0.63fF +C2298 la_data_out[35] vdd 0.63fF +C2299 la_data_in[35] vdd 0.63fF +C2300 la_oenb[34] vdd 0.63fF +C2301 la_data_out[34] vdd 0.63fF +C2302 la_data_in[34] vdd 0.63fF +C2303 la_oenb[33] vdd 0.63fF +C2304 la_data_out[33] vdd 0.63fF +C2305 la_data_in[33] vdd 0.63fF +C2306 la_oenb[32] vdd 0.63fF +C2307 la_data_out[32] vdd 0.63fF +C2308 la_data_in[32] vdd 0.63fF +C2309 la_oenb[31] vdd 0.63fF +C2310 la_data_out[31] vdd 0.63fF +C2311 la_data_in[31] vdd 0.63fF +C2312 la_oenb[30] vdd 0.63fF +C2313 la_data_out[30] vdd 0.63fF +C2314 la_data_in[30] vdd 0.63fF +C2315 la_oenb[29] vdd 0.63fF +C2316 la_data_out[29] vdd 0.63fF +C2317 la_data_in[29] vdd 0.63fF +C2318 la_oenb[28] vdd 0.63fF +C2319 la_data_out[28] vdd 0.63fF +C2320 la_data_in[28] vdd 0.63fF +C2321 la_oenb[27] vdd 0.63fF +C2322 la_data_out[27] vdd 0.63fF +C2323 la_data_in[27] vdd 0.63fF +C2324 la_oenb[26] vdd 0.63fF +C2325 la_data_out[26] vdd 0.63fF +C2326 la_data_in[26] vdd 0.63fF +C2327 la_oenb[25] vdd 0.63fF +C2328 la_data_out[25] vdd 0.63fF +C2329 la_data_in[25] vdd 0.63fF +C2330 la_oenb[24] vdd 0.63fF +C2331 la_data_out[24] vdd 0.63fF +C2332 la_data_in[24] vdd 0.63fF +C2333 la_oenb[23] vdd 0.63fF +C2334 la_data_out[23] vdd 0.63fF +C2335 la_data_in[23] vdd 0.63fF +C2336 la_oenb[22] vdd 0.63fF +C2337 la_data_out[22] vdd 0.63fF +C2338 la_data_in[22] vdd 0.63fF +C2339 la_oenb[21] vdd 0.63fF +C2340 la_data_out[21] vdd 0.63fF +C2341 la_data_in[21] vdd 0.63fF +C2342 la_oenb[20] vdd 0.63fF +C2343 la_data_out[20] vdd 0.63fF +C2344 la_data_in[20] vdd 0.63fF +C2345 la_oenb[19] vdd 0.63fF +C2346 la_data_out[19] vdd 0.63fF +C2347 la_data_in[19] vdd 0.63fF +C2348 la_oenb[18] vdd 0.63fF +C2349 la_data_out[18] vdd 0.63fF +C2350 la_data_in[18] vdd 0.63fF +C2351 la_oenb[17] vdd 0.63fF +C2352 la_data_out[17] vdd 0.63fF +C2353 la_data_in[17] vdd 0.63fF +C2354 la_oenb[16] vdd 0.63fF +C2355 la_data_out[16] vdd 0.63fF +C2356 la_data_in[16] vdd 0.63fF +C2357 la_oenb[15] vdd 0.63fF +C2358 la_data_out[15] vdd 0.63fF +C2359 la_data_in[15] vdd 0.63fF +C2360 la_oenb[14] vdd 0.63fF +C2361 la_data_out[14] vdd 0.63fF +C2362 la_data_in[14] vdd 0.63fF +C2363 la_oenb[13] vdd 0.63fF +C2364 la_data_out[13] vdd 0.63fF +C2365 la_data_in[13] vdd 0.63fF +C2366 la_oenb[12] vdd 0.63fF +C2367 la_data_out[12] vdd 0.63fF +C2368 la_data_in[12] vdd 0.63fF +C2369 la_oenb[11] vdd 0.63fF +C2370 la_data_out[11] vdd 0.63fF +C2371 la_data_in[11] vdd 0.63fF +C2372 la_oenb[10] vdd 0.63fF +C2373 la_data_out[10] vdd 0.63fF +C2374 la_data_in[10] vdd 0.63fF +C2375 la_oenb[9] vdd 0.63fF +C2376 la_data_out[9] vdd 0.63fF +C2377 la_data_in[9] vdd 0.63fF +C2378 la_oenb[8] vdd 0.63fF +C2379 la_data_out[8] vdd 0.63fF +C2380 la_data_in[8] vdd 0.63fF +C2381 la_oenb[7] vdd 0.63fF +C2382 la_data_out[7] vdd 0.63fF +C2383 la_data_in[7] vdd 0.63fF +C2384 la_oenb[6] vdd 0.63fF +C2385 la_data_out[6] vdd 0.63fF +C2386 la_data_in[6] vdd 0.63fF +C2387 la_oenb[5] vdd 0.63fF +C2388 la_data_out[5] vdd 0.63fF +C2389 la_data_in[5] vdd 0.63fF +C2390 la_oenb[4] vdd 0.63fF +C2391 la_data_out[4] vdd 0.63fF +C2392 la_data_in[4] vdd 0.63fF +C2393 la_oenb[3] vdd 0.63fF +C2394 la_data_out[3] vdd 0.63fF +C2395 la_data_in[3] vdd 0.63fF +C2396 la_oenb[2] vdd 0.63fF +C2397 la_data_out[2] vdd 0.63fF +C2398 la_data_in[2] vdd 0.63fF +C2399 la_oenb[1] vdd 0.63fF +C2400 la_data_out[1] vdd 0.63fF +C2401 la_data_in[1] vdd 0.63fF +C2402 la_oenb[0] vdd 0.63fF +C2403 la_data_out[0] vdd 0.63fF +C2404 la_data_in[0] vdd 0.63fF +C2405 wbs_dat_o[31] vdd 0.63fF +C2406 wbs_dat_i[31] vdd 0.63fF +C2407 wbs_adr_i[31] vdd 0.63fF +C2408 wbs_dat_o[30] vdd 0.63fF +C2409 wbs_dat_i[30] vdd 0.63fF +C2410 wbs_adr_i[30] vdd 0.63fF +C2411 wbs_dat_o[29] vdd 0.63fF +C2412 wbs_dat_i[29] vdd 0.63fF +C2413 wbs_adr_i[29] vdd 0.63fF +C2414 wbs_dat_o[28] vdd 0.63fF +C2415 wbs_dat_i[28] vdd 0.63fF +C2416 wbs_adr_i[28] vdd 0.63fF +C2417 wbs_dat_o[27] vdd 0.63fF +C2418 wbs_dat_i[27] vdd 0.63fF +C2419 wbs_adr_i[27] vdd 0.63fF +C2420 wbs_dat_o[26] vdd 0.63fF +C2421 wbs_dat_i[26] vdd 0.63fF +C2422 wbs_adr_i[26] vdd 0.63fF +C2423 wbs_dat_o[25] vdd 0.63fF +C2424 wbs_dat_i[25] vdd 0.63fF +C2425 wbs_adr_i[25] vdd 0.63fF +C2426 wbs_dat_o[24] vdd 0.63fF +C2427 wbs_dat_i[24] vdd 0.63fF +C2428 wbs_adr_i[24] vdd 0.63fF +C2429 wbs_dat_o[23] vdd 0.63fF +C2430 wbs_dat_i[23] vdd 0.63fF +C2431 wbs_adr_i[23] vdd 0.63fF +C2432 wbs_dat_o[22] vdd 0.63fF +C2433 wbs_dat_i[22] vdd 0.63fF +C2434 wbs_adr_i[22] vdd 0.63fF +C2435 wbs_dat_o[21] vdd 0.63fF +C2436 wbs_dat_i[21] vdd 0.63fF +C2437 wbs_adr_i[21] vdd 0.63fF +C2438 wbs_dat_o[20] vdd 0.63fF +C2439 wbs_dat_i[20] vdd 0.63fF +C2440 wbs_adr_i[20] vdd 0.63fF +C2441 wbs_dat_o[19] vdd 0.63fF +C2442 wbs_dat_i[19] vdd 0.63fF +C2443 wbs_adr_i[19] vdd 0.63fF +C2444 wbs_dat_o[18] vdd 0.63fF +C2445 wbs_dat_i[18] vdd 0.63fF +C2446 wbs_adr_i[18] vdd 0.63fF +C2447 wbs_dat_o[17] vdd 0.63fF +C2448 wbs_dat_i[17] vdd 0.63fF +C2449 wbs_adr_i[17] vdd 0.63fF +C2450 wbs_dat_o[16] vdd 0.63fF +C2451 wbs_dat_i[16] vdd 0.63fF +C2452 wbs_adr_i[16] vdd 0.63fF +C2453 wbs_dat_o[15] vdd 0.63fF +C2454 wbs_dat_i[15] vdd 0.63fF +C2455 wbs_adr_i[15] vdd 0.63fF +C2456 wbs_dat_o[14] vdd 0.63fF +C2457 wbs_dat_i[14] vdd 0.63fF +C2458 wbs_adr_i[14] vdd 0.63fF +C2459 wbs_dat_o[13] vdd 0.63fF +C2460 wbs_dat_i[13] vdd 0.63fF +C2461 wbs_adr_i[13] vdd 0.63fF +C2462 wbs_dat_o[12] vdd 0.63fF +C2463 wbs_dat_i[12] vdd 0.63fF +C2464 wbs_adr_i[12] vdd 0.63fF +C2465 wbs_dat_o[11] vdd 0.63fF +C2466 wbs_dat_i[11] vdd 0.63fF +C2467 wbs_adr_i[11] vdd 0.63fF +C2468 wbs_dat_o[10] vdd 0.63fF +C2469 wbs_dat_i[10] vdd 0.63fF +C2470 wbs_adr_i[10] vdd 0.63fF +C2471 wbs_dat_o[9] vdd 0.63fF +C2472 wbs_dat_i[9] vdd 0.63fF +C2473 wbs_adr_i[9] vdd 0.63fF +C2474 wbs_dat_o[8] vdd 0.63fF +C2475 wbs_dat_i[8] vdd 0.63fF +C2476 wbs_adr_i[8] vdd 0.63fF +C2477 wbs_dat_o[7] vdd 0.63fF +C2478 wbs_dat_i[7] vdd 0.63fF +C2479 wbs_adr_i[7] vdd 0.63fF +C2480 wbs_dat_o[6] vdd 0.63fF +C2481 wbs_dat_i[6] vdd 0.63fF +C2482 wbs_adr_i[6] vdd 0.63fF +C2483 wbs_dat_o[5] vdd 0.63fF +C2484 wbs_dat_i[5] vdd 0.63fF +C2485 wbs_adr_i[5] vdd 0.63fF +C2486 wbs_dat_o[4] vdd 0.63fF +C2487 wbs_dat_i[4] vdd 0.63fF +C2488 wbs_adr_i[4] vdd 0.63fF +C2489 wbs_sel_i[3] vdd 0.63fF +C2490 wbs_dat_o[3] vdd 0.63fF +C2491 wbs_dat_i[3] vdd 0.63fF +C2492 wbs_adr_i[3] vdd 0.63fF +C2493 wbs_sel_i[2] vdd 0.63fF +C2494 wbs_dat_o[2] vdd 0.63fF +C2495 wbs_dat_i[2] vdd 0.63fF +C2496 wbs_adr_i[2] vdd 0.63fF +C2497 wbs_sel_i[1] vdd 0.63fF +C2498 wbs_dat_o[1] vdd 0.63fF +C2499 wbs_dat_i[1] vdd 0.63fF +C2500 wbs_adr_i[1] vdd 0.63fF +C2501 wbs_sel_i[0] vdd 0.63fF +C2502 wbs_dat_o[0] vdd 0.63fF +C2503 wbs_dat_i[0] vdd 0.63fF +C2504 wbs_adr_i[0] vdd 0.63fF +C2505 wbs_we_i vdd 0.63fF +C2506 wbs_stb_i vdd 0.63fF +C2507 wbs_cyc_i vdd 0.63fF +C2508 wbs_ack_o vdd 0.63fF +C2509 wb_rst_i vdd 0.63fF +C2510 wb_clk_i vdd 0.63fF +C2511 m2_494098_659718# vdd 0.80fF **FLOATING +C2512 pll_full_0/divider_0/and_0/Z1 vdd 0.33fF +C2513 pll_full_0/divider_0/and_0/B vdd 1.79fF +C2514 pll_full_0/divider_0/and_0/A vdd 1.66fF +C2515 pll_full_0/divider_0/and_0/out1 vdd 2.71fF +C2516 pll_full_0/divider_0/tspc_2/Z4 vdd 0.42fF +C2517 pll_full_0/divbuf_0/IN vdd 6.23fF +C2518 pll_full_0/divider_0/tspc_2/Z3 vdd 2.00fF +C2519 pll_full_0/divider_0/tspc_2/Z2 vdd 1.29fF +C2520 pll_full_0/divider_0/tspc_2/Z1 vdd 0.99fF +C2521 pll_full_0/divider_0/nor_0/B vdd 5.25fF +C2522 pll_full_0/divider_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2523 pll_full_0/divider_0/tspc_1/Z4 vdd 0.42fF +C2524 pll_full_0/divider_0/tspc_1/Q vdd 2.79fF +C2525 pll_full_0/divider_0/tspc_1/Z3 vdd 2.00fF +C2526 pll_full_0/divider_0/tspc_1/Z2 vdd 1.29fF +C2527 pll_full_0/divider_0/tspc_1/Z1 vdd 0.99fF +C2528 pll_full_0/divider_0/nor_1/B vdd 5.95fF +C2529 pll_full_0/divider_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2530 pll_full_0/divider_0/tspc_0/Z4 vdd 0.42fF +C2531 pll_full_0/divider_0/tspc_0/Q vdd 2.81fF +C2532 pll_full_0/divider_0/tspc_0/Z3 vdd 2.00fF +C2533 pll_full_0/divider_0/tspc_0/Z2 vdd 1.30fF +C2534 pll_full_0/divider_0/tspc_0/Z1 vdd 0.99fF +C2535 pll_full_0/divider_0/nor_1/A vdd 6.02fF +C2536 pll_full_0/divider_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2537 pll_full_0/divider_0/clk vdd 31.77fF +C2538 pll_full_0/divider_0/prescaler_0/Out vdd 4.13fF +C2539 pll_full_0/divider_0/prescaler_0/nand_1/z1 vdd 0.20fF +C2540 gnd vdd 91.98fF +C2541 pll_full_0/divider_0/prescaler_0/tspc_2/D vdd 2.59fF +C2542 pll_full_0/divider_0/prescaler_0/tspc_0/Q vdd 3.30fF +C2543 pll_full_0/divider_0/prescaler_0/tspc_1/Q vdd 2.78fF +C2544 pll_full_0/divider_0/prescaler_0/nand_0/z1 vdd 0.20fF +C2545 pll_full_0/divider_0/prescaler_0/tspc_0/D vdd 3.07fF +C2546 pll_full_0/divider_0/and_0/OUT vdd 5.35fF +C2547 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 vdd 0.42fF +C2548 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 vdd 2.00fF +C2549 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 vdd 1.30fF +C2550 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF +C2551 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2552 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# vdd 1.89fF **FLOATING +C2553 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 vdd 0.42fF +C2554 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 vdd 2.00fF +C2555 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 vdd 1.31fF +C2556 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF +C2557 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2558 pll_full_0/divider_0/prescaler_0/m1_2700_2190# vdd 3.99fF **FLOATING +C2559 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 vdd 0.42fF +C2560 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 vdd 2.00fF +C2561 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 vdd 1.30fF +C2562 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF +C2563 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2564 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# vdd 1.89fF **FLOATING +C2565 pll_full_0/divider_0/nor_1/Z1 vdd 1.33fF +C2566 pll_full_0/divider_0/nor_0/Z1 vdd 1.33fF +C2567 pll_full_0/divbuf_1/OUT vdd 363.82fF +C2568 pll_full_0/divbuf_1/OUT5 vdd 350.37fF +C2569 pll_full_0/divbuf_1/OUT4 vdd 133.72fF +C2570 pll_full_0/divbuf_1/OUT3 vdd 34.03fF +C2571 pll_full_0/divbuf_1/OUT2 vdd 8.71fF +C2572 pll_full_0/divbuf_1/a_492_n240# vdd 2.46fF **FLOATING +C2573 pll_full_0/divbuf_0/OUT5 vdd 350.37fF +C2574 pll_full_0/divbuf_0/OUT4 vdd 133.72fF +C2575 pll_full_0/divbuf_0/OUT3 vdd 34.03fF +C2576 pll_full_0/divbuf_0/OUT2 vdd 8.71fF +C2577 pll_full_0/divbuf_0/a_492_n240# vdd 2.46fF **FLOATING +C2578 pll_full_0/ro_complete_0/cbank_2/v vdd 17.88fF +C2579 pll_full_0/ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF +C2580 pll_full_0/ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF +C2581 pll_full_0/ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF +C2582 pll_full_0/ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF +C2583 pll_full_0/ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF +C2584 pll_full_0/ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF +C2585 pll_full_0/ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF +C2586 pll_full_0/ro_complete_0/a0 vdd 7.88fF +C2587 pll_full_0/ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF +C2588 pll_full_0/ro_complete_0/a1 vdd 5.39fF +C2589 pll_full_0/ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF +C2590 pll_full_0/ro_complete_0/a3 vdd 6.85fF +C2591 pll_full_0/ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF +C2592 pll_full_0/ro_complete_0/a2 vdd 5.48fF +C2593 pll_full_0/ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF +C2594 pll_full_0/ro_complete_0/a4 vdd 5.36fF +C2595 pll_full_0/ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF +C2596 pll_full_0/ro_complete_0/a5 vdd 5.19fF +C2597 pll_full_0/ro_complete_0/cbank_0/v vdd 15.02fF +C2598 pll_full_0/ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF +C2599 pll_full_0/ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF +C2600 pll_full_0/ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF +C2601 pll_full_0/ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF +C2602 pll_full_0/ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF +C2603 pll_full_0/ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF +C2604 pll_full_0/ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF +C2605 pll_full_0/filter_0/a_4216_n5230# vdd 419.25fF **FLOATING +C2606 pll_full_0/filter_0/a_4216_n2998# vdd 1.39fF **FLOATING +C2607 pll_full_0/cp_0/down vdd 1.54fF +C2608 pll_full_0/cp_0/upbar vdd 1.79fF +C2609 pll_full_0/cp_0/a_7110_n2840# vdd 0.17fF **FLOATING +C2610 pll_full_0/cp_0/a_3060_n2840# vdd 1.71fF **FLOATING +C2611 pll_full_0/cp_0/a_7110_0# vdd 0.17fF **FLOATING +C2612 pll_full_0/cp_0/a_6370_0# vdd 0.40fF **FLOATING +C2613 pll_full_0/cp_0/a_3060_0# vdd 2.49fF **FLOATING +C2614 pll_full_0/cp_0/a_1710_0# vdd 7.47fF **FLOATING +C2615 pll_full_0/pd_0/and_pd_0/Z1 vdd 0.39fF +C2616 pll_full_0/pd_0/and_pd_0/Out1 vdd 2.22fF +C2617 pll_full_0/pd_0/tspc_r_1/z5 vdd 1.10fF +C2618 pll_full_0/pd_0/tspc_r_1/Z4 vdd 1.07fF +C2619 pll_full_0/pd_0/tspc_r_1/Qbar vdd 0.88fF +C2620 pll_full_0/pd_0/tspc_r_1/Z2 vdd 1.22fF +C2621 pll_full_0/pd_0/tspc_r_1/Z1 vdd 0.67fF +C2622 pll_full_0/pd_0/UP vdd 6.61fF +C2623 pll_full_0/pd_0/tspc_r_1/Qbar1 vdd 1.34fF +C2624 pll_full_0/pd_0/tspc_r_1/Z3 vdd 2.12fF +C2625 pll_full_0/pd_0/REF vdd 6.44fF +C2626 pll_full_0/pd_0/tspc_r_0/z5 vdd 1.10fF +C2627 pll_full_0/pd_0/tspc_r_0/Z4 vdd 1.07fF +C2628 pll_full_0/pd_0/R vdd 3.05fF +C2629 pll_full_0/pd_0/tspc_r_0/Qbar vdd 0.79fF +C2630 pll_full_0/pd_0/tspc_r_0/Z2 vdd 1.22fF +C2631 pll_full_0/pd_0/tspc_r_0/Z1 vdd 0.67fF +C2632 pll_full_0/pd_0/DOWN vdd 7.24fF +C2633 pll_full_0/pd_0/tspc_r_0/Qbar1 vdd 1.34fF +C2634 pll_full_0/pd_0/tspc_r_0/Z3 vdd 2.12fF +C2635 pll_full_0/pd_0/DIV vdd 371.86fF +C2636 divbuf_19/OUT vdd 363.82fF +C2637 divbuf_19/OUT5 vdd 350.37fF +C2638 divbuf_19/OUT4 vdd 133.72fF +C2639 divbuf_19/OUT3 vdd 34.03fF +C2640 divbuf_19/OUT2 vdd 8.71fF +C2641 divbuf_19/IN vdd 0.89fF +C2642 divbuf_19/a_492_n240# vdd 2.46fF **FLOATING +C2643 divbuf_18/OUT vdd 363.82fF +C2644 divbuf_18/OUT5 vdd 350.37fF +C2645 divbuf_18/OUT4 vdd 133.72fF +C2646 divbuf_18/OUT3 vdd 34.03fF +C2647 divbuf_18/OUT2 vdd 8.71fF +C2648 divbuf_18/IN vdd 0.89fF +C2649 divbuf_18/a_492_n240# vdd 2.46fF **FLOATING +C2650 divbuf_17/OUT vdd 363.82fF +C2651 divbuf_17/OUT5 vdd 350.37fF +C2652 divbuf_17/OUT4 vdd 133.72fF +C2653 divbuf_17/OUT3 vdd 34.03fF +C2654 divbuf_17/OUT2 vdd 8.71fF +C2655 divbuf_17/IN vdd 0.89fF +C2656 divbuf_17/a_492_n240# vdd 2.46fF **FLOATING +C2657 divider_2/and_0/Z1 vdd 0.33fF +C2658 divider_2/and_0/B vdd 1.79fF +C2659 divider_2/and_0/A vdd 1.66fF +C2660 divider_2/and_0/out1 vdd 2.71fF +C2661 divider_2/tspc_2/Z4 vdd 0.42fF +C2662 divider_2/Out vdd 1.31fF +C2663 divider_2/tspc_2/Z3 vdd 2.00fF +C2664 divider_2/tspc_2/Z2 vdd 1.29fF +C2665 divider_2/tspc_2/Z1 vdd 0.99fF +C2666 divider_2/nor_0/B vdd 5.25fF +C2667 divider_2/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2668 divider_2/tspc_1/Z4 vdd 0.42fF +C2669 divider_2/tspc_1/Q vdd 2.79fF +C2670 divider_2/tspc_1/Z3 vdd 2.00fF +C2671 divider_2/tspc_1/Z2 vdd 1.29fF +C2672 divider_2/tspc_1/Z1 vdd 0.99fF +C2673 divider_2/nor_1/B vdd 5.95fF +C2674 divider_2/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2675 divider_2/tspc_0/Z4 vdd 0.42fF +C2676 divider_2/tspc_0/Q vdd 2.81fF +C2677 divider_2/tspc_0/Z3 vdd 2.00fF +C2678 divider_2/tspc_0/Z2 vdd 1.30fF +C2679 divider_2/tspc_0/Z1 vdd 0.99fF +C2680 divider_2/nor_1/A vdd 6.02fF +C2681 divider_2/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2682 divider_2/clk vdd 5.56fF +C2683 divider_2/prescaler_0/Out vdd 4.13fF +C2684 divider_2/prescaler_0/nand_1/z1 vdd 0.20fF +C2685 divider_2/prescaler_0/tspc_2/D vdd 2.59fF +C2686 divider_2/prescaler_0/tspc_0/Q vdd 3.30fF +C2687 divider_2/prescaler_0/tspc_1/Q vdd 2.78fF +C2688 divider_2/prescaler_0/nand_0/z1 vdd 0.20fF +C2689 divider_2/prescaler_0/tspc_0/D vdd 3.07fF +C2690 divider_2/and_0/OUT vdd 5.35fF +C2691 divider_2/prescaler_0/tspc_2/Z4 vdd 0.42fF +C2692 divider_2/prescaler_0/tspc_2/Z3 vdd 2.00fF +C2693 divider_2/prescaler_0/tspc_2/Z2 vdd 1.30fF +C2694 divider_2/prescaler_0/tspc_2/Z1 vdd 0.99fF +C2695 divider_2/prescaler_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2696 divider_2/prescaler_0/tspc_2/a_740_n680# vdd 1.89fF **FLOATING +C2697 divider_2/prescaler_0/tspc_1/Z4 vdd 0.42fF +C2698 divider_2/prescaler_0/tspc_1/Z3 vdd 2.00fF +C2699 divider_2/prescaler_0/tspc_1/Z2 vdd 1.31fF +C2700 divider_2/prescaler_0/tspc_1/Z1 vdd 0.99fF +C2701 divider_2/prescaler_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2702 divider_2/prescaler_0/m1_2700_2190# vdd 3.99fF **FLOATING +C2703 divider_2/prescaler_0/tspc_0/Z4 vdd 0.42fF +C2704 divider_2/prescaler_0/tspc_0/Z3 vdd 2.00fF +C2705 divider_2/prescaler_0/tspc_0/Z2 vdd 1.30fF +C2706 divider_2/prescaler_0/tspc_0/Z1 vdd 0.99fF +C2707 divider_2/prescaler_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2708 divider_2/prescaler_0/tspc_0/a_740_n680# vdd 1.89fF **FLOATING +C2709 divider_2/nor_1/Z1 vdd 1.33fF +C2710 divider_2/nor_0/Z1 vdd 1.33fF +C2711 divider_2/mc2 vdd 3.93fF +C2712 divbuf_16/OUT vdd 363.82fF +C2713 divbuf_16/OUT5 vdd 350.37fF +C2714 divbuf_16/OUT4 vdd 133.72fF +C2715 divbuf_16/OUT3 vdd 34.03fF +C2716 divbuf_16/OUT2 vdd 8.71fF +C2717 divbuf_16/IN vdd 0.89fF +C2718 divbuf_16/a_492_n240# vdd 2.46fF **FLOATING +C2719 divider_1/and_0/Z1 vdd 0.33fF +C2720 divider_1/and_0/B vdd 1.79fF +C2721 divider_1/and_0/A vdd 1.66fF +C2722 divider_1/and_0/out1 vdd 2.71fF +C2723 divider_1/tspc_2/Z4 vdd 0.42fF +C2724 divider_1/Out vdd 1.31fF +C2725 divider_1/tspc_2/Z3 vdd 2.00fF +C2726 divider_1/tspc_2/Z2 vdd 1.29fF +C2727 divider_1/tspc_2/Z1 vdd 0.99fF +C2728 divider_1/nor_0/B vdd 5.25fF +C2729 divider_1/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2730 divider_1/tspc_1/Z4 vdd 0.42fF +C2731 divider_1/tspc_1/Q vdd 2.79fF +C2732 divider_1/tspc_1/Z3 vdd 2.00fF +C2733 divider_1/tspc_1/Z2 vdd 1.29fF +C2734 divider_1/tspc_1/Z1 vdd 0.99fF +C2735 divider_1/nor_1/B vdd 5.95fF +C2736 divider_1/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2737 divider_1/tspc_0/Z4 vdd 0.42fF +C2738 divider_1/tspc_0/Q vdd 2.81fF +C2739 divider_1/tspc_0/Z3 vdd 2.00fF +C2740 divider_1/tspc_0/Z2 vdd 1.30fF +C2741 divider_1/tspc_0/Z1 vdd 0.99fF +C2742 divider_1/nor_1/A vdd 6.02fF +C2743 divider_1/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2744 divider_1/clk vdd 5.56fF +C2745 divider_1/prescaler_0/Out vdd 4.13fF +C2746 divider_1/prescaler_0/nand_1/z1 vdd 0.20fF +C2747 divider_1/prescaler_0/tspc_2/D vdd 2.59fF +C2748 divider_1/prescaler_0/tspc_0/Q vdd 3.30fF +C2749 divider_1/prescaler_0/tspc_1/Q vdd 2.78fF +C2750 divider_1/prescaler_0/nand_0/z1 vdd 0.20fF +C2751 divider_1/prescaler_0/tspc_0/D vdd 3.07fF +C2752 divider_1/and_0/OUT vdd 5.35fF +C2753 divider_1/prescaler_0/tspc_2/Z4 vdd 0.42fF +C2754 divider_1/prescaler_0/tspc_2/Z3 vdd 2.00fF +C2755 divider_1/prescaler_0/tspc_2/Z2 vdd 1.30fF +C2756 divider_1/prescaler_0/tspc_2/Z1 vdd 0.99fF +C2757 divider_1/prescaler_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2758 divider_1/prescaler_0/tspc_2/a_740_n680# vdd 1.89fF **FLOATING +C2759 divider_1/prescaler_0/tspc_1/Z4 vdd 0.42fF +C2760 divider_1/prescaler_0/tspc_1/Z3 vdd 2.00fF +C2761 divider_1/prescaler_0/tspc_1/Z2 vdd 1.31fF +C2762 divider_1/prescaler_0/tspc_1/Z1 vdd 0.99fF +C2763 divider_1/prescaler_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2764 divider_1/prescaler_0/m1_2700_2190# vdd 3.99fF **FLOATING +C2765 divider_1/prescaler_0/tspc_0/Z4 vdd 0.42fF +C2766 divider_1/prescaler_0/tspc_0/Z3 vdd 2.00fF +C2767 divider_1/prescaler_0/tspc_0/Z2 vdd 1.30fF +C2768 divider_1/prescaler_0/tspc_0/Z1 vdd 0.99fF +C2769 divider_1/prescaler_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2770 divider_1/prescaler_0/tspc_0/a_740_n680# vdd 1.89fF **FLOATING +C2771 divider_1/nor_1/Z1 vdd 1.33fF +C2772 divider_1/nor_0/Z1 vdd 1.33fF +C2773 divider_1/mc2 vdd 3.93fF +C2774 divbuf_15/OUT vdd 363.82fF +C2775 divbuf_15/OUT5 vdd 350.37fF +C2776 divbuf_15/OUT4 vdd 133.72fF +C2777 divbuf_15/OUT3 vdd 34.03fF +C2778 divbuf_15/OUT2 vdd 8.71fF +C2779 divbuf_15/IN vdd 0.89fF +C2780 divbuf_15/a_492_n240# vdd 2.46fF **FLOATING +C2781 divbuf_25/OUT vdd 363.82fF +C2782 divbuf_25/OUT5 vdd 350.37fF +C2783 divbuf_25/OUT4 vdd 133.72fF +C2784 divbuf_25/OUT3 vdd 34.03fF +C2785 divbuf_25/OUT2 vdd 8.71fF +C2786 divbuf_25/IN vdd 0.89fF +C2787 divbuf_25/a_492_n240# vdd 2.46fF **FLOATING +C2788 divbuf_14/OUT vdd 363.82fF +C2789 divbuf_14/OUT5 vdd 350.37fF +C2790 divbuf_14/OUT4 vdd 133.72fF +C2791 divbuf_14/OUT3 vdd 34.03fF +C2792 divbuf_14/OUT2 vdd 8.71fF +C2793 divbuf_14/IN vdd 0.89fF +C2794 divbuf_14/a_492_n240# vdd 2.46fF **FLOATING +C2795 divider_0/and_0/Z1 vdd 0.33fF +C2796 divider_0/and_0/B vdd 1.79fF +C2797 divider_0/and_0/A vdd 1.66fF +C2798 divider_0/and_0/out1 vdd 2.71fF +C2799 divider_0/tspc_2/Z4 vdd 0.42fF +C2800 divider_0/Out vdd 1.31fF +C2801 divider_0/tspc_2/Z3 vdd 2.00fF +C2802 divider_0/tspc_2/Z2 vdd 1.29fF +C2803 divider_0/tspc_2/Z1 vdd 0.99fF +C2804 divider_0/nor_0/B vdd 5.25fF +C2805 divider_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2806 divider_0/tspc_1/Z4 vdd 0.42fF +C2807 divider_0/tspc_1/Q vdd 2.79fF +C2808 divider_0/tspc_1/Z3 vdd 2.00fF +C2809 divider_0/tspc_1/Z2 vdd 1.29fF +C2810 divider_0/tspc_1/Z1 vdd 0.99fF +C2811 divider_0/nor_1/B vdd 5.95fF +C2812 divider_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2813 divider_0/tspc_0/Z4 vdd 0.42fF +C2814 divider_0/tspc_0/Q vdd 2.81fF +C2815 divider_0/tspc_0/Z3 vdd 2.00fF +C2816 divider_0/tspc_0/Z2 vdd 1.30fF +C2817 divider_0/tspc_0/Z1 vdd 0.99fF +C2818 divider_0/nor_1/A vdd 6.02fF +C2819 divider_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2820 divider_0/clk vdd 5.56fF +C2821 divider_0/prescaler_0/Out vdd 4.13fF +C2822 divider_0/prescaler_0/nand_1/z1 vdd 0.20fF +C2823 divider_0/prescaler_0/tspc_2/D vdd 2.59fF +C2824 divider_0/prescaler_0/tspc_0/Q vdd 3.30fF +C2825 divider_0/prescaler_0/tspc_1/Q vdd 2.78fF +C2826 divider_0/prescaler_0/nand_0/z1 vdd 0.20fF +C2827 divider_0/prescaler_0/tspc_0/D vdd 3.07fF +C2828 divider_0/and_0/OUT vdd 5.35fF +C2829 divider_0/prescaler_0/tspc_2/Z4 vdd 0.42fF +C2830 divider_0/prescaler_0/tspc_2/Z3 vdd 2.00fF +C2831 divider_0/prescaler_0/tspc_2/Z2 vdd 1.30fF +C2832 divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF +C2833 divider_0/prescaler_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2834 divider_0/prescaler_0/tspc_2/a_740_n680# vdd 1.89fF **FLOATING +C2835 divider_0/prescaler_0/tspc_1/Z4 vdd 0.42fF +C2836 divider_0/prescaler_0/tspc_1/Z3 vdd 2.00fF +C2837 divider_0/prescaler_0/tspc_1/Z2 vdd 1.31fF +C2838 divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF +C2839 divider_0/prescaler_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2840 divider_0/prescaler_0/m1_2700_2190# vdd 3.99fF **FLOATING +C2841 divider_0/prescaler_0/tspc_0/Z4 vdd 0.42fF +C2842 divider_0/prescaler_0/tspc_0/Z3 vdd 2.00fF +C2843 divider_0/prescaler_0/tspc_0/Z2 vdd 1.30fF +C2844 divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF +C2845 divider_0/prescaler_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2846 divider_0/prescaler_0/tspc_0/a_740_n680# vdd 1.89fF **FLOATING +C2847 divider_0/nor_1/Z1 vdd 1.33fF +C2848 divider_0/nor_0/Z1 vdd 1.33fF +C2849 divider_0/mc2 vdd 3.93fF +C2850 divbuf_24/OUT vdd 363.82fF +C2851 divbuf_24/OUT5 vdd 350.37fF +C2852 divbuf_24/OUT4 vdd 133.72fF +C2853 divbuf_24/OUT3 vdd 34.03fF +C2854 divbuf_24/OUT2 vdd 8.71fF +C2855 divbuf_24/IN vdd 0.89fF +C2856 divbuf_24/a_492_n240# vdd 2.46fF **FLOATING +C2857 divbuf_9/OUT vdd 363.82fF +C2858 divbuf_9/OUT5 vdd 350.37fF +C2859 divbuf_9/OUT4 vdd 133.72fF +C2860 divbuf_9/OUT3 vdd 34.03fF +C2861 divbuf_9/OUT2 vdd 8.71fF +C2862 divbuf_9/IN vdd 0.89fF +C2863 divbuf_9/a_492_n240# vdd 2.46fF **FLOATING +C2864 divbuf_13/OUT vdd 363.82fF +C2865 divbuf_13/OUT5 vdd 350.37fF +C2866 divbuf_13/OUT4 vdd 133.72fF +C2867 divbuf_13/OUT3 vdd 34.03fF +C2868 divbuf_13/OUT2 vdd 8.71fF +C2869 divbuf_13/IN vdd 0.89fF +C2870 divbuf_13/a_492_n240# vdd 2.46fF **FLOATING +C2871 divbuf_23/OUT vdd 363.82fF +C2872 divbuf_23/OUT5 vdd 350.37fF +C2873 divbuf_23/OUT4 vdd 133.72fF +C2874 divbuf_23/OUT3 vdd 34.03fF +C2875 divbuf_23/OUT2 vdd 8.71fF +C2876 divbuf_23/IN vdd 0.89fF +C2877 divbuf_23/a_492_n240# vdd 2.46fF **FLOATING +C2878 divbuf_8/OUT vdd 363.82fF +C2879 divbuf_8/OUT5 vdd 350.37fF +C2880 divbuf_8/OUT4 vdd 133.72fF +C2881 divbuf_8/OUT3 vdd 34.03fF +C2882 divbuf_8/OUT2 vdd 8.71fF +C2883 divbuf_8/IN vdd 0.89fF +C2884 divbuf_8/a_492_n240# vdd 2.46fF **FLOATING +C2885 divbuf_12/OUT vdd 363.82fF +C2886 divbuf_12/OUT5 vdd 350.37fF +C2887 divbuf_12/OUT4 vdd 133.72fF +C2888 divbuf_12/OUT3 vdd 34.03fF +C2889 divbuf_12/OUT2 vdd 8.71fF +C2890 divbuf_12/IN vdd 0.89fF +C2891 divbuf_12/a_492_n240# vdd 2.46fF **FLOATING +C2892 divbuf_22/OUT vdd 363.82fF +C2893 divbuf_22/OUT5 vdd 350.37fF +C2894 divbuf_22/OUT4 vdd 133.72fF +C2895 divbuf_22/OUT3 vdd 34.03fF +C2896 divbuf_22/OUT2 vdd 8.71fF +C2897 divbuf_22/IN vdd 0.89fF +C2898 divbuf_22/a_492_n240# vdd 2.46fF **FLOATING +C2899 divbuf_11/OUT vdd 363.82fF +C2900 divbuf_11/OUT5 vdd 350.37fF +C2901 divbuf_11/OUT4 vdd 133.72fF +C2902 divbuf_11/OUT3 vdd 34.03fF +C2903 divbuf_11/OUT2 vdd 8.71fF +C2904 divbuf_11/IN vdd 0.89fF +C2905 divbuf_11/a_492_n240# vdd 2.46fF **FLOATING +C2906 divbuf_7/OUT vdd 363.82fF +C2907 divbuf_7/OUT5 vdd 350.37fF +C2908 divbuf_7/OUT4 vdd 133.72fF +C2909 divbuf_7/OUT3 vdd 34.03fF +C2910 divbuf_7/OUT2 vdd 8.71fF +C2911 divbuf_7/IN vdd 0.89fF +C2912 divbuf_7/a_492_n240# vdd 2.46fF **FLOATING +C2913 divbuf_21/OUT vdd 363.82fF +C2914 divbuf_21/OUT5 vdd 350.37fF +C2915 divbuf_21/OUT4 vdd 133.72fF +C2916 divbuf_21/OUT3 vdd 34.03fF +C2917 divbuf_21/OUT2 vdd 8.71fF +C2918 divbuf_21/IN vdd 0.89fF +C2919 divbuf_21/a_492_n240# vdd 2.46fF **FLOATING +C2920 divbuf_20/OUT vdd 363.82fF +C2921 divbuf_20/OUT5 vdd 350.37fF +C2922 divbuf_20/OUT4 vdd 133.72fF +C2923 divbuf_20/OUT3 vdd 34.03fF +C2924 divbuf_20/OUT2 vdd 8.71fF +C2925 divbuf_20/IN vdd 0.89fF +C2926 divbuf_20/a_492_n240# vdd 2.46fF **FLOATING +C2927 divbuf_10/OUT vdd 363.82fF +C2928 divbuf_10/OUT5 vdd 350.37fF +C2929 divbuf_10/OUT4 vdd 133.72fF +C2930 divbuf_10/OUT3 vdd 34.03fF +C2931 divbuf_10/OUT2 vdd 8.71fF +C2932 divbuf_10/IN vdd 0.89fF +C2933 divbuf_10/a_492_n240# vdd 2.46fF **FLOATING +C2934 divbuf_6/OUT vdd 363.82fF +C2935 divbuf_6/OUT5 vdd 350.37fF +C2936 divbuf_6/OUT4 vdd 133.72fF +C2937 divbuf_6/OUT3 vdd 34.03fF +C2938 divbuf_6/OUT2 vdd 8.71fF +C2939 divbuf_6/IN vdd 0.89fF +C2940 divbuf_6/a_492_n240# vdd 2.46fF **FLOATING +C2941 divbuf_5/OUT vdd 363.82fF +C2942 divbuf_5/OUT5 vdd 350.37fF +C2943 divbuf_5/OUT4 vdd 133.72fF +C2944 divbuf_5/OUT3 vdd 34.03fF +C2945 divbuf_5/OUT2 vdd 8.71fF +C2946 divbuf_5/IN vdd 0.89fF +C2947 divbuf_5/a_492_n240# vdd 2.46fF **FLOATING +C2948 divbuf_4/OUT vdd 363.82fF +C2949 divbuf_4/OUT5 vdd 350.37fF +C2950 divbuf_4/OUT4 vdd 133.72fF +C2951 divbuf_4/OUT3 vdd 34.03fF +C2952 divbuf_4/OUT2 vdd 8.71fF +C2953 divbuf_4/IN vdd 0.89fF +C2954 divbuf_4/a_492_n240# vdd 2.46fF **FLOATING +C2955 divbuf_3/OUT vdd 363.82fF +C2956 divbuf_3/OUT5 vdd 350.37fF +C2957 divbuf_3/OUT4 vdd 133.72fF +C2958 divbuf_3/OUT3 vdd 34.03fF +C2959 divbuf_3/OUT2 vdd 8.71fF +C2960 divbuf_3/IN vdd 0.89fF +C2961 divbuf_3/a_492_n240# vdd 2.46fF **FLOATING +C2962 divbuf_2/OUT vdd 363.82fF +C2963 divbuf_2/OUT5 vdd 350.37fF +C2964 divbuf_2/OUT4 vdd 133.72fF +C2965 divbuf_2/OUT3 vdd 34.03fF +C2966 divbuf_2/OUT2 vdd 8.71fF +C2967 divbuf_2/IN vdd 0.89fF +C2968 divbuf_2/a_492_n240# vdd 2.46fF **FLOATING +C2969 divbuf_1/OUT vdd 363.82fF +C2970 divbuf_1/OUT5 vdd 350.37fF +C2971 divbuf_1/OUT4 vdd 133.72fF +C2972 divbuf_1/OUT3 vdd 34.03fF +C2973 divbuf_1/OUT2 vdd 8.71fF +C2974 divbuf_1/IN vdd 0.89fF +C2975 divbuf_1/a_492_n240# vdd 2.46fF **FLOATING +C2976 ro_complete_1/cbank_2/v vdd 17.84fF +C2977 ro_complete_1/cbank_2/switch_5/vin vdd 0.78fF +C2978 ro_complete_1/cbank_2/switch_4/vin vdd 1.50fF +C2979 ro_complete_1/cbank_2/switch_2/vin vdd 1.30fF +C2980 ro_complete_1/cbank_2/switch_3/vin vdd 0.56fF +C2981 ro_complete_1/cbank_2/switch_1/vin vdd 1.14fF +C2982 ro_complete_1/cbank_2/switch_0/vin vdd 1.02fF +C2983 ro_complete_1/cbank_1/v vdd 16.34fF +C2984 ro_complete_1/cbank_1/switch_5/vin vdd 0.78fF +C2985 ro_complete_1/a0 vdd 7.88fF +C2986 ro_complete_1/cbank_1/switch_4/vin vdd 1.50fF +C2987 ro_complete_1/a1 vdd 5.39fF +C2988 ro_complete_1/cbank_1/switch_2/vin vdd 1.30fF +C2989 ro_complete_1/a3 vdd 6.85fF +C2990 ro_complete_1/cbank_1/switch_3/vin vdd 0.56fF +C2991 ro_complete_1/a2 vdd 5.48fF +C2992 ro_complete_1/cbank_1/switch_1/vin vdd 1.14fF +C2993 ro_complete_1/a4 vdd 5.36fF +C2994 ro_complete_1/cbank_1/switch_0/vin vdd 1.02fF +C2995 ro_complete_1/a5 vdd 5.19fF +C2996 ro_complete_1/cbank_0/v vdd 14.98fF +C2997 ro_complete_1/cbank_0/switch_5/vin vdd 0.78fF +C2998 ro_complete_1/cbank_0/switch_4/vin vdd 1.50fF +C2999 ro_complete_1/cbank_0/switch_2/vin vdd 1.30fF +C3000 ro_complete_1/cbank_0/switch_3/vin vdd 0.56fF +C3001 ro_complete_1/cbank_0/switch_1/vin vdd 1.14fF +C3002 ro_complete_1/cbank_0/switch_0/vin vdd 1.02fF +C3003 ro_complete_1/ro_var_extend_0/vcont vdd 0.27fF +C3004 divbuf_0/OUT vdd 363.82fF +C3005 divbuf_0/OUT5 vdd 350.37fF +C3006 divbuf_0/OUT4 vdd 133.72fF +C3007 divbuf_0/OUT3 vdd 34.03fF +C3008 divbuf_0/OUT2 vdd 8.71fF +C3009 divbuf_0/IN vdd 0.89fF +C3010 divbuf_0/a_492_n240# vdd 2.46fF **FLOATING +C3011 ro_complete_0/cbank_2/v vdd 17.84fF +C3012 ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF +C3013 ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF +C3014 ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF +C3015 ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF +C3016 ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF +C3017 ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF +C3018 ro_complete_0/cbank_1/v vdd 16.38fF +C3019 ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF +C3020 ro_complete_0/a0 vdd 7.88fF +C3021 ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF +C3022 ro_complete_0/a1 vdd 5.39fF +C3023 ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF +C3024 ro_complete_0/a3 vdd 6.85fF +C3025 ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF +C3026 ro_complete_0/a2 vdd 5.48fF +C3027 ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF +C3028 ro_complete_0/a4 vdd 5.36fF +C3029 ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF +C3030 ro_complete_0/a5 vdd 5.19fF +C3031 ro_complete_0/cbank_0/v vdd 14.98fF +C3032 ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF +C3033 ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF +C3034 ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF +C3035 ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF +C3036 ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF +C3037 ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF +C3038 ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF +C3039 filter_0/v vdd 85.69fF +C3040 filter_0/a_4216_n5230# vdd 418.47fF **FLOATING +C3041 filter_0/a_4216_n2998# vdd 1.03fF **FLOATING +C3042 cp_0/down vdd 1.54fF +C3043 cp_0/vbias vdd 2.41fF +C3044 cp_0/out vdd 5.26fF +C3045 cp_0/upbar vdd 1.50fF +C3046 cp_0/a_7110_n2840# vdd 0.17fF **FLOATING +C3047 cp_0/a_3060_n2840# vdd 1.71fF **FLOATING +C3048 cp_0/a_7110_0# vdd 0.17fF **FLOATING +C3049 cp_0/a_6370_0# vdd 0.40fF **FLOATING +C3050 cp_0/a_3060_0# vdd 1.65fF **FLOATING +C3051 cp_0/a_1710_0# vdd 5.76fF **FLOATING +C3052 cp_0/a_1710_n2840# vdd 4.89fF **FLOATING +C3053 cp_0/a_10_n50# vdd 2.96fF **FLOATING +C3054 pd_1/and_pd_0/Z1 vdd 0.39fF +C3055 pd_1/and_pd_0/Out1 vdd 2.22fF +C3056 pd_1/tspc_r_1/z5 vdd 1.10fF +C3057 pd_1/tspc_r_1/Z4 vdd 1.07fF +C3058 pd_1/tspc_r_1/Qbar vdd 0.88fF +C3059 pd_1/tspc_r_1/Z2 vdd 1.22fF +C3060 pd_1/tspc_r_1/Z1 vdd 0.67fF +C3061 pd_1/UP vdd 2.21fF +C3062 pd_1/tspc_r_1/Qbar1 vdd 1.34fF +C3063 pd_1/tspc_r_1/Z3 vdd 2.12fF +C3064 pd_1/REF vdd 1.80fF +C3065 pd_1/tspc_r_0/z5 vdd 1.10fF +C3066 pd_1/tspc_r_0/Z4 vdd 1.07fF +C3067 pd_1/R vdd 3.05fF +C3068 pd_1/tspc_r_0/Qbar vdd 0.79fF +C3069 pd_1/tspc_r_0/Z2 vdd 1.22fF +C3070 pd_1/tspc_r_0/Z1 vdd 0.67fF +C3071 pd_1/DOWN vdd 3.08fF +C3072 pd_1/tspc_r_0/Qbar1 vdd 1.34fF +C3073 pd_1/tspc_r_0/Z3 vdd 2.12fF +C3074 pd_1/DIV vdd 1.82fF +C3075 pd_0/and_pd_0/Z1 vdd 0.39fF +C3076 pd_0/and_pd_0/Out1 vdd 2.22fF +C3077 pd_0/tspc_r_1/z5 vdd 1.10fF +C3078 pd_0/tspc_r_1/Z4 vdd 1.07fF +C3079 pd_0/tspc_r_1/Qbar vdd 0.88fF +C3080 pd_0/tspc_r_1/Z2 vdd 1.22fF +C3081 pd_0/tspc_r_1/Z1 vdd 0.67fF +C3082 pd_0/UP vdd 2.21fF +C3083 pd_0/tspc_r_1/Qbar1 vdd 1.34fF +C3084 pd_0/tspc_r_1/Z3 vdd 2.12fF +C3085 pd_0/REF vdd 1.80fF +C3086 pd_0/tspc_r_0/z5 vdd 1.10fF +C3087 pd_0/tspc_r_0/Z4 vdd 1.07fF +C3088 pd_0/R vdd 3.05fF +C3089 pd_0/tspc_r_0/Qbar vdd 0.79fF +C3090 pd_0/tspc_r_0/Z2 vdd 1.22fF +C3091 pd_0/tspc_r_0/Z1 vdd 0.67fF +C3092 pd_0/DOWN vdd 3.08fF +C3093 pd_0/tspc_r_0/Qbar1 vdd 1.34fF +C3094 pd_0/tspc_r_0/Z3 vdd 2.12fF +C3095 pd_0/DIV vdd 1.82fF .ends