pins
diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz index 417b6a4..8c348af 100644 --- a/gds/user_analog_project_wrapper.gds.gz +++ b/gds/user_analog_project_wrapper.gds.gz Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag index 6160710..7de6300 100644 --- a/mag/user_analog_project_wrapper.mag +++ b/mag/user_analog_project_wrapper.mag
@@ -1,7 +1,7 @@ magic tech sky130A magscale 1 2 -timestamp 1647920904 +timestamp 1647921435 << psubdiff >> rect 193788 665794 196518 666014 rect 193788 663430 194026 665794 @@ -9741,7 +9741,8 @@ rect 313346 515642 318880 517296 rect 314104 512772 318880 515642 rect 314104 507240 318786 512772 -rect 313774 500898 318848 507240 +rect 313774 504986 318848 507240 +rect 313774 500898 318848 501878 rect 313774 500874 318950 500898 rect 313526 499890 318950 500874 rect 313468 493068 318950 499890
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice index 7e6adb4..914e3a6 100644 --- a/netgen/user_analog_project_wrapper.spice +++ b/netgen/user_analog_project_wrapper.spice
@@ -88,7 +88,7 @@ + la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] + la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] + la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2] -+ vccd1 vccd2 vssa1 vdda2 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] ++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] + wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] + wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] + wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] @@ -106,2201 +106,2201 @@ + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] + wbs_stb_i wbs_we_i -C0 div_pd_buffered_0/tapered_buf_3/in4 div_pd_buffered_0/tapered_buf_3/in5 29.21fF -C1 io_analog[9] divider_buffered_0/divider_0/clk 0.40fF -C2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/tapered_buf_3/in 0.03fF -C3 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in5 0.22fF -C4 io_analog[4] ro_divider_buffered_0/tapered_buf_4/in1 0.19fF -C5 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF -C6 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/out 0.61fF -C7 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/B 0.18fF -C8 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C9 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C10 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C11 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 0.31fF -C12 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.15fF -C13 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/Z3 0.20fF -C14 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.35fF -C15 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C16 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C17 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.14fF -C18 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.29fF -C19 io_analog[3] ro_complete_buffered_0/ro_complete_0/a1 0.17fF -C20 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C21 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C22 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.04fF -C23 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.05fF -C24 io_analog[3] io_analog[8] 1.02fF -C25 io_analog[4] io_analog[9] 1.28fF -C26 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in5 0.84fF -C27 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in4 4.78fF -C28 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/Out 0.05fF -C29 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/UP 2.89fF -C30 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C31 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF -C32 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C33 div_pd_buffered_0/tapered_buf_0/in5 div_pd_buffered_0/tapered_buf_0/in1 0.22fF -C34 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z3 0.65fF -C35 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C36 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/B 0.20fF -C37 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.35fF -C38 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C39 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z2 0.15fF -C40 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF -C41 pd_buffered_0/tapered_buf_3/in3 pd_buffered_0/tapered_buf_3/in5 2.89fF -C42 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C43 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in2 0.37fF -C44 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.29fF -C45 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.29fF -C46 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.05fF -C47 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/and_0/OUT 0.06fF -C48 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF -C49 pd_buffered_0/tapered_buf_0/in4 pd_buffered_0/tapered_buf_0/in5 29.21fF -C50 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C51 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in5 2.89fF -C52 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/REF 0.12fF -C53 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/DOWN 0.03fF -C54 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.06fF -C55 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.15fF -C56 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF -C57 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.05fF -C58 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in5 2.89fF -C59 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/nor_1/B 0.30fF -C60 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C61 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF -C62 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF -C63 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF -C64 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF -C65 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/Z1 0.04fF -C66 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z2 0.01fF -C67 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/clk 0.05fF -C68 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF -C69 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/R 0.61fF -C70 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.09fF -C71 gpio_analog[8] io_analog[9] 1.10fF -C72 gpio_analog[3] gpio_noesd[5] 0.96fF -C73 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/mc2 0.05fF -C74 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in5 2.89fF -C75 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF -C76 io_analog[8] ro_divider_buffered_0/tapered_buf_8/in1 0.19fF -C77 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.04fF -C78 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z2 0.36fF -C79 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C80 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_0/B 0.06fF -C81 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.08fF -C82 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C83 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF -C84 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/Z1 0.04fF -C85 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z2 0.01fF -C86 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/clk 0.05fF -C87 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/clk 0.45fF -C88 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF -C89 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF -C90 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF -C91 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF -C92 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF -C93 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in5 0.84fF -C94 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C95 pd_buffered_0/pd_0/tspc_r_1/Qbar pd_buffered_0/pd_0/DOWN 0.21fF -C96 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF -C97 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/div 0.27fF -C98 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in5 29.21fF -C99 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF -C100 gpio_analog[8] cp_buffered_0/tapered_buf_0/in1 0.19fF -C101 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF -C102 io_analog[9] gpio_noesd[13] 2.15fF -C103 io_analog[3] io_analog[9] 1.00fF -C104 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF -C105 divider_buffered_0/tapered_buf_1/in3 divider_buffered_0/tapered_buf_1/in5 2.89fF -C106 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF -C107 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF -C108 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C109 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C110 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in2 1.27fF -C111 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF -C112 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/B 0.18fF -C113 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z2 0.14fF -C114 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF -C115 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/div 0.27fF -C116 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF -C117 ro_divider_buffered_0/tapered_buf_0/in3 ro_divider_buffered_0/tapered_buf_0/in2 1.27fF -C118 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.00fF -C119 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF -C120 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.51fF -C121 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF -C122 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C123 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C124 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/A 0.01fF -C125 gpio_analog[9] gpio_noesd[7] 1.96fF -C126 ro_divider_buffered_0/tapered_buf_2/in2 ro_divider_buffered_0/tapered_buf_2/in1 0.37fF -C127 gpio_noesd[10] pd_buffered_0/tapered_buf_2/in5 26.29fF -C128 gpio_noesd[14] gpio_analog[9] 2.63fF -C129 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF -C130 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.45fF -C131 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C132 io_analog[8] ro_divider_buffered_0/ro_complete_0/a0 0.22fF -C133 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.51fF -C134 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF -C135 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C136 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C137 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C138 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a4 0.09fF -C139 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a5 0.09fF -C140 gpio_noesd[14] gpio_noesd[8] 2.61fF -C141 div_pd_buffered_0/tapered_buf_1/in4 div_pd_buffered_0/tapered_buf_1/in3 4.78fF -C142 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.00fF -C143 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_0/Q 0.14fF -C144 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF -C145 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/clk 0.01fF -C146 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z1 0.03fF -C147 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF -C148 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C149 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF -C150 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C151 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF -C152 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF -C153 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF -C154 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_5/in5 29.21fF -C155 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF -C156 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C157 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C158 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in5 0.22fF -C159 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF -C160 gpio_analog[7] cp_buffered_0/tapered_buf_2/in1 0.19fF -C161 gpio_noesd[7] io_analog[10] 5.73fF -C162 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF -C163 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C164 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in5 2.89fF -C165 gpio_noesd[14] io_analog[10] 2.21fF -C166 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z3 0.06fF -C167 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_1/in5 26.29fF -C168 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF -C169 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/Out 0.05fF -C170 gpio_noesd[10] gpio_noesd[8] 0.51fF -C171 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in5 0.22fF -C172 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF -C173 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.65fF -C174 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C175 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/divider_0/clk 0.10fF -C176 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/tspc_r_0/Z1 0.71fF -C177 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C178 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 1.21fF -C179 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/UP 0.61fF -C180 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in5 2.89fF -C181 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF -C182 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C183 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF -C184 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in2 0.37fF -C185 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C186 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF -C187 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/R 0.27fF -C188 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/UP 0.21fF -C189 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z2 0.36fF -C190 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.16fF -C191 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C192 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 1.21fF -C193 gpio_noesd[10] io_analog[10] 1.21fF -C194 div_pd_buffered_0/pd_0/UP div_pd_buffered_0/tapered_buf_0/in1 0.19fF -C195 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/nor_1/B 1.21fF -C196 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C197 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C198 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF -C199 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z3 0.38fF -C200 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.14fF -C201 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/vco 0.51fF -C202 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/nor_1/B 0.47fF -C203 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.08fF -C204 io_analog[4] io_analog[7] 1.11fF -C205 io_analog[5] io_analog[6] 21.00fF -C206 ro_divider_buffered_0/tapered_buf_5/in4 ro_divider_buffered_0/tapered_buf_5/in5 29.21fF -C207 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C208 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.14fF -C209 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/vco 0.51fF -C210 ro_divider_buffered_0/tapered_buf_7/in5 ro_divider_buffered_0/ro_complete_0/a1 26.29fF -C211 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C212 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF -C213 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C214 pll_full_buffered2_0/tapered_buf_2/in2 pll_full_buffered2_0/tapered_buf_2/in1 0.37fF -C215 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/nor_0/B 0.22fF -C216 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF -C217 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.01fF -C218 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.08fF -C219 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF -C220 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C221 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF -C222 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF -C223 pd_buffered_0/pd_0/DIV io_analog[10] 0.52fF -C224 pd_buffered_0/tapered_buf_0/in5 gpio_noesd[11] 26.29fF -C225 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/tapered_buf_3/in1 0.22fF -C226 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a1 3.18fF -C227 gpio_noesd[11] io_analog[9] 3.74fF -C228 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C229 ro_complete_buffered_0/tapered_buf_3/in1 io_analog[7] 0.19fF -C230 io_analog[9] pll_full_buffered2_0/tapered_buf_1/in1 0.19fF -C231 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C232 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C233 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/div 0.12fF -C234 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF -C235 io_analog[10] div_pd_buffered_0/divider_0/clk 0.61fF -C236 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C237 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.08fF -C238 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF -C239 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C240 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF -C241 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a5 2.39fF -C242 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C243 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/B 0.08fF -C244 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/nor_0/B 0.22fF -C245 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF -C246 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/clk 0.01fF -C247 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF -C248 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in5 0.22fF -C249 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z2 0.23fF -C250 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C251 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/divider_0/clk 1.30fF -C252 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/upbar 0.29fF -C253 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF -C254 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.21fF -C255 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.40fF -C256 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/Out 0.04fF -C257 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/clk 0.29fF -C258 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.31fF -C259 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C260 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF -C261 gpio_noesd[11] gpio_analog[10] 0.49fF -C262 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/tapered_buf_3/in 0.02fF -C263 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.30fF -C264 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in2 0.37fF -C265 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_1/in5 26.29fF -C266 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/pd_0/DIV 26.29fF -C267 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Out1 0.05fF -C268 io_analog[6] ro_divider_buffered_0/ro_complete_0/a2 0.24fF -C269 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in2 0.37fF -C270 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF -C271 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/nor_0/B 0.42fF -C272 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF -C273 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.03fF -C274 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/A 0.35fF -C275 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C276 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C277 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/clk 0.51fF -C278 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/and_0/B 0.78fF -C279 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF -C280 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF -C281 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C282 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C283 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.09fF -C284 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.31fF -C285 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C286 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF -C287 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF -C288 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.40fF -C289 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/clk 0.29fF -C290 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF -C291 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF -C292 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z3 0.05fF -C293 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z1 0.03fF -C294 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Q 0.04fF -C295 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C296 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/divider_0/clk 1.27fF -C297 gpio_analog[3] gpio_analog[6] 1.30fF -C298 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF -C299 gpio_noesd[9] cp_buffered_0/cp_0/down 0.38fF -C300 io_analog[3] ro_complete_buffered_0/ro_complete_0/a5 0.15fF -C301 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in2 0.37fF -C302 gpio_analog[10] div_pd_buffered_0/tapered_buf_3/in1 0.19fF -C303 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 0.09fF -C304 io_analog[3] io_analog[7] 0.92fF -C305 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in4 4.78fF -C306 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF -C307 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C308 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.09fF -C309 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Q 0.04fF -C310 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF -C311 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C312 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C313 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/clk 0.11fF -C314 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C315 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C316 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF -C317 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in2 0.84fF -C318 cp_buffered_0/tapered_buf_2/in1 cp_buffered_0/tapered_buf_2/in5 0.22fF -C319 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C320 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C321 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF -C322 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/nor_0/B 0.47fF -C323 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 4.79fF -C324 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C325 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_1/Z3 0.27fF -C326 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C327 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.18fF -C328 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C329 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z2 0.16fF -C330 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C331 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/nor_0/B 0.47fF -C332 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z3 0.05fF -C333 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF -C334 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF -C335 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C336 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C337 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF -C338 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF -C339 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/B 0.18fF -C340 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF -C341 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF -C342 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.27fF -C343 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.05fF -C344 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered1_0/pll_full_0/vco 1.36fF -C345 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF -C346 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/divider_0/Out 0.19fF -C347 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/out1 0.31fF -C348 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/tspc_0/Q 0.15fF -C349 divider_buffered_0/tapered_buf_1/in4 divider_buffered_0/tapered_buf_1/in3 4.78fF -C350 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/tapered_buf_3/in 5.03fF -C351 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C352 gpio_analog[8] gpio_noesd[7] 1.68fF -C353 io_analog[3] ro_divider_buffered_0/tapered_buf_3/in1 0.19fF -C354 gpio_noesd[14] gpio_analog[8] 2.77fF -C355 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF -C356 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF -C357 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C358 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/out1 0.31fF -C359 div_pd_buffered_0/divider_0/tspc_1/Z4 div_pd_buffered_0/divider_0/tspc_0/Q 0.15fF -C360 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered2_0/pll_full_0/vco 1.36fF -C361 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in5 2.89fF -C362 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF -C363 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF -C364 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF -C365 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C366 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in2 0.84fF -C367 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/B 0.35fF -C368 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF -C369 pll_full_buffered2_0/tapered_buf_5/in pll_full_buffered2_0/tapered_buf_5/in1 0.19fF -C370 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/and_0/B 0.29fF -C371 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C372 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C373 gpio_noesd[7] gpio_noesd[13] 0.80fF -C374 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.04fF -C375 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF -C376 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in3 1.27fF -C377 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/R 0.36fF -C378 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF -C379 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF -C380 div_pd_buffered_0/pd_0/tspc_r_1/Z1 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF -C381 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/UP 0.03fF -C382 gpio_noesd[14] gpio_noesd[13] 2.55fF -C383 ro_divider_buffered_0/tapered_buf_5/in5 ro_divider_buffered_0/ro_complete_0/a3 26.29fF -C384 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.35fF -C385 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Q 0.05fF -C386 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z4 0.36fF -C387 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z2 0.01fF -C388 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/and_0/B 0.78fF -C389 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.01fF -C390 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF -C391 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF -C392 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C393 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.06fF -C394 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF -C395 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C396 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C397 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/and_0/B 0.29fF -C398 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C399 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C400 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF -C401 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF -C402 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in5 2.89fF -C403 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/nor_1/B 0.20fF -C404 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF -C405 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in4 4.78fF -C406 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/clk 0.11fF -C407 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C408 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in2 0.84fF -C409 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C410 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C411 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/UP 0.33fF -C412 io_analog[7] ro_divider_buffered_0/ro_complete_0/a0 0.33fF -C413 io_analog[5] io_clamp_high[1] 0.53fF -C414 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF -C415 divider_buffered_0/divider_0/tspc_0/Z4 divider_buffered_0/divider_0/tspc_0/Z2 0.36fF -C416 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C417 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C418 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF -C419 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF -C420 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C421 filter_buffered_0/filter_0/a_4216_n5230# filter_buffered_0/filter_0/v 0.19fF -C422 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in1 0.22fF -C423 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C424 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z2 0.14fF -C425 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z3 0.05fF -C426 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF -C427 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF -C428 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in5 2.89fF -C429 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C430 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF -C431 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/Z2 0.14fF -C432 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.05fF -C433 ro_divider_buffered_0/tapered_buf_2/in1 gpio_analog[5] 0.19fF -C434 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/REF 0.19fF -C435 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF -C436 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C437 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C438 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF -C439 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF -C440 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF -C441 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z2 0.14fF -C442 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF -C443 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF -C444 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/clk 0.26fF -C445 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C446 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in1 0.22fF -C447 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF -C448 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C449 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF -C450 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C451 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C452 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C453 gpio_noesd[8] pll_full_buffered2_0/tapered_buf_3/in 0.23fF -C454 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in5 0.22fF -C455 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.04fF -C456 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.06fF -C457 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/Out 0.42fF -C458 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/in1 0.22fF -C459 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF -C460 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z4 0.00fF -C461 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.12fF -C462 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered1_0/pll_full_0/div 0.04fF -C463 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in4 4.78fF -C464 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C465 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z2 0.16fF -C466 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered2_0/pll_full_0/vco 1.58fF -C467 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF -C468 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C469 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in3 1.27fF -C470 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in1 0.37fF -C471 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/nor_1/B 0.38fF -C472 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C473 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C474 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C475 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C476 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z3 0.06fF -C477 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C478 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C479 io_analog[10] pll_full_buffered2_0/tapered_buf_3/in 0.42fF -C480 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Q 0.51fF -C481 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z2 0.01fF -C482 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C483 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C484 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/DOWN 0.03fF -C485 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z2 1.07fF -C486 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z3 0.38fF -C487 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z4 0.12fF -C488 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in2 0.37fF -C489 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF -C490 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in 0.19fF -C491 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in3 1.27fF -C492 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.32fF -C493 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C494 io_analog[4] io_analog[6] 1.25fF -C495 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.19fF -C496 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF -C497 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C498 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/nor_1/B 1.21fF -C499 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in4 4.78fF -C500 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Q 0.51fF -C501 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C502 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C503 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C504 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/clk 0.51fF -C505 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF -C506 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C507 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF -C508 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C509 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF -C510 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.20fF -C511 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/out1 0.06fF -C512 gpio_analog[3] ashish_0/a 0.27fF -C513 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C514 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/B 0.31fF -C515 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/Z1 0.36fF -C516 io_analog[6] ro_complete_buffered_0/tapered_buf_4/in1 0.19fF -C517 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z3 0.06fF -C518 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/Z3 0.20fF -C519 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/DIV 0.04fF -C520 gpio_noesd[11] gpio_noesd[7] 0.79fF -C521 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.11fF -C522 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.33fF -C523 gpio_noesd[14] gpio_noesd[11] 2.58fF -C524 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in5 0.22fF -C525 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF -C526 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C527 div_pd_buffered_0/pd_0/and_pd_0/Z1 div_pd_buffered_0/pd_0/UP 0.06fF -C528 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C529 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.20fF -C530 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C531 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C532 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C533 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/nor_1/B 1.21fF -C534 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF -C535 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/R 0.36fF -C536 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF -C537 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF -C538 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in5 0.84fF -C539 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in4 4.78fF -C540 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C541 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C542 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF -C543 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in5 0.84fF -C544 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/pd_0/REF 26.29fF -C545 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/R 0.03fF -C546 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z4 0.12fF -C547 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C548 gpio_noesd[10] gpio_noesd[11] 6.19fF -C549 io_analog[5] ro_divider_buffered_0/ro_complete_0/a2 0.35fF -C550 io_analog[10] div_pd_buffered_0/tapered_buf_1/in1 0.19fF -C551 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C552 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C553 pll_full_buffered1_0/tapered_buf_1/in1 io_analog[10] 0.19fF -C554 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF -C555 pll_full_buffered1_0/tapered_buf_1/in5 pll_full_buffered1_0/pll_full_0/ref 26.29fF -C556 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in3 1.27fF -C557 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF -C558 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C559 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C560 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.06fF -C561 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/and_0/OUT 0.14fF -C562 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/clk 0.51fF -C563 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.01fF -C564 gpio_analog[4] gpio_noesd[4] 0.91fF -C565 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF -C566 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C567 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C568 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.01fF -C569 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF -C570 io_analog[3] io_analog[6] 1.03fF -C571 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in5 0.84fF -C572 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in4 4.78fF -C573 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF -C574 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/UP 0.03fF -C575 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.20fF -C576 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C577 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C578 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.13fF -C579 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF -C580 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.01fF -C581 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C582 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/REF 0.61fF -C583 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF -C584 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF -C585 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C586 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C587 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/B 0.08fF -C588 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF -C589 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C590 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF -C591 pll_full_buffered2_0/tapered_buf_0/in4 pll_full_buffered2_0/tapered_buf_0/in5 29.21fF -C592 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C593 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in5 2.89fF -C594 gpio_noesd[14] pll_full_buffered1_0/pll_full_0/vco 0.69fF -C595 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF -C596 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z3 0.05fF -C597 pll_full_buffered2_0/tapered_buf_5/in5 gpio_noesd[7] 26.29fF -C598 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF -C599 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.04fF -C600 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.13fF -C601 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/clk 0.04fF -C602 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C603 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C604 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 gpio_noesd[14] 26.29fF -C605 div_pd_buffered_0/tapered_buf_0/in5 gpio_noesd[12] 26.29fF -C606 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF -C607 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C608 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF -C609 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF -C610 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z2 1.07fF -C611 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/R 0.03fF -C612 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.14fF -C613 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/vco 0.01fF -C614 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.21fF -C615 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/B 0.31fF -C616 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C617 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF -C618 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF -C619 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in3 2.89fF -C620 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a3 2.04fF -C621 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z4 0.12fF -C622 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.30fF -C623 io_analog[7] ro_divider_buffered_0/tapered_buf_7/in1 0.19fF -C624 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in2 0.84fF -C625 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF -C626 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.18fF -C627 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF -C628 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF -C629 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/div 0.19fF -C630 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF -C631 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C632 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/a3 0.09fF -C633 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_1/B 0.06fF -C634 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.14fF -C635 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/vco 0.01fF -C636 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/B 0.31fF -C637 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C638 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF -C639 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C640 io_analog[10] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.36fF -C641 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF -C642 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/div 0.01fF -C643 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C644 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.00fF -C645 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in5 2.89fF -C646 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF -C647 cp_buffered_0/cp_0/out cp_buffered_0/tapered_buf_1/in1 0.19fF -C648 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/a0 3.46fF -C649 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C650 io_analog[8] ro_complete_buffered_0/ro_complete_0/a0 0.23fF -C651 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z4 0.21fF -C652 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF -C653 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in5 0.84fF -C654 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in4 4.78fF -C655 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.01fF -C656 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF -C657 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C658 divider_buffered_0/tapered_buf_0/in2 divider_buffered_0/tapered_buf_0/in3 1.27fF -C659 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C660 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C661 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C662 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C663 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/div 0.01fF -C664 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C665 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z4 0.00fF -C666 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z4 0.22fF -C667 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z3 0.16fF -C668 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C669 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C670 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF -C671 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.06fF -C672 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z3 0.45fF -C673 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF -C674 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in5 0.84fF -C675 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in4 4.78fF -C676 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C677 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C678 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C679 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C680 io_analog[6] ro_divider_buffered_0/ro_complete_0/a0 0.21fF -C681 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/clk 0.04fF -C682 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C683 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C684 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/A 0.01fF -C685 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.78fF -C686 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF -C687 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF -C688 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C689 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C690 divider_buffered_0/divider_0/and_0/A divider_buffered_0/divider_0/and_0/B 0.18fF -C691 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_divider_buffered_0/divider_0/clk 1.36fF -C692 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C693 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z3 0.38fF -C694 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in2 0.37fF -C695 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.06fF -C696 gpio_analog[9] gpio_noesd[8] 1.10fF -C697 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in3 2.89fF -C698 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Q 0.55fF -C699 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.06fF -C700 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C701 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C702 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in5 2.89fF -C703 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C704 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/clk 0.11fF -C705 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C706 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in5 0.22fF -C707 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.35fF -C708 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF -C709 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C710 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_0/B 0.06fF -C711 divider_buffered_0/tapered_buf_0/in3 divider_buffered_0/tapered_buf_0/in4 4.78fF -C712 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF -C713 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF -C714 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/tapered_buf_3/in 0.32fF -C715 gpio_analog[9] io_analog[10] 1.15fF -C716 pll_full_buffered2_0/tapered_buf_4/in4 pll_full_buffered2_0/tapered_buf_4/in5 29.21fF -C717 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in2 0.37fF -C718 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/div 0.12fF -C719 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_1/B 0.51fF -C720 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C721 io_analog[10] gpio_noesd[8] 3.39fF -C722 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C723 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C724 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/ro_complete_0/a1 26.29fF -C725 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF -C726 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C727 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF -C728 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_divider_buffered_0/divider_0/clk 1.30fF -C729 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF -C730 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.03fF -C731 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C732 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C733 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF -C734 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in3 1.27fF -C735 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/nor_1/A 0.01fF -C736 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C737 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C738 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF -C739 io_analog[4] io_analog[5] 20.14fF -C740 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C741 ro_divider_buffered_0/tapered_buf_4/in4 ro_divider_buffered_0/tapered_buf_4/in5 29.21fF -C742 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF -C743 io_analog[9] gpio_noesd[12] 1.79fF -C744 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF -C745 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF -C746 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.03fF -C747 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C748 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C749 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/tapered_buf_4/in1 0.19fF -C750 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C751 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in4 29.21fF -C752 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C753 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_0/B 0.15fF -C754 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF -C755 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C756 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C757 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF -C758 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF -C759 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.05fF -C760 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in5 0.22fF -C761 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a4 0.12fF -C762 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C763 io_analog[6] ro_complete_buffered_0/ro_complete_0/a2 0.25fF -C764 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z4 0.02fF -C765 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C766 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/UP 0.45fF -C767 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z1 0.17fF -C768 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C769 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF -C770 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/clk 0.11fF -C771 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF -C772 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C773 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C774 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF -C775 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C776 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 1.07fF -C777 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.16fF -C778 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C779 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.18fF -C780 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF -C781 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF -C782 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C783 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF -C784 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.05fF -C785 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C786 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF -C787 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF -C788 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in2 0.84fF -C789 pd_buffered_0/tapered_buf_0/in4 pd_buffered_0/tapered_buf_0/in3 4.78fF -C790 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in3 1.27fF -C791 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C792 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF -C793 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/REF 0.02fF -C794 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in5 2.89fF -C795 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/vco 0.55fF -C796 io_analog[4] ro_divider_buffered_0/ro_complete_0/a2 0.24fF -C797 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z1 0.01fF -C798 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF -C799 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF -C800 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C801 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/div 0.51fF -C802 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in2 0.37fF -C803 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C804 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/A 0.16fF -C805 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF -C806 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF -C807 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF -C808 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C809 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/clk 0.11fF -C810 pd_buffered_0/tapered_buf_3/in1 io_analog[10] 0.19fF -C811 pll_full_buffered1_0/tapered_buf_0/in pll_full_buffered1_0/tapered_buf_0/in1 0.19fF -C812 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C813 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in5 0.22fF -C814 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.65fF -C815 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/pd_0/DOWN 0.19fF -C816 pd_buffered_0/tapered_buf_1/in1 gpio_analog[9] 0.19fF -C817 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in2 0.37fF -C818 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.10fF -C819 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/a0 0.09fF -C820 io_analog[3] io_analog[5] 0.93fF -C821 io_analog[8] gpio_analog[6] 0.64fF -C822 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/DOWN 0.03fF -C823 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/UP 0.11fF -C824 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/R 0.61fF -C825 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C826 cp_buffered_0/cp_0/upbar cp_buffered_0/tapered_buf_2/in5 26.29fF -C827 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C828 ro_divider_buffered_0/tapered_buf_8/in4 ro_divider_buffered_0/tapered_buf_8/in5 29.21fF -C829 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C830 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C831 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF -C832 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF -C833 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C834 div_pd_buffered_0/divider_0/tspc_2/Z3 div_pd_buffered_0/divider_0/tspc_2/Z4 0.65fF -C835 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C836 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.05fF -C837 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF -C838 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.78fF -C839 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/Out 0.05fF -C840 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z4 0.36fF -C841 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/ro_complete_0/a4 26.29fF -C842 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/ro_complete_0/a3 26.29fF -C843 filter_buffered_0/tapered_buf_1/in1 gpio_analog[17] 0.19fF -C844 cp_buffered_0/tapered_buf_0/in4 cp_buffered_0/tapered_buf_0/in5 29.21fF -C845 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C846 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in5 2.89fF -C847 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C848 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF -C849 io_analog[7] ro_divider_buffered_0/ro_complete_0/a1 0.33fF -C850 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.05fF -C851 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF -C852 io_analog[4] io_clamp_high[0] 0.53fF -C853 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C854 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C855 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C856 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C857 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 4.79fF -C858 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C859 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C860 pll_full_buffered1_0/pll_full_0/cp_0/vbias pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# 0.19fF -C861 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C862 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/pd_0/UP 0.19fF -C863 io_analog[9] pll_full_buffered2_0/pll_full_0/div 0.68fF -C864 io_analog[8] ro_complete_buffered_0/tapered_buf_2/in1 0.19fF -C865 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF -C866 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in3 1.27fF -C867 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF -C868 io_analog[3] ro_divider_buffered_0/ro_complete_0/a2 0.24fF -C869 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in1 0.22fF -C870 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/DOWN 0.36fF -C871 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF -C872 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C873 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in5 2.89fF -C874 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in1 0.37fF -C875 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF -C876 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/ro_complete_0/a0 26.29fF -C877 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C878 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C879 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.11fF -C880 pll_full_buffered2_0/tapered_buf_3/in2 pll_full_buffered2_0/tapered_buf_3/in5 0.84fF -C881 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/B 0.01fF -C882 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF -C883 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF -C884 gpio_noesd[9] io_analog[9] 1.19fF -C885 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in3 1.27fF -C886 io_analog[7] ro_complete_buffered_0/ro_complete_0/a0 0.23fF -C887 ro_divider_buffered_0/tapered_buf_4/in5 ro_divider_buffered_0/ro_complete_0/a4 26.29fF -C888 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in2 1.27fF -C889 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF -C890 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF -C891 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C892 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF -C893 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/divider_0/mc2 26.29fF -C894 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF -C895 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/B 0.01fF -C896 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.38fF -C897 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF -C898 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C899 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.03fF -C900 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/Out 0.05fF -C901 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C902 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C903 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C904 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in4 29.21fF -C905 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in5 0.22fF -C906 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF -C907 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF -C908 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in4 4.78fF -C909 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C910 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF -C911 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF -C912 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF -C913 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in3 1.27fF -C914 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C915 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.27fF -C916 gpio_analog[8] io_analog[10] 1.48fF -C917 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C918 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered1_0/pll_full_0/vco 1.58fF -C919 io_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.31fF -C920 gpio_noesd[8] gpio_noesd[13] 0.55fF -C921 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C922 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C923 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.38fF -C924 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF -C925 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C926 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C927 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF -C928 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF -C929 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF -C930 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in5 0.84fF -C931 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.18fF -C932 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z4 0.12fF -C933 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF -C934 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C935 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C936 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered1_0/pll_full_0/vco 1.58fF -C937 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_0/Q 0.14fF -C938 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/clk 0.01fF -C939 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C940 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_1/Z2 0.21fF -C941 io_analog[10] gpio_noesd[13] 1.85fF -C942 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF -C943 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF -C944 gpio_analog[4] divider_buffered_0/tapered_buf_2/in1 0.19fF -C945 io_analog[6] io_clamp_low[2] 0.53fF -C946 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C947 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered2_0/pll_full_0/vco 1.58fF -C948 pd_buffered_0/tapered_buf_3/in4 pd_buffered_0/tapered_buf_3/in5 29.21fF -C949 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in2 0.37fF -C950 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.35fF -C951 pll_full_buffered2_0/tapered_buf_2/in5 gpio_noesd[8] 26.29fF -C952 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in2 1.27fF -C953 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in2 1.27fF -C954 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/mc2 0.04fF -C955 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C956 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF -C957 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.03fF -C958 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF -C959 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C960 io_clamp_low[2] io_clamp_high[2] 0.53fF -C961 io_analog[9] div_pd_buffered_0/tapered_buf_2/in1 0.19fF -C962 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in5 0.22fF -C963 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/tapered_buf_0/in2 0.37fF -C964 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C965 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF -C966 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in5 0.84fF -C967 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in4 4.78fF -C968 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in5 0.84fF -C969 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C970 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in2 0.37fF -C971 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in3 1.27fF -C972 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z3 0.45fF -C973 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/div 0.02fF -C974 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in5 29.21fF -C975 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C976 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C977 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C978 div_pd_buffered_0/tapered_buf_1/in2 div_pd_buffered_0/tapered_buf_1/in3 1.27fF -C979 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C980 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/tapered_buf_1/in5 0.22fF -C981 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF -C982 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C983 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in2 0.37fF -C984 io_analog[0] gpio_analog[3] 3.87fF -C985 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF -C986 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF -C987 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.78fF -C988 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/divider_0/clk 1.30fF -C989 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C990 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in3 1.27fF -C991 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF -C992 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C993 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF -C994 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF -C995 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF -C996 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in2 0.84fF -C997 io_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.27fF -C998 gpio_noesd[7] gpio_noesd[12] 0.68fF -C999 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/A 0.80fF -C1000 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF -C1001 gpio_noesd[14] gpio_noesd[12] 2.57fF -C1002 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1003 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1004 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/REF 0.02fF -C1005 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C1006 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF -C1007 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C1008 pll_full_buffered1_0/pll_full_0/div pll_full_buffered1_0/pll_full_0/vco 2.26fF -C1009 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C1010 cp_buffered_0/tapered_buf_0/in5 cp_buffered_0/cp_0/down 26.29fF -C1011 io_analog[5] ro_complete_buffered_0/ro_complete_0/a2 0.25fF -C1012 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/and_0/OUT 0.14fF -C1013 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.04fF -C1014 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1015 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C1016 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1017 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in5 0.22fF -C1018 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C1019 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C1020 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in3 2.89fF -C1021 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C1022 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/A 0.16fF -C1023 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C1024 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C1025 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF -C1026 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in5 0.84fF -C1027 pd_buffered_0/tapered_buf_3/in3 pd_buffered_0/tapered_buf_3/in4 4.78fF -C1028 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 3.73fF -C1029 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/clk 0.11fF -C1030 pll_full_buffered2_0/pll_full_0/div pll_full_buffered2_0/pll_full_0/vco 2.26fF -C1031 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/R 0.61fF -C1032 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.01fF -C1033 gpio_analog[3] io_analog[1] 1.96fF -C1034 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.55fF -C1035 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF -C1036 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in3 1.27fF -C1037 divider_buffered_0/divider_0/and_0/B divider_buffered_0/divider_0/and_0/Z1 0.07fF -C1038 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/B 0.20fF -C1039 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.22fF -C1040 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in5 0.84fF -C1041 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in4 4.78fF -C1042 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/REF 0.65fF -C1043 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.20fF -C1044 gpio_noesd[11] gpio_noesd[8] 0.55fF -C1045 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a2 1.38fF -C1046 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in3 2.89fF -C1047 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in3 2.89fF -C1048 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/divider_0/clk 26.29fF -C1049 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a3 3.17fF -C1050 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C1051 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Q 0.55fF -C1052 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.55fF -C1053 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF -C1054 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF -C1055 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.03fF -C1056 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C1057 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C1058 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/clk 0.01fF -C1059 pd_buffered_0/tapered_buf_1/in1 pd_buffered_0/tapered_buf_1/in2 0.37fF -C1060 gpio_analog[3] ashish_0/b 0.27fF -C1061 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF -C1062 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.22fF -C1063 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/ro_complete_0/a2 26.29fF -C1064 io_analog[3] io_analog[4] 0.88fF -C1065 gpio_noesd[11] io_analog[10] 1.30fF -C1066 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in5 0.84fF -C1067 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in4 4.78fF -C1068 io_analog[7] gpio_analog[6] 0.64fF -C1069 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/div 0.19fF -C1070 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_1/B 0.18fF -C1071 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/A 0.15fF -C1072 filter_buffered_0/filter_0/v gpio_analog[17] 0.54fF -C1073 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in1 0.22fF -C1074 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C1075 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_3/in3 1.27fF -C1076 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF -C1077 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.22fF -C1078 cp_buffered_0/cp_0/a_10_n50# cp_buffered_0/cp_0/a_1710_0# 0.04fF -C1079 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in1 0.22fF -C1080 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF -C1081 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C1082 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C1083 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/divider_0/clk 1.30fF -C1084 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C1085 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1086 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.35fF -C1087 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/clk 0.60fF -C1088 pd_buffered_0/pd_0/tspc_r_1/Qbar pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.01fF -C1089 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF -C1090 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF -C1091 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF -C1092 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/A 0.01fF -C1093 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.05fF -C1094 gpio_analog[3] gpio_analog[4] 1.29fF -C1095 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in3 2.89fF -C1096 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in5 0.84fF -C1097 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF -C1098 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in3 1.27fF -C1099 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF -C1100 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/DOWN 0.07fF -C1101 io_analog[6] ro_divider_buffered_0/ro_complete_0/a1 0.20fF -C1102 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in1 0.22fF -C1103 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C1104 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.80fF -C1105 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1106 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF -C1107 pll_full_buffered2_0/tapered_buf_1/in4 pll_full_buffered2_0/tapered_buf_1/in5 29.21fF -C1108 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF -C1109 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.08fF -C1110 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C1111 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in3 1.27fF -C1112 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/A 0.01fF -C1113 div_pd_buffered_0/divider_0/tspc_0/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.05fF -C1114 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z1 0.01fF -C1115 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF -C1116 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF -C1117 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF -C1118 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF -C1119 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF -C1120 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.05fF -C1121 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/Out 1.14fF -C1122 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF -C1123 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF -C1124 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C1125 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Q 0.05fF -C1126 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.36fF -C1127 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C1128 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a4 0.09fF -C1129 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a5 0.09fF -C1130 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF -C1131 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/and_0/OUT 0.03fF -C1132 io_analog[6] ro_divider_buffered_0/tapered_buf_6/in1 0.19fF -C1133 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/Z2 0.14fF -C1134 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C1135 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF -C1136 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C1137 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF -C1138 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C1139 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C1140 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF -C1141 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C1142 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C1143 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.06fF -C1144 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.36fF -C1145 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF -C1146 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C1147 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C1148 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in5 2.89fF -C1149 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF -C1150 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C1151 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF -C1152 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/in5 29.21fF -C1153 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_1/in5 0.22fF -C1154 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/DIV 0.51fF -C1155 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_0/Qbar 0.03fF -C1156 gpio_noesd[9] gpio_noesd[7] 3.28fF -C1157 pll_full_buffered1_0/pll_full_0/vco io_analog[10] 0.56fF -C1158 io_analog[6] ro_complete_buffered_0/ro_complete_0/a0 0.23fF -C1159 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/DOWN 0.02fF -C1160 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/R 0.30fF -C1161 divider_buffered_0/tapered_buf_1/in2 divider_buffered_0/tapered_buf_1/in3 1.27fF -C1162 gpio_noesd[14] gpio_noesd[9] 2.58fF -C1163 io_analog[9] io_analog[8] 1.33fF -C1164 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in5 0.84fF -C1165 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in4 4.78fF -C1166 io_analog[10] div_pd_buffered_0/divider_0/mc2 0.64fF -C1167 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z4 0.15fF -C1168 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C1169 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z2 1.07fF -C1170 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C1171 gpio_analog[5] ro_divider_buffered_0/divider_0/Out 0.75fF -C1172 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.01fF -C1173 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C1174 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C1175 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in3 1.27fF -C1176 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Q 0.05fF -C1177 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.36fF -C1178 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/div 0.03fF -C1179 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/vco 0.06fF -C1180 io_analog[3] ro_complete_buffered_0/tapered_buf_1/in1 0.19fF -C1181 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C1182 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/tapered_buf_3/in 0.11fF -C1183 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in5 0.84fF -C1184 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in4 4.78fF -C1185 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/R 0.51fF -C1186 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C1187 io_analog[4] ro_divider_buffered_0/ro_complete_0/a0 0.22fF -C1188 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/in1 0.22fF -C1189 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/out 0.84fF -C1190 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z1 0.00fF -C1191 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.06fF -C1192 div_pd_buffered_0/tapered_buf_1/in1 div_pd_buffered_0/tapered_buf_1/in2 0.37fF -C1193 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C1194 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1195 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/div 0.03fF -C1196 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/vco 0.06fF -C1197 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C1198 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF -C1199 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/vco 0.64fF -C1200 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF -C1201 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/divider_0/mc2 26.29fF -C1202 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C1203 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in5 2.89fF -C1204 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C1205 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/vco 0.64fF -C1206 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/clk 0.14fF -C1207 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C1208 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.04fF -C1209 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF -C1210 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.30fF -C1211 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF -C1212 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF -C1213 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF -C1214 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a5 2.39fF -C1215 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C1216 filter_buffered_0/tapered_buf_0/in4 filter_buffered_0/tapered_buf_0/in5 29.21fF -C1217 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/nor_1/A 0.03fF -C1218 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C1219 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.12fF -C1220 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C1221 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1222 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/div 0.65fF -C1223 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1224 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF -C1225 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF -C1226 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF -C1227 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/A 0.01fF -C1228 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF -C1229 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in3 1.27fF -C1230 pll_full_buffered2_0/tapered_buf_3/in4 pll_full_buffered2_0/tapered_buf_3/in5 29.21fF -C1231 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/nor_1/B 0.38fF -C1232 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z1 0.00fF -C1233 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C1234 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/divider_0/clk 0.05fF -C1235 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF -C1236 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.04fF -C1237 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.26fF -C1238 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z3 0.05fF -C1239 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z1 0.03fF -C1240 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in2 0.37fF -C1241 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.29fF -C1242 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in1 0.37fF -C1243 io_analog[9] gpio_analog[10] 3.28fF -C1244 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in3 2.89fF -C1245 ro_divider_buffered_0/tapered_buf_3/in4 ro_divider_buffered_0/tapered_buf_3/in5 29.21fF -C1246 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/div 0.51fF -C1247 io_analog[4] ro_divider_buffered_0/ro_complete_0/a3 0.23fF -C1248 io_analog[3] ro_divider_buffered_0/ro_complete_0/a0 0.22fF -C1249 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in1 0.37fF -C1250 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/nor_1/A 0.01fF -C1251 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF -C1252 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1253 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z2 0.15fF -C1254 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF -C1255 io_analog[9] ro_divider_buffered_0/tapered_buf_1/in1 0.19fF -C1256 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF -C1257 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.03fF -C1258 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1259 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF -C1260 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.04fF -C1261 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.26fF -C1262 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/pd_0/REF 26.29fF -C1263 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF -C1264 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z1 0.03fF -C1265 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF -C1266 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C1267 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/vco 0.01fF -C1268 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z2 0.01fF -C1269 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/clk 0.05fF -C1270 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF -C1271 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C1272 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_divider_buffered_0/divider_0/clk 1.43fF -C1273 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF -C1274 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF -C1275 io_analog[4] ro_complete_buffered_0/ro_complete_0/a2 0.37fF -C1276 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in1 0.22fF -C1277 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in4 29.21fF -C1278 divider_buffered_0/tapered_buf_1/in4 divider_buffered_0/tapered_buf_1/in5 29.21fF -C1279 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C1280 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in4 4.78fF -C1281 div_pd_buffered_0/pd_0/tspc_r_1/Z4 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF -C1282 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_1/Z4 0.02fF -C1283 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z3 0.06fF -C1284 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF -C1285 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C1286 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in3 2.89fF -C1287 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF -C1288 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF -C1289 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF -C1290 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/DOWN 0.02fF -C1291 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF -C1292 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1293 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C1294 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/B 0.18fF -C1295 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.65fF -C1296 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C1297 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF -C1298 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/DIV 0.51fF -C1299 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 divider_buffered_0/divider_0/and_0/OUT 0.01fF -C1300 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.09fF -C1301 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.36fF -C1302 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z1 0.06fF -C1303 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF -C1304 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in2 0.37fF -C1305 gpio_analog[7] io_analog[9] 1.40fF -C1306 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in5 2.89fF -C1307 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C1308 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/UP 0.33fF -C1309 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.45fF -C1310 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C1311 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_2/in1 0.37fF -C1312 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/Z1 0.04fF -C1313 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF -C1314 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1315 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C1316 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.45fF -C1317 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/A 0.80fF -C1318 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF -C1319 filter_buffered_0/filter_0/a_4216_n2998# filter_buffered_0/filter_0/v 0.31fF -C1320 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C1321 io_clamp_low[1] io_clamp_high[1] 0.53fF -C1322 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C1323 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF -C1324 io_analog[6] gpio_analog[6] 0.64fF -C1325 io_analog[7] ro_complete_buffered_0/ro_complete_0/a1 0.23fF -C1326 cp_buffered_0/tapered_buf_2/in4 cp_buffered_0/tapered_buf_2/in5 29.21fF -C1327 io_analog[7] io_analog[8] 1.38fF -C1328 io_analog[3] ro_divider_buffered_0/ro_complete_0/a3 0.23fF -C1329 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in4 29.21fF -C1330 ro_divider_buffered_0/tapered_buf_7/in4 ro_divider_buffered_0/tapered_buf_7/in5 29.21fF -C1331 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in5 0.84fF -C1332 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF -C1333 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z3 0.16fF -C1334 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z2 1.07fF -C1335 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF -C1336 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF -C1337 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C1338 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C1339 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C1340 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF -C1341 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in5 0.84fF -C1342 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in4 4.78fF -C1343 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C1344 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z2 0.36fF -C1345 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C1346 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/vco 0.26fF -C1347 cp_buffered_0/tapered_buf_1/in4 cp_buffered_0/tapered_buf_1/in5 29.21fF -C1348 io_analog[3] ro_complete_buffered_0/ro_complete_0/a2 0.22fF -C1349 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF -C1350 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C1351 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF -C1352 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF -C1353 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF -C1354 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF -C1355 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/R 0.01fF -C1356 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF -C1357 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF -C1358 io_analog[5] ro_divider_buffered_0/ro_complete_0/a1 0.30fF -C1359 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C1360 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/clk 0.01fF -C1361 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C1362 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in5 29.21fF -C1363 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z4 0.00fF -C1364 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C1365 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in5 0.22fF -C1366 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C1367 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1368 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/vco 0.26fF -C1369 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF -C1370 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Q 0.55fF -C1371 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_divider_buffered_0/divider_0/clk 1.30fF -C1372 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF -C1373 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C1374 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in4 4.78fF -C1375 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF -C1376 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C1377 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/UP 0.61fF -C1378 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF -C1379 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C1380 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C1381 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1382 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z4 0.00fF -C1383 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF -C1384 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C1385 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 29.21fF -C1386 io_analog[5] io_clamp_low[1] 0.53fF -C1387 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF -C1388 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF -C1389 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF -C1390 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z1 0.01fF -C1391 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/Q 0.22fF -C1392 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C1393 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/UP 0.11fF -C1394 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF -C1395 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in5 0.84fF -C1396 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF -C1397 filter_buffered_0/tapered_buf_0/in5 gpio_analog[17] 26.29fF -C1398 io_analog[5] ro_complete_buffered_0/ro_complete_0/a0 0.23fF -C1399 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/REF 0.17fF -C1400 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z2 1.07fF -C1401 gpio_noesd[10] pd_buffered_0/pd_0/DOWN 0.54fF -C1402 io_analog[9] io_analog[7] 1.28fF -C1403 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/div 4.07fF -C1404 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF -C1405 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF -C1406 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C1407 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/out1 0.06fF -C1408 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C1409 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a1 3.18fF -C1410 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z1 0.01fF -C1411 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_0/Q 0.22fF -C1412 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in5 0.84fF -C1413 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C1414 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/A 0.80fF -C1415 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C1416 pd_buffered_0/tapered_buf_2/in4 pd_buffered_0/tapered_buf_2/in3 4.78fF -C1417 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF -C1418 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF -C1419 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1420 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF -C1421 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.32fF -C1422 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C1423 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z2 1.07fF -C1424 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z3 0.38fF -C1425 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z4 0.12fF -C1426 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF -C1427 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in3 1.27fF -C1428 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C1429 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in1 0.37fF -C1430 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C1431 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/div 0.02fF -C1432 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.47fF -C1433 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/clk 0.12fF -C1434 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF -C1435 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF -C1436 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1437 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/B 0.30fF -C1438 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/divider_0/Out 0.20fF -C1439 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF -C1440 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF -C1441 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z2 1.07fF -C1442 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z3 0.38fF -C1443 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z4 0.12fF -C1444 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z4 0.12fF -C1445 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C1446 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF -C1447 io_analog[0] ashish_0/a 4.11fF -C1448 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF -C1449 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z2 0.40fF -C1450 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/Out 0.04fF -C1451 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/clk 0.29fF -C1452 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.33fF -C1453 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/Z1 0.36fF -C1454 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/div 0.05fF -C1455 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF -C1456 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in1 0.37fF -C1457 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C1458 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF -C1459 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.21fF -C1460 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in5 29.21fF -C1461 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF -C1462 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/down 0.32fF -C1463 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/UP 0.03fF -C1464 gpio_analog[5] ro_divider_buffered_0/divider_0/mc2 0.49fF -C1465 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/clk 0.26fF -C1466 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF -C1467 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Z4 0.12fF -C1468 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C1469 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/clk 0.64fF -C1470 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF -C1471 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C1472 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/div 0.05fF -C1473 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF -C1474 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C1475 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF -C1476 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 0.38fF -C1477 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/Z1 0.36fF -C1478 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in1 0.37fF -C1479 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C1480 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C1481 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF -C1482 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/A 0.26fF -C1483 pll_full_buffered2_0/tapered_buf_0/in5 pll_full_buffered2_0/pll_full_0/ref 26.29fF -C1484 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/DIV 0.02fF -C1485 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.14fF -C1486 gpio_noesd[7] io_analog[9] 1.42fF -C1487 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in3 1.27fF -C1488 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C1489 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z2 0.01fF -C1490 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF -C1491 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C1492 gpio_noesd[14] io_analog[9] 3.54fF -C1493 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C1494 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C1495 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in2 0.37fF -C1496 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.04fF -C1497 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C1498 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1499 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/nor_1/B 0.22fF -C1500 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.01fF -C1501 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF -C1502 ashish_0/a io_analog[1] 8.93fF -C1503 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF -C1504 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C1505 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF -C1506 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/clk 0.04fF -C1507 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in3 1.27fF -C1508 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF -C1509 gpio_noesd[7] gpio_analog[10] 0.77fF -C1510 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/R 0.21fF -C1511 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/UP 0.45fF -C1512 gpio_noesd[14] gpio_analog[10] 2.60fF -C1513 io_analog[4] ro_divider_buffered_0/ro_complete_0/a4 0.19fF -C1514 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.13fF -C1515 ro_divider_buffered_0/tapered_buf_3/in5 ro_divider_buffered_0/ro_complete_0/a5 26.29fF -C1516 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C1517 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1518 gpio_noesd[10] io_analog[9] 3.45fF -C1519 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C1520 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF -C1521 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C1522 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF -C1523 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C1524 pll_full_buffered1_0/tapered_buf_0/in4 pll_full_buffered1_0/tapered_buf_0/in5 29.21fF -C1525 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/clk 0.04fF -C1526 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF -C1527 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF -C1528 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C1529 divider_buffered_0/tapered_buf_2/in1 divider_buffered_0/tapered_buf_2/in5 0.22fF -C1530 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in2 0.84fF -C1531 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/clk 0.64fF -C1532 ashish_0/a ashish_0/b 7.45fF -C1533 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C1534 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C1535 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF -C1536 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF -C1537 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.27fF -C1538 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.05fF -C1539 cp_buffered_0/tapered_buf_1/in5 gpio_noesd[9] 26.29fF -C1540 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C1541 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C1542 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in5 0.22fF -C1543 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF -C1544 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/divider_0/clk 26.29fF -C1545 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C1546 gpio_noesd[10] gpio_analog[10] 1.36fF -C1547 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Z4 0.65fF -C1548 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C1549 gpio_noesd[8] gpio_noesd[12] 0.46fF -C1550 gpio_noesd[7] pll_full_buffered2_0/tapered_buf_5/in 0.54fF -C1551 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in5 0.84fF -C1552 pll_full_buffered2_0/tapered_buf_5/in5 pll_full_buffered2_0/tapered_buf_5/in1 0.22fF -C1553 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C1554 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C1555 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF -C1556 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_4/in5 29.21fF -C1557 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/and_0/B 0.29fF -C1558 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF -C1559 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/A 0.01fF -C1560 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in5 2.89fF -C1561 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/clk 0.64fF -C1562 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in4 4.78fF -C1563 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/UP 0.45fF -C1564 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z2 0.11fF -C1565 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/div 0.45fF -C1566 gpio_analog[7] gpio_noesd[14] 2.55fF -C1567 io_analog[10] gpio_noesd[12] 1.57fF -C1568 io_analog[9] div_pd_buffered_0/divider_0/clk 0.65fF -C1569 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF -C1570 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/out1 0.31fF -C1571 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/nor_1/B 0.21fF -C1572 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z4 0.21fF -C1573 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z3 0.65fF -C1574 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF -C1575 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF -C1576 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C1577 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z3 0.45fF -C1578 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.04fF -C1579 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/A 0.26fF -C1580 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_1/in5 29.21fF -C1581 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF -C1582 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C1583 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/a3 0.09fF -C1584 io_analog[5] gpio_analog[6] 0.64fF -C1585 io_analog[6] ro_complete_buffered_0/ro_complete_0/a1 0.22fF -C1586 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF -C1587 io_analog[6] io_analog[8] 1.24fF -C1588 io_analog[3] ro_divider_buffered_0/ro_complete_0/a4 0.19fF -C1589 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/nor_1/A 0.15fF -C1590 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF -C1591 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z2 0.23fF -C1592 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C1593 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/div 0.17fF -C1594 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C1595 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.09fF -C1596 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z3 0.45fF -C1597 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/A 0.26fF -C1598 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF -C1599 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C1600 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF -C1601 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z4 0.02fF -C1602 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C1603 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF -C1604 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF -C1605 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in5 0.84fF -C1606 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in4 4.78fF -C1607 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C1608 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.22fF -C1609 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.16fF -C1610 io_analog[4] ro_complete_buffered_0/tapered_buf_6/in1 0.19fF -C1611 io_analog[5] ro_complete_buffered_0/tapered_buf_5/in1 0.19fF -C1612 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF -C1613 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C1614 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.12fF -C1615 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C1616 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/out 26.29fF -C1617 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF -C1618 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF -C1619 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF -C1620 io_analog[4] ro_divider_buffered_0/ro_complete_0/a1 0.21fF -C1621 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in5 0.22fF -C1622 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF -C1623 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C1624 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C1625 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C1626 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.22fF -C1627 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z3 0.16fF -C1628 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF -C1629 gpio_analog[3] gpio_noesd[4] 1.38fF -C1630 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z4 0.21fF -C1631 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1632 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/divider_0/clk 0.05fF -C1633 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C1634 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z3 0.06fF -C1635 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/Out 0.44fF -C1636 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 0.22fF -C1637 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/nor_1/A 0.03fF -C1638 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in3 1.27fF -C1639 ro_divider_buffered_0/divider_0/and_0/A ro_divider_buffered_0/divider_0/and_0/B 0.18fF -C1640 gpio_analog[8] cp_buffered_0/cp_0/down 0.25fF -C1641 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in5 0.22fF -C1642 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in3 1.27fF -C1643 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z4 0.65fF -C1644 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C1645 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C1646 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1647 io_analog[5] ro_divider_buffered_0/tapered_buf_5/in1 0.19fF -C1648 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF -C1649 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/out1 0.06fF -C1650 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Z4 0.21fF -C1651 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z3 0.45fF -C1652 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C1653 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/vco 0.01fF -C1654 ro_divider_buffered_0/tapered_buf_0/in5 gpio_noesd[5] 26.29fF -C1655 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A 0.15fF -C1656 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.09fF -C1657 div_pd_buffered_0/divider_0/and_0/A div_pd_buffered_0/divider_0/and_0/B 0.18fF -C1658 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C1659 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C1660 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C1661 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C1662 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/UP 1.14fF -C1663 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.07fF -C1664 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/tspc_r_1/Z3 0.11fF -C1665 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/div 0.25fF -C1666 io_analog[4] ro_complete_buffered_0/ro_complete_0/a0 0.33fF -C1667 io_analog[6] io_analog[9] 1.28fF -C1668 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A 0.15fF -C1669 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.09fF -C1670 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in5 0.84fF -C1671 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in4 4.78fF -C1672 ro_divider_buffered_0/tapered_buf_8/in5 ro_divider_buffered_0/ro_complete_0/a0 26.29fF -C1673 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C1674 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_0/B 0.15fF -C1675 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C1676 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C1677 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in3 1.27fF -C1678 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C1679 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z2 1.07fF -C1680 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.07fF -C1681 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF -C1682 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C1683 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF -C1684 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/clk 0.26fF -C1685 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF -C1686 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF -C1687 io_clamp_low[0] io_clamp_high[0] 0.53fF -C1688 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in5 2.89fF -C1689 gpio_analog[9] gpio_noesd[9] 1.46fF -C1690 io_analog[10] pll_full_buffered2_0/pll_full_0/div 0.47fF -C1691 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C1692 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1693 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF -C1694 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in5 2.89fF -C1695 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/div 0.65fF -C1696 gpio_noesd[9] gpio_noesd[8] 1.97fF -C1697 io_analog[3] ro_divider_buffered_0/ro_complete_0/a1 0.19fF -C1698 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/nor_1/B 0.38fF -C1699 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.05fF -C1700 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in3 1.27fF -C1701 div_pd_buffered_0/pd_0/DOWN gpio_noesd[12] 0.33fF -C1702 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in3 2.89fF -C1703 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z2 0.11fF -C1704 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_0/in1 0.19fF -C1705 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.13fF -C1706 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C1707 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C1708 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/clk 0.26fF -C1709 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF -C1710 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF -C1711 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z3 0.45fF -C1712 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/divider_0/clk 0.05fF -C1713 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF -C1714 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C1715 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C1716 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in2 0.37fF -C1717 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/UP 0.45fF -C1718 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.35fF -C1719 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/vco 0.60fF -C1720 gpio_analog[6] ro_complete_buffered_0/tapered_buf_0/in1 0.19fF -C1721 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C1722 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF -C1723 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/A 0.35fF -C1724 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C1725 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/R 0.36fF -C1726 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF -C1727 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF -C1728 gpio_noesd[9] io_analog[10] 1.63fF -C1729 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in5 2.89fF -C1730 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.12fF -C1731 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C1732 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.13fF -C1733 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/divider_0/mc2 0.34fF -C1734 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in2 1.27fF -C1735 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF -C1736 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/R 0.21fF -C1737 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.80fF -C1738 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF -C1739 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C1740 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C1741 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF -C1742 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in3 4.78fF -C1743 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF -C1744 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_1/Z2 0.01fF -C1745 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.35fF -C1746 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/vco 0.60fF -C1747 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/a_1710_0# 0.83fF -C1748 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_0/Z3 0.29fF -C1749 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF -C1750 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C1751 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF -C1752 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C1753 divider_buffered_0/divider_0/tspc_2/Z4 divider_buffered_0/divider_0/nor_1/B 0.02fF -C1754 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in3 1.27fF -C1755 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in1 0.37fF -C1756 filter_buffered_0/tapered_buf_1/in4 filter_buffered_0/tapered_buf_1/in5 29.21fF -C1757 io_analog[3] ro_complete_buffered_0/ro_complete_0/a0 0.20fF -C1758 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF -C1759 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C1760 gpio_noesd[14] gpio_noesd[7] 2.93fF -C1761 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z4 0.12fF -C1762 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/UP 0.06fF -C1763 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF -C1764 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C1765 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C1766 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C1767 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C1768 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in3 2.89fF -C1769 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.06fF -C1770 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z2 0.11fF -C1771 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1772 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF -C1773 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z4 0.15fF -C1774 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.45fF -C1775 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in2 0.37fF -C1776 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF -C1777 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF -C1778 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF -C1779 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF -C1780 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in3 1.27fF -C1781 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in4 4.78fF -C1782 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in2 0.84fF -C1783 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C1784 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a4 0.13fF -C1785 cp_buffered_0/tapered_buf_2/in4 cp_buffered_0/tapered_buf_2/in3 4.78fF -C1786 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in2 0.84fF -C1787 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_0/B 0.22fF -C1788 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_0/Q 0.15fF -C1789 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C1790 gpio_noesd[13] gpio_noesd[12] 0.45fF -C1791 gpio_noesd[10] gpio_noesd[7] 0.73fF -C1792 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/A 0.04fF -C1793 gpio_noesd[14] gpio_noesd[10] 2.89fF -C1794 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.45fF -C1795 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a3 2.04fF -C1796 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z4 0.15fF -C1797 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF -C1798 io_analog[9] pll_full_buffered2_0/tapered_buf_3/in 0.61fF -C1799 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in3 1.27fF -C1800 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in5 0.22fF -C1801 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C1802 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF -C1803 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF -C1804 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C1805 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/Out 0.05fF -C1806 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.36fF -C1807 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF -C1808 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF -C1809 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_6/in5 29.21fF -C1810 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/nor_1/A 0.15fF -C1811 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/R 0.03fF -C1812 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF -C1813 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C1814 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF -C1815 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/UP 0.03fF -C1816 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C1817 pll_full_buffered2_0/tapered_buf_2/in1 pll_full_buffered2_0/pll_full_0/div 0.19fF -C1818 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in5 2.89fF -C1819 ro_divider_buffered_0/tapered_buf_6/in5 ro_divider_buffered_0/ro_complete_0/a2 26.29fF -C1820 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF -C1821 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C1822 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C1823 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C1824 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C1825 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF -C1826 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF -C1827 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in1 0.37fF -C1828 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in5 2.89fF -C1829 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/a0 3.46fF -C1830 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF -C1831 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C1832 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z4 0.36fF -C1833 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF -C1834 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z4 0.00fF -C1835 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C1836 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in2 0.37fF -C1837 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C1838 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 3.73fF -C1839 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF -C1840 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in5 2.89fF -C1841 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C1842 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in5 0.84fF -C1843 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in2 0.37fF -C1844 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C1845 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C1846 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C1847 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in4 29.21fF -C1848 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/B 0.08fF -C1849 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF -C1850 io_analog[4] io_clamp_low[0] 0.53fF -C1851 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C1852 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C1853 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in5 0.22fF -C1854 io_analog[9] divider_buffered_0/tapered_buf_0/in1 0.19fF -C1855 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C1856 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C1857 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.14fF -C1858 ro_divider_buffered_0/tapered_buf_1/in1 ro_divider_buffered_0/tapered_buf_1/in2 0.37fF -C1859 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.02fF -C1860 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C1861 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF -C1862 gpio_analog[3] gpio_analog[5] 1.06fF -C1863 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/pd_0/DOWN 0.19fF -C1864 io_analog[4] gpio_analog[6] 0.64fF -C1865 io_analog[5] ro_complete_buffered_0/ro_complete_0/a1 0.22fF -C1866 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in4 29.21fF -C1867 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.06fF -C1868 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.01fF -C1869 io_analog[5] io_analog[8] 1.24fF -C1870 io_analog[6] io_analog[7] 1.12fF -C1871 ro_divider_buffered_0/tapered_buf_6/in4 ro_divider_buffered_0/tapered_buf_6/in5 29.21fF -C1872 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C1873 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1874 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C1875 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/clk 0.14fF -C1876 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C1877 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.14fF -C1878 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in5 0.84fF -C1879 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in4 4.78fF -C1880 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.02fF -C1881 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C1882 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/clk 0.45fF -C1883 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF -C1884 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C1885 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C1886 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF -C1887 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF -C1888 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF -C1889 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C1890 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in5 0.22fF -C1891 div_pd_buffered_0/tapered_buf_2/in2 div_pd_buffered_0/tapered_buf_2/in3 1.27fF -C1892 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF -C1893 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF -C1894 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C1895 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a1 1.84fF -C1896 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in4 4.78fF -C1897 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF -C1898 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C1899 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C1900 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.30fF -C1901 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in3 2.89fF -C1902 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.04fF -C1903 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF -C1904 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/vco 0.05fF -C1905 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 io_analog[2] 26.29fF -C1906 gpio_noesd[9] gpio_analog[8] 2.46fF -C1907 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in2 0.37fF -C1908 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF -C1909 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF -C1910 cp_buffered_0/cp_0/out cp_buffered_0/cp_0/down 0.79fF -C1911 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.43fF -C1912 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.45fF -C1913 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in1 0.22fF -C1914 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF -C1915 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/DOWN 0.12fF -C1916 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in1 0.37fF -C1917 io_analog[10] pll_full_buffered2_0/tapered_buf_0/in1 0.19fF -C1918 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/and_0/OUT 0.14fF -C1919 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_0/B 0.15fF -C1920 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.30fF -C1921 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in1 0.22fF -C1922 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C1923 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.04fF -C1924 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF -C1925 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/vco 0.05fF -C1926 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF -C1927 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in2 0.37fF -C1928 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF -C1929 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C1930 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF -C1931 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in5 0.84fF -C1932 io_analog[3] gpio_analog[6] 0.53fF -C1933 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF -C1934 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF -C1935 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C1936 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF -C1937 io_analog[5] io_analog[9] 1.28fF -C1938 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in4 29.21fF -C1939 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF -C1940 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF -C1941 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a4 0.12fF -C1942 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C1943 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C1944 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/clk 0.12fF -C1945 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/clk 0.45fF -C1946 divider_buffered_0/tapered_buf_2/in4 divider_buffered_0/tapered_buf_2/in3 4.78fF -C1947 io_analog[9] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.53fF -C1948 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 0.06fF -C1949 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF -C1950 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF -C1951 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF -C1952 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/UP 0.21fF -C1953 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.00fF -C1954 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF -C1955 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in3 1.27fF -C1956 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF -C1957 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in3 2.89fF -C1958 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C1959 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C1960 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/mc2 0.04fF -C1961 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C1962 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in4 4.78fF -C1963 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/REF 0.04fF -C1964 div_pd_buffered_0/tapered_buf_4/in4 div_pd_buffered_0/tapered_buf_4/in5 29.21fF -C1965 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1966 io_analog[3] ro_divider_buffered_0/ro_complete_0/a5 0.17fF -C1967 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z2 0.14fF -C1968 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1969 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C1970 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF -C1971 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C1972 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1973 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/clk 0.45fF -C1974 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_3/in3 4.78fF -C1975 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/B 0.20fF -C1976 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.00fF -C1977 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF -C1978 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C1979 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/divider_0/clk 0.05fF -C1980 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF -C1981 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF -C1982 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C1983 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in5 0.84fF -C1984 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C1985 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/clk 0.12fF -C1986 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.04fF -C1987 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1988 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z4 0.65fF -C1989 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z2 0.19fF -C1990 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C1991 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.09fF -C1992 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 0.09fF -C1993 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/DOWN 0.11fF -C1994 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF -C1995 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF -C1996 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF -C1997 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C1998 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C1999 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C2000 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF -C2001 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/nor_1/A 0.15fF -C2002 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/a0 0.09fF -C2003 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C2004 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C2005 io_analog[0] io_analog[1] 8.34fF -C2006 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF -C2007 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C2008 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/vco 0.15fF -C2009 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/tspc_2/Z4 0.65fF -C2010 pd_buffered_0/tapered_buf_1/in3 pd_buffered_0/tapered_buf_1/in4 4.78fF -C2011 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF -C2012 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/DOWN 0.11fF -C2013 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 29.21fF -C2014 pll_full_buffered2_0/tapered_buf_3/in5 pll_full_buffered2_0/tapered_buf_3/out 26.29fF -C2015 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/and_0/Z1 0.07fF -C2016 io_analog[4] ro_complete_buffered_0/ro_complete_0/a4 0.20fF -C2017 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF -C2018 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/mc2 0.33fF -C2019 divider_buffered_0/tapered_buf_1/in2 divider_buffered_0/tapered_buf_1/in1 0.37fF -C2020 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF -C2021 pll_full_buffered2_0/tapered_buf_5/in4 pll_full_buffered2_0/tapered_buf_5/in5 29.21fF -C2022 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in3 1.27fF -C2023 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/pll_full_0/vco 0.19fF -C2024 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C2025 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C2026 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF -C2027 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C2028 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/vco 0.15fF -C2029 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in3 4.78fF -C2030 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C2031 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C2032 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C2033 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 0.22fF -C2034 div_pd_buffered_0/divider_0/and_0/B div_pd_buffered_0/divider_0/and_0/Z1 0.07fF -C2035 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.00fF -C2036 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/tspc_r_0/z5 0.02fF -C2037 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/A 0.16fF -C2038 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.06fF -C2039 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF -C2040 io_analog[0] ashish_0/b 8.93fF -C2041 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF -C2042 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in3 4.78fF -C2043 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a3 3.17fF -C2044 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C2045 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF -C2046 gpio_analog[9] io_analog[9] 0.93fF -C2047 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in5 0.22fF -C2048 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C2049 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF -C2050 io_analog[9] gpio_noesd[8] 0.91fF -C2051 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF -C2052 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF -C2053 pll_full_buffered1_0/tapered_buf_1/in4 pll_full_buffered1_0/tapered_buf_1/in5 29.21fF -C2054 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z3 0.38fF -C2055 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 div_pd_buffered_0/divider_0/clk 0.12fF -C2056 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF -C2057 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C2058 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF -C2059 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C2060 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C2061 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF -C2062 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.35fF -C2063 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/clk 0.60fF -C2064 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.22fF -C2065 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF -C2066 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF -C2067 ro_divider_buffered_0/tapered_buf_2/in4 ro_divider_buffered_0/tapered_buf_2/in5 29.21fF -C2068 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.19fF -C2069 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C2070 pll_full_buffered2_0/pll_full_0/cp_0/vbias pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# 0.19fF -C2071 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C2072 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in3 4.78fF -C2073 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in5 0.22fF -C2074 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF -C2075 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/div 0.17fF -C2076 gpio_noesd[8] gpio_analog[10] 0.48fF -C2077 io_analog[9] io_analog[10] 1065.06fF -C2078 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.33fF -C2079 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF -C2080 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C2081 div_pd_buffered_0/tapered_buf_0/in4 div_pd_buffered_0/tapered_buf_0/in5 29.21fF -C2082 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF -C2083 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C2084 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.22fF -C2085 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF -C2086 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF -C2087 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.35fF -C2088 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/clk 0.60fF -C2089 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF -C2090 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C2091 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C2092 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z2 1.07fF -C2093 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/divider_0/clk 0.05fF -C2094 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/nor_1/B 0.30fF -C2095 io_analog[1] ashish_0/b 4.11fF -C2096 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF -C2097 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/div 0.04fF -C2098 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/vco 0.29fF -C2099 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in2 0.84fF -C2100 ro_divider_buffered_0/tapered_buf_2/in4 ro_divider_buffered_0/tapered_buf_2/in3 4.78fF -C2101 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in5 0.22fF -C2102 io_analog[3] ro_complete_buffered_0/ro_complete_0/a4 0.17fF -C2103 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.08fF -C2104 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C2105 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C2106 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C2107 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.11fF -C2108 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C2109 io_analog[10] gpio_analog[10] 1.17fF -C2110 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C2111 pd_buffered_0/tapered_buf_1/in3 pd_buffered_0/tapered_buf_1/in2 1.27fF -C2112 divider_buffered_0/tapered_buf_1/in2 divider_buffered_0/tapered_buf_1/in5 0.84fF -C2113 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF -C2114 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C2115 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF -C2116 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in2 0.37fF -C2117 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z2 0.23fF -C2118 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C2119 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF -C2120 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF -C2121 io_analog[9] ro_divider_buffered_0/divider_0/Out 1.19fF -C2122 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF -C2123 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/div 0.04fF -C2124 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/vco 0.29fF -C2125 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in5 2.89fF -C2126 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C2127 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF -C2128 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C2129 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF -C2130 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.04fF -C2131 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C2132 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/vco 1.27fF -C2133 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.45fF -C2134 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in2 0.84fF -C2135 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 0.38fF -C2136 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C2137 ro_divider_buffered_0/tapered_buf_2/in2 ro_divider_buffered_0/tapered_buf_2/in3 1.27fF -C2138 io_analog[4] ro_complete_buffered_0/ro_complete_0/a1 0.32fF -C2139 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF -C2140 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF -C2141 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C2142 io_analog[4] io_analog[8] 1.24fF -C2143 io_analog[5] io_analog[7] 1.11fF -C2144 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF -C2145 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.06fF -C2146 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF -C2147 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C2148 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/B 0.01fF -C2149 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/clk 0.12fF -C2150 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C2151 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.04fF -C2152 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C2153 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/vco 1.27fF -C2154 io_analog[6] io_clamp_high[2] 0.53fF -C2155 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF -C2156 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C2157 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.11fF -C2158 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in5 2.89fF -C2159 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.47fF -C2160 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.16fF -C2161 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF -C2162 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in5 0.84fF -C2163 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in4 4.78fF -C2164 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C2165 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in5 2.89fF -C2166 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_0/Z2 0.21fF -C2167 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/R 0.29fF -C2168 div_pd_buffered_0/tapered_buf_4/in5 gpio_noesd[13] 26.29fF -C2169 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/divider_0/mc2 26.29fF -C2170 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a5 0.13fF -C2171 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in5 0.22fF -C2172 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/B 0.06fF -C2173 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/nor_1/A 0.21fF -C2174 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C2175 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_0/B 0.06fF -C2176 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered2_0/pll_full_0/div 0.04fF -C2177 gpio_analog[7] io_analog[10] 2.78fF -C2178 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C2179 cp_buffered_0/cp_0/upbar cp_buffered_0/cp_0/down 0.02fF -C2180 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C2181 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.47fF -C2182 div_pd_buffered_0/divider_0/tspc_0/Z2 div_pd_buffered_0/divider_0/tspc_0/Z3 0.16fF -C2183 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/clk 0.12fF -C2184 divider_buffered_0/tapered_buf_1/in5 gpio_noesd[4] 26.29fF -C2185 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C2186 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.00fF -C2187 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF -C2188 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 0.31fF -C2189 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.15fF -Xpll_full_buffered1_0 vssa1 vssa1 pll_full_buffered1 +C0 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C1 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.14fF +C5 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in4 4.78fF +C6 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in5 0.84fF +C7 pd_buffered_0/tapered_buf_0/in3 pd_buffered_0/tapered_buf_0/in4 4.78fF +C8 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in5 0.84fF +C9 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C10 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.01fF +C11 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF +C12 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.04fF +C13 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C14 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in2 0.37fF +C15 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C16 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C17 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF +C18 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF +C19 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a2 1.38fF +C20 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z2 0.30fF +C21 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Q 0.04fF +C22 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF +C23 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/nor_0/Z1 0.18fF +C24 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C25 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/R 0.21fF +C26 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_2/Z2 0.20fF +C27 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF +C28 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C29 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/R 0.03fF +C30 io_analog[6] ro_complete_buffered_0/ro_complete_0/a0 0.23fF +C31 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C32 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/upbar 0.29fF +C33 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.12fF +C34 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF +C35 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/clk 0.04fF +C36 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/DIV 0.17fF +C37 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered1_0/pll_full_0/vco 1.36fF +C38 gpio_noesd[7] io_analog[10] 5.73fF +C39 io_analog[4] ro_divider_buffered_0/ro_complete_0/a2 0.24fF +C40 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in5 0.22fF +C41 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in2 0.37fF +C42 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z2 0.01fF +C43 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C44 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_1/Z2 0.30fF +C45 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF +C46 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF +C47 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/divider_0/clk 26.29fF +C48 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/clk 0.26fF +C49 divider_buffered_0/tapered_buf_1/in3 divider_buffered_0/tapered_buf_1/in2 1.27fF +C50 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.30fF +C51 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/R 0.01fF +C52 gpio_noesd[14] gpio_noesd[10] 2.89fF +C53 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Z4 0.65fF +C54 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.04fF +C55 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF +C56 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/vco 0.05fF +C57 pll_full_buffered2_0/tapered_buf_3/in2 pll_full_buffered2_0/tapered_buf_3/in3 1.27fF +C58 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in2 0.37fF +C59 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF +C60 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF +C61 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C62 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.06fF +C63 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in2 0.37fF +C64 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/and_0/B 0.29fF +C65 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF +C66 ro_divider_buffered_0/tapered_buf_8/in4 ro_divider_buffered_0/tapered_buf_8/in5 29.21fF +C67 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/Z1 0.36fF +C68 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF +C69 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF +C70 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/UP 0.45fF +C71 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF +C72 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_2/in5 0.84fF +C73 divider_buffered_0/tapered_buf_2/in1 gpio_analog[4] 0.19fF +C74 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C75 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C76 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF +C77 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF +C78 ro_divider_buffered_0/tapered_buf_2/in4 ro_divider_buffered_0/tapered_buf_2/in5 29.21fF +C79 filter_buffered_0/tapered_buf_1/in1 gpio_analog[17] 0.19fF +C80 cp_buffered_0/tapered_buf_0/in4 cp_buffered_0/tapered_buf_0/in5 29.21fF +C81 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C82 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C83 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF +C84 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF +C85 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF +C86 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C87 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/a3 0.09fF +C88 ro_divider_buffered_0/divider_0/tspc_0/Q ro_divider_buffered_0/divider_0/nor_1/B 0.22fF +C89 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF +C90 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/div 0.25fF +C91 divider_buffered_0/divider_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/Out 0.11fF +C92 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in3 2.89fF +C93 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_1/in5 29.21fF +C94 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF +C95 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C96 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/a3 0.09fF +C97 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in2 1.27fF +C98 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C99 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/in3 2.89fF +C100 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF +C101 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/nor_1/A 0.15fF +C102 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF +C103 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.00fF +C104 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF +C105 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in4 4.78fF +C106 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C107 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z3 0.45fF +C108 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/A 0.26fF +C109 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF +C110 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C111 ro_divider_buffered_0/tapered_buf_2/in1 ro_divider_buffered_0/tapered_buf_2/in5 0.22fF +C112 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in3 1.27fF +C113 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C114 pll_full_buffered1_0/pll_full_0/vco io_analog[10] 0.56fF +C115 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in4 4.78fF +C116 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in5 0.84fF +C117 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.20fF +C118 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF +C119 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF +C120 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF +C121 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF +C122 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C123 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF +C124 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF +C125 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C126 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.09fF +C127 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 0.09fF +C128 io_analog[6] ro_complete_buffered_0/tapered_buf_4/in1 0.19fF +C129 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF +C130 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C131 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C132 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/B 0.31fF +C133 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C134 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF +C135 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF +C136 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C137 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/R 0.29fF +C138 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in4 4.78fF +C139 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in5 0.84fF +C140 io_analog[6] io_clamp_high[2] 0.53fF +C141 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered1_0/pll_full_0/vco 1.58fF +C142 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF +C143 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C144 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z3 0.16fF +C145 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.22fF +C146 io_analog[6] ro_divider_buffered_0/ro_complete_0/a0 0.21fF +C147 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z3 0.06fF +C148 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/Out 0.44fF +C149 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C150 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in3 1.27fF +C151 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C152 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C153 io_analog[9] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.53fF +C154 io_analog[10] pll_full_buffered2_0/tapered_buf_0/in1 0.19fF +C155 ro_divider_buffered_0/tapered_buf_4/in5 ro_divider_buffered_0/ro_complete_0/a4 26.29fF +C156 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 0.22fF +C157 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in5 29.21fF +C158 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C159 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF +C160 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C161 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF +C162 io_analog[4] ro_complete_buffered_0/ro_complete_0/a2 0.37fF +C163 pd_buffered_0/tapered_buf_1/in1 pd_buffered_0/tapered_buf_1/in2 0.37fF +C164 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF +C165 gpio_noesd[8] gpio_noesd[12] 0.46fF +C166 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/out1 0.06fF +C167 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Z4 0.21fF +C168 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z3 0.45fF +C169 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_0/B 0.22fF +C170 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C171 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF +C172 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C173 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/vco 0.15fF +C174 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF +C175 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in5 0.22fF +C176 ro_divider_buffered_0/tapered_buf_2/in2 ro_divider_buffered_0/tapered_buf_2/in1 0.37fF +C177 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in3 1.27fF +C178 div_pd_buffered_0/divider_0/and_0/A div_pd_buffered_0/divider_0/and_0/B 0.18fF +C179 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z4 0.00fF +C180 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C181 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C182 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF +C183 io_analog[7] io_analog[9] 1.28fF +C184 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/out1 0.31fF +C185 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.33fF +C186 gpio_analog[9] gpio_noesd[8] 1.10fF +C187 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C188 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C189 pd_buffered_0/tapered_buf_0/in4 pd_buffered_0/tapered_buf_0/in5 29.21fF +C190 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF +C191 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C192 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C193 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF +C194 gpio_analog[8] gpio_noesd[14] 2.77fF +C195 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C196 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF +C197 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF +C198 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/pll_full_0/vco 0.19fF +C199 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF +C200 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C201 gpio_analog[3] ashish_0/a 0.27fF +C202 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C203 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in1 0.22fF +C204 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.06fF +C205 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Q 0.51fF +C206 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C207 pll_full_buffered2_0/pll_full_0/cp_0/vbias pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# 0.19fF +C208 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C209 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C210 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C211 div_pd_buffered_0/pd_0/DOWN gpio_noesd[12] 0.33fF +C212 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in3 2.89fF +C213 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z2 0.11fF +C214 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF +C215 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C216 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/UP 0.03fF +C217 io_analog[6] gpio_analog[6] 0.64fF +C218 io_analog[7] ro_complete_buffered_0/ro_complete_0/a1 0.23fF +C219 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C220 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C221 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/clk 0.26fF +C222 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.22fF +C223 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF +C224 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF +C225 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF +C226 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in2 0.37fF +C227 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C228 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in5 2.89fF +C229 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.40fF +C230 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/Out 0.04fF +C231 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C232 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in3 1.27fF +C233 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_3/in5 29.21fF +C234 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z3 0.06fF +C235 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_1/Q 0.51fF +C236 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.11fF +C237 pll_full_buffered2_0/tapered_buf_2/in1 pll_full_buffered2_0/pll_full_0/div 0.19fF +C238 gpio_analog[6] ro_complete_buffered_0/tapered_buf_0/in1 0.19fF +C239 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C240 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF +C241 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C242 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/divider_0/mc2 0.34fF +C243 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in2 1.27fF +C244 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF +C245 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/R 0.21fF +C246 io_analog[3] ro_complete_buffered_0/tapered_buf_1/in1 0.19fF +C247 divider_buffered_0/tapered_buf_1/in3 divider_buffered_0/tapered_buf_1/in4 4.78fF +C248 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF +C249 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C250 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF +C251 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF +C252 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in3 1.27fF +C253 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C254 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C255 gpio_analog[4] gpio_noesd[4] 0.91fF +C256 gpio_noesd[11] gpio_noesd[7] 0.79fF +C257 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/and_0/B 0.78fF +C258 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF +C259 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/div 0.04fF +C260 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/vco 0.29fF +C261 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF +C262 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C263 io_analog[3] io_analog[5] 0.93fF +C264 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/and_0/OUT 0.14fF +C265 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/clk 0.51fF +C266 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.01fF +C267 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in3 1.27fF +C268 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C269 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.11fF +C270 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.01fF +C271 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF +C272 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C273 io_clamp_low[1] io_clamp_high[1] 0.53fF +C274 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF +C275 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z4 0.12fF +C276 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.13fF +C277 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C278 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.04fF +C279 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C280 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/vco 1.27fF +C281 gpio_noesd[8] io_analog[10] 3.39fF +C282 cp_buffered_0/tapered_buf_0/in5 cp_buffered_0/cp_0/down 26.29fF +C283 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/Z3 0.20fF +C284 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/REF 0.04fF +C285 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C286 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C287 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C288 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in2 0.37fF +C289 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF +C290 ro_divider_buffered_0/divider_0/tspc_0/Q ro_divider_buffered_0/divider_0/tspc_1/Z2 0.14fF +C291 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF +C292 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C293 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF +C294 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF +C295 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in5 0.22fF +C296 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF +C297 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF +C298 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/Out 0.15fF +C299 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF +C300 io_analog[7] ro_complete_buffered_0/tapered_buf_3/in1 0.19fF +C301 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_0/Z3 0.05fF +C302 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C303 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in4 4.78fF +C304 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 0.00fF +C305 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered2_0/pll_full_0/div 0.04fF +C306 gpio_noesd[13] gpio_noesd[12] 0.45fF +C307 io_analog[5] ro_complete_buffered_0/ro_complete_0/a0 0.23fF +C308 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/A 0.04fF +C309 cp_buffered_0/cp_0/a_10_n50# cp_buffered_0/cp_0/a_1710_0# 0.04fF +C310 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.18fF +C311 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF +C312 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF +C313 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/div 0.19fF +C314 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 0.38fF +C315 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z4 0.15fF +C316 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.47fF +C317 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in4 4.78fF +C318 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in5 0.84fF +C319 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.14fF +C320 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/vco 0.01fF +C321 gpio_noesd[4] divider_buffered_0/tapered_buf_1/in5 26.29fF +C322 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.00fF +C323 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C324 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF +C325 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/clk 0.45fF +C326 gpio_noesd[7] io_analog[9] 1.42fF +C327 io_analog[3] ro_divider_buffered_0/ro_complete_0/a2 0.24fF +C328 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_6/in5 29.21fF +C329 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/nor_0/B 0.22fF +C330 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C331 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF +C332 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF +C333 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C334 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/tapered_buf_3/in 0.03fF +C335 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C336 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/R 0.30fF +C337 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF +C338 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/UP 0.03fF +C339 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C340 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C341 pll_full_buffered1_0/tapered_buf_1/in4 pll_full_buffered1_0/tapered_buf_1/in5 29.21fF +C342 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in4 4.78fF +C343 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in5 0.84fF +C344 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C345 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z4 0.36fF +C346 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C347 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 0.31fF +C348 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.15fF +C349 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.04fF +C350 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in4 4.78fF +C351 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in5 0.84fF +C352 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/div 0.01fF +C353 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C354 io_analog[7] ro_divider_buffered_0/ro_complete_0/a1 0.33fF +C355 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z4 0.00fF +C356 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in4 29.21fF +C357 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/out1 0.06fF +C358 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 3.73fF +C359 io_analog[9] divider_buffered_0/tapered_buf_0/in1 0.19fF +C360 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in2 0.37fF +C361 ro_divider_buffered_0/tapered_buf_0/in5 gpio_noesd[5] 26.29fF +C362 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C363 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C364 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C365 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF +C366 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 0.16fF +C367 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C368 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C369 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z2 0.14fF +C370 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.35fF +C371 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C372 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in3 1.27fF +C373 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF +C374 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C375 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C376 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C377 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C378 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in5 0.84fF +C379 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.78fF +C380 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF +C381 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/clk 0.01fF +C382 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.29fF +C383 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C384 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/tspc_0/Z4 0.65fF +C385 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C386 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C387 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF +C388 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/pd_0/DOWN 0.19fF +C389 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/Out 0.08fF +C390 gpio_analog[3] gpio_noesd[4] 1.38fF +C391 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.35fF +C392 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.06fF +C393 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF +C394 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF +C395 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.05fF +C396 pd_buffered_0/tapered_buf_0/in5 gpio_noesd[11] 26.29fF +C397 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C398 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.02fF +C399 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C400 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/clk 0.45fF +C401 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF +C402 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF +C403 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C404 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C405 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF +C406 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_1/A 0.04fF +C407 io_analog[6] ro_divider_buffered_0/tapered_buf_6/in1 0.19fF +C408 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.00fF +C409 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_divider_buffered_0/divider_0/clk 1.36fF +C410 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.18fF +C411 div_pd_buffered_0/tapered_buf_2/in2 div_pd_buffered_0/tapered_buf_2/in3 1.27fF +C412 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF +C413 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF +C414 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/R 0.61fF +C415 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C416 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/A 0.01fF +C417 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in1 0.37fF +C418 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C419 io_analog[10] gpio_noesd[13] 1.85fF +C420 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF +C421 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF +C422 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF +C423 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF +C424 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.11fF +C425 io_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.31fF +C426 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF +C427 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C428 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in4 4.78fF +C429 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in5 0.84fF +C430 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 io_analog[2] 26.29fF +C431 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.06fF +C432 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/Out 0.42fF +C433 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.43fF +C434 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/OUT 0.05fF +C435 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in1 0.22fF +C436 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF +C437 io_analog[3] ro_complete_buffered_0/ro_complete_0/a2 0.22fF +C438 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C439 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/A 0.16fF +C440 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF +C441 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C442 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF +C443 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/and_0/OUT 0.14fF +C444 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_0/B 0.15fF +C445 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF +C446 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/div 0.27fF +C447 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C448 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in4 4.78fF +C449 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in5 0.84fF +C450 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF +C451 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.03fF +C452 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C453 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C454 io_analog[6] io_analog[9] 1.28fF +C455 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in3 1.27fF +C456 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C457 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF +C458 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_divider_buffered_0/divider_0/clk 1.30fF +C459 divider_buffered_0/divider_0/tspc_0/Z2 divider_buffered_0/divider_0/nor_1/A 0.23fF +C460 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in5 0.84fF +C461 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF +C462 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C463 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/UP 0.45fF +C464 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in4 29.21fF +C465 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF +C466 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF +C467 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C468 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C469 gpio_noesd[7] gpio_analog[10] 0.77fF +C470 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/clk 0.45fF +C471 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.51fF +C472 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF +C473 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C474 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C475 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C476 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/clk 0.12fF +C477 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C478 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF +C479 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C480 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C481 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF +C482 gpio_noesd[9] gpio_noesd[7] 3.28fF +C483 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C484 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C485 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in5 2.89fF +C486 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF +C487 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.05fF +C488 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in3 1.27fF +C489 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C490 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF +C491 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C492 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C493 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/divider_0/clk 1.30fF +C494 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/REF 0.04fF +C495 div_pd_buffered_0/tapered_buf_4/in4 div_pd_buffered_0/tapered_buf_4/in5 29.21fF +C496 gpio_analog[3] gpio_analog[6] 1.30fF +C497 gpio_noesd[11] gpio_noesd[8] 0.55fF +C498 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF +C499 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C500 io_analog[5] gpio_analog[6] 0.64fF +C501 io_analog[6] ro_complete_buffered_0/ro_complete_0/a1 0.22fF +C502 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF +C503 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF +C504 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C505 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/div 0.51fF +C506 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 4.79fF +C507 gpio_noesd[14] gpio_noesd[12] 2.57fF +C508 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF +C509 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/clk 0.45fF +C510 io_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.27fF +C511 divider_buffered_0/tapered_buf_1/in2 divider_buffered_0/tapered_buf_1/in5 0.84fF +C512 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C513 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/clk 0.12fF +C514 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C515 filter_buffered_0/tapered_buf_0/in4 filter_buffered_0/tapered_buf_0/in5 29.21fF +C516 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF +C517 gpio_analog[5] ro_divider_buffered_0/divider_0/Out 0.75fF +C518 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF +C519 ro_divider_buffered_0/tapered_buf_1/in1 ro_divider_buffered_0/tapered_buf_1/in2 0.37fF +C520 ro_divider_buffered_0/tapered_buf_1/in1 io_analog[9] 0.19fF +C521 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z2 0.14fF +C522 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C523 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF +C524 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_0/B 0.06fF +C525 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF +C526 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C527 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF +C528 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/DOWN 0.11fF +C529 io_analog[4] ro_complete_buffered_0/tapered_buf_6/in1 0.19fF +C530 io_analog[5] ro_complete_buffered_0/tapered_buf_5/in1 0.19fF +C531 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C532 gpio_analog[9] gpio_noesd[14] 2.63fF +C533 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C534 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C535 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF +C536 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C537 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 1.21fF +C538 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C539 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in3 1.27fF +C540 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C541 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C542 io_analog[3] io_analog[4] 0.88fF +C543 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/tspc_2/Z4 0.65fF +C544 ro_divider_buffered_0/tapered_buf_3/in4 ro_divider_buffered_0/tapered_buf_3/in5 29.21fF +C545 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/tspc_r_0/Z1 0.71fF +C546 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/A 0.16fF +C547 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in3 1.27fF +C548 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in1 0.22fF +C549 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 29.21fF +C550 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF +C551 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in5 0.22fF +C552 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF +C553 pll_full_buffered2_0/tapered_buf_5/in pll_full_buffered2_0/tapered_buf_5/in1 0.19fF +C554 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C555 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C556 pd_buffered_0/tapered_buf_1/in3 pd_buffered_0/tapered_buf_1/in4 4.78fF +C557 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in5 0.84fF +C558 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C559 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C560 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/Z1 0.04fF +C561 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.14fF +C562 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/vco 0.51fF +C563 gpio_noesd[8] io_analog[9] 0.91fF +C564 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF +C565 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.05fF +C566 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF +C567 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF +C568 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C569 div_pd_buffered_0/divider_0/and_0/B div_pd_buffered_0/divider_0/and_0/Z1 0.07fF +C570 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a3 3.17fF +C571 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C572 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF +C573 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in3 4.78fF +C574 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a3 3.17fF +C575 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C576 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 0.00fF +C577 io_analog[9] divider_buffered_0/divider_0/clk 0.40fF +C578 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/divider_0/Out 0.20fF +C579 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF +C580 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C581 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/div 0.12fF +C582 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/out 26.29fF +C583 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF +C584 io_analog[4] ro_complete_buffered_0/ro_complete_0/a0 0.33fF +C585 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C586 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z3 0.38fF +C587 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 div_pd_buffered_0/divider_0/clk 0.12fF +C588 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/A 0.80fF +C589 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.08fF +C590 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF +C591 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C592 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF +C593 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in5 0.22fF +C594 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF +C595 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C596 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C597 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.65fF +C598 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C599 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in2 0.37fF +C600 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/tapered_buf_3/in 0.02fF +C601 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.30fF +C602 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.19fF +C603 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C604 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/clk 0.14fF +C605 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF +C606 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF +C607 div_pd_buffered_0/tapered_buf_0/in4 div_pd_buffered_0/tapered_buf_0/in5 29.21fF +C608 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF +C609 io_analog[5] io_clamp_high[1] 0.53fF +C610 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in2 1.27fF +C611 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/out 0.61fF +C612 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF +C613 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.35fF +C614 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/clk 0.60fF +C615 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF +C616 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.31fF +C617 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C618 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF +C619 gpio_noesd[14] io_analog[10] 2.21fF +C620 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF +C621 io_analog[6] ro_divider_buffered_0/ro_complete_0/a1 0.20fF +C622 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in4 4.78fF +C623 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in5 0.84fF +C624 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C625 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C626 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_0/B 0.15fF +C627 io_analog[7] io_analog[8] 1.38fF +C628 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.00fF +C629 ro_divider_buffered_0/tapered_buf_7/in4 ro_divider_buffered_0/tapered_buf_7/in5 29.21fF +C630 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.08fF +C631 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C632 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF +C633 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF +C634 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C635 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.09fF +C636 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF +C637 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C638 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z2 0.23fF +C639 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C640 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF +C641 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in5 2.89fF +C642 cp_buffered_0/tapered_buf_1/in4 cp_buffered_0/tapered_buf_1/in5 29.21fF +C643 cp_buffered_0/cp_0/upbar cp_buffered_0/cp_0/down 0.02fF +C644 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.38fF +C645 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF +C646 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C647 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C648 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in5 0.22fF +C649 io_analog[10] div_pd_buffered_0/divider_0/mc2 0.64fF +C650 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C651 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF +C652 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF +C653 gpio_noesd[10] io_analog[10] 1.21fF +C654 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z3 0.45fF +C655 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z1 0.17fF +C656 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF +C657 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF +C658 gpio_noesd[5] gpio_analog[3] 0.96fF +C659 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in5 0.84fF +C660 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C661 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C662 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in2 0.84fF +C663 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 0.38fF +C664 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C665 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF +C666 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF +C667 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF +C668 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C669 io_clamp_low[0] io_clamp_high[0] 0.53fF +C670 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C671 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF +C672 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.06fF +C673 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C674 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C675 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF +C676 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF +C677 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C678 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.47fF +C679 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in4 29.21fF +C680 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C681 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered1_0/pll_full_0/vco 1.58fF +C682 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF +C683 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF +C684 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF +C685 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in4 4.78fF +C686 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in5 0.84fF +C687 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/clk 0.01fF +C688 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in5 2.89fF +C689 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/mc2 0.04fF +C690 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/tapered_buf_3/in 5.03fF +C691 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/R 0.29fF +C692 div_pd_buffered_0/tapered_buf_4/in5 gpio_noesd[13] 26.29fF +C693 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in3 1.27fF +C694 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF +C695 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/B 0.06fF +C696 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/nor_1/A 0.21fF +C697 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C698 pd_buffered_0/tapered_buf_3/in3 pd_buffered_0/tapered_buf_3/in4 4.78fF +C699 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in5 0.84fF +C700 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 3.73fF +C701 io_analog[9] gpio_noesd[13] 2.15fF +C702 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered2_0/pll_full_0/vco 1.36fF +C703 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/div 0.02fF +C704 div_pd_buffered_0/divider_0/tspc_0/Z2 div_pd_buffered_0/divider_0/tspc_0/Z3 0.16fF +C705 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/clk 0.12fF +C706 io_analog[4] ro_divider_buffered_0/ro_complete_0/a0 0.22fF +C707 gpio_analog[5] ro_divider_buffered_0/divider_0/mc2 0.49fF +C708 filter_buffered_0/tapered_buf_0/in5 gpio_analog[17] 26.29fF +C709 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF +C710 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C711 divider_buffered_0/tapered_buf_1/in4 divider_buffered_0/tapered_buf_1/in5 29.21fF +C712 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C713 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C714 io_analog[9] pll_full_buffered2_0/tapered_buf_1/in1 0.19fF +C715 div_pd_buffered_0/tapered_buf_3/in4 div_pd_buffered_0/tapered_buf_3/in5 29.21fF +C716 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C717 gpio_noesd[8] gpio_analog[10] 0.48fF +C718 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF +C719 ro_complete_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_2/in5 29.21fF +C720 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.04fF +C721 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/clk 0.64fF +C722 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF +C723 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF +C724 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C725 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.06fF +C726 gpio_noesd[9] gpio_noesd[8] 1.97fF +C727 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/B 0.18fF +C728 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF +C729 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C730 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF +C731 io_analog[0] gpio_analog[3] 3.87fF +C732 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF +C733 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/div 0.65fF +C734 io_analog[5] io_analog[9] 1.28fF +C735 ro_complete_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_2/in3 4.78fF +C736 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z1 0.01fF +C737 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in4 4.78fF +C738 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in5 0.84fF +C739 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.04fF +C740 pll_full_buffered2_0/tapered_buf_5/in1 pll_full_buffered2_0/tapered_buf_5/in2 0.37fF +C741 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.04fF +C742 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/Out 0.05fF +C743 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/UP 2.89fF +C744 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z4 0.00fF +C745 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.14fF +C746 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C747 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C748 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.29fF +C749 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C750 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C751 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF +C752 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF +C753 pd_buffered_0/tapered_buf_1/in4 pd_buffered_0/tapered_buf_1/in5 29.21fF +C754 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C755 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C756 div_pd_buffered_0/tapered_buf_0/in5 div_pd_buffered_0/tapered_buf_0/in1 0.22fF +C757 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z3 0.65fF +C758 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C759 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/B 0.20fF +C760 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.13fF +C761 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C762 filter_buffered_0/filter_0/v gpio_analog[17] 0.54fF +C763 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C764 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF +C765 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.01fF +C766 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C767 pll_full_buffered1_0/pll_full_0/div pll_full_buffered1_0/pll_full_0/vco 2.26fF +C768 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C769 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF +C770 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/Z1 0.04fF +C771 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C772 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/divider_0/clk 0.05fF +C773 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C774 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/REF 0.12fF +C775 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.65fF +C776 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF +C777 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C778 io_analog[4] gpio_analog[6] 0.64fF +C779 io_analog[5] ro_complete_buffered_0/ro_complete_0/a1 0.22fF +C780 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C781 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C782 cp_buffered_0/tapered_buf_2/in4 cp_buffered_0/tapered_buf_2/in5 29.21fF +C783 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF +C784 io_analog[4] ro_divider_buffered_0/ro_complete_0/a3 0.23fF +C785 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_3/in5 0.84fF +C786 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z2 0.19fF +C787 gpio_analog[3] io_analog[1] 1.96fF +C788 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.55fF +C789 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF +C790 gpio_analog[8] io_analog[10] 1.48fF +C791 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a4 0.13fF +C792 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in 0.19fF +C793 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in3 1.27fF +C794 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C795 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.09fF +C796 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF +C797 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.04fF +C798 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z2 0.36fF +C799 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C800 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_0/B 0.06fF +C801 divider_buffered_0/tapered_buf_0/in3 divider_buffered_0/tapered_buf_0/in5 2.89fF +C802 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered2_0/pll_full_0/vco 1.58fF +C803 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF +C804 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C805 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C806 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C807 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/Z1 0.04fF +C808 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z2 0.01fF +C809 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/clk 0.05fF +C810 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C811 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C812 gpio_analog[3] ashish_0/b 0.27fF +C813 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF +C814 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.22fF +C815 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/nor_1/A 0.03fF +C816 io_analog[4] ro_divider_buffered_0/ro_complete_0/a4 0.19fF +C817 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C818 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in5 29.21fF +C819 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.65fF +C820 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.32fF +C821 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C822 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF +C823 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF +C824 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF +C825 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF +C826 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF +C827 gpio_noesd[11] gpio_noesd[14] 2.58fF +C828 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C829 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/out1 0.31fF +C830 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF +C831 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in5 2.89fF +C832 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF +C833 cp_buffered_0/tapered_buf_1/in5 gpio_noesd[9] 26.29fF +C834 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C835 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.80fF +C836 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C837 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/B 0.18fF +C838 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z4 0.12fF +C839 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in4 4.78fF +C840 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/A 0.01fF +C841 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z3 0.05fF +C842 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z1 0.03fF +C843 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF +C844 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C845 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C846 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/divider_0/clk 1.30fF +C847 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in5 0.22fF +C848 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/DIV 0.65fF +C849 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF +C850 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF +C851 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF +C852 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 0.15fF +C853 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.33fF +C854 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF +C855 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.45fF +C856 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/UP 0.33fF +C857 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF +C858 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C859 io_analog[3] ro_complete_buffered_0/ro_complete_0/a0 0.20fF +C860 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF +C861 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF +C862 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF +C863 gpio_noesd[11] gpio_noesd[10] 6.19fF +C864 div_pd_buffered_0/tapered_buf_1/in4 div_pd_buffered_0/tapered_buf_1/in3 4.78fF +C865 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.00fF +C866 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_0/Q 0.14fF +C867 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF +C868 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/clk 0.01fF +C869 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C870 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF +C871 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.08fF +C872 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C873 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in4 4.78fF +C874 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF +C875 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C876 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_5/in5 29.21fF +C877 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.21fF +C878 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF +C879 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF +C880 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C881 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C882 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.36fF +C883 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z3 0.45fF +C884 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF +C885 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF +C886 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C887 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C888 divider_buffered_0/tapered_buf_0/in3 divider_buffered_0/tapered_buf_0/in4 4.78fF +C889 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z3 0.06fF +C890 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z4 0.65fF +C891 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z4 0.00fF +C892 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C893 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/clk 0.01fF +C894 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C895 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C896 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/cp_0/upbar 26.29fF +C897 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C898 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/UP 0.61fF +C899 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/pd_0/DOWN 0.19fF +C900 gpio_noesd[14] io_analog[9] 3.54fF +C901 io_analog[5] ro_divider_buffered_0/ro_complete_0/a1 0.30fF +C902 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C903 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C904 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C905 io_analog[6] io_analog[8] 1.24fF +C906 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in2 0.37fF +C907 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF +C908 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C909 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.01fF +C910 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF +C911 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF +C912 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/R 0.27fF +C913 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF +C914 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/UP 0.21fF +C915 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C916 div_pd_buffered_0/pd_0/UP div_pd_buffered_0/tapered_buf_0/in1 0.19fF +C917 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/nor_1/B 1.21fF +C918 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C919 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C920 filter_buffered_0/filter_0/v filter_buffered_0/filter_0/a_4216_n2998# 0.31fF +C921 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.01fF +C922 gpio_noesd[10] io_analog[9] 3.45fF +C923 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/DIV 0.51fF +C924 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/DOWN 0.03fF +C925 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/div 0.03fF +C926 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/vco 0.06fF +C927 pll_full_buffered2_0/tapered_buf_0/in4 pll_full_buffered2_0/tapered_buf_0/in5 29.21fF +C928 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in3 2.89fF +C929 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF +C930 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in5 0.22fF +C931 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C932 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z3 0.06fF +C933 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.16fF +C934 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.13fF +C935 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in3 1.27fF +C936 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/pd_0/UP 0.19fF +C937 io_analog[4] ro_complete_buffered_0/ro_complete_0/a4 0.20fF +C938 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C939 divider_buffered_0/tapered_buf_0/in2 divider_buffered_0/tapered_buf_0/in5 0.84fF +C940 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C941 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C942 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/UP 1.14fF +C943 gpio_analog[8] cp_buffered_0/cp_0/down 0.25fF +C944 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in5 0.22fF +C945 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/vco 0.64fF +C946 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C947 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a1 3.18fF +C948 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in5 2.89fF +C949 io_analog[5] ro_divider_buffered_0/tapered_buf_5/in1 0.19fF +C950 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/tapered_buf_3/in1 0.22fF +C951 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a1 3.18fF +C952 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF +C953 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C954 ro_complete_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_3/in4 4.78fF +C955 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.18fF +C956 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF +C957 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF +C958 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/div 0.19fF +C959 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF +C960 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C961 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C962 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF +C963 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.21fF +C964 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/B 0.08fF +C965 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/nor_0/B 0.22fF +C966 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF +C967 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/clk 0.01fF +C968 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.14fF +C969 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/vco 0.01fF +C970 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF +C971 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF +C972 io_analog[3] ro_divider_buffered_0/ro_complete_0/a0 0.22fF +C973 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.04fF +C974 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/B 0.08fF +C975 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in4 4.78fF +C976 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in5 0.84fF +C977 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_1/in5 26.29fF +C978 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/Out 0.05fF +C979 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF +C980 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF +C981 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Out1 0.05fF +C982 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C983 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF +C984 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/nor_0/B 0.42fF +C985 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF +C986 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.03fF +C987 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/A 0.35fF +C988 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C989 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C990 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF +C991 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.40fF +C992 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/clk 0.29fF +C993 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/div 0.01fF +C994 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C995 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF +C996 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.04fF +C997 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.26fF +C998 pll_full_buffered1_0/tapered_buf_1/in1 io_analog[10] 0.19fF +C999 io_analog[4] io_analog[9] 1.28fF +C1000 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z3 0.05fF +C1001 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z1 0.03fF +C1002 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C1003 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/Out 1.14fF +C1004 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/nor_1/A 0.55fF +C1005 gpio_analog[10] div_pd_buffered_0/tapered_buf_3/in1 0.19fF +C1006 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF +C1007 io_analog[10] pll_full_buffered2_0/pll_full_0/div 0.47fF +C1008 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z4 0.02fF +C1009 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C1010 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C1011 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C1012 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1013 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in4 4.78fF +C1014 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.78fF +C1015 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF +C1016 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF +C1017 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C1018 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Q 0.04fF +C1019 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF +C1020 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C1021 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C1022 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C1023 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/clk 0.11fF +C1024 pll_full_buffered1_0/tapered_buf_1/in5 pll_full_buffered1_0/pll_full_0/ref 26.29fF +C1025 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF +C1026 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C1027 ro_complete_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_2/in5 0.22fF +C1028 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF +C1029 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.03fF +C1030 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in5 2.89fF +C1031 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF +C1032 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF +C1033 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_4/in5 29.21fF +C1034 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF +C1035 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z2 1.07fF +C1036 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z3 0.38fF +C1037 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z4 0.12fF +C1038 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C1039 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_divider_buffered_0/divider_0/clk 1.43fF +C1040 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 4.79fF +C1041 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C1042 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C1043 gpio_noesd[14] gpio_analog[10] 2.60fF +C1044 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1045 io_analog[3] gpio_analog[6] 0.53fF +C1046 io_analog[4] ro_complete_buffered_0/ro_complete_0/a1 0.32fF +C1047 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.18fF +C1048 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C1049 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF +C1050 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.27fF +C1051 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF +C1052 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.05fF +C1053 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C1054 cp_buffered_0/tapered_buf_2/in1 cp_buffered_0/tapered_buf_2/in5 0.22fF +C1055 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in5 0.22fF +C1056 gpio_noesd[9] gpio_noesd[14] 2.58fF +C1057 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/nor_0/B 0.47fF +C1058 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z3 0.05fF +C1059 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF +C1060 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF +C1061 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF +C1062 io_analog[3] ro_divider_buffered_0/ro_complete_0/a3 0.23fF +C1063 ro_divider_buffered_0/tapered_buf_3/in5 ro_divider_buffered_0/ro_complete_0/a5 26.29fF +C1064 filter_buffered_0/tapered_buf_1/in4 filter_buffered_0/tapered_buf_1/in5 29.21fF +C1065 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF +C1066 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1067 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C1068 gpio_analog[8] io_analog[9] 1.10fF +C1069 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF +C1070 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z3 0.05fF +C1071 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z1 0.03fF +C1072 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C1073 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/tapered_buf_3/in 0.32fF +C1074 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C1075 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C1076 gpio_noesd[10] gpio_analog[10] 1.36fF +C1077 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF +C1078 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/R 0.21fF +C1079 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 gpio_noesd[14] 26.29fF +C1080 io_analog[4] io_clamp_high[0] 0.53fF +C1081 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/out1 0.31fF +C1082 div_pd_buffered_0/divider_0/tspc_1/Z4 div_pd_buffered_0/divider_0/tspc_0/Q 0.15fF +C1083 gpio_noesd[8] pll_full_buffered2_0/tapered_buf_3/in 0.23fF +C1084 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.45fF +C1085 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C1086 io_analog[10] gpio_noesd[12] 1.57fF +C1087 io_analog[3] ro_divider_buffered_0/ro_complete_0/a4 0.19fF +C1088 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in3 1.27fF +C1089 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C1090 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/B 0.31fF +C1091 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C1092 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF +C1093 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C1094 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C1095 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/R 0.36fF +C1096 div_pd_buffered_0/pd_0/tspc_r_1/Z1 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF +C1097 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF +C1098 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF +C1099 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C1100 gpio_analog[7] gpio_noesd[14] 2.55fF +C1101 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/out1 0.06fF +C1102 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF +C1103 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.03fF +C1104 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C1105 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C1106 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/R 0.27fF +C1107 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z4 0.36fF +C1108 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Q 0.05fF +C1109 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.35fF +C1110 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z2 0.01fF +C1111 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/and_0/B 0.78fF +C1112 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C1113 gpio_analog[9] io_analog[10] 1.15fF +C1114 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/and_0/B 0.29fF +C1115 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/vco 0.26fF +C1116 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in5 2.89fF +C1117 ro_divider_buffered_0/tapered_buf_6/in5 ro_divider_buffered_0/ro_complete_0/a2 26.29fF +C1118 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/tapered_buf_0/in2 0.37fF +C1119 ro_divider_buffered_0/divider_0/and_0/A ro_divider_buffered_0/divider_0/and_0/B 0.18fF +C1120 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/UP 0.45fF +C1121 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/UP 0.45fF +C1122 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C1123 gpio_analog[7] cp_buffered_0/tapered_buf_2/in1 0.19fF +C1124 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C1125 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1126 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF +C1127 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C1128 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C1129 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF +C1130 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF +C1131 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in1 0.22fF +C1132 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a1 1.84fF +C1133 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF +C1134 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.05fF +C1135 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in5 2.89fF +C1136 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in5 2.89fF +C1137 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF +C1138 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C1139 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_divider_buffered_0/divider_0/clk 1.30fF +C1140 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C1141 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in2 0.37fF +C1142 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_1/Z1 0.03fF +C1143 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF +C1144 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in5 2.89fF +C1145 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C1146 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/REF 0.19fF +C1147 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/in2 0.84fF +C1148 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF +C1149 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF +C1150 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF +C1151 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF +C1152 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C1153 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/div 0.51fF +C1154 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF +C1155 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF +C1156 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF +C1157 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z2 0.14fF +C1158 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF +C1159 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF +C1160 io_analog[4] ro_divider_buffered_0/ro_complete_0/a1 0.21fF +C1161 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C1162 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/tapered_buf_1/in5 26.29fF +C1163 io_analog[6] io_analog[7] 1.12fF +C1164 io_analog[5] io_analog[8] 1.24fF +C1165 ro_divider_buffered_0/tapered_buf_6/in4 ro_divider_buffered_0/tapered_buf_6/in5 29.21fF +C1166 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in5 0.22fF +C1167 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/ro_complete_0/a2 26.29fF +C1168 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C1169 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/in1 0.22fF +C1170 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF +C1171 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C1172 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C1173 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in1 0.37fF +C1174 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/nor_1/B 0.38fF +C1175 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1176 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C1177 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C1178 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_2/in1 0.37fF +C1179 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/A 0.26fF +C1180 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1181 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF +C1182 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/R 0.61fF +C1183 io_analog[6] io_clamp_low[2] 0.53fF +C1184 ro_divider_buffered_0/tapered_buf_2/in2 ro_divider_buffered_0/tapered_buf_2/in3 1.27fF +C1185 pd_buffered_0/tapered_buf_2/in4 pd_buffered_0/tapered_buf_2/in3 4.78fF +C1186 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF +C1187 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF +C1188 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1189 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in5 0.22fF +C1190 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z3 0.06fF +C1191 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z2 1.07fF +C1192 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z3 0.38fF +C1193 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z4 0.12fF +C1194 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C1195 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C1196 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF +C1197 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/ro_complete_0/a1 26.29fF +C1198 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/and_0/B 0.29fF +C1199 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C1200 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF +C1201 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C1202 io_analog[3] ro_complete_buffered_0/ro_complete_0/a4 0.17fF +C1203 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/tapered_buf_2/in2 0.37fF +C1204 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Q 0.51fF +C1205 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C1206 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C1207 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/clk 0.51fF +C1208 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C1209 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF +C1210 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.05fF +C1211 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/R 0.51fF +C1212 gpio_noesd[9] gpio_analog[8] 2.46fF +C1213 cp_buffered_0/cp_0/out cp_buffered_0/cp_0/down 0.79fF +C1214 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/Z2 0.14fF +C1215 io_analog[0] ashish_0/a 4.11fF +C1216 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF +C1217 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF +C1218 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/Z1 0.36fF +C1219 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.16fF +C1220 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z4 0.21fF +C1221 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C1222 ro_divider_buffered_0/tapered_buf_8/in5 ro_divider_buffered_0/ro_complete_0/a0 26.29fF +C1223 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF +C1224 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/div 0.05fF +C1225 io_analog[8] ro_complete_buffered_0/tapered_buf_2/in1 0.19fF +C1226 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/tapered_buf_1/in5 0.22fF +C1227 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF +C1228 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C1229 div_pd_buffered_0/pd_0/and_pd_0/Z1 div_pd_buffered_0/pd_0/UP 0.06fF +C1230 filter_buffered_0/filter_0/a_4216_n5230# filter_buffered_0/filter_0/v 0.19fF +C1231 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in5 2.89fF +C1232 pd_buffered_0/tapered_buf_0/in3 pd_buffered_0/tapered_buf_0/in5 2.89fF +C1233 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in4 29.21fF +C1234 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF +C1235 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C1236 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/R 0.36fF +C1237 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF +C1238 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.20fF +C1239 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.21fF +C1240 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C1241 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C1242 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in2 1.27fF +C1243 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z2 1.07fF +C1244 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z3 0.38fF +C1245 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z4 0.12fF +C1246 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C1247 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF +C1248 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C1249 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C1250 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a4 0.12fF +C1251 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C1252 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF +C1253 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/pd_0/REF 26.29fF +C1254 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/R 0.03fF +C1255 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C1256 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF +C1257 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in3 2.89fF +C1258 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF +C1259 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1260 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in5 0.22fF +C1261 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C1262 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF +C1263 ashish_0/a io_analog[1] 8.93fF +C1264 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF +C1265 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1266 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF +C1267 io_analog[3] io_analog[9] 1.00fF +C1268 ro_divider_buffered_0/divider_0/Out io_analog[9] 1.19fF +C1269 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in4 4.78fF +C1270 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in5 0.84fF +C1271 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z3 0.05fF +C1272 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z1 0.03fF +C1273 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/clk 0.04fF +C1274 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF +C1275 ro_complete_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_3/in5 2.89fF +C1276 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z2 1.07fF +C1277 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_1/Z3 0.38fF +C1278 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF +C1279 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF +C1280 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF +C1281 io_analog[9] pll_full_buffered2_0/pll_full_0/div 0.68fF +C1282 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1283 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF +C1284 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/UP 0.03fF +C1285 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.38fF +C1286 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF +C1287 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C1288 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C1289 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C1290 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/R 0.36fF +C1291 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF +C1292 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C1293 pll_full_buffered1_0/tapered_buf_0/in pll_full_buffered1_0/tapered_buf_0/in1 0.19fF +C1294 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF +C1295 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF +C1296 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C1297 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF +C1298 ashish_0/a ashish_0/b 7.45fF +C1299 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/clk 0.64fF +C1300 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C1301 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF +C1302 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF +C1303 io_analog[3] ro_complete_buffered_0/ro_complete_0/a1 0.17fF +C1304 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF +C1305 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C1306 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered2_0/pll_full_0/vco 1.58fF +C1307 cp_buffered_0/tapered_buf_2/in1 cp_buffered_0/tapered_buf_2/in2 0.37fF +C1308 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/R 0.03fF +C1309 div_pd_buffered_0/tapered_buf_0/in5 gpio_noesd[12] 26.29fF +C1310 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF +C1311 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C1312 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/REF 0.02fF +C1313 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/clk 0.11fF +C1314 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C1315 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in3 1.27fF +C1316 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a3 2.04fF +C1317 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z4 0.02fF +C1318 ro_divider_buffered_0/divider_0/tspc_0/Q ro_divider_buffered_0/divider_0/tspc_1/Z1 0.01fF +C1319 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF +C1320 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in3 2.89fF +C1321 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a3 2.04fF +C1322 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF +C1323 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C1324 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/clk 0.11fF +C1325 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/div 0.02fF +C1326 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/in4 29.21fF +C1327 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in2 0.84fF +C1328 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF +C1329 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF +C1330 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C1331 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/div 0.17fF +C1332 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF +C1333 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/B 0.31fF +C1334 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C1335 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF +C1336 pll_full_buffered2_0/tapered_buf_3/in5 pll_full_buffered2_0/tapered_buf_3/out 26.29fF +C1337 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in5 0.22fF +C1338 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF +C1339 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C1340 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C1341 io_analog[9] gpio_noesd[12] 1.79fF +C1342 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in5 2.89fF +C1343 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/a0 3.46fF +C1344 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C1345 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C1346 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF +C1347 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF +C1348 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z4 0.15fF +C1349 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_0/B 0.15fF +C1350 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF +C1351 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.12fF +C1352 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C1353 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.01fF +C1354 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF +C1355 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C1356 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in5 2.89fF +C1357 pll_full_buffered2_0/tapered_buf_5/in gpio_noesd[7] 0.54fF +C1358 pll_full_buffered2_0/tapered_buf_5/in1 pll_full_buffered2_0/tapered_buf_5/in5 0.22fF +C1359 pll_full_buffered2_0/tapered_buf_2/in1 pll_full_buffered2_0/tapered_buf_2/in2 0.37fF +C1360 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in4 4.78fF +C1361 gpio_analog[9] io_analog[9] 0.93fF +C1362 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z4 0.00fF +C1363 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in5 0.22fF +C1364 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF +C1365 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z3 0.16fF +C1366 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z4 0.22fF +C1367 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C1368 ro_divider_buffered_0/divider_0/Out ro_divider_buffered_0/tapered_buf_0/in1 0.19fF +C1369 io_analog[9] div_pd_buffered_0/tapered_buf_2/in1 0.19fF +C1370 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C1371 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.04fF +C1372 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 0.06fF +C1373 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C1374 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1375 divider_buffered_0/tapered_buf_1/in3 divider_buffered_0/tapered_buf_1/in5 2.89fF +C1376 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z1 0.01fF +C1377 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/B 0.01fF +C1378 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C1379 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF +C1380 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF +C1381 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C1382 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1383 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/clk 0.04fF +C1384 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C1385 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C1386 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in1 0.37fF +C1387 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a5 0.13fF +C1388 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C1389 pll_full_buffered2_0/pll_full_0/div pll_full_buffered2_0/pll_full_0/vco 2.26fF +C1390 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_0/in1 0.19fF +C1391 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in5 0.22fF +C1392 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C1393 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/vco 0.01fF +C1394 gpio_noesd[11] io_analog[10] 1.30fF +C1395 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/tspc_0/Z4 0.36fF +C1396 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.05fF +C1397 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C1398 divider_buffered_0/divider_0/and_0/A divider_buffered_0/divider_0/and_0/B 0.18fF +C1399 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1400 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/divider_0/clk 0.05fF +C1401 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/nor_1/B 1.21fF +C1402 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C1403 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/tspc_1/Z3 0.16fF +C1404 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C1405 divider_buffered_0/divider_0/mc2 divider_buffered_0/tapered_buf_0/in5 26.29fF +C1406 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1407 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF +C1408 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.55fF +C1409 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF +C1410 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A 0.15fF +C1411 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.09fF +C1412 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/clk 0.11fF +C1413 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF +C1414 io_analog[3] ro_divider_buffered_0/ro_complete_0/a1 0.19fF +C1415 gpio_analog[5] ro_divider_buffered_0/tapered_buf_2/in1 0.19fF +C1416 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C1417 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C1418 io_analog[5] io_analog[7] 1.11fF +C1419 io_analog[4] io_analog[8] 1.24fF +C1420 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in2 0.84fF +C1421 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.16fF +C1422 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z4 0.21fF +C1423 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.07fF +C1424 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C1425 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/mc2 0.06fF +C1426 divider_buffered_0/divider_0/tspc_0/Z2 divider_buffered_0/divider_0/tspc_0/Z1 1.07fF +C1427 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C1428 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/divider_0/clk 26.29fF +C1429 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1430 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_2/Z4 0.02fF +C1431 pd_buffered_0/tapered_buf_3/in4 pd_buffered_0/tapered_buf_3/in5 29.21fF +C1432 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z4 0.65fF +C1433 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C1434 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF +C1435 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.22fF +C1436 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/pd_0/DIV 26.29fF +C1437 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.03fF +C1438 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C1439 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF +C1440 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF +C1441 io_analog[9] io_analog[10] 1065.06fF +C1442 pll_full_buffered2_0/tapered_buf_1/in4 pll_full_buffered2_0/tapered_buf_1/in5 29.21fF +C1443 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z2 1.07fF +C1444 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z3 0.38fF +C1445 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z4 0.12fF +C1446 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in5 0.22fF +C1447 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in3 1.27fF +C1448 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/clk 0.26fF +C1449 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF +C1450 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF +C1451 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/tapered_buf_2/in5 0.22fF +C1452 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.13fF +C1453 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in2 0.37fF +C1454 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C1455 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.80fF +C1456 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1457 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF +C1458 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in2 0.84fF +C1459 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in2 0.37fF +C1460 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1461 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF +C1462 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF +C1463 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF +C1464 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C1465 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C1466 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in5 0.22fF +C1467 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C1468 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C1469 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C1470 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/nor_1/A 0.15fF +C1471 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/divider_0/clk 0.05fF +C1472 io_analog[4] ro_divider_buffered_0/tapered_buf_4/in1 0.19fF +C1473 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.35fF +C1474 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/vco 0.60fF +C1475 ro_complete_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_3/in2 1.27fF +C1476 ro_divider_buffered_0/tapered_buf_0/in2 ro_divider_buffered_0/tapered_buf_0/in3 1.27fF +C1477 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/and_0/Z1 0.07fF +C1478 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in5 0.22fF +C1479 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a4 0.12fF +C1480 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C1481 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z4 0.12fF +C1482 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF +C1483 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1484 divider_buffered_0/tapered_buf_2/in4 divider_buffered_0/tapered_buf_2/in3 4.78fF +C1485 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF +C1486 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in3 1.27fF +C1487 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1488 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/clk 0.11fF +C1489 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C1490 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF +C1491 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C1492 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_0/Z3 0.11fF +C1493 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in2 0.37fF +C1494 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.36fF +C1495 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF +C1496 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF +C1497 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF +C1498 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C1499 ro_divider_buffered_0/divider_0/tspc_0/Q ro_divider_buffered_0/divider_0/tspc_1/Z3 0.45fF +C1500 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C1501 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1502 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in4 4.78fF +C1503 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in5 0.84fF +C1504 pd_buffered_0/tapered_buf_3/in1 io_analog[10] 0.19fF +C1505 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF +C1506 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF +C1507 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C1508 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/divider_0/clk 0.05fF +C1509 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C1510 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in3 1.27fF +C1511 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1512 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/REF 0.02fF +C1513 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in5 2.89fF +C1514 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/tapered_buf_4/in1 0.19fF +C1515 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 0.36fF +C1516 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C1517 gpio_analog[9] gpio_noesd[9] 1.46fF +C1518 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/a_1710_0# 0.83fF +C1519 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in3 1.27fF +C1520 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C1521 gpio_noesd[7] gpio_noesd[13] 0.80fF +C1522 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C1523 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/clk 0.11fF +C1524 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C1525 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C1526 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1527 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in5 2.89fF +C1528 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.45fF +C1529 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/ro_complete_0/a0 26.29fF +C1530 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.02fF +C1531 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z1 0.01fF +C1532 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z2 0.15fF +C1533 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z3 0.05fF +C1534 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C1535 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/tapered_buf_3/in 0.11fF +C1536 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.10fF +C1537 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/a0 0.09fF +C1538 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C1539 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/DOWN 0.03fF +C1540 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/R 0.61fF +C1541 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/UP 0.11fF +C1542 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C1543 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C1544 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C1545 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.19fF +C1546 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in5 2.89fF +C1547 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF +C1548 div_pd_buffered_0/divider_0/tspc_2/Z3 div_pd_buffered_0/divider_0/tspc_2/Z4 0.65fF +C1549 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/div 0.03fF +C1550 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/vco 0.06fF +C1551 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in5 2.89fF +C1552 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF +C1553 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF +C1554 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z4 0.36fF +C1555 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/Out 0.05fF +C1556 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/ro_complete_0/a4 26.29fF +C1557 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/ro_complete_0/a3 26.29fF +C1558 io_analog[8] ro_divider_buffered_0/tapered_buf_8/in1 0.19fF +C1559 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/nor_1/Z1 0.06fF +C1560 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C1561 io_analog[3] ro_complete_buffered_0/ro_complete_0/a5 0.15fF +C1562 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C1563 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF +C1564 pd_buffered_0/tapered_buf_1/in1 pd_buffered_0/tapered_buf_1/in5 0.22fF +C1565 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in2 0.84fF +C1566 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C1567 pll_full_buffered1_0/pll_full_0/cp_0/vbias pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# 0.19fF +C1568 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1569 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C1570 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z3 0.45fF +C1571 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/vco 0.64fF +C1572 gpio_analog[8] cp_buffered_0/tapered_buf_0/in1 0.19fF +C1573 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF +C1574 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/a0 3.46fF +C1575 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF +C1576 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C1577 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C1578 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF +C1579 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/B 0.01fF +C1580 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF +C1581 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/Out 0.19fF +C1582 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in2 0.37fF +C1583 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Q 0.05fF +C1584 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF +C1585 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF +C1586 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C1587 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1588 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/div 0.65fF +C1589 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.06fF +C1590 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF +C1591 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C1592 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1593 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.11fF +C1594 io_analog[10] gpio_analog[10] 1.17fF +C1595 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF +C1596 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF +C1597 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C1598 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.14fF +C1599 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF +C1600 gpio_noesd[9] io_analog[10] 1.63fF +C1601 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C1602 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF +C1603 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.36fF +C1604 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Q 0.05fF +C1605 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1606 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF +C1607 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF +C1608 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z1 0.03fF +C1609 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.29fF +C1610 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C1611 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a4 0.09fF +C1612 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/B 0.08fF +C1613 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF +C1614 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C1615 io_analog[5] io_clamp_low[1] 0.53fF +C1616 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF +C1617 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C1618 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/B 0.01fF +C1619 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF +C1620 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.04fF +C1621 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.26fF +C1622 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C1623 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C1624 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in5 2.89fF +C1625 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in4 4.78fF +C1626 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.16fF +C1627 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.22fF +C1628 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.78fF +C1629 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C1630 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.27fF +C1631 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C1632 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/B 0.20fF +C1633 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF +C1634 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C1635 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C1636 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in3 1.27fF +C1637 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in5 2.89fF +C1638 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.30fF +C1639 gpio_analog[7] io_analog[10] 2.78fF +C1640 gpio_noesd[11] io_analog[9] 3.74fF +C1641 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF +C1642 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF +C1643 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z2 0.11fF +C1644 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in2 0.37fF +C1645 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.04fF +C1646 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF +C1647 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/vco 0.05fF +C1648 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in5 0.22fF +C1649 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/A 0.35fF +C1650 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C1651 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF +C1652 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF +C1653 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 0.06fF +C1654 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF +C1655 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.20fF +C1656 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C1657 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF +C1658 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1659 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C1660 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF +C1661 io_analog[3] ro_divider_buffered_0/ro_complete_0/a5 0.17fF +C1662 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.05fF +C1663 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF +C1664 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF +C1665 io_analog[3] io_analog[8] 1.02fF +C1666 io_analog[4] io_analog[7] 1.11fF +C1667 io_analog[5] io_analog[6] 21.00fF +C1668 ro_divider_buffered_0/tapered_buf_5/in4 ro_divider_buffered_0/tapered_buf_5/in5 29.21fF +C1669 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF +C1670 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in5 0.22fF +C1671 ro_divider_buffered_0/divider_0/tspc_0/Q ro_divider_buffered_0/divider_0/tspc_1/Z4 0.15fF +C1672 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C1673 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/mc2 0.33fF +C1674 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/and_0/OUT 0.06fF +C1675 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF +C1676 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in4 4.78fF +C1677 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in5 0.84fF +C1678 pll_full_buffered2_0/tapered_buf_4/in1 pll_full_buffered2_0/tapered_buf_4/in2 0.37fF +C1679 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 0.22fF +C1680 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C1681 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF +C1682 div_pd_buffered_0/tapered_buf_1/in2 div_pd_buffered_0/tapered_buf_1/in3 1.27fF +C1683 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C1684 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF +C1685 gpio_noesd[14] gpio_noesd[7] 2.93fF +C1686 gpio_noesd[10] pd_buffered_0/pd_0/DOWN 0.54fF +C1687 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.00fF +C1688 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF +C1689 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C1690 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z3 0.45fF +C1691 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF +C1692 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF +C1693 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF +C1694 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C1695 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF +C1696 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF +C1697 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C1698 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.09fF +C1699 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 0.09fF +C1700 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF +C1701 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C1702 io_analog[8] ro_complete_buffered_0/ro_complete_0/a0 0.23fF +C1703 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/A 0.80fF +C1704 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/vco 0.26fF +C1705 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C1706 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in2 0.37fF +C1707 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF +C1708 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF +C1709 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1710 gpio_noesd[10] gpio_noesd[7] 0.73fF +C1711 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C1712 io_analog[6] ro_divider_buffered_0/ro_complete_0/a2 0.24fF +C1713 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/nor_1/B 0.22fF +C1714 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in5 0.22fF +C1715 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/B 0.20fF +C1716 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in2 0.37fF +C1717 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C1718 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/UP 0.61fF +C1719 gpio_noesd[8] gpio_noesd[13] 0.55fF +C1720 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_1/Z4 0.21fF +C1721 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C1722 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1723 pd_buffered_0/tapered_buf_1/in3 pd_buffered_0/tapered_buf_1/in5 2.89fF +C1724 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF +C1725 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/R 0.61fF +C1726 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z4 0.15fF +C1727 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF +C1728 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C1729 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C1730 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/A 0.16fF +C1731 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C1732 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/pd_0/REF 26.29fF +C1733 gpio_noesd[9] cp_buffered_0/cp_0/down 0.38fF +C1734 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/a0 0.09fF +C1735 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in2 0.37fF +C1736 io_analog[0] io_analog[1] 8.34fF +C1737 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF +C1738 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C1739 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/vco 0.15fF +C1740 divider_buffered_0/divider_0/and_0/B divider_buffered_0/divider_0/and_0/Z1 0.07fF +C1741 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.15fF +C1742 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/B 0.01fF +C1743 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C1744 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C1745 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in2 0.84fF +C1746 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF +C1747 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.22fF +C1748 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.36fF +C1749 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/REF 0.65fF +C1750 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z4 0.12fF +C1751 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/div 4.07fF +C1752 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF +C1753 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF +C1754 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in3 2.89fF +C1755 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C1756 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/B 0.18fF +C1757 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C1758 gpio_noesd[14] pll_full_buffered1_0/pll_full_0/vco 0.69fF +C1759 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Q 0.55fF +C1760 pll_full_buffered2_0/tapered_buf_3/in2 pll_full_buffered2_0/tapered_buf_3/in5 0.84fF +C1761 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF +C1762 io_analog[0] ashish_0/b 8.93fF +C1763 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF +C1764 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF +C1765 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C1766 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C1767 gpio_noesd[11] gpio_analog[10] 0.49fF +C1768 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/A 0.15fF +C1769 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF +C1770 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF +C1771 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1772 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/out 0.84fF +C1773 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF +C1774 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C1775 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF +C1776 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in5 2.89fF +C1777 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.35fF +C1778 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/clk 0.60fF +C1779 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C1780 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C1781 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.22fF +C1782 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF +C1783 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF +C1784 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.36fF +C1785 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/Out 0.05fF +C1786 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/clk 0.60fF +C1787 gpio_analog[3] gpio_analog[4] 1.29fF +C1788 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF +C1789 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.21fF +C1790 divider_buffered_0/tapered_buf_0/in3 divider_buffered_0/tapered_buf_0/in2 1.27fF +C1791 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z3 0.45fF +C1792 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1793 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF +C1794 pll_full_buffered2_0/tapered_buf_3/in4 pll_full_buffered2_0/tapered_buf_3/in5 29.21fF +C1795 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF +C1796 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C1797 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF +C1798 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in4 4.78fF +C1799 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in5 0.84fF +C1800 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C1801 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF +C1802 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/div 0.05fF +C1803 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/A 0.01fF +C1804 div_pd_buffered_0/divider_0/tspc_0/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.05fF +C1805 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF +C1806 io_analog[8] ro_divider_buffered_0/ro_complete_0/a0 0.22fF +C1807 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z2 0.01fF +C1808 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/divider_0/clk 0.05fF +C1809 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a5 0.09fF +C1810 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in3 1.27fF +C1811 io_analog[1] ashish_0/b 4.11fF +C1812 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF +C1813 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/div 0.04fF +C1814 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/vco 0.29fF +C1815 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C1816 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a4 0.09fF +C1817 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a5 0.09fF +C1818 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.04fF +C1819 pll_full_buffered2_0/tapered_buf_0/in5 pll_full_buffered2_0/pll_full_0/ref 26.29fF +C1820 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.05fF +C1821 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF +C1822 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF +C1823 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C1824 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/R 0.21fF +C1825 io_analog[6] ro_complete_buffered_0/ro_complete_0/a2 0.25fF +C1826 pll_full_buffered2_0/tapered_buf_2/in5 gpio_noesd[8] 26.29fF +C1827 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in2 0.37fF +C1828 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF +C1829 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF +C1830 io_analog[9] gpio_analog[10] 3.28fF +C1831 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF +C1832 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/clk 0.12fF +C1833 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C1834 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.04fF +C1835 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C1836 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/vco 1.27fF +C1837 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF +C1838 gpio_analog[8] gpio_noesd[7] 1.68fF +C1839 gpio_noesd[9] io_analog[9] 1.19fF +C1840 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C1841 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.01fF +C1842 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF +C1843 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/nor_1/A 0.01fF +C1844 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in1 0.37fF +C1845 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in5 2.89fF +C1846 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/B 0.35fF +C1847 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF +C1848 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/in5 29.21fF +C1849 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_1/in5 0.22fF +C1850 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z2 0.14fF +C1851 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/DOWN 0.02fF +C1852 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/R 0.30fF +C1853 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/tspc_1/Z4 0.36fF +C1854 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1855 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in3 1.27fF +C1856 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z2 1.07fF +C1857 pd_buffered_0/tapered_buf_3/in3 pd_buffered_0/tapered_buf_3/in5 2.89fF +C1858 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered1_0/pll_full_0/div 0.04fF +C1859 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 29.21fF +C1860 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF +C1861 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1862 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF +C1863 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.47fF +C1864 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF +C1865 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z4 0.15fF +C1866 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF +C1867 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/A 0.80fF +C1868 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C1869 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF +C1870 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.27fF +C1871 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF +C1872 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.05fF +C1873 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C1874 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/R 0.51fF +C1875 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/clk 0.51fF +C1876 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C1877 div_pd_buffered_0/tapered_buf_1/in1 div_pd_buffered_0/tapered_buf_1/in2 0.37fF +C1878 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/UP 0.21fF +C1879 io_analog[8] gpio_analog[6] 0.64fF +C1880 gpio_analog[7] io_analog[9] 1.40fF +C1881 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C1882 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF +C1883 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 0.31fF +C1884 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.15fF +C1885 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/div 0.12fF +C1886 io_analog[10] div_pd_buffered_0/divider_0/clk 0.61fF +C1887 ro_divider_buffered_0/tapered_buf_7/in5 ro_divider_buffered_0/ro_complete_0/a1 26.29fF +C1888 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in5 2.89fF +C1889 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in3 4.78fF +C1890 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in2 0.84fF +C1891 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/A 0.01fF +C1892 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in3 1.27fF +C1893 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/divider_0/mc2 26.29fF +C1894 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C1895 divider_buffered_0/divider_0/tspc_0/Z2 divider_buffered_0/divider_0/tspc_0/Z4 0.36fF +C1896 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/div 0.45fF +C1897 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C1898 gpio_noesd[14] gpio_noesd[8] 2.61fF +C1899 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/clk 0.12fF +C1900 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C1901 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.30fF +C1902 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/clk 0.14fF +C1903 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in3 1.27fF +C1904 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.35fF +C1905 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C1906 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C1907 io_analog[3] io_analog[7] 0.92fF +C1908 io_analog[4] io_analog[6] 1.25fF +C1909 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.29fF +C1910 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a5 2.39fF +C1911 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in4 4.78fF +C1912 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C1913 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.14fF +C1914 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/nor_1/B 1.21fF +C1915 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C1916 io_analog[10] pll_full_buffered2_0/tapered_buf_3/in 0.42fF +C1917 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a5 2.39fF +C1918 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C1919 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/divider_0/clk 1.30fF +C1920 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/div 0.17fF +C1921 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF +C1922 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/nor_1/A 0.03fF +C1923 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C1924 gpio_noesd[10] gpio_noesd[8] 0.51fF +C1925 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C1926 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF +C1927 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C1928 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.06fF +C1929 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF +C1930 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/A 0.01fF +C1931 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF +C1932 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.05fF +C1933 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF +C1934 pll_full_buffered2_0/tapered_buf_5/in4 pll_full_buffered2_0/tapered_buf_5/in5 29.21fF +C1935 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in5 0.22fF +C1936 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in2 0.37fF +C1937 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.00fF +C1938 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/A 0.01fF +C1939 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in1 0.37fF +C1940 divider_buffered_0/divider_0/tspc_0/Z2 divider_buffered_0/divider_0/tspc_0/Z3 0.16fF +C1941 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.12fF +C1942 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C1943 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C1944 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/and_pd_0/Out1 0.05fF +C1945 io_analog[7] ro_complete_buffered_0/ro_complete_0/a0 0.23fF +C1946 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/nor_1/A 0.01fF +C1947 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF +C1948 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1949 pll_full_buffered2_0/tapered_buf_2/in1 pll_full_buffered2_0/tapered_buf_2/in5 0.22fF +C1950 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in2 0.37fF +C1951 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF +C1952 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1953 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF +C1954 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z1 0.03fF +C1955 io_analog[3] ro_divider_buffered_0/tapered_buf_3/in1 0.19fF +C1956 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/vco 0.55fF +C1957 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF +C1958 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF +C1959 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF +C1960 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF +C1961 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z2 0.01fF +C1962 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/clk 0.05fF +C1963 io_analog[5] ro_divider_buffered_0/ro_complete_0/a2 0.35fF +C1964 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C1965 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/clk 0.05fF +C1966 div_pd_buffered_0/pd_0/tspc_r_1/Z4 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF +C1967 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C1968 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1969 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/clk 0.04fF +C1970 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C1971 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C1972 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/vco 0.01fF +C1973 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/UP 0.03fF +C1974 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_1/Z4 0.02fF +C1975 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z3 0.06fF +C1976 pll_full_buffered1_0/tapered_buf_0/in4 pll_full_buffered1_0/tapered_buf_0/in5 29.21fF +C1977 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in4 4.78fF +C1978 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_1/in5 26.29fF +C1979 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF +C1980 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C1981 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z2 0.01fF +C1982 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z2 0.23fF +C1983 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.04fF +C1984 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in4 4.78fF +C1985 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in5 0.84fF +C1986 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/DIV 0.12fF +C1987 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF +C1988 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/div 0.27fF +C1989 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in5 2.89fF +C1990 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/B 0.18fF +C1991 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.36fF +C1992 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.09fF +C1993 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in5 2.89fF +C1994 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C1995 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/UP 0.33fF +C1996 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A 0.15fF +C1997 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.09fF +C1998 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF +C1999 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C2000 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C2001 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in3 1.27fF +C2002 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C2003 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.45fF +C2004 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C2005 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF +C2006 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.07fF +C2007 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF +C2008 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in5 2.89fF +C2009 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.51fF +C2010 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF +C2011 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C2012 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C2013 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z2 0.01fF +C2014 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C2015 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF +C2016 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in1 0.22fF +C2017 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C2018 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in4 4.78fF +C2019 gpio_noesd[14] gpio_noesd[13] 2.55fF +C2020 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in5 0.84fF +C2021 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF +C2022 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z3 0.16fF +C2023 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z2 1.07fF +C2024 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF +C2025 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/nor_0/B 0.47fF +C2026 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF +C2027 gpio_noesd[10] pd_buffered_0/tapered_buf_2/in5 26.29fF +C2028 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF +C2029 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C2030 io_analog[4] io_clamp_low[0] 0.53fF +C2031 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF +C2032 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF +C2033 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z3 0.65fF +C2034 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF +C2035 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C2036 ro_divider_buffered_0/tapered_buf_5/in5 ro_divider_buffered_0/ro_complete_0/a3 26.29fF +C2037 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/DOWN 0.02fF +C2038 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF +C2039 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.35fF +C2040 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/A 0.26fF +C2041 io_analog[7] ro_divider_buffered_0/tapered_buf_7/in1 0.19fF +C2042 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C2043 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/R 0.36fF +C2044 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF +C2045 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF +C2046 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF +C2047 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/R 0.01fF +C2048 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF +C2049 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF +C2050 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.13fF +C2051 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z4 0.00fF +C2052 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C2053 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C2054 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C2055 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C2056 cp_buffered_0/cp_0/out cp_buffered_0/tapered_buf_1/in1 0.19fF +C2057 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/down 0.32fF +C2058 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C2059 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 1.21fF +C2060 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.35fF +C2061 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/vco 0.60fF +C2062 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/Out 0.05fF +C2063 io_analog[7] ro_divider_buffered_0/ro_complete_0/a0 0.33fF +C2064 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF +C2065 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C2066 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/divider_0/clk 0.10fF +C2067 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/DOWN 0.11fF +C2068 io_analog[10] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.36fF +C2069 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in4 4.78fF +C2070 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in5 0.84fF +C2071 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF +C2072 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C2073 io_clamp_low[2] io_clamp_high[2] 0.53fF +C2074 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z4 0.00fF +C2075 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/tapered_buf_1/in2 0.37fF +C2076 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z4 0.21fF +C2077 io_analog[5] ro_complete_buffered_0/ro_complete_0/a2 0.25fF +C2078 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF +C2079 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF +C2080 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF +C2081 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C2082 ro_divider_buffered_0/tapered_buf_2/in2 ro_divider_buffered_0/tapered_buf_2/in5 0.84fF +C2083 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in4 4.78fF +C2084 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in5 0.84fF +C2085 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.14fF +C2086 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/vco 0.51fF +C2087 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C2088 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF +C2089 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in5 29.21fF +C2090 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z2 0.15fF +C2091 ro_divider_buffered_0/divider_0/tspc_0/Q ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF +C2092 io_analog[8] io_analog[9] 1.33fF +C2093 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF +C2094 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF +C2095 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF +C2096 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in5 0.84fF +C2097 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/REF 0.17fF +C2098 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/in1 0.22fF +C2099 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF +C2100 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C2101 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C2102 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in3 1.27fF +C2103 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C2104 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.32fF +C2105 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z1 0.01fF +C2106 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_0/Q 0.22fF +C2107 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.45fF +C2108 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in2 0.37fF +C2109 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z3 0.09fF +C2110 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.08fF +C2111 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF +C2112 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C2113 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF +C2114 gpio_noesd[7] gpio_noesd[12] 0.68fF +C2115 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF +C2116 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C2117 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in3 1.27fF +C2118 pll_full_buffered2_0/tapered_buf_5/in5 gpio_noesd[7] 26.29fF +C2119 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/nor_0/B 0.47fF +C2120 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF +C2121 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.01fF +C2122 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C2123 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in5 2.89fF +C2124 pd_buffered_0/pd_0/DIV io_analog[10] 0.52fF +C2125 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/R 0.03fF +C2126 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C2127 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z3 0.38fF +C2128 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C2129 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/B 0.30fF +C2130 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in5 2.89fF +C2131 divider_buffered_0/tapered_buf_0/in4 divider_buffered_0/tapered_buf_0/in5 29.21fF +C2132 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C2133 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF +C2134 io_analog[7] gpio_analog[6] 0.64fF +C2135 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF +C2136 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in3 1.27fF +C2137 gpio_analog[9] gpio_noesd[7] 1.96fF +C2138 gpio_analog[5] gpio_analog[3] 1.06fF +C2139 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z2 1.07fF +C2140 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z3 0.38fF +C2141 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z4 0.12fF +C2142 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_0/B 0.06fF +C2143 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF +C2144 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF +C2145 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in2 0.37fF +C2146 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.31fF +C2147 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C2148 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF +C2149 io_analog[9] div_pd_buffered_0/divider_0/clk 0.65fF +C2150 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z2 0.40fF +C2151 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/Out 0.04fF +C2152 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/clk 0.29fF +C2153 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C2154 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in1 0.37fF +C2155 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/clk 0.29fF +C2156 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF +C2157 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C2158 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF +C2159 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C2160 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C2161 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/UP 0.11fF +C2162 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF +C2163 gpio_analog[9] pd_buffered_0/tapered_buf_1/in1 0.19fF +C2164 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF +C2165 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C2166 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.09fF +C2167 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Z4 0.12fF +C2168 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C2169 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/clk 0.64fF +C2170 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF +C2171 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/clk 0.26fF +C2172 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF +C2173 io_analog[10] div_pd_buffered_0/tapered_buf_1/in1 0.19fF +C2174 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/Z1 0.36fF +C2175 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.12fF +C2176 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF +C2177 io_analog[4] io_analog[5] 20.14fF +C2178 io_analog[3] io_analog[6] 1.03fF +C2179 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/A 0.35fF +C2180 ro_divider_buffered_0/tapered_buf_4/in4 ro_divider_buffered_0/tapered_buf_4/in5 29.21fF +C2181 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF +C2182 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.06fF +C2183 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Q 0.55fF +C2184 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C2185 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/divider_0/clk 1.27fF +C2186 io_analog[9] pll_full_buffered2_0/tapered_buf_3/in 0.61fF +C2187 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.06fF +C2188 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.14fF +C2189 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/UP 0.06fF +Xpll_full_buffered1_0 vssa1 vdda1 pll_full_buffered1 Xashish_0 io_analog[1] io_analog[0] gpio_analog[3] vssa1 vdd ashish_0/a ashish_0/b + ashish Xpd_buffered_0 vssa1 vssa1 pd_buffered -Xcp_buffered_0 vssa1 vssa1 cp_buffered +Xcp_buffered_0 vssa1 vdda1 cp_buffered Xfilter_buffered_0 vssa1 gpio_analog[17] filter_buffered Xro_divider_buffered_0 vssa1 vssa1 ro_divider_buffered Xpll_full_buffered2_0 vssa1 vssa1 pll_full_buffered2