fixed drc errors
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds index 283c64c..e629dc3 100644 --- a/gds/user_analog_project_wrapper.gds +++ b/gds/user_analog_project_wrapper.gds Binary files differ
diff --git a/mag/pll_full.mag b/mag/pll_full.mag index 3b2019e..c1a00c0 100644 --- a/mag/pll_full.mag +++ b/mag/pll_full.mag
@@ -1,6 +1,6 @@ magic tech sky130A -timestamp 1643048290 +timestamp 1643054004 << nwell >> rect -3185 7805 -3090 9815 rect -3290 7585 -2985 7805 @@ -16,20 +16,22 @@ rect 3136 10783 3360 11282 rect 4565 10810 4789 11309 rect 6163 10788 6387 11287 -rect 7803 9114 8347 9515 +rect 8310 9515 8778 9518 +rect 7803 9114 8778 9515 +rect 8310 9112 8778 9114 rect -3205 7755 -3070 7765 rect -3205 7645 -3195 7755 rect -3080 7645 -3070 7755 rect -3205 7640 -3070 7645 -rect 7885 6690 8734 6954 +rect 7885 6690 8744 6954 rect -5053 5917 -4915 6349 rect -4015 5926 -3823 6332 -rect 7861 4862 8710 5126 +rect 7861 4862 8720 5126 rect -4902 4072 -4702 4384 rect -4254 4037 -3882 4394 rect -331 3685 129 3956 rect -378 2878 294 3207 -rect 7909 3059 8758 3323 +rect 7919 3059 8768 3323 rect -331 2025 129 2296 rect 535 -1232 958 -444 rect 1849 -1174 2272 -386 @@ -51,8 +53,9 @@ rect -4980 12330 -4975 12360 rect -4945 12330 -4940 12360 rect -4980 12325 -4940 12330 -rect 380 9245 4010 9380 -rect 4015 9245 8130 9370 +rect 3986 9380 4062 9382 +rect 380 9370 4062 9380 +rect 380 9245 8140 9370 rect -4815 7770 -4775 7775 rect -4815 7740 -4810 7770 rect -4780 7740 -4775 7770 @@ -62,9 +65,11 @@ rect -3080 7645 -3070 7755 rect -3205 7640 -3070 7645 rect 380 7630 460 9245 -rect 8055 8900 8130 9245 -rect 8055 8810 8565 8900 -rect 8055 8805 8130 8810 +rect 8065 8900 8140 9245 +rect 8065 8899 8575 8900 +rect 8065 8810 9181 8899 +rect 8065 8805 8140 8810 +rect 8526 8805 9181 8810 rect -595 7510 465 7630 rect 380 7505 460 7510 rect -4815 7420 -4775 7425 @@ -167,8 +172,8 @@ rect -3325 5360 -3270 5370 rect -5250 4720 -4960 4740 rect -5250 -2095 -5200 4720 -rect 12130 4220 12260 4935 -rect -5160 4185 12260 4220 +rect 12610 4220 12740 4935 +rect -5160 4185 12740 4220 rect -5160 2435 -5140 4185 rect -4675 3800 -4625 3810 rect -4675 3770 -4665 3800 @@ -259,34 +264,34 @@ rect -4630 3765 -4625 3805 rect -4675 3760 -4625 3765 rect -5791 3090 -4643 3260 -use divider divider_0 -timestamp 1643048290 -transform 1 0 -4910 0 1 1985 -box -490 -235 4690 2150 -use cp cp_0 -timestamp 1640911461 -transform 1 0 -4895 0 1 7840 -box -415 -1715 4690 2035 +use ro_complete ro_complete_0 +timestamp 1643054004 +transform 1 0 8617 0 1 8475 +box -348 -5690 4661 1440 +use filter filter_0 +timestamp 1643054004 +transform 1 0 1810 0 1 10450 +box -1800 -11005 6240 390 use pd pd_0 -timestamp 1643048290 +timestamp 1643054004 transform 1 0 -4845 0 1 5180 box -215 -855 1685 810 -use ro_complete ro_complete_0 -timestamp 1643048290 -transform 1 0 8137 0 1 8475 -box -57 -5330 4455 1440 -use filter filter_0 -timestamp 1640983258 -transform 1 0 1800 0 1 10450 -box -1800 -11005 6240 390 -use divbuf divbuf_1 -timestamp 1641017053 -transform 1 0 -4770 0 1 12340 -box -460 -1085 31200 495 +use divider divider_0 +timestamp 1643054004 +transform 1 0 -4910 0 1 1985 +box -490 -235 4690 2150 use divbuf divbuf_0 timestamp 1641017053 transform 1 0 -4955 0 1 -1605 box -460 -1085 31200 495 +use divbuf divbuf_1 +timestamp 1641017053 +transform 1 0 -4770 0 1 12340 +box -460 -1085 31200 495 +use cp cp_0 +timestamp 1640911461 +transform 1 0 -4895 0 1 7840 +box -415 -1715 4690 2035 << labels >> rlabel locali -3140 7755 -3140 7755 1 vdd! << end >>
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag index d9070e5..9ff137f 100644 --- a/mag/user_analog_project_wrapper.mag +++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,21 @@ magic tech sky130A -timestamp 1643052028 +timestamp 1643054636 +<< nwell >> +rect 26424 264625 26589 264812 +rect 23497 264291 23832 264611 +<< nsubdiff >> +rect 26431 264775 26576 264790 +rect 26431 264665 26446 264775 +rect 26561 264665 26576 264775 +rect 26431 264655 26576 264665 +rect 23581 264447 23730 264462 +rect 23581 264330 23597 264447 +rect 23716 264330 23730 264447 +rect 23581 264315 23730 264330 +<< nsubdiffcont >> +rect 26446 264665 26561 264775 +rect 23597 264330 23716 264447 << locali >> rect 247445 329554 247576 329570 rect 247445 329454 247459 329554 @@ -39,6 +54,14 @@ rect 266009 265202 266024 265300 rect 266126 265202 266147 265300 rect 266009 265179 266147 265202 +rect 26436 264775 26571 264785 +rect 26436 264665 26446 264775 +rect 26561 264665 26571 264775 +rect 26436 264660 26571 264665 +rect 23581 264447 23730 264462 +rect 23581 264330 23597 264447 +rect 23716 264330 23730 264447 +rect 23581 264315 23730 264330 rect 29735 263623 30347 264617 rect 32446 263589 33058 264583 rect 35412 263614 36024 264608 @@ -135,6 +158,8 @@ rect 25922 316004 25972 316054 rect 25928 315653 25978 315703 rect 266024 265202 266126 265300 +rect 26446 264665 26561 264775 +rect 23597 264330 23716 264447 rect 265944 262844 266046 262942 rect 265865 260359 265967 260457 rect 242684 240947 242756 241013 @@ -178,6 +203,14 @@ rect 266017 265202 266024 265300 rect 266126 265202 266133 265300 rect 266017 265191 266133 265202 +rect 26436 264775 26571 264785 +rect 26436 264665 26446 264775 +rect 26561 264665 26571 264775 +rect 26436 264660 26571 264665 +rect 23581 264447 23730 264462 +rect 23581 264330 23597 264447 +rect 23716 264330 23730 264447 +rect 23581 264315 23730 264330 rect 265937 262942 266053 262951 rect 265937 262844 265944 262942 rect 266046 262844 266053 262942 @@ -242,6 +275,8 @@ rect 25922 316004 25972 316054 rect 25928 315653 25978 315703 rect 266024 265202 266126 265300 +rect 26446 264665 26561 264775 +rect 23597 264330 23716 264447 rect 265944 262844 266046 262942 rect 265865 260359 265967 260457 rect 242684 240947 242756 241013 @@ -286,6 +321,14 @@ rect 266017 265202 266024 265300 rect 266126 265202 266133 265300 rect 266017 265191 266133 265202 +rect 26436 264775 26571 264785 +rect 26436 264665 26446 264775 +rect 26561 264665 26571 264775 +rect 26436 264660 26571 264665 +rect 23581 264447 23730 264462 +rect 23581 264330 23597 264447 +rect 23716 264330 23730 264447 +rect 23581 264315 23730 264330 rect 265937 262942 266053 262951 rect 265937 262844 265944 262942 rect 266046 262844 266053 262942 @@ -844,6 +887,7 @@ rect 25922 316004 25972 316054 rect 25928 315653 25978 315703 rect 266024 265202 266126 265300 +rect 26446 264665 26561 264775 rect 265944 262844 266046 262942 rect 265865 260359 265967 260457 rect 242684 240947 242756 241013 @@ -977,6 +1021,10 @@ rect 266017 265202 266024 265300 rect 266126 265202 266133 265300 rect 266017 265191 266133 265202 +rect 26436 264775 26571 264785 +rect 26436 264665 26446 264775 +rect 26561 264665 26571 264775 +rect 26436 264660 26571 264665 rect 265937 262942 266053 262951 rect 265937 262844 265944 262942 rect 266046 262844 266053 262942 @@ -1190,6 +1238,13 @@ rect -400 39004 240 39060 rect -400 38413 240 38469 rect -400 37822 240 37878 +rect 39779 30775 40392 30778 +rect 39734 30146 40392 30775 +rect 39734 30143 40347 30146 +rect 39831 30099 40271 30143 +rect 39831 29869 39950 30099 +rect 40206 29869 40271 30099 +rect 39831 29839 40271 29869 rect 291760 25230 292400 25286 rect 291760 24639 292400 24695 rect 291760 24048 292400 24104 @@ -1268,6 +1323,7 @@ rect 245363 306451 245413 306501 rect 273813 275847 275123 276989 rect 266024 265202 266126 265300 +rect 26446 264665 26561 264775 rect 265944 262844 266046 262942 rect 265865 260359 265967 260457 rect 242684 240947 242756 241013 @@ -1283,8 +1339,7 @@ rect 268969 140283 269079 140387 rect 268890 137823 269000 137927 rect 281123 73748 282980 75451 -rect 39675 30442 39774 30539 -rect 40101 30442 40200 30539 +rect 39950 29869 40206 30099 << metal4 >> rect 82797 351150 85297 352400 rect 87947 351150 90447 352400 @@ -1444,6 +1499,10 @@ rect 28721 266590 28859 267193 rect 26420 266258 28859 266590 rect 28721 265891 28859 266258 +rect 26424 264775 26589 264812 +rect 26424 264665 26446 264775 +rect 26561 264665 26589 264775 +rect 26424 264625 26589 264665 rect 28636 263423 28777 264812 rect 18465 263165 20622 263265 rect 18465 262910 21722 263165 @@ -1715,11 +1774,10 @@ rect 24119 45529 25709 45531 rect 25833 45529 27392 45653 rect 24119 45514 27392 45529 -rect 39396 30539 40707 30635 -rect 39396 30442 39675 30539 -rect 39774 30442 40101 30539 -rect 40200 30442 40707 30539 -rect 39396 28000 40707 30442 +rect 39396 30099 40707 30135 +rect 39396 29869 39950 30099 +rect 40206 29869 40707 30099 +rect 39396 28000 40707 29869 rect 46028 28000 48233 28003 rect 164365 28000 166665 69372 rect 11000 26000 276000 28000 @@ -2044,149 +2102,149 @@ rect 292000 0 292050 352000 rect -50 -50 292050 0 use divbuf divbuf_19 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 27511 0 1 45357 box -460 -1085 31200 495 use filter filter_1 -timestamp 1640983258 +timestamp 1643054636 transform 1 0 38025 0 1 41313 box -1800 -11005 6240 390 -use divider divider_3 -timestamp 1643050476 -transform 1 0 31863 0 1 169542 -box -490 -235 4690 2150 use pd pd_5 -timestamp 1643050476 +timestamp 1643054636 transform 1 0 38673 0 1 170517 box -215 -855 1685 810 -use divider divider_0 -timestamp 1643050476 -transform 1 0 246803 0 1 129340 +use divider divider_3 +timestamp 1643054636 +transform 1 0 31863 0 1 169542 box -490 -235 4690 2150 use divbuf divbuf_25 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 237817 0 1 138431 box -460 -1085 31200 495 use divbuf divbuf_24 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 237896 0 1 140897 box -460 -1085 31200 495 use divbuf divbuf_23 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 237976 0 1 143283 box -460 -1085 31200 495 +use divider divider_0 +timestamp 1643054636 +transform 1 0 246803 0 1 129340 +box -490 -235 4690 2150 use divbuf divbuf_18 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 30445 0 1 186973 box -460 -1085 31200 495 use divbuf divbuf_17 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 30365 0 1 184587 box -460 -1085 31200 495 use divbuf divbuf_16 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 30286 0 1 182121 box -460 -1085 31200 495 use divbuf divbuf_15 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 30286 0 1 179927 box -460 -1085 31200 495 -use pd pd_4 -timestamp 1643050476 -transform 1 0 36668 0 1 222858 -box -215 -855 1685 810 use divbuf divbuf_14 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 31964 0 1 233669 box -460 -1085 31200 495 use divbuf divbuf_13 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 31964 0 1 235863 box -460 -1085 31200 495 use divbuf divbuf_12 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 32043 0 1 238329 box -460 -1085 31200 495 use divbuf divbuf_11 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 32123 0 1 240715 box -460 -1085 31200 495 use divbuf divbuf_8 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 28673 0 1 263178 box -460 -1085 31200 495 use cp cp_0 -timestamp 1640911461 +timestamp 1643054636 transform 1 0 21911 0 1 264642 box -415 -1715 4690 2035 -use ro_complete ro_complete_0 -timestamp 1643050476 -transform 1 0 242309 0 1 239846 -box -348 -5690 4661 1440 -use divider divider_1 -timestamp 1643050476 -transform 1 0 250269 0 1 235475 -box -490 -235 4690 2150 +use pd pd_4 +timestamp 1643054636 +transform 1 0 36668 0 1 222858 +box -215 -855 1685 810 use divbuf divbuf_21 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 234867 0 1 263433 box -460 -1085 31200 495 use divbuf divbuf_20 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 234788 0 1 260967 box -460 -1085 31200 495 +use divider divider_1 +timestamp 1643054636 +transform 1 0 250269 0 1 235475 +box -490 -235 4690 2150 +use ro_complete ro_complete_0 +timestamp 1643054636 +transform 1 0 242309 0 1 239846 +box -348 -5690 4661 1440 use divbuf divbuf_10 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 28832 0 1 268030 box -460 -1085 31200 495 use divbuf divbuf_9 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 28752 0 1 265644 box -460 -1085 31200 495 use divbuf divbuf_22 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 234947 0 1 265819 box -460 -1085 31200 495 use divbuf divbuf_7 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 245779 0 1 306691 box -460 -1085 31200 495 use divbuf divbuf_6 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 245858 0 1 309157 box -460 -1085 31200 495 use divbuf divbuf_5 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 245938 0 1 311543 box -460 -1085 31200 495 use pll_full pll_full_1 -timestamp 1643050476 +timestamp 1643054636 transform 1 0 31292 0 1 318138 box -5794 -2690 26430 12835 -use ro_complete ro_complete_1 -timestamp 1643050476 -transform 1 0 247313 0 1 328719 -box -348 -5690 4661 1440 use divbuf divbuf_2 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 246097 0 1 316394 box -460 -1085 31200 495 use divbuf divbuf_4 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 246017 0 1 314009 box -460 -1085 31200 495 use divbuf divbuf_1 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 246176 0 1 318860 box -460 -1085 31200 495 use divbuf divbuf_0 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 244268 0 1 335005 box -460 -1085 31200 495 use divbuf divbuf_3 -timestamp 1641017053 +timestamp 1643054636 transform 1 0 244347 0 1 337471 box -460 -1085 31200 495 +use ro_complete ro_complete_1 +timestamp 1643054636 +transform 1 0 247313 0 1 328719 +box -348 -5690 4661 1440 << labels >> flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0] port 0 nsew signal bidirectional
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice index dd453ac..866040c 100644 --- a/netgen/user_analog_project_wrapper.spice +++ b/netgen/user_analog_project_wrapper.spice
@@ -106,1724 +106,1724 @@ + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] + wbs_stb_i wbs_we_i -C0 pll_full_0/divbuf_0/OUT pll_full_0/divbuf_0/OUT4 1.11fF -C1 divider_0/tspc_0/Z3 divider_0/Out 0.05fF -C2 divider_0/tspc_0/Z2 divider_0/nor_1/B 0.40fF -C3 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF -C4 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF -C5 divbuf_16/OUT5 divbuf_16/OUT 43.38fF -C6 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF -C7 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF -C8 divider_0/prescaler_0/tspc_2/Q divider_0/clk 0.05fF -C9 divbuf_20/OUT3 divbuf_20/OUT 0.26fF -C10 divbuf_20/OUT4 divbuf_20/OUT5 20.26fF -C11 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF -C12 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C13 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C14 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF -C15 divbuf_17/a_492_n240# divbuf_17/IN 0.13fF -C16 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.14fF -C17 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF -C18 pd_1/REF pd_1/tspc_r_1/Z1 0.17fF -C19 pd_1/tspc_r_1/Qbar1 pd_1/UP 0.11fF -C20 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.45fF -C21 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/a_740_n680# 0.33fF -C22 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C23 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF -C24 ro_complete_1/a2 ro_complete_1/cbank_2/switch_2/vin 0.14fF -C25 ro_complete_1/a3 ro_complete_1/cbank_2/switch_1/vin 0.13fF -C26 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF -C27 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF -C28 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C29 divbuf_15/OUT4 divbuf_15/OUT3 5.16fF -C30 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF -C31 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF -C32 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF -C33 divbuf_23/OUT3 divbuf_23/OUT5 0.01fF -C34 divbuf_23/OUT2 divbuf_23/OUT 0.06fF -C35 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF -C36 divider_2/nor_0/A divider_2/tspc_2/Z4 0.21fF -C37 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF -C38 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF -C39 ro_complete_1/a5 ro_complete_1/cbank_2/v 0.08fF -C40 io_clamp_low[1] io_analog[5] 0.53fF -C41 divbuf_15/OUT2 divbuf_15/OUT3 1.37fF -C42 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Q 0.05fF -C43 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF -C44 divbuf_5/OUT4 divbuf_5/OUT 1.11fF -C45 divider_1/tspc_0/Z2 divider_1/nor_1/B 0.40fF -C46 divbuf_22/a_492_n240# divbuf_22/OUT5 0.01fF -C47 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z3 0.25fF -C48 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF -C49 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z2 0.01fF -C50 divider_2/tspc_2/Q divider_2/tspc_1/Z3 0.45fF -C51 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF -C52 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF -C53 divbuf_25/OUT2 divbuf_25/OUT5 0.02fF -C54 divbuf_25/OUT3 divbuf_25/OUT4 5.16fF -C55 divbuf_19/OUT5 divbuf_19/OUT 43.38fF -C56 divider_2/and_0/B divider_2/and_0/Z1 0.07fF -C57 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z4 0.01fF -C58 divbuf_1/IN divbuf_1/a_492_n240# 0.13fF -C59 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF -C60 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF -C61 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF -C62 ro_complete_1/a0 ro_complete_1/cbank_2/switch_5/vin 0.09fF -C63 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C64 divbuf_18/OUT divbuf_18/OUT2 0.06fF -C65 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF -C66 divbuf_11/OUT3 divbuf_11/OUT 0.26fF -C67 divbuf_11/OUT4 divbuf_11/OUT5 20.26fF -C68 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z1 0.08fF -C69 cp_0/a_1710_n2840# cp_0/a_1710_0# 0.83fF -C70 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF -C71 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF -C72 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C73 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF -C74 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF -C75 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF -C76 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.06fF -C77 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF -C78 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF -C79 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C80 divbuf_10/a_492_n240# divbuf_10/OUT 0.00fF -C81 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z2 0.11fF -C82 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C83 pd_1/DIV pd_1/tspc_r_0/Z2 0.19fF -C84 pd_0/DOWN pd_0/R 0.36fF -C85 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF -C86 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF -C87 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF -C88 cp_0/a_1710_0# cp_0/down 0.32fF -C89 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF -C90 divbuf_13/OUT3 divbuf_13/OUT5 0.01fF -C91 divbuf_13/OUT2 divbuf_13/OUT 0.06fF -C92 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/switch_1/vin 0.19fF -C93 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF -C94 divider_1/tspc_0/Z4 divider_1/tspc_0/a_630_n680# 0.12fF -C95 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z3 0.11fF -C96 divider_0/prescaler_0/Out divider_0/tspc_2/Z2 0.11fF -C97 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF -C98 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C99 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF -C100 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF -C101 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C102 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C103 divbuf_16/OUT4 divbuf_16/OUT 1.11fF -C104 divbuf_6/OUT4 divbuf_6/OUT 1.11fF -C105 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF -C106 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.01fF -C107 divider_2/nor_1/B divider_2/tspc_0/Z1 0.03fF -C108 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z4 0.01fF -C109 divbuf_8/a_492_n240# divbuf_8/OUT5 0.01fF -C110 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF -C111 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF -C112 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF -C113 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF -C114 divider_2/tspc_0/Z1 divider_2/tspc_0/Z3 0.06fF -C115 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_2/D 0.16fF -C116 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF -C117 divbuf_19/IN divbuf_19/OUT5 0.00fF -C118 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF -C119 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF -C120 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF -C121 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF -C122 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF -C123 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/Q 0.19fF -C124 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.01fF -C125 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF -C126 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C127 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C128 divider_1/nor_1/B divider_1/nor_0/B 0.47fF -C129 divider_1/tspc_0/Z2 divider_1/tspc_0/Z1 1.07fF -C130 divbuf_21/OUT2 divbuf_21/OUT3 1.37fF -C131 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Q 0.22fF -C132 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF -C133 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C134 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C135 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/A 0.35fF -C136 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.29fF -C137 divbuf_18/OUT5 divbuf_18/a_492_n240# 0.01fF -C138 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF -C139 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF -C140 divbuf_12/OUT3 divbuf_12/OUT 0.26fF -C141 divbuf_12/OUT4 divbuf_12/OUT5 20.26fF -C142 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF -C143 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/switch_1/vin 0.19fF -C144 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF -C145 divider_0/nor_0/B divider_0/tspc_2/Q 0.22fF -C146 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.35fF -C147 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF -C148 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF -C149 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF -C150 pll_full_0/divbuf_0/OUT pll_full_0/divbuf_0/OUT5 43.38fF -C151 divider_1/prescaler_0/Out divider_1/clk 0.51fF -C152 divider_0/tspc_2/a_630_n680# divider_0/nor_0/A 0.35fF -C153 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.29fF -C154 divbuf_3/IN divbuf_3/OUT5 0.00fF -C155 ro_complete_1/cbank_1/v ro_complete_1/cbank_2/v 1.36fF -C156 divbuf_19/OUT2 divbuf_19/OUT 0.06fF -C157 divbuf_20/OUT5 divbuf_20/OUT 43.38fF -C158 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.00fF -C159 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C160 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C161 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C162 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C163 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF -C164 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF -C165 divbuf_17/a_492_n240# divbuf_17/OUT2 0.42fF -C166 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z2 0.25fF -C167 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF -C168 divbuf_0/OUT divbuf_0/OUT2 0.06fF -C169 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/a_740_n680# 0.08fF -C170 divbuf_1/OUT3 divbuf_1/OUT5 0.01fF -C171 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.00fF -C172 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF -C173 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF -C174 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF -C175 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF -C176 divider_0/nor_0/Z1 divider_0/and_0/A 0.80fF -C177 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF -C178 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C179 divbuf_16/OUT2 divbuf_16/OUT 0.06fF -C180 divider_0/and_0/out1 divider_0/and_0/A 0.01fF -C181 divbuf_4/IN divbuf_4/OUT5 0.00fF -C182 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF -C183 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C184 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/A 0.26fF -C185 divbuf_23/OUT4 divbuf_23/OUT 1.11fF -C186 pd_0/R pd_0/tspc_r_1/Z3 0.29fF -C187 divbuf_9/a_492_n240# divbuf_9/OUT5 0.01fF -C188 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF -C189 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF -C190 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF -C191 divider_0/tspc_0/Z2 divider_0/tspc_0/a_630_n680# 0.01fF -C192 ro_complete_1/a1 ro_complete_1/cbank_1/v 0.05fF -C193 divider_1/nor_1/Z1 divider_1/nor_0/B 0.18fF -C194 divider_1/tspc_0/Z4 divider_1/tspc_1/Q 0.15fF -C195 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF -C196 divider_0/nor_0/B divider_0/and_0/A 0.26fF -C197 divider_2/tspc_1/Q divider_2/tspc_1/a_630_n680# 0.04fF -C198 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF -C199 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z4 0.00fF -C200 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF -C201 divider_2/nor_1/B divider_2/tspc_0/Z3 0.38fF -C202 divbuf_22/OUT2 divbuf_22/OUT3 1.37fF -C203 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.29fF -C204 pd_1/tspc_r_0/Qbar pd_1/tspc_r_0/Qbar1 0.01fF -C205 divider_2/mc2 divider_2/and_0/out1 0.06fF -C206 divider_2/tspc_2/Q divider_2/tspc_1/Z4 0.15fF -C207 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF -C208 divbuf_25/OUT3 divbuf_25/OUT 0.26fF -C209 divbuf_25/OUT4 divbuf_25/OUT5 20.26fF -C210 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF -C211 ro_complete_1/a0 ro_complete_1/cbank_2/v 0.05fF -C212 divider_0/nor_1/B divider_0/and_0/B 0.29fF -C213 divbuf_20/a_492_n240# divbuf_20/OUT2 0.42fF -C214 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF -C215 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z3 0.38fF -C216 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_1/B 0.22fF -C217 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z3 0.11fF -C218 divbuf_11/OUT5 divbuf_11/OUT 43.38fF -C219 divbuf_24/a_492_n240# divbuf_24/OUT 0.00fF -C220 pd_1/R pd_1/tspc_r_1/Qbar 0.03fF -C221 divider_2/tspc_2/Q divider_2/tspc_2/Z3 0.05fF -C222 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z3 0.16fF -C223 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF -C224 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF -C225 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF -C226 divbuf_2/IN divbuf_2/OUT5 0.00fF -C227 pll_full_0/divbuf_0/OUT pll_full_0/divbuf_0/a_492_n240# 0.00fF -C228 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT2 1.37fF -C229 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF -C230 divider_0/nor_0/B divider_0/tspc_1/Z3 0.38fF -C231 divider_0/tspc_1/Q divider_0/nor_1/B 0.22fF -C232 divider_1/nor_0/B divider_1/tspc_2/a_630_n680# 0.01fF -C233 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/D 0.03fF -C234 divbuf_10/IN divbuf_10/OUT5 0.00fF -C235 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF -C236 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF -C237 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF -C238 divider_2/tspc_0/Z4 divider_2/tspc_0/Z1 0.00fF -C239 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF -C240 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF -C241 divbuf_23/a_492_n240# divbuf_23/IN 0.13fF -C242 divbuf_13/OUT4 divbuf_13/OUT 1.11fF -C243 pd_1/UP pd_1/and_pd_0/Out1 0.33fF -C244 divbuf_19/a_492_n240# divbuf_19/OUT 0.00fF -C245 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF -C246 divider_2/prescaler_0/tspc_2/Q divider_2/clk 0.05fF -C247 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF -C248 ro_complete_1/a4 ro_complete_1/cbank_0/switch_1/vin 0.09fF -C249 divbuf_2/OUT5 divbuf_2/a_492_n240# 0.01fF -C250 ro_complete_1/a3 ro_complete_1/cbank_2/switch_2/vin 0.09fF -C251 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C252 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C253 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z4 0.28fF -C254 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.05fF -C255 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C256 divbuf_16/OUT3 divbuf_16/OUT 0.26fF -C257 divider_1/tspc_0/Z2 divider_1/tspc_0/Z3 0.16fF -C258 divider_1/prescaler_0/tspc_1/Q divider_1/nor_0/A 0.03fF -C259 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_0/A 0.15fF -C260 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF -C261 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C262 pd_1/tspc_r_0/Qbar pd_1/DOWN 0.21fF -C263 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF -C264 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF -C265 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z2 0.19fF -C266 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF -C267 divider_2/prescaler_0/Out divider_2/clk 0.51fF -C268 divbuf_8/OUT2 divbuf_8/OUT3 1.37fF -C269 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF -C270 divider_0/tspc_0/Z2 divider_0/tspc_1/Q 0.14fF -C271 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF -C272 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF -C273 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C274 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/v 1.30fF -C275 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Q 0.91fF -C276 divider_0/tspc_1/Z2 divider_0/nor_0/A 0.15fF -C277 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/D 0.32fF -C278 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF -C279 divbuf_21/OUT2 divbuf_21/OUT5 0.02fF -C280 divbuf_21/OUT3 divbuf_21/OUT4 5.16fF -C281 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C282 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C283 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF -C284 divider_1/tspc_2/Q divider_1/tspc_2/a_630_n680# 0.04fF -C285 divbuf_11/a_492_n240# divbuf_11/OUT2 0.42fF -C286 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF -C287 pd_1/R pd_1/tspc_r_0/Qbar1 0.01fF -C288 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C289 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Q 0.05fF -C290 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF -C291 divbuf_12/OUT5 divbuf_12/OUT 43.38fF -C292 divbuf_14/a_492_n240# divbuf_14/OUT 0.00fF -C293 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a4 0.12fF -C294 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF -C295 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/a_630_n680# 0.05fF -C296 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF -C297 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF -C298 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF -C299 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C300 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF -C301 divbuf_3/OUT2 divbuf_3/OUT 0.06fF -C302 divbuf_18/OUT divbuf_18/OUT3 0.26fF -C303 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF -C304 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF -C305 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF -C306 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C307 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C308 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C309 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF -C310 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/Out 0.21fF -C311 divider_1/mc2 divider_1/and_0/out1 0.06fF -C312 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF -C313 divider_2/mc2 divider_2/nor_0/B 0.06fF -C314 divbuf_7/IN divbuf_7/OUT5 0.00fF -C315 pd_1/R pd_1/and_pd_0/Z1 0.02fF -C316 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/Qbar 0.01fF -C317 divbuf_19/a_492_n240# divbuf_19/IN 0.13fF -C318 divbuf_13/a_492_n240# divbuf_13/IN 0.13fF -C319 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF -C320 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C321 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF -C322 divider_0/tspc_2/Q divider_0/tspc_1/Z3 0.45fF -C323 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF -C324 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF -C325 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF -C326 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF -C327 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF -C328 divbuf_4/OUT2 divbuf_4/OUT 0.06fF -C329 divider_2/nor_1/B divider_2/tspc_0/Z4 0.22fF -C330 pd_0/R pd_0/UP 0.45fF -C331 divider_2/tspc_0/Z4 divider_2/tspc_0/Z3 0.65fF -C332 divbuf_9/OUT2 divbuf_9/OUT3 1.37fF -C333 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C334 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/a_740_n680# 0.19fF -C335 divbuf_1/OUT4 divbuf_1/OUT5 20.26fF -C336 io_clamp_high[0] io_analog[4] 0.53fF -C337 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C338 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF -C339 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF -C340 divbuf_22/OUT2 divbuf_22/OUT5 0.02fF -C341 divbuf_22/OUT3 divbuf_22/OUT4 5.16fF -C342 divider_2/tspc_0/Z2 divider_2/nor_0/B 0.20fF -C343 pd_1/DOWN pd_1/R 0.36fF -C344 pd_0/UP pd_0/and_pd_0/Out1 0.33fF -C345 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF -C346 divider_2/mc2 divider_2/and_0/A 0.16fF -C347 divbuf_12/a_492_n240# divbuf_12/OUT2 0.42fF -C348 pll_full_0/pd_0/DIV pll_full_0/divbuf_1/OUT2 0.06fF -C349 divbuf_25/OUT5 divbuf_25/OUT 43.38fF -C350 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z1 0.08fF -C351 divider_0/mc2 divider_0/nor_1/B 0.15fF -C352 divbuf_0/OUT2 divbuf_0/OUT5 0.02fF -C353 divbuf_18/OUT4 divbuf_18/OUT3 5.16fF -C354 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C355 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z4 0.21fF -C356 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/nor_1/B 0.38fF -C357 divider_1/nor_0/B divider_1/tspc_1/Z2 0.30fF -C358 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF -C359 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/B 0.08fF -C360 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z4 0.28fF -C361 divider_1/and_0/out1 divider_1/and_0/B 0.18fF -C362 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/R 0.01fF -C363 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/Q 0.19fF -C364 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.01fF -C365 divbuf_24/IN divbuf_24/OUT5 0.00fF -C366 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF -C367 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF -C368 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF -C369 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF -C370 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z4 0.36fF -C371 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/Out 0.05fF -C372 divider_0/nor_0/B divider_0/tspc_1/Z4 0.21fF -C373 divider_0/tspc_0/Z3 divider_0/nor_1/B 0.38fF -C374 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF -C375 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C376 divider_0/nor_0/A divider_0/and_0/B 0.08fF -C377 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF -C378 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF -C379 divbuf_10/OUT3 divbuf_10/OUT5 0.01fF -C380 divbuf_10/OUT2 divbuf_10/OUT 0.06fF -C381 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C382 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF -C383 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF -C384 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z3 0.06fF -C385 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF -C386 divider_1/nor_0/B divider_1/nor_0/A 1.21fF -C387 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Q 0.91fF -C388 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF -C389 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF -C390 pll_full_0/pd_0/DIV pll_full_0/divbuf_1/a_492_n240# 0.00fF -C391 divider_2/tspc_2/a_630_n680# divider_2/nor_0/A 0.35fF -C392 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.29fF -C393 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a5 0.09fF -C394 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C395 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/cbank_0/v 1.30fF -C396 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF -C397 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Q 0.20fF -C398 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF -C399 divider_2/tspc_1/Q divider_2/tspc_0/Z1 0.01fF -C400 divider_1/mc2 divider_1/nor_0/B 0.06fF -C401 divider_1/tspc_2/Q divider_1/tspc_1/Z2 0.14fF -C402 divider_1/tspc_0/Z2 divider_1/tspc_0/a_630_n680# 0.01fF -C403 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF -C404 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.01fF -C405 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C406 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF -C407 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF -C408 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C409 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF -C410 divider_1/and_0/OUT divider_1/clk 0.04fF -C411 divbuf_8/OUT2 divbuf_8/OUT5 0.02fF -C412 divbuf_8/OUT3 divbuf_8/OUT4 5.16fF -C413 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF -C414 divbuf_17/OUT3 divbuf_17/OUT2 1.37fF -C415 divider_2/tspc_2/Q divider_2/tspc_1/a_630_n680# 0.01fF -C416 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF -C417 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF -C418 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF -C419 divider_2/and_0/out1 divider_2/and_0/A 0.01fF -C420 divbuf_25/a_492_n240# divbuf_25/OUT2 0.42fF -C421 ro_complete_1/a4 ro_complete_1/cbank_2/switch_0/vin 0.12fF -C422 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF -C423 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF -C424 divbuf_16/a_492_n240# divbuf_16/OUT5 0.01fF -C425 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF -C426 divider_0/tspc_0/a_630_n680# divider_0/tspc_1/Q 0.01fF -C427 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF -C428 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.05fF -C429 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/D 0.09fF -C430 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF -C431 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/tspc_0/D 0.04fF -C432 divider_1/tspc_2/Q divider_1/nor_0/A 0.55fF -C433 divider_1/nor_0/B divider_1/tspc_1/Z1 0.03fF -C434 divbuf_21/OUT3 divbuf_21/OUT 0.26fF -C435 divbuf_21/OUT4 divbuf_21/OUT5 20.26fF -C436 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.04fF -C437 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C438 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.58fF -C439 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z2 0.23fF -C440 divider_1/nor_0/A divider_1/and_0/A 0.01fF -C441 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Z3 0.11fF -C442 divbuf_19/OUT3 divbuf_19/OUT 0.26fF -C443 divbuf_19/OUT4 divbuf_19/OUT5 20.26fF -C444 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF -C445 divbuf_14/IN divbuf_14/OUT5 0.00fF -C446 divbuf_1/OUT2 divbuf_1/OUT 0.06fF -C447 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/a0 0.13fF -C448 pll_full_0/divbuf_0/OUT pll_full_0/divbuf_0/OUT2 0.06fF -C449 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF -C450 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C451 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/a_630_n680# 0.12fF -C452 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z1 1.07fF -C453 divider_0/tspc_1/Q divider_0/tspc_1/a_630_n680# 0.04fF -C454 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF -C455 divbuf_3/OUT4 divbuf_3/OUT 1.11fF -C456 divbuf_18/OUT divbuf_18/OUT5 43.38fF -C457 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z2 0.01fF -C458 divider_0/nor_0/A divider_0/tspc_2/Z2 0.23fF -C459 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_0/A 0.01fF -C460 divider_1/mc2 divider_1/and_0/A 0.16fF -C461 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF -C462 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.15fF -C463 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF -C464 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/B 0.22fF -C465 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C466 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C467 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF -C468 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF -C469 divbuf_7/OUT2 divbuf_7/OUT 0.06fF -C470 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF -C471 divbuf_17/OUT5 divbuf_17/IN 0.00fF -C472 divider_2/nor_1/B divider_2/and_0/B 0.29fF -C473 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF -C474 pd_1/REF pd_1/tspc_r_1/z5 0.04fF -C475 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF -C476 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF -C477 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF -C478 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C479 divider_1/prescaler_0/Out divider_1/prescaler_0/m1_2700_2190# 0.11fF -C480 divider_0/tspc_2/Q divider_0/tspc_1/Z4 0.15fF -C481 divider_0/tspc_0/Z4 divider_0/nor_1/B 0.22fF -C482 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF -C483 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF -C484 divbuf_4/OUT4 divbuf_4/OUT 1.11fF -C485 divider_1/tspc_2/Q divider_1/tspc_1/Z1 0.01fF -C486 divider_1/tspc_1/a_630_n680# divider_1/nor_0/B 0.35fF -C487 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF -C488 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF -C489 divider_1/nor_0/B divider_1/and_0/B 0.31fF -C490 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF -C491 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/Z3 0.05fF -C492 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF -C493 pd_1/DIV pd_1/tspc_r_0/z5 0.04fF -C494 divbuf_9/OUT2 divbuf_9/OUT5 0.02fF -C495 divbuf_9/OUT3 divbuf_9/OUT4 5.16fF -C496 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF -C497 divbuf_1/OUT5 divbuf_1/OUT 43.38fF -C498 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF -C499 divider_2/tspc_1/Q divider_2/nor_1/B 0.22fF -C500 divider_0/tspc_2/Q divider_0/tspc_2/Z3 0.05fF -C501 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF -C502 divider_2/tspc_1/Q divider_2/tspc_0/Z3 0.45fF -C503 divider_1/tspc_0/Z2 divider_1/tspc_1/Q 0.14fF -C504 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF -C505 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF -C506 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C507 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF -C508 divider_1/nor_0/A divider_1/tspc_2/Z1 0.03fF -C509 divbuf_22/OUT3 divbuf_22/OUT 0.26fF -C510 divbuf_22/OUT4 divbuf_22/OUT5 20.26fF -C511 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF -C512 divbuf_18/a_492_n240# divbuf_18/IN 0.13fF -C513 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.05fF -C514 pll_full_0/pd_0/DIV pll_full_0/divbuf_1/OUT4 1.11fF -C515 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF -C516 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF -C517 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF -C518 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF -C519 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z3 0.11fF -C520 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C521 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF -C522 ro_complete_1/cbank_2/switch_2/vin ro_complete_1/cbank_2/v 1.30fF -C523 divbuf_18/OUT4 divbuf_18/OUT5 20.26fF -C524 divider_1/tspc_2/Q divider_1/tspc_1/a_630_n680# 0.01fF -C525 divbuf_20/a_492_n240# divbuf_20/OUT 0.00fF -C526 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF -C527 divider_1/tspc_1/Z1 divider_1/tspc_1/Z3 0.06fF -C528 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C529 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF -C530 divider_1/and_0/A divider_1/and_0/B 0.18fF -C531 divbuf_24/OUT3 divbuf_24/OUT5 0.01fF -C532 divbuf_24/OUT2 divbuf_24/OUT 0.06fF -C533 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF -C534 divider_2/tspc_1/Z2 divider_2/nor_0/A 0.15fF -C535 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/D 0.32fF -C536 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF -C537 divider_2/nor_0/B divider_2/and_0/A 0.26fF -C538 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF -C539 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF -C540 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C541 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF -C542 divider_0/mc2 divider_0/nor_0/A 0.04fF -C543 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C544 ro_complete_1/a5 ro_complete_1/cbank_2/switch_0/vin 0.09fF -C545 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF -C546 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF -C547 divider_1/nor_0/Z1 divider_1/and_0/B 0.18fF -C548 divbuf_10/OUT4 divbuf_10/OUT 1.11fF -C549 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z4 0.00fF -C550 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_0/z1 0.24fF -C551 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF -C552 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C553 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF -C554 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF -C555 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF -C556 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF -C557 divbuf_23/a_492_n240# divbuf_23/OUT5 0.01fF -C558 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Out1 0.05fF -C559 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF -C560 divider_1/Out divider_1/nor_1/B 0.22fF -C561 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF -C562 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF -C563 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Q 0.04fF -C564 divider_0/prescaler_0/Out divider_0/clk 0.51fF -C565 divbuf_2/OUT2 divbuf_2/OUT 0.06fF -C566 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF -C567 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF -C568 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z3 0.05fF -C569 divider_2/nor_1/B divider_2/tspc_0/a_630_n680# 0.35fF -C570 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z4 0.65fF -C571 divider_2/nor_0/Z1 divider_2/and_0/A 0.80fF -C572 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF -C573 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.26fF -C574 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C575 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF -C576 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF -C577 pd_0/REF pd_0/tspc_r_1/z5 0.04fF -C578 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF -C579 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF -C580 divider_2/nor_0/B divider_2/tspc_1/Z3 0.38fF -C581 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z3 0.05fF -C582 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF -C583 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF -C584 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF -C585 divbuf_8/OUT3 divbuf_8/OUT 0.26fF -C586 divbuf_8/OUT4 divbuf_8/OUT5 20.26fF -C587 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF -C588 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF -C589 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF -C590 divbuf_15/OUT divbuf_15/OUT5 43.38fF -C591 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/nand_1/z1 0.01fF -C592 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF -C593 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/IN 0.13fF -C594 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C595 divbuf_21/OUT5 divbuf_21/OUT 43.38fF -C596 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C597 divider_1/nor_0/B divider_1/tspc_1/Q 0.51fF -C598 divbuf_11/a_492_n240# divbuf_11/OUT 0.00fF -C599 divider_2/prescaler_0/Out divider_2/prescaler_0/m1_2700_2190# 0.11fF -C600 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF -C601 cp_0/a_1710_n2840# cp_0/upbar 0.29fF -C602 pd_1/R pd_1/REF 0.61fF -C603 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF -C604 divbuf_14/OUT3 divbuf_14/OUT5 0.01fF -C605 divbuf_14/OUT2 divbuf_14/OUT 0.06fF -C606 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF -C607 divbuf_16/a_492_n240# divbuf_16/OUT2 0.42fF -C608 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF -C609 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF -C610 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF -C611 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C612 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/Out 0.04fF -C613 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF -C614 divbuf_10/a_492_n240# divbuf_10/IN 0.13fF -C615 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C616 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C617 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.14fF -C618 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.78fF -C619 divider_1/tspc_1/Z2 divider_1/tspc_1/Z4 0.36fF -C620 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF -C621 divbuf_7/OUT4 divbuf_7/OUT 1.11fF -C622 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF -C623 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF -C624 divbuf_17/OUT5 divbuf_17/OUT2 0.02fF -C625 divider_2/mc2 divider_2/prescaler_0/tspc_2/a_630_n680# 0.33fF -C626 cp_0/upbar cp_0/down 0.02fF -C627 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF -C628 divbuf_13/a_492_n240# divbuf_13/OUT5 0.01fF -C629 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF -C630 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C631 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF -C632 divider_0/mc2 divider_0/and_0/B 0.20fF -C633 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/v 1.30fF -C634 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF -C635 divider_2/tspc_1/Q divider_2/tspc_0/Z4 0.15fF -C636 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C637 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF -C638 divider_2/nor_1/Z1 divider_2/nor_0/B 0.18fF -C639 divider_1/tspc_1/Z4 divider_1/nor_0/A 0.02fF -C640 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF -C641 divbuf_18/OUT3 divbuf_18/OUT2 1.37fF -C642 pd_1/and_pd_0/Out1 pd_1/and_pd_0/Z1 0.18fF -C643 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF -C644 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF -C645 divider_2/nor_0/A divider_2/and_0/B 0.08fF -C646 divbuf_9/OUT3 divbuf_9/OUT 0.26fF -C647 divbuf_9/OUT4 divbuf_9/OUT5 20.26fF -C648 divider_0/nor_1/Z1 divider_0/nor_0/B 0.18fF -C649 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C650 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF -C651 divbuf_21/a_492_n240# divbuf_21/OUT2 0.42fF -C652 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z4 0.12fF -C653 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z3 0.45fF -C654 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_1/B 0.40fF -C655 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF -C656 divbuf_22/OUT5 divbuf_22/OUT 43.38fF -C657 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF -C658 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF -C659 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF -C660 divider_1/nor_0/A divider_1/tspc_2/Z3 0.38fF -C661 divbuf_12/a_492_n240# divbuf_12/OUT 0.00fF -C662 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF -C663 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF -C664 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF -C665 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Q 0.20fF -C666 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF -C667 ro_complete_1/a4 ro_complete_1/cbank_1/v 0.05fF -C668 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C669 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF -C670 divider_0/tspc_1/Q divider_0/tspc_0/Z3 0.45fF -C671 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z4 0.28fF -C672 divider_1/prescaler_0/Out divider_1/tspc_2/Z3 0.45fF -C673 divider_0/and_0/OUT divider_0/and_0/B 0.01fF -C674 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/switch_5/vin 0.20fF -C675 divider_1/tspc_1/Q divider_1/tspc_1/Z3 0.05fF -C676 divider_1/tspc_1/Z1 divider_1/tspc_1/Z4 0.00fF -C677 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF -C678 divbuf_20/IN divbuf_20/OUT5 0.00fF -C679 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF -C680 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C681 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF -C682 divbuf_24/OUT4 divbuf_24/OUT 1.11fF -C683 cp_0/a_1710_n2840# cp_0/out 0.61fF -C684 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF -C685 pd_1/REF pd_1/tspc_r_1/Qbar1 0.12fF -C686 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF -C687 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/tspc_0/D 0.04fF -C688 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF -C689 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF -C690 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF -C691 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF -C692 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C693 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF -C694 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF -C695 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Q 0.91fF -C696 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C697 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF -C698 divbuf_17/a_492_n240# divbuf_17/OUT5 0.01fF -C699 divbuf_17/OUT4 divbuf_17/OUT3 5.16fF -C700 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/Q 0.04fF -C701 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF -C702 divbuf_23/OUT2 divbuf_23/OUT3 1.37fF -C703 divider_2/tspc_0/Z4 divider_2/tspc_0/a_630_n680# 0.12fF -C704 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF -C705 divider_2/nor_0/A divider_2/tspc_2/Z2 0.23fF -C706 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF -C707 divbuf_2/OUT4 divbuf_2/OUT 1.11fF -C708 ro_complete_1/a2 ro_complete_1/cbank_2/v 0.05fF -C709 io_clamp_low[2] io_analog[6] 0.53fF -C710 divider_1/mc2 divider_1/prescaler_0/tspc_2/a_630_n680# 0.33fF -C711 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z4 0.12fF -C712 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF -C713 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF -C714 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF -C715 divbuf_22/a_492_n240# divbuf_22/OUT2 0.42fF -C716 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C717 divbuf_8/OUT5 divbuf_8/OUT 43.38fF -C718 pd_0/R pd_0/and_pd_0/Z1 0.02fF -C719 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF -C720 divider_2/nor_0/B divider_2/tspc_1/Z4 0.21fF -C721 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF -C722 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF -C723 divbuf_25/a_492_n240# divbuf_25/OUT 0.00fF -C724 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF -C725 divbuf_0/a_492_n240# divbuf_0/IN 0.13fF -C726 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF -C727 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF -C728 ro_complete_1/cbank_1/switch_5/vin ro_complete_1/cbank_1/v 1.30fF -C729 divbuf_15/a_492_n240# divbuf_15/OUT5 0.01fF -C730 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_1/z1 0.21fF -C731 divider_1/prescaler_0/m1_2700_2190# divider_1/and_0/OUT 0.14fF -C732 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z4 0.15fF -C733 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C734 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.11fF -C735 divbuf_11/IN divbuf_11/OUT5 0.00fF -C736 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF -C737 divbuf_24/a_492_n240# divbuf_24/IN 0.13fF -C738 pd_1/R pd_1/tspc_r_1/Qbar1 0.30fF -C739 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Qbar1 0.38fF -C740 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF -C741 divider_2/tspc_2/Q divider_2/tspc_2/a_630_n680# 0.04fF -C742 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF -C743 divbuf_14/OUT4 divbuf_14/OUT 1.11fF -C744 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF -C745 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF -C746 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C747 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF -C748 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF -C749 divider_0/tspc_1/Q divider_0/tspc_0/Z4 0.15fF -C750 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF -C751 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF -C752 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C753 pd_0/DIV pd_0/R 0.51fF -C754 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF -C755 divbuf_13/OUT2 divbuf_13/OUT3 1.37fF -C756 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF -C757 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a2 0.09fF -C758 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF -C759 pll_full_0/pd_0/DIV pll_full_0/divbuf_1/IN 5.26fF -C760 ro_complete_1/a5 ro_complete_1/cbank_1/v 0.10fF -C761 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_0/vin 0.19fF -C762 divider_1/tspc_0/Z4 divider_1/tspc_0/Z2 0.36fF -C763 divider_1/Out divider_1/tspc_0/Z3 0.05fF -C764 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF -C765 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF -C766 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF -C767 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.45fF -C768 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF -C769 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF -C770 pd_1/DIV pd_1/tspc_r_0/Qbar1 0.12fF -C771 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF -C772 divbuf_18/OUT5 divbuf_18/OUT2 0.02fF -C773 divider_2/prescaler_0/Out divider_2/tspc_2/Z3 0.45fF -C774 divbuf_8/a_492_n240# divbuf_8/OUT2 0.42fF -C775 divbuf_9/OUT5 divbuf_9/OUT 43.38fF -C776 filter_0/a_4216_n2998# filter_0/v 0.31fF -C777 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF -C778 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF -C779 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/Out 0.21fF -C780 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a2 0.09fF -C781 ro_complete_1/a4 ro_complete_1/cbank_2/switch_1/vin 0.09fF -C782 ro_complete_1/a0 ro_complete_1/cbank_1/switch_5/vin 0.09fF -C783 divbuf_16/OUT5 divbuf_16/OUT4 20.26fF -C784 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF -C785 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF -C786 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF -C787 divider_1/nor_0/A divider_1/tspc_2/Z4 0.21fF -C788 pd_1/DOWN pd_1/tspc_r_0/Z3 0.03fF -C789 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF -C790 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Q 0.04fF -C791 divbuf_12/IN divbuf_12/OUT5 0.00fF -C792 divbuf_14/a_492_n240# divbuf_14/IN 0.13fF -C793 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C794 divider_0/mc2 divider_0/and_0/OUT 0.05fF -C795 divider_0/tspc_0/Z1 divider_0/nor_1/B 0.03fF -C796 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF -C797 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/v 1.30fF -C798 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C799 divider_1/prescaler_0/Out divider_1/tspc_2/Z4 0.12fF -C800 divbuf_20/OUT3 divbuf_20/OUT5 0.01fF -C801 divbuf_20/OUT2 divbuf_20/OUT 0.06fF -C802 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C803 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF -C804 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF -C805 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF -C806 divbuf_19/OUT3 divbuf_19/OUT4 5.16fF -C807 divider_1/and_0/B divider_1/and_0/Z1 0.07fF -C808 pd_1/tspc_r_1/Z3 pd_1/UP 0.03fF -C809 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/nand_1/z1 0.01fF -C810 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF -C811 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF -C812 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF -C813 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF -C814 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C815 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF -C816 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C817 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF -C818 pd_0/DOWN pd_0/UP 0.46fF -C819 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF -C820 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF -C821 divbuf_23/OUT2 divbuf_23/OUT5 0.02fF -C822 divbuf_23/OUT3 divbuf_23/OUT4 5.16fF -C823 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF -C824 divbuf_9/a_492_n240# divbuf_9/OUT2 0.42fF -C825 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF -C826 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF -C827 divbuf_16/OUT5 divbuf_16/OUT2 0.02fF -C828 divider_1/tspc_0/Z4 divider_1/nor_0/B 0.02fF -C829 divider_1/nor_1/Z1 divider_1/nor_1/B 0.06fF -C830 divbuf_15/IN divbuf_15/OUT5 0.00fF -C831 ro_complete_1/cbank_1/switch_2/vin ro_complete_1/cbank_1/v 1.30fF -C832 divbuf_5/OUT3 divbuf_5/OUT 0.26fF -C833 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF -C834 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF -C835 divider_2/tspc_1/Q divider_2/tspc_0/a_630_n680# 0.01fF -C836 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF -C837 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z3 0.09fF -C838 divider_2/tspc_2/Q divider_2/tspc_1/Z2 0.14fF -C839 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF -C840 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF -C841 divbuf_25/IN divbuf_25/OUT5 0.00fF -C842 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF -C843 divider_0/prescaler_0/Out divider_0/prescaler_0/m1_2700_2190# 0.11fF -C844 ro_complete_1/cbank_0/v ro_complete_1/cbank_2/v 0.04fF -C845 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_1/B 0.47fF -C846 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z4 0.65fF -C847 divbuf_17/OUT4 divbuf_17/OUT5 20.26fF -C848 divider_1/nor_1/B divider_1/tspc_0/Z1 0.03fF -C849 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_2/D 0.16fF -C850 divbuf_11/OUT3 divbuf_11/OUT5 0.01fF -C851 divbuf_11/OUT2 divbuf_11/OUT 0.06fF -C852 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF -C853 divider_2/tspc_2/Q divider_2/nor_0/A 0.55fF -C854 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF -C855 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_4/vin 0.20fF -C856 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_4/vin 0.20fF -C857 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF -C858 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF -C859 divider_0/nor_0/B divider_0/nor_1/B 0.47fF -C860 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF -C861 divbuf_15/OUT5 divbuf_15/OUT4 20.26fF -C862 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF -C863 divbuf_10/a_492_n240# divbuf_10/OUT5 0.01fF -C864 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C865 pd_1/DIV pd_1/tspc_r_0/Z1 0.17fF -C866 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF -C867 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF -C868 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF -C869 pll_full_0/pd_0/DIV pll_full_0/divbuf_1/OUT5 43.38fF -C870 divider_2/and_0/OUT divider_2/and_0/B 0.01fF -C871 divbuf_13/OUT2 divbuf_13/OUT5 0.02fF -C872 divbuf_13/OUT3 divbuf_13/OUT4 5.16fF -C873 divbuf_2/OUT2 divbuf_2/a_492_n240# 0.42fF -C874 divider_1/Out divider_1/tspc_0/a_630_n680# 0.04fF -C875 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z2 0.19fF -C876 divbuf_15/OUT2 divbuf_15/OUT5 0.02fF -C877 divider_0/nor_0/B divider_0/tspc_2/a_630_n680# 0.01fF -C878 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C879 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_1/Q 0.14fF -C880 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF -C881 divbuf_6/OUT3 divbuf_6/OUT 0.26fF -C882 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF -C883 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF -C884 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF -C885 divider_2/tspc_1/Z1 divider_2/tspc_2/Q 0.01fF -C886 divider_2/prescaler_0/Out divider_2/tspc_2/Z4 0.12fF -C887 divider_2/nor_0/B divider_2/tspc_1/a_630_n680# 0.35fF -C888 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF -C889 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF -C890 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/v 1.30fF -C891 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF -C892 divider_0/tspc_0/Z2 divider_0/nor_0/B 0.20fF -C893 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.04fF -C894 ro_complete_1/a0 ro_complete_1/cbank_1/v 0.05fF -C895 ro_complete_1/a3 ro_complete_1/cbank_2/v 0.05fF -C896 divbuf_16/OUT5 divbuf_16/OUT3 0.01fF -C897 divbuf_21/a_492_n240# divbuf_21/OUT 0.00fF -C898 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.18fF -C899 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C900 divbuf_17/OUT5 divbuf_17/OUT3 0.01fF -C901 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF -C902 divbuf_12/OUT3 divbuf_12/OUT5 0.01fF -C903 divbuf_12/OUT2 divbuf_12/OUT 0.06fF -C904 pll_full_0/pd_0/DIV pll_full_0/pd_0/R 0.51fF -C905 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF -C906 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/switch_5/vin 0.20fF -C907 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF -C908 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF -C909 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF -C910 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.64fF -C911 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C912 divbuf_19/OUT2 divbuf_19/OUT5 0.02fF -C913 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF -C914 divbuf_20/OUT4 divbuf_20/OUT 1.11fF -C915 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF -C916 cp_0/a_10_n50# cp_0/vbias 0.19fF -C917 pd_1/R pd_1/and_pd_0/Out1 0.33fF -C918 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z1 0.09fF -C919 pd_1/REF pd_1/tspc_r_1/Z2 0.19fF -C920 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_1/z1 0.21fF -C921 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_0/a_740_n680# 0.21fF -C922 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF -C923 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF -C924 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C925 divbuf_17/OUT divbuf_17/OUT2 0.06fF -C926 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.04fF -C927 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C928 pd_0/R pd_0/REF 0.61fF -C929 divbuf_23/OUT3 divbuf_23/OUT 0.26fF -C930 divbuf_23/OUT4 divbuf_23/OUT5 20.26fF -C931 io_clamp_low[2] io_clamp_high[2] 0.53fF -C932 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF -C933 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF -C934 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/switch_5/vin 0.20fF -C935 io_clamp_high[1] io_analog[5] 0.53fF -C936 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C937 divider_0/tspc_2/Q divider_0/tspc_2/a_630_n680# 0.04fF -C938 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/D 0.03fF -C939 divbuf_5/OUT5 divbuf_5/OUT 43.38fF -C940 divider_1/tspc_0/Z3 divider_1/nor_1/B 0.38fF -C941 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF -C942 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z1 0.03fF -C943 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF -C944 divbuf_18/OUT3 divbuf_18/OUT5 0.01fF -C945 divider_2/tspc_0/Z2 divider_2/tspc_0/Z1 1.07fF -C946 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF -C947 divider_1/prescaler_0/tspc_2/Q divider_1/clk 0.05fF -C948 divbuf_22/a_492_n240# divbuf_22/OUT 0.00fF -C949 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/nor_0/A 0.03fF -C950 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z3 0.05fF -C951 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF -C952 divbuf_25/OUT3 divbuf_25/OUT5 0.01fF -C953 divbuf_25/OUT2 divbuf_25/OUT 0.06fF -C954 divider_0/nor_0/B divider_0/tspc_1/Z1 0.03fF -C955 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF -C956 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C957 divider_0/prescaler_0/tspc_1/Q divider_0/nor_0/A 0.03fF -C958 divbuf_20/a_492_n240# divbuf_20/IN 0.13fF -C959 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF -C960 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z2 0.30fF -C961 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z2 0.19fF -C962 divbuf_11/OUT4 divbuf_11/OUT 1.11fF -C963 pd_1/R pd_1/tspc_r_1/Z2 0.21fF -C964 divbuf_24/a_492_n240# divbuf_24/OUT5 0.01fF -C965 divbuf_0/a_492_n240# divbuf_0/OUT 0.00fF -C966 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF -C967 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF -C968 divider_0/nor_0/B divider_0/tspc_1/Z2 0.30fF -C969 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF -C970 ro_complete_1/cbank_2/switch_5/vin ro_complete_1/cbank_2/v 1.30fF -C971 divbuf_16/OUT4 divbuf_16/OUT3 5.16fF -C972 divbuf_15/OUT5 divbuf_15/OUT3 0.01fF -C973 divbuf_10/OUT2 divbuf_10/OUT3 1.37fF -C974 divider_2/nor_1/B divider_2/mc2 0.15fF -C975 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Q 0.05fF -C976 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF -C977 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z3 0.45fF -C978 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_0/A 1.21fF -C979 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF -C980 divbuf_13/OUT3 divbuf_13/OUT 0.26fF -C981 divbuf_13/OUT4 divbuf_13/OUT5 20.26fF -C982 divbuf_19/a_492_n240# divbuf_19/OUT5 0.01fF -C983 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/a5 0.09fF -C984 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF -C985 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF -C986 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF -C987 divider_0/prescaler_0/Out divider_0/tspc_2/Z3 0.45fF -C988 divider_0/nor_0/B divider_0/nor_0/A 1.21fF -C989 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C990 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF -C991 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF -C992 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C993 divbuf_17/OUT divbuf_17/a_492_n240# 0.00fF -C994 divider_1/mc2 divider_1/nor_1/B 0.15fF -C995 divbuf_6/OUT5 divbuf_6/OUT 43.38fF -C996 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF -C997 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF -C998 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z1 0.17fF -C999 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.64fF -C1000 divbuf_8/a_492_n240# divbuf_8/OUT 0.00fF -C1001 divider_0/tspc_0/Z1 divider_0/tspc_1/Q 0.01fF -C1002 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF -C1003 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF -C1004 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF -C1005 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF -C1006 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF -C1007 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF -C1008 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/IN 0.00fF -C1009 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C1010 divbuf_21/IN divbuf_21/OUT5 0.00fF -C1011 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_2/Q 0.01fF -C1012 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/a_630_n680# 0.35fF -C1013 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF -C1014 divider_2/nor_1/B divider_2/tspc_0/Z2 0.40fF -C1015 divider_1/tspc_0/Z3 divider_1/tspc_0/Z1 0.06fF -C1016 divbuf_11/a_492_n240# divbuf_11/IN 0.13fF -C1017 divider_2/tspc_0/Z2 divider_2/tspc_0/Z3 0.16fF -C1018 pd_1/R pd_1/tspc_r_0/Z3 0.27fF -C1019 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C1020 divbuf_12/OUT4 divbuf_12/OUT 1.11fF -C1021 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF -C1022 divbuf_14/a_492_n240# divbuf_14/OUT5 0.01fF -C1023 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/a_630_n680# 0.01fF -C1024 divider_0/tspc_1/Z1 divider_0/tspc_2/Q 0.01fF -C1025 divider_0/nor_0/B divider_0/tspc_1/a_630_n680# 0.35fF -C1026 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/v 1.30fF -C1027 divbuf_16/OUT2 divbuf_16/OUT3 1.37fF -C1028 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF -C1029 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF -C1030 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF -C1031 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF -C1032 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C1033 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z3 0.33fF -C1034 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF -C1035 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF -C1036 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF -C1037 divider_0/nor_0/Z1 divider_0/and_0/B 0.18fF -C1038 divider_0/tspc_2/Q divider_0/tspc_1/Z2 0.14fF -C1039 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF -C1040 divbuf_1/OUT3 divbuf_1/OUT 0.26fF -C1041 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C1042 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1043 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF -C1044 divider_1/tspc_1/a_630_n680# divider_1/nor_1/B 0.00fF -C1045 divider_0/and_0/out1 divider_0/and_0/B 0.18fF -C1046 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF -C1047 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF -C1048 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF -C1049 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.31fF -C1050 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/nor_0/A 0.55fF -C1051 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C1052 divider_2/nor_1/B divider_2/Out 0.22fF -C1053 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/Q 0.19fF -C1054 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.01fF -C1055 divider_1/nor_1/B divider_1/and_0/B 0.29fF -C1056 divbuf_23/OUT5 divbuf_23/OUT 43.38fF -C1057 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z2 0.71fF -C1058 pd_1/DIV pd_1/R 0.51fF -C1059 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF -C1060 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF -C1061 divider_2/Out divider_2/tspc_0/Z3 0.05fF -C1062 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF -C1063 divbuf_9/a_492_n240# divbuf_9/OUT 0.00fF -C1064 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF -C1065 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1066 divbuf_15/OUT divbuf_15/a_492_n240# 0.00fF -C1067 divider_0/nor_0/B divider_0/and_0/B 0.31fF -C1068 divider_0/tspc_2/Q divider_0/nor_0/A 0.55fF -C1069 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF -C1070 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/v 1.30fF -C1071 io_clamp_low[0] io_analog[4] 0.53fF -C1072 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1073 divbuf_19/OUT2 divbuf_19/a_492_n240# 0.42fF -C1074 divider_1/tspc_0/Z2 divider_1/nor_0/B 0.20fF -C1075 divider_1/tspc_0/a_630_n680# divider_1/nor_1/B 0.35fF -C1076 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF -C1077 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF -C1078 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Q 0.51fF -C1079 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z4 0.36fF -C1080 divbuf_22/IN divbuf_22/OUT5 0.00fF -C1081 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.06fF -C1082 divider_1/tspc_2/a_630_n680# divider_1/nor_0/A 0.35fF -C1083 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.29fF -C1084 divbuf_12/a_492_n240# divbuf_12/IN 0.13fF -C1085 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF -C1086 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF -C1087 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF -C1088 divbuf_25/OUT4 divbuf_25/OUT 1.11fF -C1089 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/v 1.43fF -C1090 ro_complete_1/a2 ro_complete_1/cbank_1/switch_3/vin 0.09fF -C1091 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF -C1092 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF -C1093 divider_0/nor_0/B divider_0/tspc_1/Q 0.51fF -C1094 divider_1/prescaler_0/Out divider_1/tspc_2/a_630_n680# 0.01fF -C1095 divider_0/and_0/OUT divider_0/clk 0.04fF -C1096 divider_1/prescaler_0/tspc_1/Z2 divider_1/and_0/OUT 0.06fF -C1097 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF -C1098 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF -C1099 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF -C1100 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF -C1101 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/A 0.01fF -C1102 divider_1/and_0/out1 divider_1/and_0/A 0.01fF -C1103 divbuf_24/OUT2 divbuf_24/OUT3 1.37fF -C1104 cp_0/a_10_n50# cp_0/a_1710_0# 0.04fF -C1105 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/R 0.27fF -C1106 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF -C1107 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF -C1108 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/v 1.30fF -C1109 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF -C1110 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF -C1111 divider_0/tspc_2/Q divider_0/tspc_1/a_630_n680# 0.01fF -C1112 divbuf_18/OUT divbuf_18/a_492_n240# 0.00fF -C1113 divider_1/nor_1/Z1 divider_1/and_0/B 0.78fF -C1114 divider_0/nor_0/A divider_0/and_0/A 0.01fF -C1115 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF -C1116 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z2 1.07fF -C1117 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF -C1118 divbuf_10/OUT2 divbuf_10/OUT5 0.02fF -C1119 divbuf_10/OUT3 divbuf_10/OUT4 5.16fF -C1120 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_0/A 0.01fF -C1121 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z4 0.12fF -C1122 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF -C1123 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF -C1124 divbuf_23/a_492_n240# divbuf_23/OUT2 0.42fF -C1125 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF -C1126 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF -C1127 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF -C1128 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF -C1129 divbuf_13/OUT5 divbuf_13/OUT 43.38fF -C1130 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF -C1131 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF -C1132 divbuf_0/OUT5 divbuf_0/IN 0.00fF -C1133 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C1134 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1135 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_0/A 0.01fF -C1136 divider_0/prescaler_0/Out divider_0/tspc_2/Z4 0.12fF -C1137 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF -C1138 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.15fF -C1139 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C1140 divider_2/nor_1/B divider_2/nor_0/B 0.47fF -C1141 divider_2/tspc_0/Z2 divider_2/tspc_0/Z4 0.36fF -C1142 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/Z3 0.16fF -C1143 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF -C1144 divbuf_8/IN divbuf_8/OUT5 0.00fF -C1145 divider_2/mc2 divider_2/nor_0/A 0.04fF -C1146 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF -C1147 divbuf_25/a_492_n240# divbuf_25/IN 0.13fF -C1148 filter_0/a_4216_n5230# filter_0/v 0.19fF -C1149 divbuf_1/IN divbuf_1/OUT5 0.00fF -C1150 divbuf_0/a_492_n240# divbuf_0/OUT5 0.01fF -C1151 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/v 1.30fF -C1152 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF -C1153 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF -C1154 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF -C1155 ro_complete_1/a1 ro_complete_1/cbank_2/v 0.05fF -C1156 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF -C1157 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1158 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF -C1159 divider_1/nor_1/B divider_1/tspc_1/Q 0.22fF -C1160 divbuf_21/OUT3 divbuf_21/OUT5 0.01fF -C1161 divbuf_21/OUT2 divbuf_21/OUT 0.06fF -C1162 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C1163 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF -C1164 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z1 0.03fF -C1165 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/Z3 0.20fF -C1166 divbuf_19/OUT3 divbuf_19/OUT5 0.01fF -C1167 divider_2/nor_0/B divider_2/tspc_2/a_630_n680# 0.01fF -C1168 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/D 0.03fF -C1169 divbuf_14/OUT2 divbuf_14/OUT3 1.37fF -C1170 divbuf_1/OUT2 divbuf_1/OUT5 0.02fF -C1171 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a3 0.13fF -C1172 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF -C1173 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_0/a_630_n680# 0.04fF -C1174 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF -C1175 divbuf_3/OUT3 divbuf_3/OUT 0.26fF -C1176 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF -C1177 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1178 divbuf_17/OUT divbuf_17/OUT4 1.11fF -C1179 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF -C1180 divider_0/nor_0/A divider_0/tspc_2/Z1 0.03fF -C1181 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z4 0.08fF -C1182 divider_1/prescaler_0/tspc_2/Z2 divider_1/and_0/OUT 0.05fF -C1183 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF -C1184 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF -C1185 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF -C1186 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF -C1187 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF -C1188 pd_1/REF pd_1/tspc_r_1/Z4 0.02fF -C1189 pd_1/UP pd_1/tspc_r_1/Qbar 0.21fF -C1190 divbuf_13/a_492_n240# divbuf_13/OUT2 0.42fF -C1191 divider_2/prescaler_0/tspc_1/Q divider_2/nor_0/A 0.03fF -C1192 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C1193 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/v 1.30fF -C1194 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C1195 divider_0/mc2 divider_0/and_0/out1 0.06fF -C1196 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF -C1197 divbuf_4/OUT3 divbuf_4/OUT 0.26fF -C1198 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF -C1199 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_0/B 0.18fF -C1200 divider_1/tspc_2/Q divider_1/nor_0/B 0.22fF -C1201 divider_0/and_0/A divider_0/and_0/B 0.18fF -C1202 divider_1/tspc_1/Z2 divider_1/nor_0/A 0.15fF -C1203 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/D 0.32fF -C1204 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF -C1205 divider_1/nor_0/B divider_1/and_0/A 0.26fF -C1206 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C1207 pd_1/DIV pd_1/tspc_r_0/Z4 0.02fF -C1208 divider_2/prescaler_0/Out divider_2/tspc_2/a_630_n680# 0.01fF -C1209 divbuf_9/IN divbuf_9/OUT5 0.00fF -C1210 io_clamp_low[1] io_clamp_high[1] 0.53fF -C1211 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF -C1212 divider_0/mc2 divider_0/nor_0/B 0.06fF -C1213 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a1 0.14fF -C1214 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF -C1215 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF -C1216 pll_full_0/pd_0/REF pll_full_0/divbuf_0/OUT5 0.00fF -C1217 divbuf_1/OUT4 divbuf_1/OUT 1.11fF -C1218 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C1219 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF -C1220 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_0/z1 0.24fF -C1221 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF -C1222 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF -C1223 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF -C1224 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF -C1225 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF -C1226 divbuf_22/OUT3 divbuf_22/OUT5 0.01fF -C1227 divbuf_22/OUT2 divbuf_22/OUT 0.06fF -C1228 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF -C1229 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.26fF -C1230 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF -C1231 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z1 0.09fF -C1232 divider_2/mc2 divider_2/and_0/B 0.20fF -C1233 pll_full_0/pd_0/DIV pll_full_0/divbuf_1/OUT3 0.26fF -C1234 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF -C1235 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF -C1236 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z2 0.19fF -C1237 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a1 0.14fF -C1238 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.43fF -C1239 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1240 divider_1/prescaler_0/Out divider_1/nor_0/A 0.15fF -C1241 divbuf_15/OUT divbuf_15/OUT4 1.11fF -C1242 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF -C1243 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.26fF -C1244 divbuf_20/a_492_n240# divbuf_20/OUT5 0.01fF -C1245 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_1/Z3 0.05fF -C1246 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF -C1247 pll_full_0/divbuf_1/IN pll_full_0/divider_0/nor_1/B 0.27fF -C1248 divbuf_17/OUT divbuf_17/OUT3 0.26fF -C1249 divider_1/tspc_1/Q divider_1/tspc_0/Z1 0.01fF -C1250 divider_1/mc2 divider_1/nor_0/A 0.04fF -C1251 divider_1/tspc_1/Z1 divider_1/tspc_1/Z2 1.07fF -C1252 divider_1/nor_0/B divider_1/tspc_1/Z3 0.38fF -C1253 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF -C1254 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF -C1255 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF -C1256 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF -C1257 divbuf_24/OUT2 divbuf_24/OUT5 0.02fF -C1258 divbuf_24/OUT3 divbuf_24/OUT4 5.16fF -C1259 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Z4 0.65fF -C1260 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C1261 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C1262 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF -C1263 divbuf_15/OUT2 divbuf_15/OUT 0.06fF -C1264 divider_0/tspc_1/Q divider_0/tspc_1/Z3 0.05fF -C1265 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF -C1266 divider_0/Out divider_0/nor_1/B 0.22fF -C1267 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF -C1268 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF -C1269 divbuf_19/OUT2 divbuf_19/OUT3 1.37fF -C1270 divider_1/nor_0/Z1 divider_1/and_0/A 0.80fF -C1271 divbuf_10/OUT3 divbuf_10/OUT 0.26fF -C1272 divbuf_10/OUT4 divbuf_10/OUT5 20.26fF -C1273 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF -C1274 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C1275 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.64fF -C1276 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF -C1277 divider_2/tspc_0/Z4 divider_2/nor_0/B 0.02fF -C1278 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF -C1279 pd_1/UP pd_1/and_pd_0/Z1 0.06fF -C1280 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF -C1281 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF -C1282 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF -C1283 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF -C1284 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.64fF -C1285 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF -C1286 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF -C1287 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF -C1288 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1289 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C1290 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.46fF -C1291 divider_2/nor_1/Z1 divider_2/nor_1/B 0.06fF -C1292 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z2 0.01fF -C1293 divider_1/tspc_2/Q divider_1/tspc_1/Z3 0.45fF -C1294 divider_1/tspc_0/Z3 divider_1/tspc_0/a_630_n680# 0.05fF -C1295 pll_full_0/divider_0/tspc_1/Z4 pll_full_0/divider_0/nor_0/A 0.02fF -C1296 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/Z4 0.36fF -C1297 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/Out 0.05fF -C1298 divbuf_8/OUT3 divbuf_8/OUT5 0.01fF -C1299 divbuf_8/OUT2 divbuf_8/OUT 0.06fF -C1300 pd_1/tspc_r_0/Z2 pd_1/R 0.21fF -C1301 pd_0/R pd_0/and_pd_0/Out1 0.33fF -C1302 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF -C1303 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF -C1304 divider_2/nor_0/B divider_2/tspc_1/Z2 0.30fF -C1305 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF -C1306 divider_2/and_0/out1 divider_2/and_0/B 0.18fF -C1307 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1308 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF -C1309 pll_full_0/pd_0/REF pll_full_0/divbuf_0/a_492_n240# 0.13fF -C1310 divider_2/tspc_1/Q divider_2/tspc_0/Z2 0.14fF -C1311 divbuf_16/a_492_n240# divbuf_16/IN 0.13fF -C1312 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/D 0.05fF -C1313 divider_0/tspc_1/Z4 divider_0/nor_0/A 0.02fF -C1314 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF -C1315 divbuf_21/OUT4 divbuf_21/OUT 1.11fF -C1316 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_0/Z4 0.02fF -C1317 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C1318 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF -C1319 divbuf_11/a_492_n240# divbuf_11/OUT5 0.01fF -C1320 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF -C1321 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF -C1322 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z3 0.38fF -C1323 divider_1/nor_0/A divider_1/and_0/B 0.08fF -C1324 pd_1/DOWN pd_1/UP 0.46fF -C1325 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Qbar1 0.20fF -C1326 divbuf_19/OUT4 divbuf_19/OUT 1.11fF -C1327 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF -C1328 divider_2/nor_0/B divider_2/nor_0/A 1.21fF -C1329 ro_complete_1/a4 ro_complete_1/cbank_1/switch_1/vin 0.09fF -C1330 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF -C1331 divbuf_14/OUT2 divbuf_14/OUT5 0.02fF -C1332 divbuf_14/OUT3 divbuf_14/OUT4 5.16fF -C1333 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF -C1334 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Z1 0.06fF -C1335 divider_0/nor_0/B divider_0/tspc_0/Z4 0.02fF -C1336 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF -C1337 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z3 0.05fF -C1338 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF -C1339 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF -C1340 divider_0/nor_0/A divider_0/tspc_2/Z3 0.38fF -C1341 divbuf_3/OUT5 divbuf_3/OUT 43.38fF -C1342 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C1343 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF -C1344 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C1345 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF -C1346 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Q 0.20fF -C1347 divider_1/mc2 divider_1/and_0/B 0.20fF -C1348 divbuf_7/OUT3 divbuf_7/OUT 0.26fF -C1349 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF -C1350 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF -C1351 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF -C1352 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF -C1353 divider_2/and_0/OUT divider_2/clk 0.04fF -C1354 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF -C1355 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF -C1356 ro_complete_1/a2 ro_complete_1/cbank_1/v 0.05fF -C1357 divbuf_15/IN divbuf_15/a_492_n240# 0.13fF -C1358 divider_0/mc2 divider_0/and_0/A 0.16fF -C1359 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF -C1360 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF -C1361 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C1362 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1363 divbuf_4/OUT5 divbuf_4/OUT 43.38fF -C1364 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF -C1365 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF -C1366 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C1367 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF -C1368 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF -C1369 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/tspc_0/D 0.04fF -C1370 pd_0/R pd_0/tspc_r_1/Z2 0.21fF -C1371 divider_2/prescaler_0/Out divider_2/nor_0/A 0.15fF -C1372 divider_2/nor_0/B divider_2/tspc_1/Z1 0.03fF -C1373 divbuf_9/OUT3 divbuf_9/OUT5 0.01fF -C1374 divbuf_9/OUT2 divbuf_9/OUT 0.06fF -C1375 divider_2/nor_0/A divider_2/and_0/A 0.01fF -C1376 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF -C1377 divider_1/prescaler_0/tspc_0/Z2 divider_1/and_0/OUT 0.06fF -C1378 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/Q 0.04fF -C1379 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF -C1380 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1381 divider_1/tspc_0/Z3 divider_1/tspc_1/Q 0.45fF -C1382 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF -C1383 divbuf_21/a_492_n240# divbuf_21/IN 0.13fF -C1384 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/B 0.03fF -C1385 divbuf_22/OUT4 divbuf_22/OUT 1.11fF -C1386 divider_2/tspc_0/Z2 divider_2/tspc_0/a_630_n680# 0.01fF -C1387 divider_1/nor_0/A divider_1/tspc_2/Z2 0.23fF -C1388 divbuf_12/a_492_n240# divbuf_12/OUT5 0.01fF -C1389 pd_1/DOWN pd_1/tspc_r_0/z5 0.03fF -C1390 pd_0/UP pd_0/and_pd_0/Z1 0.06fF -C1391 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_0/A 0.01fF -C1392 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF -C1393 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.15fF -C1394 ro_complete_1/a2 ro_complete_1/cbank_0/switch_2/vin 0.14fF -C1395 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF -C1396 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF -C1397 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF -C1398 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF -C1399 divider_1/prescaler_0/Out divider_1/tspc_2/Z2 0.11fF -C1400 divbuf_15/OUT divbuf_15/OUT3 0.26fF -C1401 divider_1/nor_0/B divider_1/tspc_1/Z4 0.21fF -C1402 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF -C1403 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF -C1404 divbuf_20/OUT2 divbuf_20/OUT3 1.37fF -C1405 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C1406 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF -C1407 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.03fF -C1408 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF -C1409 divbuf_24/OUT3 divbuf_24/OUT 0.26fF -C1410 divbuf_24/OUT4 divbuf_24/OUT5 20.26fF -C1411 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF -C1412 pd_1/REF pd_1/tspc_r_1/Z3 0.65fF -C1413 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF -C1414 divider_2/nor_0/B divider_2/and_0/B 0.31fF -C1415 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_4/vin 0.20fF -C1416 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C1417 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF -C1418 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF -C1419 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C1420 divbuf_15/OUT2 divbuf_15/a_492_n240# 0.42fF -C1421 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF -C1422 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF -C1423 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF -C1424 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF -C1425 divbuf_10/OUT5 divbuf_10/OUT 43.38fF -C1426 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C1427 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF -C1428 divider_2/mc2 divider_2/and_0/OUT 0.05fF -C1429 divider_2/Out divider_2/tspc_0/a_630_n680# 0.04fF -C1430 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF -C1431 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF -C1432 divbuf_23/a_492_n240# divbuf_23/OUT 0.00fF -C1433 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF -C1434 divider_2/nor_0/A divider_2/tspc_2/Z1 0.03fF -C1435 divbuf_2/OUT3 divbuf_2/OUT 0.26fF -C1436 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/a0 0.09fF -C1437 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C1438 divbuf_16/a_492_n240# divbuf_16/OUT 0.00fF -C1439 divider_1/tspc_0/Z4 divider_1/nor_1/B 0.22fF -C1440 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF -C1441 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF -C1442 divbuf_5/IN divbuf_5/OUT5 0.00fF -C1443 divbuf_17/OUT divbuf_17/OUT5 43.38fF -C1444 divider_2/tspc_1/Q divider_2/nor_0/B 0.51fF -C1445 divider_1/tspc_2/Q divider_1/tspc_1/Z4 0.15fF -C1446 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/a_630_n680# 0.19fF -C1447 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divbuf_1/IN 0.04fF -C1448 divider_2/nor_0/Z1 divider_2/and_0/B 0.18fF -C1449 divbuf_22/a_492_n240# divbuf_22/IN 0.13fF -C1450 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.45fF -C1451 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z4 0.14fF -C1452 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF -C1453 divbuf_18/a_492_n240# divbuf_18/OUT2 0.42fF -C1454 divbuf_18/OUT5 divbuf_18/IN 0.00fF -C1455 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF -C1456 divbuf_8/OUT4 divbuf_8/OUT 1.11fF -C1457 divbuf_25/a_492_n240# divbuf_25/OUT5 0.01fF -C1458 divider_2/and_0/A divider_2/and_0/B 0.18fF -C1459 divider_0/tspc_0/a_630_n680# divider_0/Out 0.04fF -C1460 divbuf_0/OUT divbuf_0/OUT5 43.38fF -C1461 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF -C1462 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C1463 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/D 0.11fF -C1464 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.45fF -C1465 divider_1/tspc_2/Q divider_1/tspc_2/Z3 0.05fF -C1466 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C1467 divbuf_11/OUT2 divbuf_11/OUT3 1.37fF -C1468 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF -C1469 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z4 0.21fF -C1470 pd_1/R pd_1/tspc_r_1/Z3 0.29fF -C1471 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_0/z1 0.24fF -C1472 divbuf_14/OUT3 divbuf_14/OUT 0.26fF -C1473 divbuf_14/OUT4 divbuf_14/OUT5 20.26fF -C1474 divbuf_0/OUT3 divbuf_0/OUT 0.26fF -C1475 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF -C1476 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z1 0.00fF -C1477 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF -C1478 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF -C1479 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF -C1480 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C1481 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1482 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z4 0.12fF -C1483 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.14fF -C1484 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF -C1485 divider_0/nor_0/A divider_0/tspc_2/Z4 0.21fF -C1486 divbuf_10/a_492_n240# divbuf_10/OUT2 0.42fF -C1487 divider_1/tspc_1/Z3 divider_1/tspc_1/Z4 0.65fF -C1488 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Q 0.04fF -C1489 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C1490 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C1491 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C1492 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF -C1493 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.06fF -C1494 divbuf_7/OUT5 divbuf_7/OUT 43.38fF -C1495 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF -C1496 pd_1/UP pd_1/tspc_r_1/z5 0.03fF -C1497 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF -C1498 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF -C1499 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.26fF -C1500 divbuf_13/a_492_n240# divbuf_13/OUT 0.00fF -C1501 divbuf_18/OUT4 divbuf_18/OUT 1.11fF -C1502 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1503 divider_0/prescaler_0/Out divider_0/tspc_2/a_630_n680# 0.01fF -C1504 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF -C1505 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF -C1506 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_0/B 0.20fF -C1507 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Q 0.04fF -C1508 divider_0/and_0/B divider_0/and_0/Z1 0.07fF -C1509 divbuf_6/IN divbuf_6/OUT5 0.00fF -C1510 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/nand_1/z1 0.01fF -C1511 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF -C1512 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF -C1513 pd_1/DIV pd_1/tspc_r_0/Z3 0.65fF -C1514 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF -C1515 divider_2/prescaler_0/Out divider_2/tspc_2/Z2 0.11fF -C1516 divbuf_8/a_492_n240# divbuf_8/IN 0.13fF -C1517 io_clamp_low[0] io_clamp_high[0] 0.53fF -C1518 divbuf_9/OUT4 divbuf_9/OUT 1.11fF -C1519 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF -C1520 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF -C1521 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF -C1522 divider_1/tspc_0/Z4 divider_1/tspc_0/Z1 0.00fF -C1523 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF -C1524 ro_complete_1/a0 ro_complete_1/cbank_2/switch_4/vin 0.13fF -C1525 ro_complete_1/cbank_0/v ro_complete_1/cbank_1/v 1.27fF -C1526 divider_2/tspc_1/Q divider_2/tspc_1/Z3 0.05fF -C1527 divider_1/mc2 divider_1/and_0/OUT 0.05fF -C1528 divider_1/tspc_0/a_630_n680# divider_1/tspc_1/Q 0.01fF -C1529 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF -C1530 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/D 0.03fF -C1531 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF -C1532 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF -C1533 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF -C1534 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF -C1535 divbuf_12/OUT2 divbuf_12/OUT3 1.37fF -C1536 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/v 1.30fF -C1537 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF -C1538 pll_full_0/divbuf_0/OUT pll_full_0/divbuf_0/OUT3 0.26fF -C1539 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF -C1540 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF -C1541 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF -C1542 divbuf_20/OUT2 divbuf_20/OUT5 0.02fF -C1543 divbuf_20/OUT3 divbuf_20/OUT4 5.16fF -C1544 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C1545 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF -C1546 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C1547 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF -C1548 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF -C1549 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF -C1550 divider_2/nor_1/Z1 divider_2/and_0/B 0.78fF -C1551 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF -C1552 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF -C1553 divider_2/tspc_1/Z4 divider_2/nor_0/A 0.02fF -C1554 divbuf_24/OUT5 divbuf_24/OUT 43.38fF -C1555 divbuf_0/OUT divbuf_0/OUT4 1.11fF -C1556 divbuf_0/a_492_n240# divbuf_0/OUT2 0.42fF -C1557 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF -C1558 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF -C1559 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_2/D 0.16fF -C1560 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.03fF -C1561 ro_complete_1/a3 ro_complete_1/cbank_1/switch_2/vin 0.09fF -C1562 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/cbank_0/v 1.30fF -C1563 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.45fF -C1564 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF -C1565 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1566 divbuf_16/OUT5 divbuf_16/IN 0.00fF -C1567 divbuf_23/IN divbuf_23/OUT5 0.00fF -C1568 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF -C1569 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF -C1570 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Z1 0.02fF -C1571 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF -C1572 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF -C1573 divider_2/nor_0/A divider_2/tspc_2/Z3 0.38fF -C1574 divbuf_9/a_492_n240# divbuf_9/IN 0.13fF -C1575 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF -C1576 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF -C1577 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z4 0.01fF -C1578 divbuf_2/OUT5 divbuf_2/OUT 43.38fF -C1579 ro_complete_1/a3 ro_complete_1/cbank_1/v 0.05fF -C1580 io_clamp_high[2] io_analog[6] 0.53fF -C1581 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF -C1582 divbuf_5/OUT2 divbuf_5/OUT 0.06fF -C1583 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF -C1584 divider_2/nor_1/B divider_2/tspc_1/a_630_n680# 0.00fF -C1585 divider_1/and_0/OUT divider_1/and_0/B 0.01fF -C1586 pd_0/UP pd_0/tspc_r_1/z5 0.03fF -C1587 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF -C1588 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF -C1589 divbuf_25/OUT2 divbuf_25/OUT3 1.37fF -C1590 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF -C1591 divider_0/mc2 divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF -C1592 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF -C1593 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF -C1594 ro_complete_1/cbank_2/switch_0/vin ro_complete_1/cbank_2/v 1.45fF -C1595 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF -C1596 divbuf_11/OUT2 divbuf_11/OUT5 0.02fF -C1597 divbuf_11/OUT3 divbuf_11/OUT4 5.16fF -C1598 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF -C1599 divbuf_24/a_492_n240# divbuf_24/OUT2 0.42fF -C1600 pd_1/DOWN pd_1/tspc_r_1/Qbar 0.02fF -C1601 pd_1/R pd_1/UP 0.45fF -C1602 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/Q 0.04fF -C1603 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF -C1604 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF -C1605 divbuf_14/OUT5 divbuf_14/OUT 43.38fF -C1606 ro_complete_1/a4 ro_complete_1/cbank_2/v 0.05fF -C1607 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/a3 0.09fF -C1608 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF -C1609 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF -C1610 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.45fF -C1611 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/nor_0/A 0.15fF -C1612 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C1613 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF -C1614 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF -C1615 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF -C1616 divbuf_13/IN divbuf_13/OUT5 0.00fF -C1617 cp_0/a_1710_0# cp_0/out 0.84fF -C1618 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF -C1619 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C1620 divbuf_2/IN divbuf_2/a_492_n240# 0.13fF -C1621 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF -C1622 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C1623 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1624 divider_1/tspc_0/Z4 divider_1/tspc_0/Z3 0.65fF -C1625 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z1 0.08fF -C1626 divider_0/prescaler_0/Out divider_0/nor_0/A 0.15fF -C1627 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF -C1628 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.14fF -C1629 divider_0/nor_1/Z1 divider_0/and_0/B 0.78fF -C1630 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_1/Q 0.01fF -C1631 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF -C1632 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_1/z1 0.21fF -C1633 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF -C1634 divbuf_6/OUT2 divbuf_6/OUT 0.06fF -C1635 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF -C1636 divider_2/nor_0/B divider_2/tspc_2/Q 0.22fF -C1637 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF -C1638 divbuf_0/OUT3 divbuf_0/OUT5 0.01fF -C1639 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF -C1640 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF -C1641 divbuf_21/a_492_n240# divbuf_21/OUT5 0.01fF -C1642 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divbuf_1/IN 0.05fF -C1643 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C1644 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/A 0.80fF -C1645 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF -C1646 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF -C1647 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF -C1648 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/clk 0.05fF -C1649 pd_1/DOWN pd_1/tspc_r_0/Qbar1 0.11fF -C1650 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF -C1651 divbuf_12/OUT2 divbuf_12/OUT5 0.02fF -C1652 divbuf_12/OUT3 divbuf_12/OUT4 5.16fF -C1653 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF -C1654 divbuf_14/a_492_n240# divbuf_14/OUT2 0.42fF +C0 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF +C1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C2 divbuf_18/IN divbuf_18/OUT5 0.00fF +C3 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF +C4 divbuf_13/OUT2 divbuf_13/OUT3 1.37fF +C5 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF +C6 divider_0/mc2 divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF +C7 divider_0/nor_1/Z1 divider_0/nor_0/B 0.18fF +C8 divbuf_2/OUT4 divbuf_2/OUT 1.11fF +C9 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a1 0.14fF +C10 divbuf_25/OUT divbuf_25/OUT4 1.11fF +C11 divider_0/nor_1/B divider_0/tspc_0/Z1 0.03fF +C12 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF +C13 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF +C14 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z2 0.01fF +C15 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/Out 0.21fF +C16 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF +C17 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF +C18 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.45fF +C19 divbuf_21/OUT2 divbuf_21/OUT5 0.02fF +C20 divbuf_21/OUT3 divbuf_21/OUT4 5.16fF +C21 divbuf_12/a_492_n240# divbuf_12/OUT2 0.42fF +C22 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z1 0.09fF +C23 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z2 0.19fF +C24 divbuf_24/OUT5 divbuf_24/OUT 43.38fF +C25 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF +C26 divbuf_14/OUT divbuf_14/OUT5 43.38fF +C27 ro_complete_1/a5 ro_complete_1/cbank_2/switch_0/vin 0.09fF +C28 divider_2/tspc_1/Q divider_2/tspc_0/Z2 0.14fF +C29 pd_1/DIV pd_1/R 0.51fF +C30 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z2 0.71fF +C31 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF +C32 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF +C33 divider_2/tspc_1/Q divider_2/tspc_0/Z4 0.15fF +C34 divider_1/tspc_1/Z3 divider_1/nor_0/B 0.38fF +C35 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF +C36 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF +C37 divider_2/mc2 divider_2/nor_0/B 0.06fF +C38 divbuf_23/IN divbuf_23/OUT5 0.00fF +C39 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/R 0.27fF +C40 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Q 0.04fF +C41 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C42 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF +C43 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF +C44 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z4 0.12fF +C45 divider_0/prescaler_0/Out divider_0/tspc_2/Z2 0.11fF +C46 divider_0/tspc_0/Z3 divider_0/tspc_0/Z2 0.16fF +C47 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF +C48 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.14fF +C49 divider_0/nor_1/Z1 divider_0/and_0/B 0.78fF +C50 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C51 divider_1/nor_0/B divider_1/tspc_1/Q 0.51fF +C52 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF +C53 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF +C54 divbuf_10/OUT3 divbuf_10/OUT5 0.01fF +C55 divbuf_10/OUT2 divbuf_10/OUT 0.06fF +C56 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C57 divider_2/tspc_0/Z2 divider_2/nor_0/B 0.20fF +C58 divider_1/and_0/B divider_1/and_0/Z1 0.07fF +C59 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF +C60 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF +C61 divbuf_17/OUT5 divbuf_17/OUT 43.38fF +C62 divider_2/nor_0/B divider_2/tspc_0/Z4 0.02fF +C63 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/nand_1/z1 0.01fF +C64 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF +C65 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF +C66 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF +C67 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF +C68 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C69 divbuf_4/OUT3 divbuf_4/OUT 0.26fF +C70 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF +C71 cp_0/a_10_n50# cp_0/a_1710_0# 0.04fF +C72 pll_full_0/divbuf_0/IN pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF +C73 divider_1/tspc_0/Z1 divider_1/tspc_0/Z3 0.06fF +C74 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF +C75 divbuf_17/OUT4 divbuf_17/OUT 1.11fF +C76 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z2 0.01fF +C77 divider_2/tspc_2/Q divider_2/tspc_1/Z3 0.45fF +C78 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF +C79 divbuf_8/OUT2 divbuf_8/OUT5 0.02fF +C80 divbuf_8/OUT3 divbuf_8/OUT4 5.16fF +C81 io_clamp_low[1] io_clamp_high[1] 0.53fF +C82 divbuf_24/a_492_n240# divbuf_24/OUT2 0.42fF +C83 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF +C84 divider_0/Out divider_0/nor_1/B 0.22fF +C85 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF +C86 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF +C87 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/a0 0.13fF +C88 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF +C89 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF +C90 divider_0/prescaler_0/tspc_2/Q divider_0/clk 0.05fF +C91 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF +C92 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF +C93 divbuf_5/OUT3 divbuf_5/OUT 0.26fF +C94 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF +C95 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF +C96 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF +C97 divider_1/nor_1/B divider_1/nor_0/B 0.47fF +C98 divider_1/tspc_1/Z1 divider_1/tspc_1/Z2 1.07fF +C99 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z1 0.08fF +C100 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF +C101 divider_1/tspc_2/a_630_n680# divider_1/nor_0/A 0.35fF +C102 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF +C103 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/nor_0/A 0.03fF +C104 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/Z2 0.40fF +C105 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF +C106 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF +C107 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.00fF +C108 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF +C109 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF +C110 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF +C111 divbuf_1/OUT5 divbuf_1/OUT 43.38fF +C112 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF +C113 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF +C114 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF +C115 ro_complete_1/a1 ro_complete_1/cbank_1/v 0.05fF +C116 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF +C117 divider_0/and_0/out1 divider_0/and_0/B 0.18fF +C118 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF +C119 divider_1/mc2 divider_1/nor_0/A 0.04fF +C120 divider_1/tspc_0/Z1 divider_1/tspc_0/Z2 1.07fF +C121 divbuf_19/a_492_n240# divbuf_19/OUT2 0.42fF +C122 divbuf_17/OUT3 divbuf_17/OUT 0.26fF +C123 divbuf_11/OUT3 divbuf_11/OUT5 0.01fF +C124 divbuf_11/OUT2 divbuf_11/OUT 0.06fF +C125 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a5 0.09fF +C126 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF +C127 divider_0/nor_0/B divider_0/tspc_2/a_630_n680# 0.01fF +C128 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Q 0.05fF +C129 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF +C130 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF +C131 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF +C132 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/Z3 0.20fF +C133 divbuf_20/a_492_n240# divbuf_20/OUT5 0.01fF +C134 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_0/A 0.15fF +C135 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z3 0.45fF +C136 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z2 0.19fF +C137 divbuf_16/OUT divbuf_16/OUT3 0.26fF +C138 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF +C139 divider_1/nor_1/B divider_1/and_0/B 0.29fF +C140 divider_2/mc2 divider_2/and_0/out1 0.06fF +C141 divider_2/and_0/OUT divider_2/and_0/B 0.01fF +C142 divbuf_13/OUT2 divbuf_13/OUT5 0.02fF +C143 divbuf_13/OUT3 divbuf_13/OUT4 5.16fF +C144 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF +C145 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z4 0.01fF +C146 ro_complete_1/a4 ro_complete_1/cbank_2/switch_1/vin 0.09fF +C147 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/v 1.30fF +C148 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C149 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF +C150 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF +C151 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.04fF +C152 pd_1/REF pd_1/tspc_r_1/Z4 0.02fF +C153 pd_1/UP pd_1/tspc_r_1/Qbar 0.21fF +C154 divbuf_21/OUT3 divbuf_21/OUT 0.26fF +C155 divbuf_21/OUT4 divbuf_21/OUT5 20.26fF +C156 divider_1/tspc_0/Z2 divider_1/tspc_0/Z3 0.16fF +C157 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF +C158 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF +C159 divider_2/tspc_1/Z2 divider_2/nor_0/B 0.30fF +C160 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF +C161 divbuf_14/OUT divbuf_14/a_492_n240# 0.00fF +C162 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF +C163 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.06fF +C164 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF +C165 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C166 divbuf_15/OUT3 divbuf_15/OUT4 5.16fF +C167 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF +C168 ro_complete_1/a3 ro_complete_1/cbank_2/switch_2/vin 0.09fF +C169 pd_1/DIV pd_1/tspc_r_0/Z4 0.02fF +C170 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF +C171 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.18fF +C172 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C173 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C174 divider_1/tspc_0/Z4 divider_1/tspc_1/Q 0.15fF +C175 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z1 0.03fF +C176 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF +C177 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.64fF +C178 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF +C179 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C180 divbuf_23/OUT3 divbuf_23/OUT5 0.01fF +C181 divbuf_23/OUT2 divbuf_23/OUT 0.06fF +C182 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF +C183 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF +C184 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a3 0.13fF +C185 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF +C186 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF +C187 divbuf_3/OUT3 divbuf_3/OUT 0.26fF +C188 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/v 1.30fF +C189 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C190 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF +C191 divbuf_10/OUT4 divbuf_10/OUT 1.11fF +C192 divider_1/tspc_0/a_630_n680# divider_1/tspc_1/Q 0.01fF +C193 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF +C194 divbuf_22/a_492_n240# divbuf_22/OUT5 0.01fF +C195 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF +C196 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_1/z1 0.21fF +C197 divider_2/nor_0/B divider_2/and_0/A 0.26fF +C198 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF +C199 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF +C200 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/Q 0.19fF +C201 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.01fF +C202 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/v 1.30fF +C203 divider_1/tspc_0/Z4 divider_1/nor_1/B 0.22fF +C204 divbuf_4/OUT5 divbuf_4/OUT 43.38fF +C205 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C206 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C207 divbuf_8/OUT3 divbuf_8/OUT 0.26fF +C208 divbuf_8/OUT4 divbuf_8/OUT5 20.26fF +C209 divbuf_17/IN divbuf_17/OUT5 0.00fF +C210 divbuf_17/OUT2 divbuf_17/OUT 0.06fF +C211 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF +C212 divider_0/tspc_1/Z1 divider_0/nor_0/B 0.03fF +C213 divider_0/tspc_1/Z3 divider_0/tspc_1/a_630_n680# 0.05fF +C214 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.35fF +C215 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF +C216 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF +C217 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_4/vin 0.20fF +C218 divbuf_15/OUT divbuf_15/OUT4 1.11fF +C219 divider_0/nor_0/A divider_0/tspc_2/Z2 0.23fF +C220 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.29fF +C221 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF +C222 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C223 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF +C224 divider_1/nor_1/B divider_1/tspc_0/a_630_n680# 0.35fF +C225 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z3 0.11fF +C226 divbuf_5/OUT5 divbuf_5/OUT 43.38fF +C227 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF +C228 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.01fF +C229 pd_1/UP pd_1/and_pd_0/Z1 0.06fF +C230 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF +C231 divider_2/prescaler_0/Out divider_2/tspc_2/a_630_n680# 0.01fF +C232 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF +C233 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF +C234 divider_1/prescaler_0/tspc_2/Q divider_1/clk 0.05fF +C235 divider_2/nor_0/B divider_2/tspc_1/Z4 0.21fF +C236 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF +C237 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF +C238 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF +C239 divbuf_15/IN divbuf_15/OUT5 0.00fF +C240 divider_0/mc2 divider_0/and_0/out1 0.06fF +C241 divider_0/nor_0/B divider_0/nor_1/B 0.47fF +C242 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF +C243 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF +C244 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF +C245 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF +C246 divider_0/nor_0/Z1 divider_0/and_0/A 0.80fF +C247 ro_complete_1/a5 ro_complete_1/cbank_2/v 0.08fF +C248 pd_1/tspc_r_0/Z2 pd_1/R 0.21fF +C249 pd_0/R pd_0/and_pd_0/Out1 0.33fF +C250 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF +C251 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF +C252 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C253 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF +C254 divbuf_10/a_492_n240# divbuf_10/IN 0.13fF +C255 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF +C256 divbuf_11/OUT4 divbuf_11/OUT 1.11fF +C257 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/A 0.01fF +C258 divider_2/tspc_0/Z2 divider_2/tspc_0/Z1 1.07fF +C259 divider_2/nor_0/Z1 divider_2/and_0/A 0.80fF +C260 divider_1/and_0/out1 divider_1/and_0/B 0.18fF +C261 divbuf_9/a_492_n240# divbuf_9/OUT5 0.01fF +C262 divider_2/tspc_0/Z1 divider_2/tspc_0/Z4 0.00fF +C263 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF +C264 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF +C265 divider_0/Out divider_0/tspc_0/a_630_n680# 0.04fF +C266 divbuf_15/a_492_n240# divbuf_15/OUT 0.00fF +C267 divider_0/tspc_1/Q divider_0/tspc_0/Z1 0.01fF +C268 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF +C269 divider_0/nor_0/B divider_0/nor_0/A 1.21fF +C270 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF +C271 pd_1/DOWN pd_1/UP 0.46fF +C272 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Qbar1 0.20fF +C273 divider_1/nor_0/B divider_1/tspc_2/a_630_n680# 0.01fF +C274 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Q 0.05fF +C275 divider_1/prescaler_0/Out divider_1/clk 0.51fF +C276 divbuf_20/OUT2 divbuf_20/OUT3 1.37fF +C277 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_0/A 0.01fF +C278 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z4 0.12fF +C279 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF +C280 divbuf_13/OUT3 divbuf_13/OUT 0.26fF +C281 divbuf_13/OUT4 divbuf_13/OUT5 20.26fF +C282 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF +C283 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF +C284 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF +C285 divbuf_15/OUT2 divbuf_15/a_492_n240# 0.42fF +C286 ro_complete_1/a2 ro_complete_1/cbank_2/v 0.05fF +C287 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF +C288 divider_1/prescaler_0/m1_2700_2190# divider_1/and_0/OUT 0.14fF +C289 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF +C290 divider_0/nor_1/B divider_0/and_0/B 0.29fF +C291 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF +C292 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF +C293 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF +C294 divider_1/mc2 divider_1/nor_0/B 0.06fF +C295 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z3 0.06fF +C296 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF +C297 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C298 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF +C299 divbuf_21/OUT5 divbuf_21/OUT 43.38fF +C300 pll_full_0/divider_0/tspc_1/Z4 pll_full_0/divider_0/nor_0/A 0.02fF +C301 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_0/Z2 0.20fF +C302 divbuf_12/a_492_n240# divbuf_12/OUT 0.00fF +C303 divider_2/and_0/out1 divider_2/and_0/A 0.01fF +C304 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF +C305 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF +C306 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF +C307 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.35fF +C308 divider_0/tspc_1/Q divider_0/nor_1/B 0.22fF +C309 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF +C310 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/a0 0.09fF +C311 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C312 divbuf_15/OUT4 divbuf_15/OUT5 20.26fF +C313 divider_0/nor_0/A divider_0/and_0/B 0.08fF +C314 pd_0/R pd_0/tspc_r_1/Z2 0.21fF +C315 divbuf_6/IN divbuf_6/OUT5 0.00fF +C316 divbuf_19/OUT5 divbuf_19/IN 0.00fF +C317 divider_1/tspc_2/Q divider_1/tspc_1/Z4 0.15fF +C318 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_0/B 0.30fF +C319 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF +C320 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF +C321 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF +C322 divbuf_11/a_492_n240# divbuf_11/IN 0.13fF +C323 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF +C324 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF +C325 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z3 0.38fF +C326 divbuf_23/OUT4 divbuf_23/OUT 1.11fF +C327 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF +C328 divbuf_2/IN divbuf_2/a_492_n240# 0.13fF +C329 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT3 0.01fF +C330 divbuf_25/OUT3 divbuf_25/OUT5 0.01fF +C331 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.05fF +C332 divbuf_3/OUT5 divbuf_3/OUT 43.38fF +C333 divider_2/nor_1/B divider_2/tspc_1/a_630_n680# 0.00fF +C334 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/Out 0.05fF +C335 pd_1/DOWN pd_1/tspc_r_0/z5 0.03fF +C336 pd_0/UP pd_0/and_pd_0/Z1 0.06fF +C337 divider_1/tspc_2/Q divider_1/tspc_2/Z3 0.05fF +C338 divider_1/mc2 divider_1/and_0/B 0.20fF +C339 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.04fF +C340 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF +C341 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C342 divbuf_18/OUT2 divbuf_18/a_492_n240# 0.42fF +C343 divider_2/mc2 divider_2/nor_0/A 0.04fF +C344 divider_2/tspc_0/Z2 divider_2/tspc_0/Z3 0.16fF +C345 divbuf_22/OUT2 divbuf_22/OUT3 1.37fF +C346 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF +C347 divbuf_18/OUT5 divbuf_18/a_492_n240# 0.01fF +C348 divider_2/prescaler_0/tspc_1/Q divider_2/nor_0/A 0.03fF +C349 divider_2/tspc_0/Z3 divider_2/tspc_0/Z4 0.65fF +C350 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF +C351 divbuf_15/a_492_n240# divbuf_15/OUT5 0.01fF +C352 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/D 0.32fF +C353 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF +C354 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C355 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C356 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF +C357 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF +C358 pd_1/REF pd_1/tspc_r_1/Z3 0.65fF +C359 divbuf_21/a_492_n240# divbuf_21/OUT2 0.42fF +C360 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/Q 0.19fF +C361 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.01fF +C362 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z2 0.14fF +C363 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C364 divbuf_8/OUT5 divbuf_8/OUT 43.38fF +C365 io_clamp_low[0] io_clamp_high[0] 0.53fF +C366 divbuf_24/a_492_n240# divbuf_24/OUT 0.00fF +C367 divider_0/tspc_1/Q divider_0/tspc_1/a_630_n680# 0.04fF +C368 divider_0/tspc_1/Z3 divider_0/nor_0/B 0.38fF +C369 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF +C370 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF +C371 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF +C372 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C373 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF +C374 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C375 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z4 0.28fF +C376 cp_0/a_1710_0# cp_0/out 0.84fF +C377 divbuf_7/IN divbuf_7/OUT5 0.00fF +C378 divider_2/prescaler_0/Out divider_2/nor_0/A 0.15fF +C379 divider_1/nor_0/A divider_1/tspc_2/Z2 0.23fF +C380 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.29fF +C381 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.06fF +C382 divbuf_23/a_492_n240# divbuf_23/IN 0.13fF +C383 divider_2/nor_1/B divider_2/tspc_1/Q 0.22fF +C384 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF +C385 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF +C386 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF +C387 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF +C388 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF +C389 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF +C390 ro_complete_1/a0 ro_complete_1/cbank_2/switch_4/vin 0.13fF +C391 ro_complete_1/cbank_0/v ro_complete_1/cbank_1/v 1.27fF +C392 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z4 0.14fF +C393 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF +C394 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF +C395 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_740_n680# 0.33fF +C396 divider_1/nor_0/B divider_1/tspc_0/Z2 0.20fF +C397 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Q 0.91fF +C398 divider_1/prescaler_0/tspc_1/Z2 divider_1/and_0/OUT 0.06fF +C399 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF +C400 divbuf_9/OUT2 divbuf_9/OUT3 1.37fF +C401 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C402 divider_0/tspc_0/Z4 divider_0/tspc_0/Z1 0.00fF +C403 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF +C404 divider_2/nor_1/B divider_2/nor_0/B 0.47fF +C405 pd_1/R pd_1/tspc_r_1/Z3 0.29fF +C406 divbuf_20/OUT2 divbuf_20/OUT5 0.02fF +C407 divbuf_20/OUT3 divbuf_20/OUT4 5.16fF +C408 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF +C409 divider_1/nor_0/B divider_1/nor_0/A 1.21fF +C410 divbuf_8/a_492_n240# divbuf_8/OUT2 0.42fF +C411 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF +C412 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF +C413 divider_2/nor_0/A divider_2/tspc_2/Z1 0.03fF +C414 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF +C415 divbuf_13/OUT5 divbuf_13/OUT 43.38fF +C416 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF +C417 divbuf_25/OUT3 divbuf_25/OUT 0.26fF +C418 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF +C419 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z1 0.08fF +C420 divider_0/mc2 divider_0/nor_1/B 0.15fF +C421 io_clamp_high[2] io_analog[6] 0.53fF +C422 divbuf_19/OUT4 divbuf_19/OUT5 20.26fF +C423 divbuf_16/OUT5 divbuf_16/a_492_n240# 0.01fF +C424 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_2/D 0.16fF +C425 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/cbank_0/v 1.30fF +C426 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C427 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C428 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF +C429 divider_1/tspc_2/Q divider_1/tspc_1/Z1 0.01fF +C430 divider_1/tspc_0/Z4 divider_1/tspc_0/Z1 0.00fF +C431 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF +C432 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z4 0.00fF +C433 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF +C434 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C435 pd_1/UP pd_1/tspc_r_1/z5 0.03fF +C436 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/A 0.26fF +C437 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF +C438 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF +C439 divbuf_12/IN divbuf_12/OUT5 0.00fF +C440 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/R 0.01fF +C441 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF +C442 divider_0/mc2 divider_0/nor_0/A 0.04fF +C443 divider_0/tspc_0/Z4 divider_0/nor_1/B 0.22fF +C444 divbuf_1/OUT divbuf_1/OUT3 0.26fF +C445 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C446 pd_1/DIV pd_1/tspc_r_0/Z3 0.65fF +C447 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF +C448 divbuf_19/OUT5 divbuf_19/OUT 43.38fF +C449 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z2 0.16fF +C450 divider_1/tspc_1/a_630_n680# divider_1/nor_0/B 0.35fF +C451 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF +C452 divbuf_6/OUT2 divbuf_6/OUT 0.06fF +C453 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C454 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF +C455 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z4 0.21fF +C456 divbuf_17/OUT4 divbuf_17/OUT5 20.26fF +C457 divider_1/nor_0/A divider_1/and_0/B 0.08fF +C458 divider_2/tspc_1/Z2 divider_2/nor_0/A 0.15fF +C459 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/D 0.03fF +C460 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF +C461 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT4 20.26fF +C462 divbuf_16/OUT5 divbuf_16/OUT 43.38fF +C463 divbuf_14/OUT divbuf_14/OUT3 0.26fF +C464 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Q 0.20fF +C465 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF +C466 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF +C467 divider_2/tspc_1/Q divider_2/tspc_1/a_630_n680# 0.04fF +C468 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C469 divider_1/tspc_0/Z4 divider_1/tspc_0/Z3 0.65fF +C470 divider_1/prescaler_0/tspc_2/Z2 divider_1/and_0/OUT 0.05fF +C471 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/nor_0/A 0.55fF +C472 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z4 0.21fF +C473 divbuf_22/OUT2 divbuf_22/OUT5 0.02fF +C474 divbuf_22/OUT3 divbuf_22/OUT4 5.16fF +C475 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF +C476 divbuf_13/a_492_n240# divbuf_13/OUT2 0.42fF +C477 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C478 divider_0/tspc_2/Q divider_0/tspc_1/Z2 0.14fF +C479 divider_0/tspc_0/a_630_n680# divider_0/tspc_1/Q 0.01fF +C480 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF +C481 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.05fF +C482 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C483 divbuf_14/OUT5 divbuf_14/OUT4 20.26fF +C484 divider_0/nor_0/B divider_0/and_0/B 0.31fF +C485 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/tspc_0/D 0.04fF +C486 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF +C487 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF +C488 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF +C489 divbuf_17/OUT3 divbuf_17/OUT5 0.01fF +C490 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z3 0.05fF +C491 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/D 0.32fF +C492 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF +C493 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF +C494 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C495 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.35fF +C496 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF +C497 divbuf_24/IN divbuf_24/OUT5 0.00fF +C498 divider_2/nor_0/A divider_2/and_0/A 0.01fF +C499 divbuf_1/OUT2 divbuf_1/OUT 0.06fF +C500 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF +C501 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF +C502 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF +C503 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF +C504 divider_0/tspc_1/Q divider_0/nor_0/B 0.51fF +C505 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF +C506 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C507 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF +C508 divbuf_17/OUT3 divbuf_17/OUT4 5.16fF +C509 divider_1/mc2 divider_1/and_0/OUT 0.05fF +C510 divider_1/tspc_0/Z4 divider_1/tspc_0/Z2 0.36fF +C511 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF +C512 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C513 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF +C514 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF +C515 cp_0/a_1710_0# cp_0/down 0.32fF +C516 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Z1 0.02fF +C517 divider_2/prescaler_0/Out divider_2/tspc_2/Z2 0.11fF +C518 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF +C519 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF +C520 divbuf_7/OUT2 divbuf_7/OUT 0.06fF +C521 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.26fF +C522 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_0/A 0.01fF +C523 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF +C524 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF +C525 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.43fF +C526 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF +C527 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF +C528 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C529 pd_0/UP pd_0/tspc_r_1/z5 0.03fF +C530 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_740_n680# 0.08fF +C531 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z2 0.01fF +C532 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF +C533 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF +C534 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/D 0.09fF +C535 divbuf_10/a_492_n240# divbuf_10/OUT5 0.01fF +C536 divbuf_9/OUT2 divbuf_9/OUT5 0.02fF +C537 divbuf_9/OUT3 divbuf_9/OUT4 5.16fF +C538 divider_2/tspc_1/Z4 divider_2/nor_0/A 0.02fF +C539 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C540 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C541 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF +C542 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF +C543 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF +C544 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF +C545 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF +C546 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF +C547 divider_2/tspc_1/Q divider_2/nor_0/B 0.51fF +C548 pd_1/DOWN pd_1/tspc_r_1/Qbar 0.02fF +C549 pd_1/R pd_1/UP 0.45fF +C550 divbuf_20/OUT3 divbuf_20/OUT 0.26fF +C551 divbuf_20/OUT4 divbuf_20/OUT5 20.26fF +C552 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C553 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.64fF +C554 divider_2/mc2 divider_2/and_0/B 0.20fF +C555 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF +C556 divbuf_18/a_492_n240# divbuf_18/OUT 0.00fF +C557 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF +C558 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF +C559 divider_2/nor_0/A divider_2/tspc_2/Z3 0.38fF +C560 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C561 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z3 0.11fF +C562 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF +C563 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF +C564 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/switch_5/vin 0.20fF +C565 io_clamp_low[1] io_analog[5] 0.53fF +C566 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF +C567 divider_2/nor_1/B divider_2/nor_1/Z1 0.06fF +C568 divbuf_16/IN divbuf_16/a_492_n240# 0.13fF +C569 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF +C570 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF +C571 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF +C572 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF +C573 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C574 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C575 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.46fF +C576 divider_1/tspc_2/Q divider_1/tspc_1/Z3 0.45fF +C577 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Z4 0.65fF +C578 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF +C579 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z2 1.07fF +C580 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF +C581 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF +C582 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF +C583 divbuf_12/OUT3 divbuf_12/OUT5 0.01fF +C584 divbuf_12/OUT2 divbuf_12/OUT 0.06fF +C585 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF +C586 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C587 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C588 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/v 1.30fF +C589 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF +C590 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF +C591 divbuf_6/OUT4 divbuf_6/OUT 1.11fF +C592 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C593 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF +C594 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z2 0.36fF +C595 divbuf_17/OUT2 divbuf_17/OUT5 0.02fF +C596 divbuf_11/a_492_n240# divbuf_11/OUT5 0.01fF +C597 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF +C598 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF +C599 divbuf_25/OUT2 divbuf_25/OUT3 1.37fF +C600 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF +C601 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Q 0.04fF +C602 divider_0/prescaler_0/Out divider_0/clk 0.51fF +C603 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF +C604 ro_complete_1/a0 ro_complete_1/cbank_2/switch_5/vin 0.09fF +C605 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C606 divider_2/nor_1/B divider_2/tspc_0/Z1 0.03fF +C607 pd_1/DOWN pd_1/tspc_r_0/Qbar1 0.11fF +C608 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF +C609 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C610 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z1 0.06fF +C611 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C612 divider_1/tspc_1/Z2 divider_1/nor_0/A 0.15fF +C613 divider_1/prescaler_0/Out divider_1/tspc_2/Z3 0.45fF +C614 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Q 0.20fF +C615 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF +C616 divbuf_22/OUT3 divbuf_22/OUT 0.26fF +C617 divbuf_22/OUT4 divbuf_22/OUT5 20.26fF +C618 divider_2/and_0/OUT divider_2/clk 0.04fF +C619 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF +C620 divider_0/mc2 divider_0/nor_0/B 0.06fF +C621 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF +C622 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF +C623 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF +C624 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/nand_1/z1 0.01fF +C625 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF +C626 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF +C627 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C628 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C629 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF +C630 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF +C631 pd_1/REF pd_1/tspc_r_1/Z1 0.17fF +C632 pd_1/tspc_r_1/Qbar1 pd_1/UP 0.11fF +C633 divbuf_21/a_492_n240# divbuf_21/OUT 0.00fF +C634 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C635 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF +C636 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF +C637 divider_1/nor_0/B divider_1/and_0/B 0.31fF +C638 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/tspc_0/D 0.04fF +C639 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF +C640 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF +C641 divbuf_24/OUT3 divbuf_24/OUT5 0.01fF +C642 divbuf_24/OUT2 divbuf_24/OUT 0.06fF +C643 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF +C644 divider_0/tspc_0/Z4 divider_0/nor_0/B 0.02fF +C645 divider_0/tspc_2/Q divider_0/tspc_1/Z4 0.15fF +C646 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF +C647 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF +C648 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF +C649 ro_complete_1/a4 ro_complete_1/cbank_1/v 0.05fF +C650 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C651 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF +C652 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/nor_0/B 0.22fF +C653 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/nor_1/B 0.38fF +C654 divbuf_17/a_492_n240# divbuf_17/OUT 0.00fF +C655 divbuf_17/OUT3 divbuf_17/OUT2 1.37fF +C656 divider_2/nor_1/B divider_2/Out 0.22fF +C657 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF +C658 divider_1/tspc_1/Z2 divider_1/tspc_1/a_630_n680# 0.01fF +C659 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF +C660 divbuf_7/OUT4 divbuf_7/OUT 1.11fF +C661 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF +C662 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.15fF +C663 divbuf_23/a_492_n240# divbuf_23/OUT5 0.01fF +C664 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF +C665 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF +C666 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF +C667 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF +C668 divbuf_14/OUT2 divbuf_14/OUT5 0.02fF +C669 divider_0/tspc_2/Q divider_0/tspc_2/Z3 0.05fF +C670 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C671 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF +C672 divider_0/mc2 divider_0/and_0/B 0.20fF +C673 divider_1/nor_0/Z1 divider_1/and_0/B 0.18fF +C674 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF +C675 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z3 0.25fF +C676 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF +C677 divbuf_10/OUT2 divbuf_10/OUT3 1.37fF +C678 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C679 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF +C680 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF +C681 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF +C682 filter_0/a_4216_n2998# filter_0/v 0.31fF +C683 divider_2/tspc_0/Z2 divider_2/tspc_0/a_630_n680# 0.01fF +C684 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z4 0.12fF +C685 divbuf_9/OUT3 divbuf_9/OUT 0.26fF +C686 divbuf_9/OUT4 divbuf_9/OUT5 20.26fF +C687 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF +C688 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C689 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF +C690 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF +C691 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF +C692 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF +C693 divbuf_25/a_492_n240# divbuf_25/IN 0.13fF +C694 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C695 divider_2/nor_1/B divider_2/tspc_0/Z3 0.38fF +C696 divbuf_4/IN divbuf_4/OUT5 0.00fF +C697 ro_complete_1/cbank_1/v ro_complete_1/cbank_2/v 1.36fF +C698 cp_0/a_1710_n2840# cp_0/a_1710_0# 0.83fF +C699 divbuf_20/OUT5 divbuf_20/OUT 43.38fF +C700 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C701 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF +C702 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF +C703 divbuf_8/a_492_n240# divbuf_8/OUT 0.00fF +C704 divbuf_18/IN divbuf_18/a_492_n240# 0.13fF +C705 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF +C706 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.03fF +C707 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF +C708 divider_2/nor_0/A divider_2/tspc_2/Z4 0.21fF +C709 divbuf_0/OUT5 divbuf_0/IN 0.00fF +C710 divider_0/tspc_1/Q divider_0/tspc_0/Z4 0.15fF +C711 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z4 0.28fF +C712 ro_complete_1/a5 ro_complete_1/cbank_1/switch_0/vin 0.09fF +C713 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/v 1.30fF +C714 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF +C715 divider_0/and_0/OUT divider_0/and_0/B 0.01fF +C716 pd_1/DIV pd_1/tspc_r_0/Z2 0.19fF +C717 pd_0/DOWN pd_0/R 0.36fF +C718 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF +C719 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF +C720 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF +C721 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C722 divider_1/tspc_0/Z4 divider_1/nor_0/B 0.02fF +C723 divbuf_5/IN divbuf_5/OUT5 0.00fF +C724 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF +C725 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.45fF +C726 divbuf_19/OUT5 divbuf_19/OUT2 0.02fF +C727 divbuf_19/OUT4 divbuf_19/OUT3 5.16fF +C728 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF +C729 divbuf_12/OUT4 divbuf_12/OUT 1.11fF +C730 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF +C731 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF +C732 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF +C733 divider_2/and_0/A divider_2/and_0/B 0.18fF +C734 ro_complete_1/a2 ro_complete_1/cbank_0/switch_3/vin 0.09fF +C735 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Q 0.91fF +C736 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C737 ro_complete_1/cbank_1/switch_2/vin ro_complete_1/cbank_1/v 1.30fF +C738 divbuf_19/OUT5 divbuf_19/a_492_n240# 0.01fF +C739 divbuf_16/OUT5 divbuf_16/OUT3 0.01fF +C740 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF +C741 divbuf_25/IN divbuf_25/OUT5 0.00fF +C742 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF +C743 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF +C744 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF +C745 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF +C746 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF +C747 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C748 divider_1/tspc_1/Z1 divider_1/tspc_1/Z4 0.00fF +C749 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C750 divbuf_11/OUT2 divbuf_11/OUT3 1.37fF +C751 divider_2/mc2 divider_2/and_0/OUT 0.05fF +C752 divider_2/nor_1/Z1 divider_2/nor_0/B 0.18fF +C753 divbuf_19/OUT divbuf_19/OUT3 0.26fF +C754 divider_2/nor_0/B divider_2/tspc_2/a_630_n680# 0.01fF +C755 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_0/z1 0.24fF +C756 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF +C757 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF +C758 divbuf_2/OUT5 divbuf_2/a_492_n240# 0.01fF +C759 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/v 1.30fF +C760 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF +C761 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/OUT3 1.37fF +C762 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C763 ro_complete_1/a0 ro_complete_1/cbank_2/v 0.05fF +C764 divider_2/tspc_1/Q divider_2/tspc_0/Z1 0.01fF +C765 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF +C766 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C767 divider_1/prescaler_0/Out divider_1/tspc_2/Z4 0.12fF +C768 divider_1/nor_1/B divider_1/Out 0.22fF +C769 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Q 0.04fF +C770 divbuf_20/a_492_n240# divbuf_20/OUT2 0.42fF +C771 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/nor_0/A 0.15fF +C772 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C773 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C774 divbuf_22/OUT5 divbuf_22/OUT 43.38fF +C775 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF +C776 divbuf_13/a_492_n240# divbuf_13/OUT 0.00fF +C777 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.26fF +C778 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF +C779 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C780 divbuf_2/OUT3 divbuf_2/OUT 0.26fF +C781 divbuf_25/a_492_n240# divbuf_25/OUT5 0.01fF +C782 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_1/z1 0.21fF +C783 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z3 0.33fF +C784 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z2 0.25fF +C785 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/nand_1/z1 0.01fF +C786 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF +C787 divbuf_21/IN divbuf_21/OUT5 0.00fF +C788 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF +C789 divbuf_12/a_492_n240# divbuf_12/IN 0.13fF +C790 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z1 0.17fF +C791 divbuf_24/OUT4 divbuf_24/OUT 1.11fF +C792 divbuf_3/OUT2 divbuf_3/a_492_n240# 0.42fF +C793 pd_0/R pd_0/tspc_r_1/Z3 0.29fF +C794 divider_1/tspc_1/Z2 divider_1/nor_0/B 0.30fF +C795 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF +C796 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF +C797 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/A 0.35fF +C798 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF +C799 divbuf_23/OUT2 divbuf_23/OUT3 1.37fF +C800 pll_full_0/pd_0/DIV pll_full_0/pd_0/R 0.51fF +C801 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF +C802 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/Out 0.04fF +C803 divbuf_14/OUT2 divbuf_14/a_492_n240# 0.42fF +C804 divider_0/tspc_0/Z3 divider_0/tspc_0/Z1 0.06fF +C805 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF +C806 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF +C807 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF +C808 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF +C809 ro_complete_1/a3 ro_complete_1/cbank_2/v 0.05fF +C810 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF +C811 divbuf_17/a_492_n240# divbuf_17/IN 0.13fF +C812 pd_1/tspc_r_0/Qbar pd_1/tspc_r_0/Qbar1 0.01fF +C813 divbuf_10/OUT2 divbuf_10/OUT5 0.02fF +C814 divbuf_10/OUT3 divbuf_10/OUT4 5.16fF +C815 divbuf_16/OUT divbuf_16/OUT4 1.11fF +C816 divider_1/tspc_2/Q divider_1/tspc_2/a_630_n680# 0.04fF +C817 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF +C818 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF +C819 filter_0/a_4216_n5230# filter_0/v 0.19fF +C820 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C821 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF +C822 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C823 divbuf_22/a_492_n240# divbuf_22/OUT2 0.42fF +C824 divbuf_9/OUT5 divbuf_9/OUT 43.38fF +C825 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF +C826 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/Out 0.21fF +C827 divbuf_0/OUT4 divbuf_0/OUT 1.11fF +C828 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF +C829 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF +C830 ro_complete_1/a4 ro_complete_1/cbank_1/switch_1/vin 0.09fF +C831 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.45fF +C832 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C833 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF +C834 divbuf_4/OUT2 divbuf_4/OUT 0.06fF +C835 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/a_630_n680# 0.05fF +C836 divider_2/tspc_1/Q divider_2/tspc_0/Z3 0.45fF +C837 divider_1/nor_1/Z1 divider_1/nor_1/B 0.06fF +C838 pd_1/R pd_1/tspc_r_1/Qbar 0.03fF +C839 divider_2/tspc_2/Q divider_2/tspc_1/Z2 0.14fF +C840 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF +C841 divbuf_8/IN divbuf_8/OUT5 0.00fF +C842 divbuf_24/a_492_n240# divbuf_24/IN 0.13fF +C843 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF +C844 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF +C845 divider_0/mc2 divider_0/and_0/OUT 0.05fF +C846 divider_0/tspc_0/Z3 divider_0/nor_1/B 0.38fF +C847 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF +C848 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF +C849 io_clamp_high[0] io_analog[4] 0.53fF +C850 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF +C851 ro_complete_1/a3 ro_complete_1/cbank_1/switch_2/vin 0.09fF +C852 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF +C853 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF +C854 divbuf_5/OUT2 divbuf_5/OUT 0.06fF +C855 divider_1/tspc_0/Z4 divider_1/tspc_0/a_630_n680# 0.12fF +C856 pd_1/UP pd_1/and_pd_0/Out1 0.33fF +C857 divider_1/and_0/OUT divider_1/and_0/B 0.01fF +C858 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/Z1 0.03fF +C859 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF +C860 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF +C861 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF +C862 divbuf_25/a_492_n240# divbuf_25/OUT 0.00fF +C863 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF +C864 ro_complete_1/a2 ro_complete_1/cbank_2/switch_3/vin 0.09fF +C865 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF +C866 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF +C867 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/a_740_n680# 0.19fF +C868 divider_0/and_0/out1 divider_0/and_0/A 0.01fF +C869 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF +C870 divbuf_1/OUT4 divbuf_1/OUT3 5.16fF +C871 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/switch_5/vin 0.20fF +C872 pd_1/tspc_r_0/Qbar pd_1/DOWN 0.21fF +C873 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF +C874 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF +C875 divider_1/tspc_1/Z3 divider_1/tspc_1/Z4 0.65fF +C876 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF +C877 divbuf_11/OUT2 divbuf_11/OUT5 0.02fF +C878 divbuf_11/OUT3 divbuf_11/OUT4 5.16fF +C879 divbuf_18/OUT2 divbuf_18/OUT3 1.37fF +C880 divbuf_18/OUT3 divbuf_18/OUT5 0.01fF +C881 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/Q 0.04fF +C882 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF +C883 divider_2/nor_0/B divider_2/nor_0/A 1.21fF +C884 divbuf_9/a_492_n240# divbuf_9/OUT2 0.42fF +C885 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF +C886 divider_0/tspc_0/Z3 divider_0/Out 0.05fF +C887 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/Out 0.11fF +C888 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.45fF +C889 pd_1/R pd_1/tspc_r_0/Qbar1 0.01fF +C890 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z2 0.11fF +C891 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C892 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF +C893 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z1 0.08fF +C894 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.06fF +C895 divbuf_13/IN divbuf_13/OUT5 0.00fF +C896 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF +C897 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C898 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF +C899 divider_0/prescaler_0/Out divider_0/prescaler_0/m1_2700_2190# 0.11fF +C900 divbuf_25/OUT divbuf_25/OUT5 43.38fF +C901 divider_0/prescaler_0/tspc_1/Q divider_0/nor_0/A 0.03fF +C902 divider_0/nor_1/B divider_0/tspc_0/Z2 0.40fF +C903 divbuf_2/OUT5 divbuf_2/OUT 43.38fF +C904 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF +C905 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF +C906 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C907 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C908 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF +C909 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z3 0.05fF +C910 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z4 0.08fF +C911 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF +C912 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_1/Q 0.45fF +C913 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF +C914 pd_1/R pd_1/and_pd_0/Z1 0.02fF +C915 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/Qbar 0.01fF +C916 divbuf_21/OUT3 divbuf_21/OUT5 0.01fF +C917 divbuf_21/OUT2 divbuf_21/OUT 0.06fF +C918 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_1/z1 0.21fF +C919 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF +C920 divider_2/tspc_1/Z1 divider_2/nor_0/B 0.03fF +C921 divider_2/tspc_2/Q divider_2/tspc_1/Z4 0.15fF +C922 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF +C923 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/switch_1/vin 0.19fF +C924 divbuf_0/a_492_n240# divbuf_0/IN 0.13fF +C925 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF +C926 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z2 0.01fF +C927 divbuf_14/OUT4 divbuf_14/OUT3 5.16fF +C928 ro_complete_1/a5 ro_complete_1/cbank_1/v 0.10fF +C929 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/cbank_0/v 1.30fF +C930 pd_0/R pd_0/UP 0.45fF +C931 divider_2/nor_1/B divider_2/and_0/B 0.29fF +C932 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF +C933 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C934 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/A 0.80fF +C935 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF +C936 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF +C937 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF +C938 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/clk 0.05fF +C939 divbuf_23/OUT2 divbuf_23/OUT5 0.02fF +C940 divbuf_23/OUT3 divbuf_23/OUT4 5.16fF +C941 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF +C942 divbuf_18/OUT4 divbuf_18/OUT3 5.16fF +C943 divider_2/tspc_2/Q divider_2/tspc_2/Z3 0.05fF +C944 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF +C945 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF +C946 divider_0/tspc_1/Z2 divider_0/nor_0/A 0.15fF +C947 divider_0/prescaler_0/Out divider_0/tspc_2/Z3 0.45fF +C948 pd_1/DOWN pd_1/R 0.36fF +C949 pd_0/UP pd_0/and_pd_0/Out1 0.33fF +C950 divbuf_16/OUT2 divbuf_16/a_492_n240# 0.42fF +C951 divider_1/tspc_2/Q divider_1/nor_0/A 0.55fF +C952 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF +C953 divbuf_10/OUT3 divbuf_10/OUT 0.26fF +C954 divbuf_10/OUT4 divbuf_10/OUT5 20.26fF +C955 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.00fF +C956 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C957 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C958 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF +C959 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.45fF +C960 divbuf_0/OUT5 divbuf_0/OUT 43.38fF +C961 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C962 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF +C963 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.04fF +C964 ro_complete_1/a2 ro_complete_1/cbank_1/v 0.05fF +C965 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF +C966 divbuf_4/OUT4 divbuf_4/OUT 1.11fF +C967 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C968 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C969 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF +C970 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF +C971 divbuf_8/OUT3 divbuf_8/OUT5 0.01fF +C972 divbuf_8/OUT2 divbuf_8/OUT 0.06fF +C973 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z3 0.05fF +C974 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF +C975 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF +C976 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF +C977 divider_0/tspc_1/Z2 divider_0/tspc_1/a_630_n680# 0.01fF +C978 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF +C979 ro_complete_1/a3 ro_complete_1/cbank_2/switch_1/vin 0.13fF +C980 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF +C981 divbuf_15/OUT divbuf_15/OUT3 0.26fF +C982 divider_0/nor_0/A divider_0/tspc_2/Z1 0.03fF +C983 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF +C984 divbuf_16/OUT divbuf_16/OUT2 0.06fF +C985 divider_1/tspc_2/Q divider_1/tspc_1/a_630_n680# 0.01fF +C986 divider_1/tspc_1/Z1 divider_1/tspc_1/Z3 0.06fF +C987 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z2 0.19fF +C988 divbuf_5/OUT4 divbuf_5/OUT 1.11fF +C989 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF +C990 cp_0/upbar cp_0/down 0.02fF +C991 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF +C992 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF +C993 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF +C994 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF +C995 divbuf_19/OUT2 divbuf_19/OUT3 1.37fF +C996 divider_2/and_0/B divider_2/and_0/Z1 0.07fF +C997 ro_complete_1/a2 ro_complete_1/cbank_0/switch_2/vin 0.14fF +C998 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a4 0.09fF +C999 divbuf_0/OUT divbuf_0/OUT2 0.06fF +C1000 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF +C1001 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF +C1002 divbuf_15/OUT2 divbuf_15/OUT3 1.37fF +C1003 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/v 1.30fF +C1004 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF +C1005 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C1006 divider_1/and_0/out1 divider_1/and_0/A 0.01fF +C1007 divider_1/tspc_0/Z3 divider_1/Out 0.05fF +C1008 divbuf_11/OUT3 divbuf_11/OUT 0.26fF +C1009 divbuf_11/OUT4 divbuf_11/OUT5 20.26fF +C1010 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF +C1011 divider_0/tspc_0/Z3 divider_0/tspc_0/a_630_n680# 0.05fF +C1012 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF +C1013 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C1014 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF +C1015 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF +C1016 divbuf_1/OUT5 divbuf_1/IN 0.00fF +C1017 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF +C1018 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C1019 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/D 0.03fF +C1020 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF +C1021 ro_complete_1/cbank_2/switch_2/vin ro_complete_1/cbank_2/v 1.30fF +C1022 divbuf_17/a_492_n240# divbuf_17/OUT5 0.01fF +C1023 divider_2/tspc_1/Q divider_2/tspc_1/Z3 0.05fF +C1024 divider_2/nor_1/B divider_2/tspc_0/a_630_n680# 0.35fF +C1025 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Z3 0.11fF +C1026 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z3 0.11fF +C1027 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.64fF +C1028 divbuf_20/a_492_n240# divbuf_20/OUT 0.00fF +C1029 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C1030 divbuf_13/OUT3 divbuf_13/OUT5 0.01fF +C1031 divbuf_13/OUT2 divbuf_13/OUT 0.06fF +C1032 divider_2/tspc_2/a_630_n680# divider_2/nor_0/A 0.35fF +C1033 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF +C1034 divbuf_15/IN divbuf_15/a_492_n240# 0.13fF +C1035 divbuf_25/OUT2 divbuf_25/a_492_n240# 0.42fF +C1036 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF +C1037 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF +C1038 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF +C1039 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C1040 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF +C1041 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z4 0.65fF +C1042 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C1043 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C1044 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z4 0.12fF +C1045 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF +C1046 cp_0/a_1710_n2840# cp_0/out 0.61fF +C1047 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF +C1048 pd_1/REF pd_1/tspc_r_1/z5 0.04fF +C1049 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF +C1050 divider_1/prescaler_0/tspc_1/Q divider_1/nor_0/A 0.03fF +C1051 divbuf_21/OUT4 divbuf_21/OUT 1.11fF +C1052 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF +C1053 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.01fF +C1054 divider_2/tspc_1/Z3 divider_2/nor_0/B 0.38fF +C1055 divider_2/tspc_0/Z1 divider_2/tspc_0/Z3 0.06fF +C1056 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_2/D 0.16fF +C1057 divbuf_12/a_492_n240# divbuf_12/OUT5 0.01fF +C1058 divbuf_15/OUT2 divbuf_15/OUT 0.06fF +C1059 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF +C1060 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF +C1061 divbuf_3/IN divbuf_3/OUT5 0.00fF +C1062 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C1063 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1064 divbuf_15/OUT3 divbuf_15/OUT5 0.01fF +C1065 divider_0/nor_0/A divider_0/and_0/A 0.01fF +C1066 pd_1/DIV pd_1/tspc_r_0/z5 0.04fF +C1067 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF +C1068 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/nor_0/B 0.03fF +C1069 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF +C1070 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF +C1071 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C1072 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C1073 divider_2/prescaler_0/Out divider_2/clk 0.51fF +C1074 divbuf_16/OUT4 divbuf_16/OUT3 5.16fF +C1075 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z2 0.23fF +C1076 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.29fF +C1077 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF +C1078 divbuf_23/OUT3 divbuf_23/OUT 0.26fF +C1079 divbuf_23/OUT4 divbuf_23/OUT5 20.26fF +C1080 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF +C1081 divbuf_25/OUT2 divbuf_25/OUT5 0.02fF +C1082 divbuf_25/OUT3 divbuf_25/OUT4 5.16fF +C1083 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_0/A 0.01fF +C1084 divider_0/prescaler_0/Out divider_0/tspc_2/Z4 0.12fF +C1085 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF +C1086 divbuf_0/a_492_n240# divbuf_0/OUT2 0.42fF +C1087 divbuf_3/OUT4 divbuf_3/OUT 1.11fF +C1088 ro_complete_1/a1 ro_complete_1/cbank_2/v 0.05fF +C1089 divbuf_10/OUT5 divbuf_10/OUT 43.38fF +C1090 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_1/B 0.47fF +C1091 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C1092 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C1093 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C1094 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C1095 divider_1/mc2 divider_1/and_0/A 0.16fF +C1096 divider_1/prescaler_0/Out divider_1/tspc_2/a_630_n680# 0.01fF +C1097 divbuf_22/a_492_n240# divbuf_22/OUT 0.00fF +C1098 divbuf_18/OUT3 divbuf_18/OUT 0.26fF +C1099 divider_2/nor_0/B divider_2/and_0/B 0.31fF +C1100 divider_2/tspc_0/Z3 divider_2/Out 0.05fF +C1101 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF +C1102 divbuf_0/OUT4 divbuf_0/OUT3 5.16fF +C1103 divider_0/tspc_0/Z3 divider_0/tspc_1/Q 0.45fF +C1104 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF +C1105 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF +C1106 divbuf_14/OUT2 divbuf_14/OUT3 1.37fF +C1107 divider_0/tspc_1/Z4 divider_0/nor_0/A 0.02fF +C1108 divider_0/nor_0/B divider_0/tspc_0/Z2 0.20fF +C1109 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C1110 divbuf_21/a_492_n240# divbuf_21/IN 0.13fF +C1111 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z1 0.01fF +C1112 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C1113 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_0/A 1.21fF +C1114 divbuf_8/OUT4 divbuf_8/OUT 1.11fF +C1115 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF +C1116 divbuf_24/a_492_n240# divbuf_24/OUT5 0.01fF +C1117 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF +C1118 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF +C1119 divider_0/tspc_1/Z2 divider_0/nor_0/B 0.30fF +C1120 divbuf_15/OUT divbuf_15/OUT5 43.38fF +C1121 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF +C1122 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF +C1123 divider_0/nor_0/A divider_0/tspc_2/Z3 0.38fF +C1124 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF +C1125 divider_1/tspc_2/Q divider_1/nor_0/B 0.22fF +C1126 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Out1 0.05fF +C1127 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF +C1128 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF +C1129 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.29fF +C1130 divider_1/nor_0/A divider_1/tspc_2/Z1 0.03fF +C1131 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF +C1132 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF +C1133 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.14fF +C1134 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF +C1135 divbuf_15/OUT2 divbuf_15/OUT5 0.02fF +C1136 divbuf_14/OUT divbuf_14/OUT4 1.11fF +C1137 divider_0/nor_0/Z1 divider_0/and_0/B 0.18fF +C1138 divider_0/tspc_2/Q divider_0/tspc_2/a_630_n680# 0.04fF +C1139 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF +C1140 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF +C1141 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF +C1142 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/v 1.43fF +C1143 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF +C1144 pd_0/REF pd_0/tspc_r_1/z5 0.04fF +C1145 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF +C1146 divbuf_10/a_492_n240# divbuf_10/OUT2 0.42fF +C1147 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF +C1148 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF +C1149 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_1/B 0.22fF +C1150 divider_1/tspc_1/Z3 divider_1/tspc_1/Q 0.05fF +C1151 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF +C1152 divbuf_11/OUT5 divbuf_11/OUT 43.38fF +C1153 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/B 0.08fF +C1154 divider_2/nor_0/Z1 divider_2/and_0/B 0.18fF +C1155 divbuf_9/a_492_n240# divbuf_9/OUT 0.00fF +C1156 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF +C1157 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF +C1158 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF +C1159 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF +C1160 divbuf_14/OUT5 divbuf_14/a_492_n240# 0.01fF +C1161 divider_0/tspc_1/Q divider_0/tspc_0/Z2 0.14fF +C1162 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF +C1163 divider_2/tspc_1/Q divider_2/tspc_0/a_630_n680# 0.01fF +C1164 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/switch_5/vin 0.20fF +C1165 cp_0/a_1710_n2840# cp_0/upbar 0.29fF +C1166 pd_1/R pd_1/REF 0.61fF +C1167 divbuf_20/IN divbuf_20/OUT5 0.00fF +C1168 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF +C1169 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z4 0.28fF +C1170 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/D 0.03fF +C1171 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF +C1172 divbuf_8/a_492_n240# divbuf_8/IN 0.13fF +C1173 divider_2/tspc_2/Q divider_2/tspc_1/a_630_n680# 0.01fF +C1174 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF +C1175 divbuf_13/OUT4 divbuf_13/OUT 1.11fF +C1176 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF +C1177 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF +C1178 divider_2/prescaler_0/tspc_2/Q divider_2/clk 0.05fF +C1179 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF +C1180 divbuf_25/OUT2 divbuf_25/OUT 0.06fF +C1181 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF +C1182 io_clamp_low[2] io_analog[6] 0.53fF +C1183 divbuf_17/a_492_n240# divbuf_17/OUT2 0.42fF +C1184 divider_0/and_0/OUT divider_0/clk 0.04fF +C1185 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF +C1186 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF +C1187 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C1188 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1189 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z3 0.16fF +C1190 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF +C1191 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C1192 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF +C1193 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF +C1194 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C1195 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Q 0.91fF +C1196 divbuf_12/OUT2 divbuf_12/OUT3 1.37fF +C1197 divider_2/tspc_0/Z2 divider_2/tspc_0/Z4 0.36fF +C1198 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF +C1199 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF +C1200 divbuf_16/OUT5 divbuf_16/IN 0.00fF +C1201 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF +C1202 divider_2/and_0/out1 divider_2/and_0/B 0.18fF +C1203 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF +C1204 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF +C1205 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF +C1206 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF +C1207 divbuf_19/OUT4 divbuf_19/OUT 1.11fF +C1208 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z1 0.06fF +C1209 divider_1/nor_1/B divider_1/tspc_1/Q 0.22fF +C1210 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF +C1211 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF +C1212 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.04fF +C1213 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/nor_0/B 0.38fF +C1214 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C1215 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C1216 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF +C1217 pd_1/and_pd_0/Out1 pd_1/and_pd_0/Z1 0.18fF +C1218 divbuf_11/a_492_n240# divbuf_11/OUT2 0.42fF +C1219 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF +C1220 divider_1/nor_0/A divider_1/and_0/A 0.01fF +C1221 divbuf_23/OUT5 divbuf_23/OUT 43.38fF +C1222 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Q 0.05fF +C1223 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF +C1224 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF +C1225 divbuf_2/OUT2 divbuf_2/a_492_n240# 0.42fF +C1226 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF +C1227 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF +C1228 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C1229 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.15fF +C1230 ro_complete_1/cbank_1/switch_5/vin ro_complete_1/cbank_1/v 1.30fF +C1231 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z4 0.65fF +C1232 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF +C1233 divider_1/prescaler_0/Out divider_1/nor_0/A 0.15fF +C1234 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C1235 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C1236 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C1237 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z4 0.01fF +C1238 divbuf_22/IN divbuf_22/OUT5 0.00fF +C1239 divbuf_13/a_492_n240# divbuf_13/IN 0.13fF +C1240 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/v 1.30fF +C1241 divider_0/tspc_2/Q divider_0/tspc_1/Z1 0.01fF +C1242 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF +C1243 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF +C1244 divbuf_1/OUT2 divbuf_1/OUT5 0.02fF +C1245 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF +C1246 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF +C1247 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C1248 divider_0/nor_0/B divider_0/and_0/A 0.26fF +C1249 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF +C1250 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF +C1251 pd_1/REF pd_1/tspc_r_1/Qbar1 0.12fF +C1252 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF +C1253 divbuf_16/OUT2 divbuf_16/OUT3 1.37fF +C1254 divider_1/tspc_1/Z4 divider_1/nor_0/A 0.02fF +C1255 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF +C1256 divider_2/tspc_2/Q divider_2/nor_0/B 0.22fF +C1257 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF +C1258 divider_2/nor_1/Z1 divider_2/and_0/B 0.78fF +C1259 divbuf_24/OUT2 divbuf_24/OUT3 1.37fF +C1260 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF +C1261 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF +C1262 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF +C1263 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C1264 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF +C1265 divider_0/nor_0/A divider_0/tspc_2/Z4 0.21fF +C1266 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF +C1267 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF +C1268 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF +C1269 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF +C1270 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF +C1271 divider_1/nor_0/A divider_1/tspc_2/Z3 0.38fF +C1272 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF +C1273 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF +C1274 divbuf_23/a_492_n240# divbuf_23/OUT2 0.42fF +C1275 divbuf_14/IN divbuf_14/OUT5 0.00fF +C1276 divider_0/tspc_2/Q divider_0/nor_0/A 0.55fF +C1277 divider_0/nor_0/B divider_0/tspc_1/Z4 0.21fF +C1278 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF +C1279 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/a_492_n240# 0.42fF +C1280 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF +C1281 ro_complete_1/a0 ro_complete_1/cbank_1/switch_5/vin 0.09fF +C1282 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1283 divider_0/and_0/A divider_0/and_0/B 0.18fF +C1284 pd_0/R pd_0/and_pd_0/Z1 0.02fF +C1285 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF +C1286 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_0/a_740_n680# 0.21fF +C1287 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z4 0.12fF +C1288 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF +C1289 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF +C1290 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/D 0.03fF +C1291 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/B 0.22fF +C1292 divbuf_18/OUT2 divbuf_18/OUT5 0.02fF +C1293 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF +C1294 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/Q 0.19fF +C1295 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.01fF +C1296 divbuf_9/IN divbuf_9/OUT5 0.00fF +C1297 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF +C1298 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF +C1299 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF +C1300 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF +C1301 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_0/z1 0.24fF +C1302 ro_complete_1/a2 ro_complete_1/cbank_2/switch_2/vin 0.14fF +C1303 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C1304 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF +C1305 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/v 1.30fF +C1306 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divbuf_0/IN 0.05fF +C1307 pd_1/R pd_1/tspc_r_1/Qbar1 0.30fF +C1308 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Qbar1 0.38fF +C1309 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF +C1310 divbuf_20/OUT3 divbuf_20/OUT5 0.01fF +C1311 divbuf_20/OUT2 divbuf_20/OUT 0.06fF +C1312 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF +C1313 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF +C1314 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C1315 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF +C1316 divider_2/mc2 divider_2/and_0/A 0.16fF +C1317 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF +C1318 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF +C1319 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF +C1320 divider_2/nor_0/A divider_2/tspc_2/Z2 0.23fF +C1321 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.29fF +C1322 divbuf_14/OUT divbuf_14/OUT2 0.06fF +C1323 divider_0/tspc_2/Q divider_0/tspc_1/a_630_n680# 0.01fF +C1324 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z2 0.19fF +C1325 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1326 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.26fF +C1327 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_0/vin 0.19fF +C1328 pd_0/DIV pd_0/R 0.51fF +C1329 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF +C1330 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.01fF +C1331 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C1332 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF +C1333 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF +C1334 divider_1/mc2 divider_1/prescaler_0/tspc_2/a_630_n680# 0.33fF +C1335 divider_1/nor_1/Z1 divider_1/nor_0/B 0.18fF +C1336 divider_1/tspc_2/Q divider_1/tspc_1/Z2 0.14fF +C1337 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z4 0.36fF +C1338 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/Out 0.05fF +C1339 cp_0/a_10_n50# cp_0/vbias 0.19fF +C1340 divider_1/and_0/OUT divider_1/clk 0.04fF +C1341 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.31fF +C1342 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF +C1343 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C1344 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF +C1345 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF +C1346 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF +C1347 divbuf_12/OUT2 divbuf_12/OUT5 0.02fF +C1348 divbuf_12/OUT3 divbuf_12/OUT4 5.16fF +C1349 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF +C1350 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1351 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF +C1352 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF +C1353 pd_1/DIV pd_1/tspc_r_0/Qbar1 0.12fF +C1354 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF +C1355 divbuf_6/OUT3 divbuf_6/OUT 0.26fF +C1356 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF +C1357 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.51fF +C1358 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C1359 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.58fF +C1360 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z1 0.00fF +C1361 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF +C1362 divbuf_18/OUT4 divbuf_18/OUT5 20.26fF +C1363 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF +C1364 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF +C1365 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF +C1366 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.64fF +C1367 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF +C1368 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF +C1369 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C1370 ro_complete_1/cbank_0/v ro_complete_1/cbank_2/v 0.04fF +C1371 pd_1/DOWN pd_1/tspc_r_0/Z3 0.03fF +C1372 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C1373 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C1374 divbuf_19/a_492_n240# divbuf_19/IN 0.13fF +C1375 divider_2/prescaler_0/Out divider_2/prescaler_0/m1_2700_2190# 0.11fF +C1376 divider_1/prescaler_0/Out divider_1/tspc_2/Z2 0.11fF +C1377 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.15fF +C1378 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.14fF +C1379 divider_1/nor_1/Z1 divider_1/and_0/B 0.78fF +C1380 divbuf_22/OUT3 divbuf_22/OUT5 0.01fF +C1381 divbuf_22/OUT2 divbuf_22/OUT 0.06fF +C1382 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF +C1383 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF +C1384 divbuf_0/OUT divbuf_0/OUT3 0.26fF +C1385 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF +C1386 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF +C1387 divider_0/tspc_2/Q divider_0/tspc_1/Z3 0.45fF +C1388 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF +C1389 divbuf_2/OUT2 divbuf_2/OUT 0.06fF +C1390 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1391 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF +C1392 pd_1/tspc_r_1/Z3 pd_1/UP 0.03fF +C1393 divbuf_21/a_492_n240# divbuf_21/OUT5 0.01fF +C1394 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF +C1395 divider_1/tspc_0/a_630_n680# divider_1/Out 0.04fF +C1396 divider_1/nor_0/B divider_1/and_0/A 0.26fF +C1397 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF +C1398 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF +C1399 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF +C1400 divider_2/nor_0/A divider_2/and_0/B 0.08fF +C1401 divbuf_24/OUT2 divbuf_24/OUT5 0.02fF +C1402 divbuf_24/OUT3 divbuf_24/OUT4 5.16fF +C1403 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF +C1404 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF +C1405 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF +C1406 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF +C1407 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF +C1408 divbuf_16/OUT5 divbuf_16/OUT4 20.26fF +C1409 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF +C1410 ro_complete_1/a4 ro_complete_1/cbank_2/switch_0/vin 0.12fF +C1411 pd_0/DOWN pd_0/UP 0.46fF +C1412 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF +C1413 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF +C1414 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF +C1415 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1416 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF +C1417 divbuf_7/OUT3 divbuf_7/OUT 0.26fF +C1418 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF +C1419 divider_2/prescaler_0/Out divider_2/tspc_2/Z3 0.45fF +C1420 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF +C1421 divider_1/nor_0/A divider_1/tspc_2/Z4 0.21fF +C1422 divider_2/tspc_2/Q divider_2/tspc_2/a_630_n680# 0.04fF +C1423 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.05fF +C1424 divbuf_2/IN divbuf_2/OUT5 0.00fF +C1425 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF +C1426 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF +C1427 divbuf_14/IN divbuf_14/a_492_n240# 0.13fF +C1428 divider_0/mc2 divider_0/and_0/A 0.16fF +C1429 divider_0/prescaler_0/Out divider_0/tspc_2/a_630_n680# 0.01fF +C1430 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF +C1431 divider_1/nor_0/Z1 divider_1/and_0/A 0.80fF +C1432 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF +C1433 ro_complete_1/a0 ro_complete_1/cbank_1/v 0.05fF +C1434 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z3 0.09fF +C1435 divider_1/tspc_0/Z1 divider_1/tspc_1/Q 0.01fF +C1436 divider_1/nor_0/B divider_1/tspc_1/Z4 0.21fF +C1437 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/D 0.05fF +C1438 divbuf_10/a_492_n240# divbuf_10/OUT 0.00fF +C1439 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1440 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF +C1441 divider_1/and_0/A divider_1/and_0/B 0.18fF +C1442 divbuf_9/OUT3 divbuf_9/OUT5 0.01fF +C1443 divbuf_9/OUT2 divbuf_9/OUT 0.06fF +C1444 divider_2/tspc_0/a_630_n680# divider_2/Out 0.04fF +C1445 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/D 0.32fF +C1446 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF +C1447 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF +C1448 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF +C1449 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C1450 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF +C1451 divbuf_1/OUT divbuf_1/OUT4 1.11fF +C1452 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_4/vin 0.20fF +C1453 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF +C1454 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF +C1455 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/Q 0.04fF +C1456 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF +C1457 divider_1/mc2 divider_1/nor_1/B 0.15fF +C1458 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF +C1459 ro_complete_1/cbank_2/switch_0/vin ro_complete_1/cbank_2/v 1.45fF +C1460 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_0/z1 0.24fF +C1461 divbuf_20/OUT4 divbuf_20/OUT 1.11fF +C1462 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1463 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF +C1464 divbuf_8/a_492_n240# divbuf_8/OUT5 0.01fF +C1465 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF +C1466 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF +C1467 io_clamp_low[2] io_clamp_high[2] 0.53fF +C1468 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/DOWN 0.21fF +C1469 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF +C1470 ro_complete_1/a2 ro_complete_1/cbank_1/switch_3/vin 0.09fF +C1471 divider_0/tspc_2/Q divider_0/nor_0/B 0.22fF +C1472 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF +C1473 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF +C1474 io_clamp_high[1] io_analog[5] 0.53fF +C1475 divbuf_14/OUT5 divbuf_14/OUT3 0.01fF +C1476 pd_1/DIV pd_1/tspc_r_0/Z1 0.17fF +C1477 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF +C1478 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF +C1479 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF +C1480 divider_1/nor_1/B divider_1/tspc_0/Z1 0.03fF +C1481 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z4 0.01fF +C1482 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF +C1483 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_0/B 0.18fF +C1484 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z4 0.12fF +C1485 divider_1/tspc_1/Q divider_1/tspc_0/Z3 0.45fF +C1486 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.26fF +C1487 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C1488 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF +C1489 divbuf_12/OUT3 divbuf_12/OUT 0.26fF +C1490 divbuf_12/OUT4 divbuf_12/OUT5 20.26fF +C1491 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF +C1492 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z3 0.05fF +C1493 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF +C1494 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF +C1495 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF +C1496 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF +C1497 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF +C1498 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF +C1499 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF +C1500 divbuf_3/OUT2 divbuf_3/OUT 0.06fF +C1501 ro_complete_1/a3 ro_complete_1/cbank_1/v 0.05fF +C1502 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C1503 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF +C1504 divbuf_16/OUT divbuf_16/a_492_n240# 0.00fF +C1505 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF +C1506 divider_1/prescaler_0/tspc_0/Z2 divider_1/and_0/OUT 0.06fF +C1507 divbuf_6/OUT5 divbuf_6/OUT 43.38fF +C1508 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_0/B 0.02fF +C1509 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF +C1510 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C1511 divbuf_11/a_492_n240# divbuf_11/OUT 0.00fF +C1512 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF +C1513 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a4 0.12fF +C1514 divbuf_19/OUT divbuf_19/OUT2 0.06fF +C1515 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF +C1516 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF +C1517 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_4/vin 0.20fF +C1518 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C1519 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF +C1520 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF +C1521 divbuf_20/a_492_n240# divbuf_20/IN 0.13fF +C1522 divbuf_19/a_492_n240# divbuf_19/OUT 0.00fF +C1523 divider_1/tspc_0/Z2 divider_1/tspc_1/Q 0.14fF +C1524 divider_1/nor_1/B divider_1/tspc_0/Z3 0.38fF +C1525 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF +C1526 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF +C1527 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/Z3 0.05fF +C1528 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z2 0.16fF +C1529 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1530 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C1531 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.14fF +C1532 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.78fF +C1533 divbuf_18/OUT2 divbuf_18/OUT 0.06fF +C1534 divbuf_22/OUT4 divbuf_22/OUT 1.11fF +C1535 divbuf_13/a_492_n240# divbuf_13/OUT5 0.01fF +C1536 divbuf_18/OUT5 divbuf_18/OUT 43.38fF +C1537 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF +C1538 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a1 0.14fF +C1539 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/a3 0.09fF +C1540 divider_2/nor_1/B divider_2/mc2 0.15fF +C1541 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.45fF +C1542 ro_complete_1/cbank_2/switch_5/vin ro_complete_1/cbank_2/v 1.30fF +C1543 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C1544 pd_1/R pd_1/and_pd_0/Out1 0.33fF +C1545 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z1 0.09fF +C1546 pd_1/REF pd_1/tspc_r_1/Z2 0.19fF +C1547 divbuf_21/OUT2 divbuf_21/OUT3 1.37fF +C1548 divbuf_24/OUT3 divbuf_24/OUT 0.26fF +C1549 divbuf_24/OUT4 divbuf_24/OUT5 20.26fF +C1550 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF +C1551 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF +C1552 divbuf_3/IN divbuf_3/a_492_n240# 0.13fF +C1553 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF +C1554 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/v 1.30fF +C1555 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1556 divider_2/nor_1/B divider_2/tspc_0/Z2 0.40fF +C1557 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_0/A 0.01fF +C1558 pd_0/R pd_0/REF 0.61fF +C1559 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF +C1560 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z4 0.15fF +C1561 pll_full_0/divbuf_0/IN pll_full_0/divider_0/nor_1/B 0.27fF +C1562 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF +C1563 divider_2/nor_1/B divider_2/tspc_0/Z4 0.22fF +C1564 divider_1/tspc_1/Z1 divider_1/nor_0/B 0.03fF +C1565 divider_1/tspc_1/Z3 divider_1/tspc_1/a_630_n680# 0.05fF +C1566 divider_1/nor_1/B divider_1/tspc_0/Z2 0.40fF +C1567 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF +C1568 divbuf_7/OUT5 divbuf_7/OUT 43.38fF +C1569 divider_2/mc2 divider_2/prescaler_0/tspc_2/a_630_n680# 0.33fF +C1570 divider_2/prescaler_0/Out divider_2/tspc_2/Z4 0.12fF +C1571 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF +C1572 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF +C1573 divider_2/tspc_2/Q divider_2/nor_0/A 0.55fF +C1574 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Q 0.20fF +C1575 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF +C1576 divbuf_23/a_492_n240# divbuf_23/OUT 0.00fF +C1577 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z3 0.05fF +C1578 divider_0/prescaler_0/Out divider_0/nor_0/A 0.15fF +C1579 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF +C1580 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF +C1581 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C1582 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF +C1583 divbuf_25/OUT4 divbuf_25/OUT5 20.26fF +C1584 divider_0/and_0/B divider_0/and_0/Z1 0.07fF +C1585 divbuf_10/IN divbuf_10/OUT5 0.00fF +C1586 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF +C1587 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C1588 divider_1/mc2 divider_1/and_0/out1 0.06fF +C1589 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Q 0.04fF +C1590 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF +C1591 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/D 0.11fF +C1592 divbuf_22/a_492_n240# divbuf_22/IN 0.13fF +C1593 divbuf_18/OUT4 divbuf_18/OUT 1.11fF +C1594 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/tspc_0/D 0.04fF +C1595 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF +C1596 divbuf_9/OUT4 divbuf_9/OUT 1.11fF +C1597 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF +C1598 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF +C1599 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF +C1600 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF +C1601 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF +C1602 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C1603 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF +C1604 divbuf_16/OUT5 divbuf_16/OUT2 0.02fF +C1605 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF +C1606 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF +C1607 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF +C1608 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF +C1609 pd_1/R pd_1/tspc_r_1/Z2 0.21fF +C1610 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/Q 0.04fF +C1611 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF +C1612 divbuf_8/OUT2 divbuf_8/OUT3 1.37fF +C1613 divider_2/tspc_2/Q divider_2/tspc_1/Z1 0.01fF +C1614 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF +C1615 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF +C1616 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF +C1617 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF +C1618 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF +C1619 io_clamp_low[0] io_analog[4] 0.53fF +C1620 divider_0/tspc_2/a_630_n680# divider_0/nor_0/A 0.35fF +C1621 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF +C1622 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF +C1623 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF +C1624 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF +C1625 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF +C1626 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF +C1627 divider_1/nor_1/B divider_1/tspc_1/a_630_n680# 0.00fF +C1628 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF +C1629 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C1630 divbuf_19/OUT5 divbuf_19/OUT3 0.01fF +C1631 divbuf_12/OUT5 divbuf_12/OUT 43.38fF +C1632 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF +C1633 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF +C1634 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF +C1635 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF +C1636 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_2/D 0.16fF +C1637 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.03fF +C1638 ro_complete_1/a4 ro_complete_1/cbank_2/v 0.05fF +C1639 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_0/vin 0.19fF +C1640 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF +C1641 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF +C1642 divider_1/tspc_1/Z2 divider_1/tspc_1/Z4 0.36fF +C1643 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C1644 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.11fF +C1645 divbuf_11/IN divbuf_11/OUT5 0.00fF +C1646 divbuf_9/a_492_n240# divbuf_9/IN 0.13fF +C1647 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF +C1648 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF +C1649 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF +C1650 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF +C1651 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C1652 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF +C1653 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF +C1654 pd_1/R pd_1/tspc_r_0/Z3 0.27fF Xpd_0 vssa1 vssa1 pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd Xpd_1 VDD vssa1 pd_1/REF pd_1/DIV pd_1/UP pd_1/DOWN pd_1/R pd Xcp_0 cp_0/vbias vssa1 gnd cp_0/out cp_0/down cp_0/upbar cp Xfilter_0 vssa1 filter_0/v filter Xro_complete_0 ro_complete_0/a0 ro_complete_0/a1 ro_complete_0/a5 ro_complete_0/a4 + ro_complete_0/a3 ro_complete_0/a2 ro_complete +Xdivbuf_0 vssa1 divbuf_0/IN divbuf_0/OUT divbuf_0/OUT2 divbuf_0/OUT3 divbuf_0/OUT4 ++ divbuf_0/OUT5 gnd divbuf Xro_complete_1 ro_complete_1/a0 ro_complete_1/a1 ro_complete_1/a5 ro_complete_1/a4 + ro_complete_1/a3 ro_complete_1/a2 ro_complete -Xdivbuf_0 vssa1 divbuf_0/IN divbuf_0/OUT divbuf_0/OUT2 divbuf_0/OUT3 divbuf_0/OUT4 -+ divbuf_0/OUT5 vssa1 divbuf Xdivbuf_1 vssa1 divbuf_1/IN divbuf_1/OUT divbuf_1/OUT2 divbuf_1/OUT3 divbuf_1/OUT4 -+ divbuf_1/OUT5 vssa1 divbuf ++ divbuf_1/OUT5 gnd divbuf Xdivbuf_2 vssa1 divbuf_2/IN divbuf_2/OUT divbuf_2/OUT2 divbuf_2/OUT3 divbuf_2/OUT4 -+ divbuf_2/OUT5 vssa1 divbuf ++ divbuf_2/OUT5 gnd divbuf Xdivbuf_3 vssa1 divbuf_3/IN divbuf_3/OUT divbuf_3/OUT2 divbuf_3/OUT3 divbuf_3/OUT4 -+ divbuf_3/OUT5 vssa1 divbuf -Xdivbuf_4 VDD divbuf_4/IN divbuf_4/OUT divbuf_4/OUT2 divbuf_4/OUT3 divbuf_4/OUT4 divbuf_4/OUT5 -+ vssa1 divbuf -Xdivbuf_5 VDD divbuf_5/IN divbuf_5/OUT divbuf_5/OUT2 divbuf_5/OUT3 divbuf_5/OUT4 divbuf_5/OUT5 -+ vssa1 divbuf -Xdivbuf_21 vssa1 divbuf_21/IN divbuf_21/OUT divbuf_21/OUT2 divbuf_21/OUT3 divbuf_21/OUT4 -+ divbuf_21/OUT5 gnd divbuf -Xdivbuf_20 vssa1 divbuf_20/IN divbuf_20/OUT divbuf_20/OUT2 divbuf_20/OUT3 divbuf_20/OUT4 -+ divbuf_20/OUT5 gnd divbuf ++ divbuf_3/OUT5 gnd divbuf +Xdivbuf_4 vssa1 divbuf_4/IN divbuf_4/OUT divbuf_4/OUT2 divbuf_4/OUT3 divbuf_4/OUT4 ++ divbuf_4/OUT5 gnd divbuf +Xdivbuf_5 vssa1 divbuf_5/IN divbuf_5/OUT divbuf_5/OUT2 divbuf_5/OUT3 divbuf_5/OUT4 ++ divbuf_5/OUT5 gnd divbuf +Xdivbuf_6 vssa1 divbuf_6/IN divbuf_6/OUT divbuf_6/OUT2 divbuf_6/OUT3 divbuf_6/OUT4 ++ divbuf_6/OUT5 gnd divbuf Xdivbuf_10 vssa1 divbuf_10/IN divbuf_10/OUT divbuf_10/OUT2 divbuf_10/OUT3 divbuf_10/OUT4 + divbuf_10/OUT5 gnd divbuf -Xdivbuf_6 VDD divbuf_6/IN divbuf_6/OUT divbuf_6/OUT2 divbuf_6/OUT3 divbuf_6/OUT4 divbuf_6/OUT5 -+ vssa1 divbuf -Xdivbuf_22 vssa1 divbuf_22/IN divbuf_22/OUT divbuf_22/OUT2 divbuf_22/OUT3 divbuf_22/OUT4 -+ divbuf_22/OUT5 gnd divbuf +Xdivbuf_20 VDD divbuf_20/IN divbuf_20/OUT divbuf_20/OUT2 divbuf_20/OUT3 divbuf_20/OUT4 ++ divbuf_20/OUT5 vssa1 divbuf +Xdivbuf_21 VDD divbuf_21/IN divbuf_21/OUT divbuf_21/OUT2 divbuf_21/OUT3 divbuf_21/OUT4 ++ divbuf_21/OUT5 vssa1 divbuf +Xdivbuf_7 vssa1 divbuf_7/IN divbuf_7/OUT divbuf_7/OUT2 divbuf_7/OUT3 divbuf_7/OUT4 ++ divbuf_7/OUT5 gnd divbuf Xdivbuf_11 vssa1 divbuf_11/IN divbuf_11/OUT divbuf_11/OUT2 divbuf_11/OUT3 divbuf_11/OUT4 + divbuf_11/OUT5 gnd divbuf -Xdivbuf_7 VDD divbuf_7/IN divbuf_7/OUT divbuf_7/OUT2 divbuf_7/OUT3 divbuf_7/OUT4 divbuf_7/OUT5 -+ vssa1 divbuf -Xdivbuf_23 vssa1 divbuf_23/IN divbuf_23/OUT divbuf_23/OUT2 divbuf_23/OUT3 divbuf_23/OUT4 -+ divbuf_23/OUT5 gnd divbuf +Xdivbuf_22 vssa1 divbuf_22/IN divbuf_22/OUT divbuf_22/OUT2 divbuf_22/OUT3 divbuf_22/OUT4 ++ divbuf_22/OUT5 vssa1 divbuf Xdivbuf_8 vssa1 divbuf_8/IN divbuf_8/OUT divbuf_8/OUT2 divbuf_8/OUT3 divbuf_8/OUT4 -+ divbuf_8/OUT5 vssa1 divbuf ++ divbuf_8/OUT5 gnd divbuf Xdivbuf_12 vssa1 divbuf_12/IN divbuf_12/OUT divbuf_12/OUT2 divbuf_12/OUT3 divbuf_12/OUT4 + divbuf_12/OUT5 gnd divbuf -Xdivbuf_24 vssa1 divbuf_24/IN divbuf_24/OUT divbuf_24/OUT2 divbuf_24/OUT3 divbuf_24/OUT4 -+ divbuf_24/OUT5 gnd divbuf +Xdivbuf_23 vssa1 divbuf_23/IN divbuf_23/OUT divbuf_23/OUT2 divbuf_23/OUT3 divbuf_23/OUT4 ++ divbuf_23/OUT5 vssa1 divbuf +Xdivbuf_9 vssa1 divbuf_9/IN divbuf_9/OUT divbuf_9/OUT2 divbuf_9/OUT3 divbuf_9/OUT4 ++ divbuf_9/OUT5 gnd divbuf Xdivbuf_13 vssa1 divbuf_13/IN divbuf_13/OUT divbuf_13/OUT2 divbuf_13/OUT3 divbuf_13/OUT4 + divbuf_13/OUT5 gnd divbuf -Xdivbuf_9 vssa1 divbuf_9/IN divbuf_9/OUT divbuf_9/OUT2 divbuf_9/OUT3 divbuf_9/OUT4 -+ divbuf_9/OUT5 vssa1 divbuf -Xdivbuf_25 vssa1 divbuf_25/IN divbuf_25/OUT divbuf_25/OUT2 divbuf_25/OUT3 divbuf_25/OUT4 -+ divbuf_25/OUT5 gnd divbuf +Xdivbuf_24 vssa1 divbuf_24/IN divbuf_24/OUT divbuf_24/OUT2 divbuf_24/OUT3 divbuf_24/OUT4 ++ divbuf_24/OUT5 vssa1 divbuf +Xdivider_0 gnd vdd divider_0/Out divider_0/clk divider_0/mc2 divider Xdivbuf_14 vssa1 divbuf_14/IN divbuf_14/OUT divbuf_14/OUT2 divbuf_14/OUT3 divbuf_14/OUT4 + divbuf_14/OUT5 gnd divbuf -Xdivider_0 gnd vdd divider_0/Out divider_0/clk divider_0/mc2 divider +Xdivbuf_25 vssa1 divbuf_25/IN divbuf_25/OUT divbuf_25/OUT2 divbuf_25/OUT3 divbuf_25/OUT4 ++ divbuf_25/OUT5 vssa1 divbuf Xdivbuf_15 vssa1 divbuf_15/IN divbuf_15/OUT divbuf_15/OUT2 divbuf_15/OUT3 divbuf_15/OUT4 + divbuf_15/OUT5 gnd divbuf Xdivider_1 vssa1 vssa1 divider_1/Out divider_1/clk divider_1/mc2 divider Xdivbuf_16 vssa1 divbuf_16/IN divbuf_16/OUT divbuf_16/OUT2 divbuf_16/OUT3 divbuf_16/OUT4 -+ divbuf_16/OUT5 gnd divbuf ++ divbuf_16/OUT5 vssa1 divbuf Xdivider_2 vssa1 vssa1 divider_2/Out divider_2/clk divider_2/mc2 divider Xdivbuf_17 vssa1 divbuf_17/IN divbuf_17/OUT divbuf_17/OUT2 divbuf_17/OUT3 divbuf_17/OUT4 -+ divbuf_17/OUT5 gnd divbuf -Xdivbuf_18 vssa1 divbuf_18/IN divbuf_18/OUT divbuf_18/OUT2 divbuf_18/OUT3 divbuf_18/OUT4 -+ divbuf_18/OUT5 gnd divbuf -Xdivbuf_19 vssa1 divbuf_19/IN divbuf_19/OUT divbuf_19/OUT2 divbuf_19/OUT3 divbuf_19/OUT4 -+ divbuf_19/OUT5 gnd divbuf ++ divbuf_17/OUT5 vssa1 divbuf +Xdivbuf_18 VDD divbuf_18/IN divbuf_18/OUT divbuf_18/OUT2 divbuf_18/OUT3 divbuf_18/OUT4 ++ divbuf_18/OUT5 vssa1 divbuf +Xdivbuf_19 VDD divbuf_19/IN divbuf_19/OUT divbuf_19/OUT2 divbuf_19/OUT3 divbuf_19/OUT4 ++ divbuf_19/OUT5 vssa1 divbuf Xpll_full_0 vssa1 pll_full C1655 io_analog[4] gnd 43.96fF C1656 io_analog[5] gnd 44.13fF @@ -2505,14 +2505,14 @@ C2332 pll_full_0/divider_0/tspc_1/a_630_n680# gnd 1.15fF **FLOATING C2333 pll_full_0/divider_0/tspc_2/Q gnd 3.14fF C2334 pll_full_0/divider_0/tspc_0/Z4 gnd 0.86fF -C2335 pll_full_0/divbuf_1/IN gnd 9.89fF +C2335 pll_full_0/divbuf_0/IN gnd 9.89fF C2336 pll_full_0/divider_0/tspc_0/Z3 gnd 2.26fF C2337 pll_full_0/divider_0/tspc_0/Z2 gnd 1.46fF C2338 pll_full_0/divider_0/tspc_0/Z1 gnd 0.99fF C2339 pll_full_0/divider_0/nor_1/B gnd 6.48fF C2340 pll_full_0/divider_0/tspc_0/a_630_n680# gnd 1.14fF **FLOATING C2341 pll_full_0/divider_0/tspc_1/Q gnd 3.12fF -C2342 pll_full_0/divider_0/clk gnd 33.52fF +C2342 pll_full_0/divider_0/clk gnd 33.42fF C2343 pll_full_0/divider_0/prescaler_0/nand_1/z1 gnd 0.36fF C2344 pll_full_0/divider_0/prescaler_0/tspc_0/D gnd 2.64fF C2345 pll_full_0/divider_0/prescaler_0/tspc_2/Q gnd 3.72fF @@ -2541,18 +2541,18 @@ C2368 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# gnd 2.11fF **FLOATING C2369 pll_full_0/divider_0/nor_1/Z1 gnd 1.34fF C2370 pll_full_0/divider_0/nor_0/Z1 gnd 1.34fF -C2371 pll_full_0/divbuf_1/OUT5 gnd 350.37fF -C2372 pll_full_0/divbuf_1/OUT4 gnd 133.72fF -C2373 pll_full_0/divbuf_1/OUT3 gnd 34.03fF -C2374 pll_full_0/divbuf_1/OUT2 gnd 8.71fF -C2375 pll_full_0/divbuf_1/a_492_n240# gnd 2.46fF **FLOATING -C2376 pll_full_0/divbuf_0/OUT gnd 363.82fF +C2371 pll_full_0/divbuf_1/OUT gnd 363.82fF +C2372 pll_full_0/divbuf_1/OUT5 gnd 350.37fF +C2373 pll_full_0/divbuf_1/OUT4 gnd 133.72fF +C2374 pll_full_0/divbuf_1/OUT3 gnd 34.03fF +C2375 pll_full_0/divbuf_1/OUT2 gnd 8.71fF +C2376 pll_full_0/divbuf_1/a_492_n240# gnd 2.46fF **FLOATING C2377 pll_full_0/divbuf_0/OUT5 gnd 350.37fF C2378 pll_full_0/divbuf_0/OUT4 gnd 133.72fF C2379 pll_full_0/divbuf_0/OUT3 gnd 34.03fF C2380 pll_full_0/divbuf_0/OUT2 gnd 8.71fF C2381 pll_full_0/divbuf_0/a_492_n240# gnd 2.46fF **FLOATING -C2382 pll_full_0/ro_complete_0/cbank_2/v gnd 16.46fF +C2382 pll_full_0/ro_complete_0/cbank_2/v gnd 16.43fF C2383 pll_full_0/ro_complete_0/cbank_2/switch_5/vin gnd 0.78fF C2384 pll_full_0/ro_complete_0/cbank_2/switch_4/vin gnd 1.50fF C2385 pll_full_0/ro_complete_0/cbank_2/switch_2/vin gnd 1.30fF @@ -2571,7 +2571,7 @@ C2398 pll_full_0/ro_complete_0/a4 gnd 5.81fF C2399 pll_full_0/ro_complete_0/cbank_1/switch_0/vin gnd 1.02fF C2400 pll_full_0/ro_complete_0/a5 gnd 6.74fF -C2401 pll_full_0/ro_complete_0/cbank_0/v gnd 15.14fF +C2401 pll_full_0/ro_complete_0/cbank_0/v gnd 15.12fF C2402 pll_full_0/ro_complete_0/cbank_0/switch_5/vin gnd 0.78fF C2403 pll_full_0/ro_complete_0/cbank_0/switch_4/vin gnd 1.50fF C2404 pll_full_0/ro_complete_0/cbank_0/switch_2/vin gnd 1.30fF @@ -2755,82 +2755,82 @@ C2582 divbuf_15/OUT2 gnd 8.71fF C2583 divbuf_15/IN gnd 0.89fF C2584 divbuf_15/a_492_n240# gnd 2.46fF **FLOATING -C2585 divider_0/and_0/Z1 gnd 0.74fF -C2586 divider_0/and_0/B gnd 2.25fF -C2587 divider_0/and_0/A gnd 2.19fF -C2588 divider_0/and_0/out1 gnd 2.93fF -C2589 divider_0/tspc_2/Z4 gnd 0.86fF -C2590 divider_0/tspc_2/Z3 gnd 2.26fF -C2591 divider_0/tspc_2/Z2 gnd 1.46fF -C2592 divider_0/tspc_2/Z1 gnd 0.99fF -C2593 divider_0/nor_0/A gnd 7.04fF -C2594 divider_0/tspc_2/a_630_n680# gnd 1.15fF **FLOATING -C2595 divider_0/tspc_1/Z4 gnd 0.86fF -C2596 divider_0/tspc_1/Z3 gnd 2.26fF -C2597 divider_0/tspc_1/Z2 gnd 1.46fF -C2598 divider_0/tspc_1/Z1 gnd 0.99fF -C2599 divider_0/nor_0/B gnd 7.05fF -C2600 divider_0/tspc_1/a_630_n680# gnd 1.15fF **FLOATING -C2601 divider_0/tspc_2/Q gnd 3.14fF -C2602 divider_0/tspc_0/Z4 gnd 0.86fF -C2603 divider_0/Out gnd 1.60fF -C2604 divider_0/tspc_0/Z3 gnd 2.26fF -C2605 divider_0/tspc_0/Z2 gnd 1.46fF -C2606 divider_0/tspc_0/Z1 gnd 0.99fF -C2607 divider_0/nor_1/B gnd 6.33fF -C2608 divider_0/tspc_0/a_630_n680# gnd 1.14fF **FLOATING -C2609 divider_0/tspc_1/Q gnd 3.12fF -C2610 divider_0/clk gnd 5.63fF -C2611 divider_0/prescaler_0/nand_1/z1 gnd 0.36fF -C2612 divider_0/prescaler_0/tspc_0/D gnd 2.64fF -C2613 divider_0/prescaler_0/tspc_2/Q gnd 3.64fF -C2614 divider_0/prescaler_0/tspc_1/Q gnd 3.61fF -C2615 divider_0/prescaler_0/nand_0/z1 gnd 0.36fF -C2616 divider_0/prescaler_0/tspc_2/D gnd 3.12fF -C2617 divider_0/and_0/OUT gnd 5.62fF -C2618 divider_0/prescaler_0/tspc_2/Z4 gnd 0.86fF -C2619 divider_0/prescaler_0/tspc_2/Z3 gnd 2.26fF -C2620 divider_0/prescaler_0/tspc_2/Z2 gnd 1.46fF -C2621 divider_0/prescaler_0/tspc_2/Z1 gnd 0.99fF -C2622 divider_0/prescaler_0/tspc_2/a_630_n680# gnd 1.14fF **FLOATING -C2623 divider_0/prescaler_0/tspc_2/a_740_n680# gnd 2.11fF **FLOATING -C2624 divider_0/prescaler_0/tspc_1/Z4 gnd 0.86fF -C2625 divider_0/prescaler_0/tspc_1/Z3 gnd 2.26fF -C2626 divider_0/prescaler_0/tspc_1/Z2 gnd 1.48fF -C2627 divider_0/prescaler_0/tspc_1/Z1 gnd 0.99fF -C2628 divider_0/prescaler_0/tspc_1/a_630_n680# gnd 1.14fF **FLOATING -C2629 divider_0/prescaler_0/m1_2700_2190# gnd 4.22fF **FLOATING -C2630 divider_0/prescaler_0/tspc_0/Z4 gnd 0.86fF -C2631 divider_0/prescaler_0/Out gnd 4.59fF -C2632 divider_0/prescaler_0/tspc_0/Z3 gnd 2.26fF -C2633 divider_0/prescaler_0/tspc_0/Z2 gnd 1.46fF -C2634 divider_0/prescaler_0/tspc_0/Z1 gnd 0.99fF -C2635 divider_0/prescaler_0/tspc_0/a_630_n680# gnd 1.16fF **FLOATING -C2636 divider_0/prescaler_0/tspc_0/a_740_n680# gnd 2.11fF **FLOATING -C2637 divider_0/nor_1/Z1 gnd 1.34fF -C2638 divider_0/mc2 gnd 5.29fF -C2639 divider_0/nor_0/Z1 gnd 1.34fF -C2640 divbuf_14/OUT gnd 363.82fF -C2641 divbuf_14/OUT5 gnd 350.37fF -C2642 divbuf_14/OUT4 gnd 133.72fF -C2643 divbuf_14/OUT3 gnd 34.03fF -C2644 divbuf_14/OUT2 gnd 8.71fF -C2645 divbuf_14/IN gnd 0.89fF -C2646 divbuf_14/a_492_n240# gnd 2.46fF **FLOATING -C2647 divbuf_25/OUT gnd 363.82fF -C2648 divbuf_25/OUT5 gnd 350.37fF -C2649 divbuf_25/OUT4 gnd 133.72fF -C2650 divbuf_25/OUT3 gnd 34.03fF -C2651 divbuf_25/OUT2 gnd 8.71fF -C2652 divbuf_25/IN gnd 0.89fF -C2653 divbuf_25/a_492_n240# gnd 2.46fF **FLOATING -C2654 divbuf_9/OUT gnd 363.82fF -C2655 divbuf_9/OUT5 gnd 350.37fF -C2656 divbuf_9/OUT4 gnd 133.72fF -C2657 divbuf_9/OUT3 gnd 34.03fF -C2658 divbuf_9/OUT2 gnd 8.71fF -C2659 divbuf_9/IN gnd 0.89fF -C2660 divbuf_9/a_492_n240# gnd 2.46fF **FLOATING +C2585 divbuf_25/OUT gnd 363.82fF +C2586 divbuf_25/OUT5 gnd 350.37fF +C2587 divbuf_25/OUT4 gnd 133.72fF +C2588 divbuf_25/OUT3 gnd 34.03fF +C2589 divbuf_25/OUT2 gnd 8.71fF +C2590 divbuf_25/IN gnd 0.89fF +C2591 divbuf_25/a_492_n240# gnd 2.46fF **FLOATING +C2592 divbuf_14/OUT gnd 363.82fF +C2593 divbuf_14/OUT5 gnd 350.37fF +C2594 divbuf_14/OUT4 gnd 133.72fF +C2595 divbuf_14/OUT3 gnd 34.03fF +C2596 divbuf_14/OUT2 gnd 8.71fF +C2597 divbuf_14/IN gnd 0.89fF +C2598 divbuf_14/a_492_n240# gnd 2.46fF **FLOATING +C2599 divider_0/and_0/Z1 gnd 0.74fF +C2600 divider_0/and_0/B gnd 2.25fF +C2601 divider_0/and_0/A gnd 2.19fF +C2602 divider_0/and_0/out1 gnd 2.93fF +C2603 divider_0/tspc_2/Z4 gnd 0.86fF +C2604 divider_0/tspc_2/Z3 gnd 2.26fF +C2605 divider_0/tspc_2/Z2 gnd 1.46fF +C2606 divider_0/tspc_2/Z1 gnd 0.99fF +C2607 divider_0/nor_0/A gnd 7.04fF +C2608 divider_0/tspc_2/a_630_n680# gnd 1.15fF **FLOATING +C2609 divider_0/tspc_1/Z4 gnd 0.86fF +C2610 divider_0/tspc_1/Z3 gnd 2.26fF +C2611 divider_0/tspc_1/Z2 gnd 1.46fF +C2612 divider_0/tspc_1/Z1 gnd 0.99fF +C2613 divider_0/nor_0/B gnd 7.05fF +C2614 divider_0/tspc_1/a_630_n680# gnd 1.15fF **FLOATING +C2615 divider_0/tspc_2/Q gnd 3.14fF +C2616 divider_0/tspc_0/Z4 gnd 0.86fF +C2617 divider_0/Out gnd 1.60fF +C2618 divider_0/tspc_0/Z3 gnd 2.26fF +C2619 divider_0/tspc_0/Z2 gnd 1.46fF +C2620 divider_0/tspc_0/Z1 gnd 0.99fF +C2621 divider_0/nor_1/B gnd 6.33fF +C2622 divider_0/tspc_0/a_630_n680# gnd 1.14fF **FLOATING +C2623 divider_0/tspc_1/Q gnd 3.12fF +C2624 divider_0/clk gnd 5.63fF +C2625 divider_0/prescaler_0/nand_1/z1 gnd 0.36fF +C2626 divider_0/prescaler_0/tspc_0/D gnd 2.64fF +C2627 divider_0/prescaler_0/tspc_2/Q gnd 3.64fF +C2628 divider_0/prescaler_0/tspc_1/Q gnd 3.61fF +C2629 divider_0/prescaler_0/nand_0/z1 gnd 0.36fF +C2630 divider_0/prescaler_0/tspc_2/D gnd 3.12fF +C2631 divider_0/and_0/OUT gnd 5.62fF +C2632 divider_0/prescaler_0/tspc_2/Z4 gnd 0.86fF +C2633 divider_0/prescaler_0/tspc_2/Z3 gnd 2.26fF +C2634 divider_0/prescaler_0/tspc_2/Z2 gnd 1.46fF +C2635 divider_0/prescaler_0/tspc_2/Z1 gnd 0.99fF +C2636 divider_0/prescaler_0/tspc_2/a_630_n680# gnd 1.14fF **FLOATING +C2637 divider_0/prescaler_0/tspc_2/a_740_n680# gnd 2.11fF **FLOATING +C2638 divider_0/prescaler_0/tspc_1/Z4 gnd 0.86fF +C2639 divider_0/prescaler_0/tspc_1/Z3 gnd 2.26fF +C2640 divider_0/prescaler_0/tspc_1/Z2 gnd 1.48fF +C2641 divider_0/prescaler_0/tspc_1/Z1 gnd 0.99fF +C2642 divider_0/prescaler_0/tspc_1/a_630_n680# gnd 1.14fF **FLOATING +C2643 divider_0/prescaler_0/m1_2700_2190# gnd 4.22fF **FLOATING +C2644 divider_0/prescaler_0/tspc_0/Z4 gnd 0.86fF +C2645 divider_0/prescaler_0/Out gnd 4.59fF +C2646 divider_0/prescaler_0/tspc_0/Z3 gnd 2.26fF +C2647 divider_0/prescaler_0/tspc_0/Z2 gnd 1.46fF +C2648 divider_0/prescaler_0/tspc_0/Z1 gnd 0.99fF +C2649 divider_0/prescaler_0/tspc_0/a_630_n680# gnd 1.16fF **FLOATING +C2650 divider_0/prescaler_0/tspc_0/a_740_n680# gnd 2.11fF **FLOATING +C2651 divider_0/nor_1/Z1 gnd 1.34fF +C2652 divider_0/mc2 gnd 5.29fF +C2653 divider_0/nor_0/Z1 gnd 1.34fF +C2654 divbuf_24/OUT gnd 363.82fF +C2655 divbuf_24/OUT5 gnd 350.37fF +C2656 divbuf_24/OUT4 gnd 133.72fF +C2657 divbuf_24/OUT3 gnd 34.03fF +C2658 divbuf_24/OUT2 gnd 8.71fF +C2659 divbuf_24/IN gnd 0.89fF +C2660 divbuf_24/a_492_n240# gnd 2.46fF **FLOATING C2661 divbuf_13/OUT gnd 363.82fF C2662 divbuf_13/OUT5 gnd 350.37fF C2663 divbuf_13/OUT4 gnd 133.72fF @@ -2838,41 +2838,41 @@ C2665 divbuf_13/OUT2 gnd 8.71fF C2666 divbuf_13/IN gnd 0.89fF C2667 divbuf_13/a_492_n240# gnd 2.46fF **FLOATING -C2668 divbuf_24/OUT gnd 363.82fF -C2669 divbuf_24/OUT5 gnd 350.37fF -C2670 divbuf_24/OUT4 gnd 133.72fF -C2671 divbuf_24/OUT3 gnd 34.03fF -C2672 divbuf_24/OUT2 gnd 8.71fF -C2673 divbuf_24/IN gnd 0.89fF -C2674 divbuf_24/a_492_n240# gnd 2.46fF **FLOATING -C2675 divbuf_12/OUT gnd 363.82fF -C2676 divbuf_12/OUT5 gnd 350.37fF -C2677 divbuf_12/OUT4 gnd 133.72fF -C2678 divbuf_12/OUT3 gnd 34.03fF -C2679 divbuf_12/OUT2 gnd 8.71fF -C2680 divbuf_12/IN gnd 0.89fF -C2681 divbuf_12/a_492_n240# gnd 2.46fF **FLOATING -C2682 divbuf_8/OUT gnd 363.82fF -C2683 divbuf_8/OUT5 gnd 350.37fF -C2684 divbuf_8/OUT4 gnd 133.72fF -C2685 divbuf_8/OUT3 gnd 34.03fF -C2686 divbuf_8/OUT2 gnd 8.71fF -C2687 divbuf_8/IN gnd 0.89fF -C2688 divbuf_8/a_492_n240# gnd 2.46fF **FLOATING -C2689 divbuf_23/OUT gnd 363.82fF -C2690 divbuf_23/OUT5 gnd 350.37fF -C2691 divbuf_23/OUT4 gnd 133.72fF -C2692 divbuf_23/OUT3 gnd 34.03fF -C2693 divbuf_23/OUT2 gnd 8.71fF -C2694 divbuf_23/IN gnd 0.89fF -C2695 divbuf_23/a_492_n240# gnd 2.46fF **FLOATING -C2696 divbuf_7/OUT gnd 363.82fF -C2697 divbuf_7/OUT5 gnd 350.37fF -C2698 divbuf_7/OUT4 gnd 133.72fF -C2699 divbuf_7/OUT3 gnd 34.03fF -C2700 divbuf_7/OUT2 gnd 8.71fF -C2701 divbuf_7/IN gnd 0.89fF -C2702 divbuf_7/a_492_n240# gnd 2.46fF **FLOATING +C2668 divbuf_9/OUT gnd 363.82fF +C2669 divbuf_9/OUT5 gnd 350.37fF +C2670 divbuf_9/OUT4 gnd 133.72fF +C2671 divbuf_9/OUT3 gnd 34.03fF +C2672 divbuf_9/OUT2 gnd 8.71fF +C2673 divbuf_9/IN gnd 0.89fF +C2674 divbuf_9/a_492_n240# gnd 2.46fF **FLOATING +C2675 divbuf_23/OUT gnd 363.82fF +C2676 divbuf_23/OUT5 gnd 350.37fF +C2677 divbuf_23/OUT4 gnd 133.72fF +C2678 divbuf_23/OUT3 gnd 34.03fF +C2679 divbuf_23/OUT2 gnd 8.71fF +C2680 divbuf_23/IN gnd 0.89fF +C2681 divbuf_23/a_492_n240# gnd 2.46fF **FLOATING +C2682 divbuf_12/OUT gnd 363.82fF +C2683 divbuf_12/OUT5 gnd 350.37fF +C2684 divbuf_12/OUT4 gnd 133.72fF +C2685 divbuf_12/OUT3 gnd 34.03fF +C2686 divbuf_12/OUT2 gnd 8.71fF +C2687 divbuf_12/IN gnd 0.89fF +C2688 divbuf_12/a_492_n240# gnd 2.46fF **FLOATING +C2689 divbuf_8/OUT gnd 363.82fF +C2690 divbuf_8/OUT5 gnd 350.37fF +C2691 divbuf_8/OUT4 gnd 133.72fF +C2692 divbuf_8/OUT3 gnd 34.03fF +C2693 divbuf_8/OUT2 gnd 8.71fF +C2694 divbuf_8/IN gnd 0.89fF +C2695 divbuf_8/a_492_n240# gnd 2.46fF **FLOATING +C2696 divbuf_22/OUT gnd 363.82fF +C2697 divbuf_22/OUT5 gnd 350.37fF +C2698 divbuf_22/OUT4 gnd 133.72fF +C2699 divbuf_22/OUT3 gnd 34.03fF +C2700 divbuf_22/OUT2 gnd 8.71fF +C2701 divbuf_22/IN gnd 0.89fF +C2702 divbuf_22/a_492_n240# gnd 2.46fF **FLOATING C2703 divbuf_11/OUT gnd 363.82fF C2704 divbuf_11/OUT5 gnd 350.37fF C2705 divbuf_11/OUT4 gnd 133.72fF @@ -2880,41 +2880,41 @@ C2707 divbuf_11/OUT2 gnd 8.71fF C2708 divbuf_11/IN gnd 0.89fF C2709 divbuf_11/a_492_n240# gnd 2.46fF **FLOATING -C2710 divbuf_22/OUT gnd 363.82fF -C2711 divbuf_22/OUT5 gnd 350.37fF -C2712 divbuf_22/OUT4 gnd 133.72fF -C2713 divbuf_22/OUT3 gnd 34.03fF -C2714 divbuf_22/OUT2 gnd 8.71fF -C2715 divbuf_22/IN gnd 0.89fF -C2716 divbuf_22/a_492_n240# gnd 2.46fF **FLOATING -C2717 divbuf_6/OUT gnd 363.82fF -C2718 divbuf_6/OUT5 gnd 350.37fF -C2719 divbuf_6/OUT4 gnd 133.72fF -C2720 divbuf_6/OUT3 gnd 34.03fF -C2721 divbuf_6/OUT2 gnd 8.71fF -C2722 divbuf_6/IN gnd 0.89fF -C2723 divbuf_6/a_492_n240# gnd 2.46fF **FLOATING -C2724 divbuf_10/OUT gnd 363.82fF -C2725 divbuf_10/OUT5 gnd 350.37fF -C2726 divbuf_10/OUT4 gnd 133.72fF -C2727 divbuf_10/OUT3 gnd 34.03fF -C2728 divbuf_10/OUT2 gnd 8.71fF -C2729 divbuf_10/IN gnd 0.89fF -C2730 divbuf_10/a_492_n240# gnd 2.46fF **FLOATING -C2731 divbuf_20/OUT gnd 363.82fF -C2732 divbuf_20/OUT5 gnd 350.37fF -C2733 divbuf_20/OUT4 gnd 133.72fF -C2734 divbuf_20/OUT3 gnd 34.03fF -C2735 divbuf_20/OUT2 gnd 8.71fF -C2736 divbuf_20/IN gnd 0.89fF -C2737 divbuf_20/a_492_n240# gnd 2.46fF **FLOATING -C2738 divbuf_21/OUT gnd 363.82fF -C2739 divbuf_21/OUT5 gnd 350.37fF -C2740 divbuf_21/OUT4 gnd 133.72fF -C2741 divbuf_21/OUT3 gnd 34.03fF -C2742 divbuf_21/OUT2 gnd 8.71fF -C2743 divbuf_21/IN gnd 0.89fF -C2744 divbuf_21/a_492_n240# gnd 2.46fF **FLOATING +C2710 divbuf_7/OUT gnd 363.82fF +C2711 divbuf_7/OUT5 gnd 350.37fF +C2712 divbuf_7/OUT4 gnd 133.72fF +C2713 divbuf_7/OUT3 gnd 34.03fF +C2714 divbuf_7/OUT2 gnd 8.71fF +C2715 divbuf_7/IN gnd 0.89fF +C2716 divbuf_7/a_492_n240# gnd 2.46fF **FLOATING +C2717 divbuf_21/OUT gnd 363.82fF +C2718 divbuf_21/OUT5 gnd 350.37fF +C2719 divbuf_21/OUT4 gnd 133.72fF +C2720 divbuf_21/OUT3 gnd 34.03fF +C2721 divbuf_21/OUT2 gnd 8.71fF +C2722 divbuf_21/IN gnd 0.89fF +C2723 divbuf_21/a_492_n240# gnd 2.46fF **FLOATING +C2724 divbuf_20/OUT gnd 363.82fF +C2725 divbuf_20/OUT5 gnd 350.37fF +C2726 divbuf_20/OUT4 gnd 133.72fF +C2727 divbuf_20/OUT3 gnd 34.03fF +C2728 divbuf_20/OUT2 gnd 8.71fF +C2729 divbuf_20/IN gnd 0.89fF +C2730 divbuf_20/a_492_n240# gnd 2.46fF **FLOATING +C2731 divbuf_10/OUT gnd 363.82fF +C2732 divbuf_10/OUT5 gnd 350.37fF +C2733 divbuf_10/OUT4 gnd 133.72fF +C2734 divbuf_10/OUT3 gnd 34.03fF +C2735 divbuf_10/OUT2 gnd 8.71fF +C2736 divbuf_10/IN gnd 0.89fF +C2737 divbuf_10/a_492_n240# gnd 2.46fF **FLOATING +C2738 divbuf_6/OUT gnd 363.82fF +C2739 divbuf_6/OUT5 gnd 350.37fF +C2740 divbuf_6/OUT4 gnd 133.72fF +C2741 divbuf_6/OUT3 gnd 34.03fF +C2742 divbuf_6/OUT2 gnd 8.71fF +C2743 divbuf_6/IN gnd 0.89fF +C2744 divbuf_6/a_492_n240# gnd 2.46fF **FLOATING C2745 divbuf_5/OUT gnd 363.82fF C2746 divbuf_5/OUT5 gnd 350.37fF C2747 divbuf_5/OUT4 gnd 133.72fF @@ -2950,41 +2950,41 @@ C2777 divbuf_1/OUT2 gnd 8.71fF C2778 divbuf_1/IN gnd 0.89fF C2779 divbuf_1/a_492_n240# gnd 2.46fF **FLOATING -C2780 divbuf_0/OUT gnd 363.82fF -C2781 divbuf_0/OUT5 gnd 350.37fF -C2782 divbuf_0/OUT4 gnd 133.72fF -C2783 divbuf_0/OUT3 gnd 34.03fF -C2784 divbuf_0/OUT2 gnd 8.71fF -C2785 divbuf_0/IN gnd 0.89fF -C2786 divbuf_0/a_492_n240# gnd 2.46fF **FLOATING -C2787 ro_complete_1/cbank_2/v gnd 16.43fF -C2788 ro_complete_1/cbank_2/switch_5/vin gnd 0.78fF -C2789 ro_complete_1/cbank_2/switch_4/vin gnd 1.50fF -C2790 ro_complete_1/cbank_2/switch_2/vin gnd 1.30fF -C2791 ro_complete_1/cbank_2/switch_3/vin gnd 0.56fF -C2792 ro_complete_1/cbank_2/switch_1/vin gnd 1.14fF -C2793 ro_complete_1/cbank_2/switch_0/vin gnd 1.02fF -C2794 ro_complete_1/cbank_1/v gnd 16.43fF -C2795 ro_complete_1/cbank_1/switch_5/vin gnd 0.78fF -C2796 ro_complete_1/a0 gnd 5.35fF -C2797 ro_complete_1/cbank_1/switch_4/vin gnd 1.50fF -C2798 ro_complete_1/a1 gnd 6.54fF -C2799 ro_complete_1/cbank_1/switch_2/vin gnd 1.30fF -C2800 ro_complete_1/a3 gnd 5.96fF -C2801 ro_complete_1/cbank_1/switch_3/vin gnd 0.56fF -C2802 ro_complete_1/a2 gnd 5.21fF -C2803 ro_complete_1/cbank_1/switch_1/vin gnd 1.14fF -C2804 ro_complete_1/a4 gnd 5.81fF -C2805 ro_complete_1/cbank_1/switch_0/vin gnd 1.02fF -C2806 ro_complete_1/a5 gnd 6.74fF -C2807 ro_complete_1/cbank_0/v gnd 15.12fF -C2808 ro_complete_1/cbank_0/switch_5/vin gnd 0.78fF -C2809 ro_complete_1/cbank_0/switch_4/vin gnd 1.50fF -C2810 ro_complete_1/cbank_0/switch_2/vin gnd 1.30fF -C2811 ro_complete_1/cbank_0/switch_3/vin gnd 0.56fF -C2812 ro_complete_1/cbank_0/switch_1/vin gnd 1.14fF -C2813 ro_complete_1/cbank_0/switch_0/vin gnd 1.02fF -C2814 ro_complete_1/ro_var_extend_0/vcont gnd 0.27fF +C2780 ro_complete_1/cbank_2/v gnd 16.43fF +C2781 ro_complete_1/cbank_2/switch_5/vin gnd 0.78fF +C2782 ro_complete_1/cbank_2/switch_4/vin gnd 1.50fF +C2783 ro_complete_1/cbank_2/switch_2/vin gnd 1.30fF +C2784 ro_complete_1/cbank_2/switch_3/vin gnd 0.56fF +C2785 ro_complete_1/cbank_2/switch_1/vin gnd 1.14fF +C2786 ro_complete_1/cbank_2/switch_0/vin gnd 1.02fF +C2787 ro_complete_1/cbank_1/v gnd 16.43fF +C2788 ro_complete_1/cbank_1/switch_5/vin gnd 0.78fF +C2789 ro_complete_1/a0 gnd 5.35fF +C2790 ro_complete_1/cbank_1/switch_4/vin gnd 1.50fF +C2791 ro_complete_1/a1 gnd 6.54fF +C2792 ro_complete_1/cbank_1/switch_2/vin gnd 1.30fF +C2793 ro_complete_1/a3 gnd 5.96fF +C2794 ro_complete_1/cbank_1/switch_3/vin gnd 0.56fF +C2795 ro_complete_1/a2 gnd 5.21fF +C2796 ro_complete_1/cbank_1/switch_1/vin gnd 1.14fF +C2797 ro_complete_1/a4 gnd 5.81fF +C2798 ro_complete_1/cbank_1/switch_0/vin gnd 1.02fF +C2799 ro_complete_1/a5 gnd 6.74fF +C2800 ro_complete_1/cbank_0/v gnd 15.12fF +C2801 ro_complete_1/cbank_0/switch_5/vin gnd 0.78fF +C2802 ro_complete_1/cbank_0/switch_4/vin gnd 1.50fF +C2803 ro_complete_1/cbank_0/switch_2/vin gnd 1.30fF +C2804 ro_complete_1/cbank_0/switch_3/vin gnd 0.56fF +C2805 ro_complete_1/cbank_0/switch_1/vin gnd 1.14fF +C2806 ro_complete_1/cbank_0/switch_0/vin gnd 1.02fF +C2807 ro_complete_1/ro_var_extend_0/vcont gnd 0.27fF +C2808 divbuf_0/OUT gnd 363.82fF +C2809 divbuf_0/OUT5 gnd 350.37fF +C2810 divbuf_0/OUT4 gnd 133.72fF +C2811 divbuf_0/OUT3 gnd 34.03fF +C2812 divbuf_0/OUT2 gnd 8.71fF +C2813 divbuf_0/IN gnd 0.89fF +C2814 divbuf_0/a_492_n240# gnd 2.46fF **FLOATING C2815 ro_complete_0/cbank_2/v gnd 16.43fF C2816 ro_complete_0/cbank_2/switch_5/vin gnd 0.78fF C2817 ro_complete_0/cbank_2/switch_4/vin gnd 1.50fF @@ -3018,15 +3018,15 @@ C2845 filter_0/a_4216_n2998# gnd 1.03fF **FLOATING C2846 cp_0/down gnd 1.54fF C2847 cp_0/vbias gnd 2.41fF -C2848 cp_0/out gnd 5.30fF +C2848 cp_0/out gnd 5.34fF C2849 cp_0/upbar gnd 1.50fF C2850 cp_0/a_7110_n2840# gnd 0.17fF **FLOATING C2851 cp_0/a_3060_n2840# gnd 1.71fF **FLOATING C2852 cp_0/a_7110_0# gnd 0.17fF **FLOATING C2853 cp_0/a_6370_0# gnd 0.40fF **FLOATING -C2854 cp_0/a_3060_0# gnd 1.65fF **FLOATING -C2855 cp_0/a_1710_0# gnd 5.76fF **FLOATING -C2856 cp_0/a_1710_n2840# gnd 4.89fF **FLOATING +C2854 cp_0/a_3060_0# gnd 1.66fF **FLOATING +C2855 cp_0/a_1710_0# gnd 5.89fF **FLOATING +C2856 cp_0/a_1710_n2840# gnd 4.91fF **FLOATING C2857 cp_0/a_10_n50# gnd 2.96fF **FLOATING C2858 pd_1/and_pd_0/Z1 gnd 0.39fF C2859 pd_1/and_pd_0/Out1 gnd 2.22fF