pin extensions complete
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds index 7ef325e..2d35c18 100644 --- a/gds/user_analog_project_wrapper.gds +++ b/gds/user_analog_project_wrapper.gds Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag index 19a717e..48429a4 100644 --- a/mag/user_analog_project_wrapper.mag +++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@ magic tech sky130A -timestamp 1642892719 +timestamp 1642896605 << metal2 >> rect 262 -400 318 240 rect 853 -400 909 240 @@ -571,8 +571,12 @@ rect 291170 272430 292400 272681 rect 286997 270537 292400 272430 rect 291170 270281 292400 270537 -rect -400 255765 240 255821 -rect -400 255174 240 255230 +rect 176 255821 1564 255918 +rect -400 255765 1564 255821 +rect 176 255663 1564 255765 +rect 190 255230 1578 255336 +rect -400 255174 1578 255230 +rect 190 255081 1578 255174 rect -400 254583 240 254639 rect -400 253992 240 254048 rect -400 253401 240 253457 @@ -583,8 +587,12 @@ rect 291760 248252 292400 248308 rect 291760 247661 292400 247717 rect 291760 247070 292400 247126 -rect -400 234154 240 234210 -rect -400 233563 240 233619 +rect 153 234210 1541 234292 +rect -400 234154 1541 234210 +rect 153 234037 1541 234154 +rect 176 233619 1564 233734 +rect -400 233563 1564 233619 +rect 176 233479 1564 233563 rect -400 232972 240 233028 rect -400 232381 240 232437 rect -400 231790 240 231846 @@ -595,8 +603,12 @@ rect 291760 226041 292400 226097 rect 291760 225450 292400 225506 rect 291760 224859 292400 224915 -rect -400 212543 240 212599 -rect -400 211952 240 212008 +rect 171 212599 1559 212727 +rect -400 212543 1559 212599 +rect 171 212472 1559 212543 +rect 175 212008 1563 212112 +rect -400 211952 1563 212008 +rect 175 211857 1563 211952 rect -400 211361 240 211417 rect -400 210770 240 210826 rect -400 210179 240 210235 @@ -607,8 +619,12 @@ rect 291760 203830 292400 203886 rect 291760 203239 292400 203295 rect 291760 202648 292400 202704 -rect -400 190932 240 190988 -rect -400 190341 240 190397 +rect 185 190988 1573 191097 +rect -400 190932 1573 190988 +rect 185 190842 1573 190932 +rect 204 190397 1592 190525 +rect -400 190341 1592 190397 +rect 204 190270 1592 190341 rect -400 189750 240 189806 rect -400 189159 240 189215 rect -400 188568 240 188624 @@ -619,8 +635,12 @@ rect 291760 180619 292400 180675 rect 291760 180028 292400 180084 rect 291760 179437 292400 179493 -rect -400 169321 240 169377 -rect -400 168730 240 168786 +rect 181 169377 1569 169509 +rect -400 169321 1569 169377 +rect 181 169254 1569 169321 +rect 199 168786 1587 168886 +rect -400 168730 1587 168786 +rect 199 168631 1587 168730 rect -400 168139 240 168195 rect -400 167548 240 167604 rect -400 166957 240 167013 @@ -631,8 +651,12 @@ rect 291760 158008 292400 158064 rect 291760 157417 292400 157473 rect 291760 156826 292400 156882 -rect -400 147710 240 147766 -rect -400 147119 240 147175 +rect 190 147766 1578 147897 +rect -400 147710 1578 147766 +rect 190 147642 1578 147710 +rect 218 147175 1606 147320 +rect -400 147119 1606 147175 +rect 218 147065 1606 147119 rect -400 146528 240 146584 rect -400 145937 240 145993 rect -400 145346 240 145402 @@ -643,8 +667,12 @@ rect 291760 135797 292400 135853 rect 291760 135206 292400 135262 rect 291760 134615 292400 134671 -rect -400 126199 240 126255 -rect -400 125608 240 125664 +rect 195 126255 1583 126392 +rect -400 126199 1583 126255 +rect 195 126137 1583 126199 +rect 204 125664 1592 125824 +rect -400 125608 1592 125664 +rect 204 125569 1592 125608 rect -400 125017 240 125073 rect -400 124426 240 124482 rect -400 123835 240 123891 @@ -671,8 +699,12 @@ rect 291170 70535 292400 70815 rect 287095 68642 292400 70535 rect 291170 68415 292400 68642 -rect -400 62388 240 62444 -rect -400 61797 240 61853 +rect 181 62444 1569 62587 +rect -400 62388 1569 62444 +rect 181 62332 1569 62388 +rect 199 61853 1587 62001 +rect -400 61797 1587 61853 +rect 199 61746 1587 61797 rect -400 61206 240 61262 rect -400 60615 240 60671 rect -400 60024 240 60080 @@ -681,8 +713,12 @@ rect 291760 46968 292400 47024 rect 291760 46377 292400 46433 rect 291760 45786 292400 45842 -rect -400 40777 240 40833 -rect -400 40186 240 40242 +rect 195 40833 1583 41003 +rect -400 40777 1583 40833 +rect 195 40748 1583 40777 +rect 204 40242 1592 40399 +rect -400 40186 1592 40242 +rect 204 40144 1592 40186 rect -400 39595 240 39651 rect -400 39004 240 39060 rect -400 38413 240 38469 @@ -691,8 +727,12 @@ rect 291760 24639 292400 24695 rect 291760 24048 292400 24104 rect 291760 23457 292400 23513 -rect -400 19166 240 19222 -rect -400 18575 240 18631 +rect 199 19222 1587 19359 +rect -400 19166 1587 19222 +rect 199 19104 1587 19166 +rect 195 18631 1583 18746 +rect -400 18575 1583 18631 +rect 195 18491 1583 18575 rect -400 17984 240 18040 rect -400 17393 240 17449 rect -400 16802 240 16858 @@ -703,10 +743,14 @@ rect 291760 10228 292400 10284 rect 291760 9637 292400 9693 rect 291760 9046 292400 9102 -rect -400 8455 240 8511 +rect 195 8511 1583 8651 +rect -400 8455 1583 8511 rect 291760 8455 292400 8511 -rect -400 7864 240 7920 +rect 195 8396 1583 8455 +rect 213 7920 1601 8041 +rect -400 7864 1601 7920 rect 291760 7864 292400 7920 +rect 213 7786 1601 7864 rect -400 7273 240 7329 rect 291760 7273 292400 7329 rect -400 6682 240 6738
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice index 1ec0b28..38cbd75 100644 --- a/netgen/user_analog_project_wrapper.spice +++ b/netgen/user_analog_project_wrapper.spice
@@ -106,856 +106,856 @@ + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] + wbs_stb_i wbs_we_i -C0 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF -C1 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF -C2 io_clamp_low[0] io_clamp_high[0] 0.53fF -C3 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF -C4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF -C5 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C6 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF -C7 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C8 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF -C9 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF -C10 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF -C11 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF -C12 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF -C13 pd_0/DOWN pd_0/R 0.36fF -C14 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF -C15 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF -C16 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF -C17 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z3 0.27fF -C18 divider_0/nor_1/B divider_0/tspc_0/a_630_n680# 0.01fF -C19 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF -C20 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF -C21 divider_0/tspc_2/Z3 divider_0/Out 0.05fF -C22 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF -C23 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF -C24 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF -C25 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C26 pll_full_0/pd_0/REF pll_full_0/pd_0/R 0.61fF -C27 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF -C28 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF -C29 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF -C30 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF -C31 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF -C32 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF -C33 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C34 divider_0/and_0/A divider_0/and_0/B 0.18fF -C35 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C36 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF -C37 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C38 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C39 divbuf_5/IN divbuf_5/OUT5 0.00fF -C40 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.01fF -C41 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.19fF -C42 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.14fF -C43 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF -C44 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF -C45 io_clamp_high[2] io_analog[6] 0.53fF -C46 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF -C47 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z3 0.38fF -C48 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C49 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C50 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF -C51 pll_full_0/divider_0/nor_0/B pll_full_0/divbuf_0/IN 0.29fF -C52 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.29fF -C53 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF -C54 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF -C55 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF -C56 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF -C57 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF -C58 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C59 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C60 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C61 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF -C62 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF -C63 pd_0/R pd_0/tspc_r_1/Z3 0.29fF -C64 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF -C65 divbuf_0/OUT divbuf_0/OUT5 43.38fF -C66 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C67 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF -C68 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C69 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C70 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF -C71 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF -C72 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF -C73 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF -C74 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C75 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF -C76 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF -C77 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF -C78 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF -C79 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF -C80 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF -C81 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C82 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C83 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF -C84 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF -C85 pll_full_0/pd_0/R pll_full_0/pd_0/DOWN 0.36fF -C86 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF -C87 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF -C88 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF -C89 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF -C90 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF -C91 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF -C92 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C93 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C94 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF -C95 cp_0/a_10_n50# cp_0/vbias 0.19fF -C96 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF -C97 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF -C98 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF -C99 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF -C100 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C101 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C102 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C103 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF -C104 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.32fF -C105 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C106 divbuf_5/OUT2 divbuf_5/OUT 0.06fF -C107 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF -C108 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z1 0.09fF -C109 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF -C110 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF -C111 io_clamp_low[1] io_analog[5] 0.53fF -C112 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT5 0.01fF -C113 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF -C114 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C115 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C116 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF -C117 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF -C118 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF -C119 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF -C120 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF -C121 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C122 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C123 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C124 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DIV 0.65fF -C125 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF -C126 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF -C127 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/A 0.35fF -C128 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C129 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C130 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C131 divbuf_2/OUT5 divbuf_2/IN 0.00fF -C132 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF -C133 pd_0/R pd_0/UP 0.45fF -C134 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF -C135 divider_0/prescaler_0/Out divider_0/tspc_0/Z2 0.11fF -C136 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF -C137 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF -C138 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF -C139 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C140 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/Out 0.08fF -C141 pd_0/UP pd_0/and_pd_0/Out1 0.33fF -C142 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C143 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF -C144 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF -C145 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF -C146 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF -C147 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C148 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF -C149 divider_0/mc2 divider_0/nor_1/A 0.04fF -C150 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/Z2 0.14fF -C151 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF -C152 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF -C153 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C154 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF -C155 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C156 divbuf_7/OUT3 divbuf_7/OUT 0.26fF -C157 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF -C158 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF -C159 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Z3 0.38fF -C160 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF -C161 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF -C162 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF -C163 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF -C164 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF -C165 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF -C166 divider_0/tspc_0/Z4 divider_0/prescaler_0/Out 0.12fF -C167 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF -C168 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF -C169 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF -C170 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C171 divider_0/and_0/B divider_0/and_0/Z1 0.07fF -C172 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF -C173 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C174 divbuf_5/OUT4 divbuf_5/OUT 1.11fF -C175 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.04fF -C176 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C177 divider_0/tspc_0/Z4 divider_0/tspc_0/Z1 0.00fF -C178 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF -C179 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF -C180 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT4 20.26fF -C181 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C182 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF -C183 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C184 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF -C185 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF -C186 divbuf_1/OUT5 divbuf_1/OUT 43.38fF -C187 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF -C188 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF -C189 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/Out 0.12fF -C190 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C191 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C192 divbuf_2/OUT2 divbuf_2/OUT 0.06fF -C193 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF -C194 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF -C195 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF -C196 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF -C197 divbuf_0/OUT divbuf_0/OUT2 0.06fF -C198 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF -C199 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF -C200 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF -C201 divider_0/and_0/out1 divider_0/and_0/A 0.01fF -C202 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT5 43.38fF -C203 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C204 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C205 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF -C206 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF -C207 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF -C208 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF -C209 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF -C210 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/Out 0.11fF -C211 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF -C212 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C213 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF -C214 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF -C215 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C216 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF -C217 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT5 0.02fF -C218 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF -C219 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF -C220 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C221 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF -C222 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF -C223 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C224 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF -C225 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF -C226 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF -C227 divbuf_3/IN divbuf_3/OUT5 0.00fF -C228 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF -C229 divbuf_7/OUT5 divbuf_7/OUT 43.38fF -C230 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF -C231 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF -C232 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z3 0.25fF -C233 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF -C234 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.19fF -C235 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF -C236 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF -C237 divbuf_4/IN divbuf_4/OUT5 0.00fF -C238 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF -C239 pd_0/REF pd_0/tspc_r_1/z5 0.04fF -C240 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF -C241 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF -C242 pll_full_0/pd_0/R pll_full_0/pd_0/DIV 0.51fF -C243 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF -C244 divider_0/nor_1/B divider_0/nor_0/B 0.47fF -C245 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF -C246 divider_0/tspc_0/Q divider_0/tspc_0/Z3 0.05fF -C247 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF -C248 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF -C249 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF -C250 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF -C251 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C252 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF -C253 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF -C254 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF -C255 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF -C256 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF -C257 io_clamp_high[0] io_analog[4] 0.53fF -C258 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C259 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF -C260 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C261 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF -C262 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF -C263 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF -C264 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF -C265 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF -C266 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF -C267 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C268 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF -C269 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF -C270 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF -C271 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF -C272 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF -C273 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF -C274 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF -C275 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF -C276 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/Z3 0.05fF -C277 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C278 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C279 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.01fF -C280 divbuf_2/OUT4 divbuf_2/OUT 1.11fF -C281 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF -C282 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z3 0.11fF -C283 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF -C284 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF -C285 divider_0/mc2 divider_0/and_0/B 0.20fF -C286 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF -C287 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/B 0.22fF -C288 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C289 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/Out 0.28fF -C290 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF -C291 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF -C292 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF -C293 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF -C294 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF -C295 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF -C296 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF -C297 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF -C298 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF -C299 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/A 0.21fF -C300 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF -C301 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF -C302 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF -C303 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/Out 0.91fF -C304 divbuf_1/OUT divbuf_1/OUT3 0.26fF -C305 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF -C306 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF -C307 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF -C308 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF -C309 divbuf_3/OUT2 divbuf_3/OUT 0.06fF -C310 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF -C311 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C312 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z3 0.45fF -C313 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF -C314 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF -C315 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF -C316 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF -C317 divbuf_4/OUT2 divbuf_4/OUT 0.06fF -C318 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF -C319 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF -C320 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C321 cp_0/upbar cp_0/down 0.02fF -C322 pd_0/R pd_0/and_pd_0/Z1 0.02fF -C323 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF -C324 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF -C325 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF -C326 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF -C327 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF -C328 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF -C329 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF -C330 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF -C331 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C332 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF -C333 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF -C334 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF -C335 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF -C336 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C337 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF -C338 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF -C339 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF -C340 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF -C341 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.01fF -C342 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF -C343 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF -C344 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF -C345 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF -C346 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF -C347 pd_0/DIV pd_0/R 0.51fF -C348 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF -C349 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/DIV 0.17fF -C350 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF -C351 divider_0/nor_0/B divider_0/Out 0.22fF -C352 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF -C353 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C354 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF -C355 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF -C356 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF -C357 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DOWN 0.03fF -C358 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF -C359 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF -C360 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF -C361 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF -C362 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF -C363 divbuf_2/a_492_n240# divbuf_2/OUT5 0.01fF -C364 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF -C365 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF -C366 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF -C367 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.44fF -C368 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF -C369 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF -C370 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF -C371 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF -C372 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z2 0.21fF -C373 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF -C374 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF -C375 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF -C376 divider_0/nor_1/B divider_0/and_0/A 0.26fF -C377 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF -C378 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C379 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF -C380 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF -C381 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF -C382 divbuf_6/OUT3 divbuf_6/OUT 0.26fF -C383 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF -C384 divider_0/mc2 divider_0/and_0/OUT 0.05fF -C385 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF -C386 divider_0/nor_1/A divider_0/and_0/B 0.08fF -C387 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C388 divbuf_3/OUT4 divbuf_3/OUT 1.11fF -C389 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF -C390 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF -C391 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF -C392 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF -C393 pd_0/DOWN pd_0/UP 0.46fF -C394 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF -C395 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF -C396 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C397 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF -C398 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF -C399 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C400 divbuf_4/OUT4 divbuf_4/OUT 1.11fF -C401 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C402 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C403 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/Out 0.11fF -C404 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF -C405 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DIV 0.12fF -C406 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF -C407 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF -C408 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF -C409 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z3 0.38fF -C410 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF -C411 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF -C412 filter_0/a_4216_n2998# filter_0/v 0.31fF -C413 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/OUT5 0.01fF -C414 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF -C415 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF -C416 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF -C417 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF -C418 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF -C419 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF -C420 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C421 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.20fF -C422 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_1/A 1.21fF -C423 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF -C424 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF -C425 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF -C426 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF -C427 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF -C428 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF -C429 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF -C430 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF -C431 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C432 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF -C433 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF -C434 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF -C435 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF -C436 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF -C437 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF -C438 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF -C439 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF -C440 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF -C441 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF -C442 divider_0/tspc_0/Q divider_0/tspc_1/a_630_n680# 0.01fF -C443 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C444 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF -C445 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF -C446 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF -C447 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF -C448 io_clamp_low[2] io_analog[6] 0.53fF -C449 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C450 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z2 0.30fF -C451 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C452 divbuf_6/OUT5 divbuf_6/OUT 43.38fF -C453 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF -C454 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF -C455 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF -C456 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF -C457 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF -C458 divider_0/tspc_0/Z4 divider_0/tspc_0/a_630_n680# 0.12fF -C459 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C460 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF -C461 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z1 0.71fF -C462 divider_0/mc2 divider_0/and_0/out1 0.06fF -C463 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF -C464 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF -C465 pd_0/R pd_0/REF 0.61fF -C466 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF -C467 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C468 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF -C469 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C470 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C471 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/DIV 0.19fF -C472 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF -C473 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z1 0.03fF -C474 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF -C475 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF -C476 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF -C477 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF -C478 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF -C479 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF -C480 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF -C481 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF -C482 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C483 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF -C484 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF -C485 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C486 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.20fF -C487 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_1/A 0.01fF -C488 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF -C489 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF -C490 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.15fF -C491 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF -C492 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF -C493 divbuf_7/IN divbuf_7/OUT5 0.00fF -C494 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C495 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF -C496 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/DOWN 0.21fF -C497 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF -C498 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF -C499 divbuf_1/OUT5 divbuf_1/IN 0.00fF -C500 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C501 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF -C502 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF -C503 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C504 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/R 0.29fF -C505 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF -C506 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF -C507 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF -C508 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF -C509 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF -C510 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF -C511 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF -C512 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C513 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C514 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C515 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF -C516 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF -C517 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF -C518 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_0/switch_0/vin 0.09fF -C519 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DIV 0.04fF -C520 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF -C521 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF -C522 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF -C523 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF -C524 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF -C525 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C526 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF -C527 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF -C528 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF -C529 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF -C530 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF -C531 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF -C532 divbuf_2/a_492_n240# divbuf_2/IN 0.13fF -C533 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF -C534 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF -C535 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C536 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF -C537 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C538 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF -C539 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF -C540 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF -C541 divider_0/prescaler_0/Out divider_0/clk 0.51fF -C542 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF -C543 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF -C544 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF -C545 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C546 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF -C547 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF -C548 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF -C549 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C550 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C551 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF -C552 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.05fF -C553 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF -C554 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C555 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF -C556 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF -C557 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF -C558 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF -C559 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF -C560 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF -C561 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C562 divbuf_7/OUT2 divbuf_7/OUT 0.06fF -C563 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF -C564 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF -C565 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF -C566 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF -C567 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF -C568 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF -C569 divider_0/mc2 divider_0/nor_0/B 0.15fF -C570 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF -C571 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF -C572 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF -C573 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C574 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF -C575 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT5 0.01fF -C576 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C577 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C578 divbuf_5/OUT3 divbuf_5/OUT 0.26fF -C579 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF -C580 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF -C581 io_clamp_low[2] io_clamp_high[2] 0.53fF -C582 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF -C583 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_0/vin 0.19fF -C584 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF -C585 io_clamp_high[1] io_analog[5] 0.53fF -C586 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF -C587 pll_full_0/divbuf_1/OUT4 pll_full_0/divbuf_1/OUT5 20.26fF -C588 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C589 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C590 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF -C591 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF -C592 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divbuf_0/IN 0.05fF -C593 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF -C594 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF -C595 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C596 divider_0/and_0/OUT divider_0/and_0/B 0.01fF -C597 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF -C598 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF -C599 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/OUT3 1.37fF -C600 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C601 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF -C602 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C603 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C604 divider_0/prescaler_0/Out divider_0/tspc_0/Z3 0.45fF -C605 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF -C606 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF -C607 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF -C608 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF -C609 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C610 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/Out 0.19fF -C611 divider_0/mc2 divider_0/nor_1/B 0.06fF -C612 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF -C613 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF -C614 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF -C615 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C616 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF -C617 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF -C618 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF -C619 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.61fF -C620 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.26fF -C621 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF -C622 filter_0/a_4216_n5230# filter_0/v 0.19fF -C623 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C624 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF -C625 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C626 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF -C627 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF -C628 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C629 divbuf_7/OUT4 divbuf_7/OUT 1.11fF -C630 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF -C631 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF -C632 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF -C633 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF -C634 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.45fF -C635 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF -C636 pd_0/R pd_0/and_pd_0/Out1 0.33fF -C637 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF -C638 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF -C639 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF -C640 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF -C641 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF -C642 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C643 divbuf_5/OUT5 divbuf_5/OUT 43.38fF -C644 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF -C645 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z4 0.04fF -C646 io_clamp_low[0] io_analog[4] 0.53fF -C647 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF -C648 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C649 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF -C650 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF -C651 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF -C652 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF -C653 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF -C654 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF -C655 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF -C656 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF -C657 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/OUT5 0.02fF -C658 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C659 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF -C660 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C661 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF -C662 divbuf_2/OUT3 divbuf_2/OUT 0.26fF -C663 pd_0/R pd_0/tspc_r_1/Z2 0.21fF -C664 divider_0/mc2 divider_0/and_0/A 0.16fF -C665 divbuf_2/a_492_n240# divbuf_2/OUT2 0.42fF -C666 divider_0/and_0/out1 divider_0/and_0/B 0.18fF -C667 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF -C668 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF -C669 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C670 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF -C671 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF -C672 pd_0/UP pd_0/and_pd_0/Z1 0.06fF -C673 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/OUT2 0.42fF -C674 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF -C675 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF -C676 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF -C677 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF -C678 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C679 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF -C680 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/A 0.55fF -C681 divbuf_6/IN divbuf_6/OUT5 0.00fF -C682 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF -C683 divbuf_1/OUT divbuf_1/OUT2 0.06fF -C684 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF -C685 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF -C686 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C687 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF -C688 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF -C689 divider_0/nor_1/A divider_0/tspc_0/Z3 0.38fF -C690 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF -C691 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF -C692 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF -C693 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF -C694 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z2 0.11fF -C695 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF -C696 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C697 divider_0/nor_1/B divider_0/nor_1/A 1.21fF -C698 divbuf_0/IN divbuf_0/OUT5 0.00fF -C699 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF -C700 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF -C701 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF -C702 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF -C703 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF -C704 divider_0/mc2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF -C705 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF -C706 divider_0/tspc_0/Z4 divider_0/tspc_0/Z3 0.65fF -C707 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF -C708 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF -C709 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF -C710 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF -C711 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/Out 0.15fF -C712 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.64fF -C713 io_clamp_low[1] io_clamp_high[1] 0.53fF -C714 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF -C715 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF -C716 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF -C717 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF -C718 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C719 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/A 0.03fF -C720 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C721 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF -C722 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF -C723 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF -C724 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF -C725 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF -C726 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF -C727 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF -C728 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF -C729 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF -C730 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF -C731 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF -C732 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF -C733 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C734 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z3 0.65fF -C735 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C736 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C737 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF -C738 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF -C739 divbuf_2/OUT5 divbuf_2/OUT 43.38fF -C740 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF -C741 cp_0/a_1710_0# cp_0/out 0.84fF -C742 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF -C743 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF -C744 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF -C745 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C746 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF -C747 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF -C748 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C749 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF -C750 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF -C751 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF -C752 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF -C753 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF -C754 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF -C755 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF -C756 divbuf_6/OUT2 divbuf_6/OUT 0.06fF -C757 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF -C758 divbuf_1/OUT divbuf_1/OUT4 1.11fF -C759 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF -C760 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C761 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF -C762 divider_0/nor_1/A divider_0/and_0/A 0.01fF -C763 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF -C764 divbuf_3/OUT3 divbuf_3/OUT 0.26fF -C765 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF -C766 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_0/D 0.16fF -C767 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.05fF -C768 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF -C769 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF -C770 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF -C771 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF -C772 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF -C773 divbuf_0/OUT divbuf_0/OUT3 0.26fF -C774 divider_0/nor_0/B divider_0/and_0/B 0.29fF -C775 divbuf_4/OUT3 divbuf_4/OUT 0.26fF -C776 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF -C777 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C778 pd_0/UP pd_0/tspc_r_1/z5 0.03fF -C779 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C780 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.32fF -C781 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z2 0.23fF -C782 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF -C783 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF -C784 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF -C785 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a2 0.09fF -C786 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF -C787 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF -C788 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF -C789 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF -C790 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF -C791 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF -C792 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF -C793 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF -C794 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF -C795 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF -C796 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF -C797 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF -C798 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF -C799 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C800 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF -C801 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C802 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF -C803 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF -C804 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF -C805 cp_0/upbar cp_0/a_1710_n2840# 0.29fF -C806 cp_0/a_1710_0# cp_0/down 0.32fF -C807 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF -C808 pll_full_0/divbuf_0/a_492_n240# pll_full_0/pd_0/DIV 0.00fF -C809 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF -C810 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF -C811 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF -C812 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF -C813 divbuf_0/OUT3 divbuf_0/OUT5 0.01fF -C814 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C815 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF -C816 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF -C817 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF -C818 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF -C819 divider_0/nor_1/B divider_0/and_0/B 0.31fF -C820 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF -C821 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF -C822 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF -C823 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C824 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF -C825 divbuf_6/OUT4 divbuf_6/OUT 1.11fF -C826 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF -C827 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF -C828 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF -C829 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/clk 0.05fF -C830 divbuf_1/a_492_n240# divbuf_1/OUT2 0.42fF -C831 pll_full_0/pd_0/REF pll_full_0/pd_0/DOWN 1.48fF -C832 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF -C833 divider_0/and_0/OUT divider_0/clk 0.04fF -C834 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/A 0.15fF -C835 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C836 divbuf_3/OUT5 divbuf_3/OUT 43.38fF -C837 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF -C838 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF -C839 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF -C840 divbuf_0/OUT divbuf_0/OUT4 1.11fF -C841 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C842 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C843 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C844 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF -C845 divbuf_4/OUT5 divbuf_4/OUT 43.38fF -C846 cp_0/a_1710_n2840# cp_0/out 0.61fF -C847 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF -C848 pll_full_0/pd_0/UP pll_full_0/pd_0/DOWN 4.58fF -C849 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF +C0 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF +C1 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF +C2 io_clamp_high[2] io_analog[6] 0.53fF +C3 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF +C4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C5 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C6 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C7 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C8 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF +C9 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF +C10 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF +C11 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.29fF +C12 pll_full_0/pd_0/UP pll_full_0/pd_0/DOWN 4.58fF +C13 divider_0/tspc_1/a_630_n680# divider_0/tspc_0/Q 0.01fF +C14 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar1 0.11fF +C15 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF +C16 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF +C17 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF +C18 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF +C19 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/A 0.15fF +C20 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z3 0.38fF +C21 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C22 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C23 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C24 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF +C25 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF +C26 pll_full_0/pd_0/R pll_full_0/pd_0/DOWN 0.36fF +C27 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF +C28 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF +C29 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C30 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF +C31 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C32 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF +C33 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C34 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C35 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF +C36 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF +C37 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF +C38 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF +C39 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF +C40 pd_0/R pd_0/and_pd_0/Out1 0.33fF +C41 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Z3 0.03fF +C42 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF +C43 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF +C44 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF +C45 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF +C46 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z2 0.30fF +C47 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF +C48 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C49 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C50 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF +C51 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF +C52 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF +C53 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF +C54 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF +C55 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF +C56 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF +C57 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT2 1.37fF +C58 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF +C59 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF +C60 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF +C61 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF +C62 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C63 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C64 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF +C65 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C66 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF +C67 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z1 0.17fF +C68 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF +C69 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C70 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C71 divbuf_2/OUT2 divbuf_2/OUT 0.06fF +C72 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF +C73 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z4 0.65fF +C74 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C75 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF +C76 divbuf_5/OUT2 divbuf_5/OUT 0.06fF +C77 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF +C78 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF +C79 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.32fF +C80 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C81 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C82 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF +C83 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF +C84 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF +C85 io_clamp_low[1] io_analog[5] 0.53fF +C86 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF +C87 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C88 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C89 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF +C90 pd_0/DIV pd_0/R 0.51fF +C91 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF +C92 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF +C93 pd_0/UP pd_0/and_pd_0/Z1 0.06fF +C94 filter_0/a_4216_n2998# filter_0/v 0.31fF +C95 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Z3 0.03fF +C96 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C97 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF +C98 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF +C99 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF +C100 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/A 0.35fF +C101 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C102 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C103 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C104 cp_0/out cp_0/a_1710_n2840# 0.61fF +C105 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF +C106 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF +C107 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF +C108 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C109 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/Out 0.08fF +C110 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF +C111 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF +C112 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C113 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF +C114 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/DIV 0.02fF +C115 divider_0/mc2 divider_0/nor_1/A 0.04fF +C116 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF +C117 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF +C118 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF +C119 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF +C120 divbuf_2/a_492_n240# divbuf_2/OUT5 0.01fF +C121 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF +C122 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF +C123 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF +C124 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C125 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C126 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/A 0.55fF +C127 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF +C128 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF +C129 pd_0/DOWN pd_0/UP 0.46fF +C130 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF +C131 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF +C132 divbuf_7/OUT3 divbuf_7/OUT 0.26fF +C133 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF +C134 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF +C135 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF +C136 divider_0/tspc_2/Z3 divider_0/Out 0.05fF +C137 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C138 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF +C139 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF +C140 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF +C141 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF +C142 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF +C143 divider_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.45fF +C144 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF +C145 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF +C146 divider_0/and_0/B divider_0/and_0/Z1 0.07fF +C147 divbuf_2/OUT4 divbuf_2/OUT 1.11fF +C148 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C149 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF +C150 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF +C151 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF +C152 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C153 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.04fF +C154 divbuf_5/OUT4 divbuf_5/OUT 1.11fF +C155 divider_0/mc2 divider_0/nor_1/B 0.06fF +C156 divider_0/tspc_0/Z3 divider_0/tspc_0/Z1 0.06fF +C157 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF +C158 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF +C159 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF +C160 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF +C161 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF +C162 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/B 0.22fF +C163 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C164 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.61fF +C165 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF +C166 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF +C167 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF +C168 pll_full_0/divider_0/nor_0/B pll_full_0/divbuf_0/IN 0.29fF +C169 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF +C170 pll_full_0/pd_0/R pll_full_0/pd_0/DIV 0.51fF +C171 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z3 0.09fF +C172 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF +C173 filter_0/a_4216_n5230# filter_0/v 0.19fF +C174 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF +C175 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C176 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF +C177 divbuf_1/OUT divbuf_1/OUT3 0.26fF +C178 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF +C179 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF +C180 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.45fF +C181 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C182 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C183 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF +C184 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF +C185 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF +C186 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF +C187 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C188 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z1 0.06fF +C189 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF +C190 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF +C191 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF +C192 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/Out 0.11fF +C193 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF +C194 pll_full_0/pd_0/UP pll_full_0/pd_0/R 0.46fF +C195 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF +C196 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF +C197 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF +C198 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C199 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF +C200 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/Z3 0.20fF +C201 pll_full_0/pd_0/tspc_r_1/z5 pll_full_0/pd_0/REF 0.04fF +C202 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF +C203 divbuf_3/IN divbuf_3/OUT5 0.00fF +C204 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF +C205 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF +C206 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF +C207 divbuf_7/OUT5 divbuf_7/OUT 43.38fF +C208 cp_0/a_10_n50# cp_0/vbias 0.19fF +C209 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF +C210 pd_0/R pd_0/REF 0.61fF +C211 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF +C212 divider_0/tspc_0/Z4 divider_0/tspc_0/a_630_n680# 0.12fF +C213 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF +C214 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF +C215 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF +C216 divbuf_4/IN divbuf_4/OUT5 0.00fF +C217 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/Z3 0.20fF +C218 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF +C219 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF +C220 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF +C221 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF +C222 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF +C223 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C224 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF +C225 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF +C226 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF +C227 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF +C228 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF +C229 io_clamp_high[0] io_analog[4] 0.53fF +C230 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C231 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF +C232 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C233 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF +C234 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF +C235 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF +C236 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF +C237 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF +C238 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z3 0.25fF +C239 divider_0/tspc_0/Z3 divider_0/nor_1/A 0.38fF +C240 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF +C241 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF +C242 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF +C243 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF +C244 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF +C245 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C246 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF +C247 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C248 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C249 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.01fF +C250 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF +C251 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF +C252 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z1 0.71fF +C253 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF +C254 divider_0/nor_1/B divider_0/nor_1/A 1.21fF +C255 divider_0/mc2 divider_0/and_0/B 0.20fF +C256 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Z3 0.38fF +C257 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF +C258 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C259 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF +C260 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/Out 0.28fF +C261 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF +C262 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z3 0.27fF +C263 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF +C264 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF +C265 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF +C266 divbuf_1/OUT5 divbuf_1/IN 0.00fF +C267 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C268 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/nor_1/A 0.38fF +C269 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF +C270 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF +C271 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF +C272 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/Out 0.91fF +C273 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF +C274 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF +C275 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C276 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF +C277 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C278 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF +C279 divbuf_3/OUT2 divbuf_3/OUT 0.06fF +C280 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF +C281 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF +C282 pll_full_0/cp_0/down pll_full_0/cp_0/upbar 0.02fF +C283 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF +C284 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF +C285 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF +C286 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF +C287 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C288 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF +C289 divbuf_4/OUT2 divbuf_4/OUT 0.06fF +C290 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_0/Z4 0.02fF +C291 pll_full_0/pd_0/REF pll_full_0/pd_0/DOWN 1.48fF +C292 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF +C293 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF +C294 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF +C295 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF +C296 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C297 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF +C298 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/Z2 0.14fF +C299 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF +C300 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF +C301 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF +C302 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF +C303 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF +C304 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF +C305 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF +C306 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF +C307 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.01fF +C308 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF +C309 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF +C310 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF +C311 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/DIV 0.19fF +C312 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF +C313 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF +C314 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF +C315 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF +C316 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C317 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF +C318 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF +C319 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF +C320 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF +C321 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF +C322 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF +C323 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF +C324 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C325 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF +C326 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF +C327 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF +C328 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF +C329 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF +C330 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF +C331 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF +C332 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF +C333 divider_0/and_0/out1 divider_0/and_0/A 0.01fF +C334 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF +C335 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF +C336 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF +C337 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF +C338 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF +C339 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF +C340 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF +C341 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF +C342 divbuf_6/OUT3 divbuf_6/OUT 0.26fF +C343 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF +C344 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z2 0.21fF +C345 divider_0/mc2 divider_0/and_0/OUT 0.05fF +C346 divider_0/nor_1/A divider_0/and_0/B 0.08fF +C347 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C348 divbuf_3/OUT4 divbuf_3/OUT 1.11fF +C349 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF +C350 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF +C351 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C352 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF +C353 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF +C354 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF +C355 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF +C356 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C357 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF +C358 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF +C359 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C360 divbuf_4/OUT4 divbuf_4/OUT 1.11fF +C361 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C362 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/Out 0.11fF +C363 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF +C364 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF +C365 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF +C366 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF +C367 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF +C368 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF +C369 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF +C370 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF +C371 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/R 0.21fF +C372 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z3 0.09fF +C373 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF +C374 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF +C375 divider_0/nor_1/B divider_0/and_0/B 0.31fF +C376 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF +C377 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF +C378 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF +C379 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C380 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.20fF +C381 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF +C382 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF +C383 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF +C384 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF +C385 pll_full_0/cp_0/a_1710_0# pll_full_0/pd_0/DOWN 0.04fF +C386 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF +C387 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF +C388 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF +C389 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF +C390 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF +C391 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF +C392 divbuf_2/a_492_n240# divbuf_2/IN 0.13fF +C393 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF +C394 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF +C395 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF +C396 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF +C397 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF +C398 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF +C399 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF +C400 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF +C401 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF +C402 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C403 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF +C404 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF +C405 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF +C406 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C407 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z3 0.25fF +C408 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF +C409 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF +C410 io_clamp_low[2] io_analog[6] 0.53fF +C411 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF +C412 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF +C413 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C414 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF +C415 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF +C416 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF +C417 divbuf_6/OUT5 divbuf_6/OUT 43.38fF +C418 pd_0/UP pd_0/and_pd_0/Out1 0.33fF +C419 divider_0/tspc_0/Z3 divider_0/tspc_0/a_630_n680# 0.05fF +C420 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C421 pd_0/R pd_0/tspc_r_1/Z2 0.21fF +C422 divider_0/nor_1/B divider_0/tspc_0/a_630_n680# 0.01fF +C423 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF +C424 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF +C425 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF +C426 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF +C427 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF +C428 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C429 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF +C430 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C431 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C432 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF +C433 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF +C434 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C435 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF +C436 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/a_630_n680# 0.05fF +C437 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF +C438 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF +C439 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF +C440 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Z3 0.38fF +C441 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF +C442 divider_0/tspc_0/Z3 divider_0/tspc_0/Q 0.05fF +C443 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF +C444 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF +C445 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF +C446 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF +C447 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C448 divbuf_2/a_492_n240# divbuf_2/OUT2 0.42fF +C449 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF +C450 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_1/A 0.01fF +C451 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z1 0.03fF +C452 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF +C453 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.15fF +C454 divbuf_7/IN divbuf_7/OUT5 0.00fF +C455 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF +C456 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF +C457 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF +C458 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF +C459 divider_0/nor_0/B divider_0/Out 0.22fF +C460 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF +C461 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF +C462 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF +C463 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF +C464 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF +C465 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF +C466 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF +C467 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF +C468 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF +C469 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF +C470 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z4 0.36fF +C471 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Q 0.05fF +C472 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C473 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C474 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF +C475 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF +C476 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF +C477 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF +C478 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF +C479 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF +C480 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF +C481 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF +C482 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C483 divbuf_0/IN divbuf_0/OUT5 0.00fF +C484 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF +C485 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF +C486 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF +C487 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF +C488 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF +C489 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF +C490 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C491 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF +C492 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF +C493 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF +C494 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C495 cp_0/a_1710_0# cp_0/down 0.32fF +C496 cp_0/upbar cp_0/a_1710_n2840# 0.29fF +C497 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF +C498 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF +C499 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF +C500 divider_0/prescaler_0/Out divider_0/clk 0.51fF +C501 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C502 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C503 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF +C504 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF +C505 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF +C506 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/Out 0.12fF +C507 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C508 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/Z2 0.14fF +C509 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C510 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF +C511 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF +C512 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z4 0.00fF +C513 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.05fF +C514 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF +C515 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF +C516 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF +C517 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF +C518 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF +C519 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C520 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF +C521 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF +C522 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF +C523 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF +C524 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C525 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF +C526 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF +C527 divbuf_7/OUT2 divbuf_7/OUT 0.06fF +C528 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C529 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF +C530 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF +C531 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF +C532 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF +C533 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF +C534 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF +C535 pd_0/UP pd_0/tspc_r_1/z5 0.03fF +C536 pll_full_0/pd_0/tspc_r_1/z5 pll_full_0/pd_0/tspc_r_0/z5 0.02fF +C537 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C538 divider_0/tspc_0/Z2 divider_0/prescaler_0/Out 0.11fF +C539 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C540 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF +C541 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C542 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C543 divbuf_2/OUT3 divbuf_2/OUT 0.26fF +C544 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C545 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF +C546 divbuf_5/OUT3 divbuf_5/OUT 0.26fF +C547 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF +C548 io_clamp_low[2] io_clamp_high[2] 0.53fF +C549 divider_0/tspc_0/Z2 divider_0/tspc_0/Z1 1.07fF +C550 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF +C551 io_clamp_high[1] io_analog[5] 0.53fF +C552 divbuf_0/OUT divbuf_0/OUT3 0.26fF +C553 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF +C554 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C555 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF +C556 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C557 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF +C558 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF +C559 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF +C560 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF +C561 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF +C562 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF +C563 divider_0/and_0/OUT divider_0/and_0/B 0.01fF +C564 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF +C565 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF +C566 divbuf_1/OUT divbuf_1/OUT2 0.06fF +C567 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C568 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C569 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF +C570 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/Out 0.11fF +C571 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF +C572 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF +C573 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF +C574 divider_0/mc2 divider_0/and_0/out1 0.06fF +C575 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF +C576 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C577 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF +C578 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C579 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z1 1.07fF +C580 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C581 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/Out 0.19fF +C582 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/R 0.30fF +C583 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C584 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C585 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF +C586 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_0/Q 0.01fF +C587 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF +C588 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF +C589 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF +C590 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF +C591 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.26fF +C592 pd_0/R pd_0/and_pd_0/Z1 0.02fF +C593 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/REF 0.02fF +C594 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF +C595 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C596 divbuf_0/OUT3 divbuf_0/OUT5 0.01fF +C597 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/A 0.21fF +C598 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C599 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF +C600 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF +C601 divbuf_7/OUT4 divbuf_7/OUT 1.11fF +C602 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF +C603 divider_0/mc2 divider_0/nor_0/B 0.15fF +C604 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF +C605 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF +C606 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF +C607 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.45fF +C608 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF +C609 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF +C610 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF +C611 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF +C612 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF +C613 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C614 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF +C615 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.32fF +C616 divbuf_2/OUT5 divbuf_2/OUT 43.38fF +C617 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF +C618 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF +C619 divbuf_5/OUT5 divbuf_5/OUT 43.38fF +C620 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF +C621 io_clamp_low[0] io_analog[4] 0.53fF +C622 divbuf_0/OUT divbuf_0/OUT4 1.11fF +C623 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF +C624 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C625 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF +C626 pd_0/DOWN pd_0/R 0.36fF +C627 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF +C628 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF +C629 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF +C630 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF +C631 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF +C632 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF +C633 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/REF 0.19fF +C634 divider_0/tspc_0/Z2 divider_0/nor_1/A 0.23fF +C635 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF +C636 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF +C637 divbuf_1/OUT divbuf_1/OUT4 1.11fF +C638 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C639 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C640 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF +C641 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF +C642 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF +C643 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF +C644 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF +C645 divider_0/mc2 divider_0/and_0/A 0.16fF +C646 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C647 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C648 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF +C649 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF +C650 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF +C651 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF +C652 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF +C653 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF +C654 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C655 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_1/A 0.23fF +C656 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF +C657 divbuf_6/IN divbuf_6/OUT5 0.00fF +C658 pll_full_0/pd_0/tspc_r_1/z5 pll_full_0/pd_0/tspc_r_1/Z3 0.11fF +C659 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF +C660 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C661 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF +C662 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF +C663 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF +C664 pd_0/R pd_0/tspc_r_1/Z3 0.29fF +C665 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/DOWN 0.02fF +C666 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C667 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF +C668 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF +C669 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C670 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF +C671 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF +C672 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF +C673 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF +C674 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF +C675 divider_0/mc2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF +C676 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C677 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF +C678 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF +C679 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF +C680 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/Out 0.15fF +C681 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.64fF +C682 io_clamp_low[1] io_clamp_high[1] 0.53fF +C683 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF +C684 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF +C685 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF +C686 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C687 divbuf_0/OUT divbuf_0/OUT5 43.38fF +C688 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/A 0.03fF +C689 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C690 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF +C691 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF +C692 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF +C693 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divbuf_0/IN 0.05fF +C694 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF +C695 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF +C696 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF +C697 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C698 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C699 divbuf_1/a_492_n240# divbuf_1/OUT2 0.42fF +C700 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF +C701 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF +C702 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C703 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C704 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF +C705 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF +C706 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF +C707 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF +C708 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF +C709 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C710 divider_0/nor_1/B divider_0/nor_0/B 0.47fF +C711 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF +C712 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF +C713 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF +C714 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF +C715 divbuf_6/OUT2 divbuf_6/OUT 0.06fF +C716 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF +C717 divider_0/nor_1/A divider_0/and_0/A 0.01fF +C718 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF +C719 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF +C720 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF +C721 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_0/D 0.16fF +C722 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.05fF +C723 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF +C724 divbuf_3/OUT3 divbuf_3/OUT 0.26fF +C725 pd_0/R pd_0/UP 0.45fF +C726 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF +C727 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF +C728 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF +C729 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF +C730 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF +C731 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF +C732 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C733 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF +C734 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF +C735 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C736 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF +C737 divbuf_4/OUT3 divbuf_4/OUT 0.26fF +C738 pll_full_0/cp_0/down pll_full_0/cp_0/a_1710_0# 0.32fF +C739 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C740 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF +C741 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF +C742 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF +C743 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/REF 0.17fF +C744 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF +C745 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C746 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF +C747 divider_0/nor_1/B divider_0/and_0/A 0.26fF +C748 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF +C749 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF +C750 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF +C751 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF +C752 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF +C753 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF +C754 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF +C755 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF +C756 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF +C757 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF +C758 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.44fF +C759 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C760 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF +C761 cp_0/upbar cp_0/down 0.02fF +C762 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF +C763 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF +C764 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF +C765 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF +C766 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF +C767 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF +C768 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF +C769 divider_0/and_0/out1 divider_0/and_0/B 0.18fF +C770 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C771 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C772 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF +C773 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF +C774 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF +C775 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF +C776 divider_0/tspc_0/Z4 divider_0/prescaler_0/Out 0.12fF +C777 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF +C778 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF +C779 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C780 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF +C781 divbuf_6/OUT4 divbuf_6/OUT 1.11fF +C782 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF +C783 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF +C784 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF +C785 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/clk 0.05fF +C786 divider_0/tspc_0/Z2 divider_0/tspc_0/a_630_n680# 0.01fF +C787 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF +C788 divider_0/and_0/OUT divider_0/clk 0.04fF +C789 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF +C790 divbuf_3/OUT5 divbuf_3/OUT 43.38fF +C791 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C792 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_1/A 1.21fF +C793 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF +C794 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF +C795 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF +C796 divider_0/nor_0/B divider_0/and_0/B 0.29fF +C797 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF +C798 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C799 divbuf_4/OUT5 divbuf_4/OUT 43.38fF +C800 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C801 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C802 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF +C803 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF +C804 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF +C805 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF +C806 divbuf_1/OUT5 divbuf_1/OUT 43.38fF +C807 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C808 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF +C809 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF +C810 io_clamp_low[0] io_clamp_high[0] 0.53fF +C811 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/R 0.03fF +C812 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/REF 0.12fF +C813 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF +C814 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF +C815 divbuf_0/OUT divbuf_0/OUT2 0.06fF +C816 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF +C817 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF +C818 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF +C819 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF +C820 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF +C821 cp_0/a_1710_0# cp_0/out 0.84fF +C822 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF +C823 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF +C824 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF +C825 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF +C826 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF +C827 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C828 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF +C829 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C830 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF +C831 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C832 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF +C833 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF +C834 pd_0/REF pd_0/tspc_r_1/z5 0.04fF +C835 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF +C836 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF +C837 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF +C838 divider_0/and_0/A divider_0/and_0/B 0.18fF +C839 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C840 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C841 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C842 divbuf_2/OUT5 divbuf_2/IN 0.00fF +C843 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF +C844 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF +C845 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C846 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.01fF +C847 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.19fF +C848 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.14fF +C849 divbuf_5/IN divbuf_5/OUT5 0.00fF Xpd_0 VDD gnd pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd Xcp_0 cp_0/vbias vdd gnd cp_0/out cp_0/down cp_0/upbar cp Xfilter_0 gnd filter_0/v filter @@ -1007,9 +1007,9 @@ C875 io_oeb[2] vdd 0.61fF C876 io_in_3v3[24] vdd 0.61fF C877 io_in_3v3[3] vdd 0.61fF -C878 gpio_noesd[17] vdd 0.61fF +C878 gpio_noesd[17] vdd 2.32fF C879 io_in[3] vdd 0.61fF -C880 gpio_analog[17] vdd 0.61fF +C880 gpio_analog[17] vdd 2.30fF C881 io_out[3] vdd 0.61fF C882 io_oeb[3] vdd 0.61fF C883 io_in_3v3[4] vdd 0.61fF @@ -1020,8 +1020,8 @@ C888 io_out[23] vdd 0.61fF C889 io_in[23] vdd 0.61fF C890 io_in_3v3[23] vdd 0.61fF -C891 gpio_noesd[16] vdd 0.61fF -C892 gpio_analog[16] vdd 0.61fF +C891 gpio_noesd[16] vdd 2.30fF +C892 gpio_analog[16] vdd 2.30fF C893 io_in_3v3[5] vdd 0.61fF C894 io_in[5] vdd 0.61fF C895 io_out[5] vdd 0.61fF @@ -1030,8 +1030,8 @@ C898 io_out[22] vdd 0.61fF C899 io_in[22] vdd 0.61fF C900 io_in_3v3[22] vdd 0.61fF -C901 gpio_noesd[15] vdd 0.61fF -C902 gpio_analog[15] vdd 0.61fF +C901 gpio_noesd[15] vdd 2.31fF +C902 gpio_analog[15] vdd 2.30fF C903 io_in_3v3[6] vdd 0.61fF C904 io_in[6] vdd 0.61fF C905 io_out[6] vdd 0.61fF @@ -1040,8 +1040,8 @@ C908 io_out[21] vdd 0.61fF C909 io_in[21] vdd 0.61fF C910 io_in_3v3[21] vdd 0.61fF -C911 gpio_noesd[14] vdd 0.61fF -C912 gpio_analog[14] vdd 0.61fF +C911 gpio_noesd[14] vdd 2.30fF +C912 gpio_analog[14] vdd 2.29fF C913 vssa1 vdd 63.32fF C914 vssd2 vdd 38.54fF C915 vssd1 vdd 13.04fF @@ -1051,8 +1051,8 @@ C919 io_out[20] vdd 0.61fF C920 io_in[20] vdd 0.61fF C921 io_in_3v3[20] vdd 0.61fF -C922 gpio_noesd[13] vdd 0.61fF -C923 gpio_analog[13] vdd 0.61fF +C922 gpio_noesd[13] vdd 2.31fF +C923 gpio_analog[13] vdd 2.30fF C924 gpio_analog[0] vdd 0.61fF C925 gpio_noesd[0] vdd 0.61fF C926 io_in_3v3[7] vdd 0.61fF @@ -1063,8 +1063,8 @@ C931 io_out[19] vdd 0.61fF C932 io_in[19] vdd 0.61fF C933 io_in_3v3[19] vdd 0.61fF -C934 gpio_noesd[12] vdd 0.61fF -C935 gpio_analog[12] vdd 0.61fF +C934 gpio_noesd[12] vdd 2.32fF +C935 gpio_analog[12] vdd 2.30fF C936 gpio_analog[1] vdd 0.61fF C937 gpio_noesd[1] vdd 0.61fF C938 io_in_3v3[8] vdd 0.61fF @@ -1075,8 +1075,8 @@ C943 io_out[18] vdd 0.61fF C944 io_in[18] vdd 0.61fF C945 io_in_3v3[18] vdd 0.61fF -C946 gpio_noesd[11] vdd 0.61fF -C947 gpio_analog[11] vdd 0.61fF +C946 gpio_noesd[11] vdd 2.30fF +C947 gpio_analog[11] vdd 2.29fF C948 gpio_analog[2] vdd 0.61fF C949 gpio_noesd[2] vdd 0.61fF C950 io_in_3v3[9] vdd 0.61fF @@ -1087,8 +1087,8 @@ C955 io_out[17] vdd 0.61fF C956 io_in[17] vdd 0.61fF C957 io_in_3v3[17] vdd 0.61fF -C958 gpio_noesd[10] vdd 0.61fF -C959 gpio_analog[10] vdd 0.61fF +C958 gpio_noesd[10] vdd 2.31fF +C959 gpio_analog[10] vdd 2.29fF C960 gpio_analog[3] vdd 0.61fF C961 gpio_noesd[3] vdd 0.61fF C962 io_in_3v3[10] vdd 0.61fF @@ -1099,8 +1099,8 @@ C967 io_out[16] vdd 0.61fF C968 io_in[16] vdd 0.61fF C969 io_in_3v3[16] vdd 0.61fF -C970 gpio_noesd[9] vdd 0.61fF -C971 gpio_analog[9] vdd 0.61fF +C970 gpio_noesd[9] vdd 2.28fF +C971 gpio_analog[9] vdd 2.28fF C972 gpio_analog[4] vdd 0.61fF C973 gpio_noesd[4] vdd 0.61fF C974 io_in_3v3[11] vdd 0.61fF @@ -1111,8 +1111,8 @@ C979 io_out[15] vdd 0.61fF C980 io_in[15] vdd 0.61fF C981 io_in_3v3[15] vdd 0.61fF -C982 gpio_noesd[8] vdd 0.61fF -C983 gpio_analog[8] vdd 0.61fF +C982 gpio_noesd[8] vdd 2.28fF +C983 gpio_analog[8] vdd 2.26fF C984 gpio_analog[5] vdd 0.61fF C985 gpio_noesd[5] vdd 0.61fF C986 io_in_3v3[12] vdd 0.61fF @@ -1123,8 +1123,8 @@ C991 io_out[14] vdd 0.61fF C992 io_in[14] vdd 0.61fF C993 io_in_3v3[14] vdd 0.61fF -C994 gpio_noesd[7] vdd 0.61fF -C995 gpio_analog[7] vdd 0.61fF +C994 gpio_noesd[7] vdd 2.30fF +C995 gpio_analog[7] vdd 2.28fF C996 vssa2 vdd 38.35fF C997 gpio_analog[6] vdd 5.71fF C998 gpio_noesd[6] vdd 5.70fF