power grids
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds index 2d35c18..4395584 100644 --- a/gds/user_analog_project_wrapper.gds +++ b/gds/user_analog_project_wrapper.gds Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag index 48429a4..bea6f88 100644 --- a/mag/user_analog_project_wrapper.mag +++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@ magic tech sky130A -timestamp 1642896605 +timestamp 1642897958 << metal2 >> rect 262 -400 318 240 rect 853 -400 909 240 @@ -562,10 +562,15 @@ rect -400 281893 830 282121 rect -400 280000 4941 281893 rect -400 279721 830 280000 +rect 273285 277424 287287 277475 rect 291170 277424 292400 277681 rect -400 276863 830 277121 +rect 273285 276989 292400 277424 rect -400 274970 4906 276863 -rect 287005 275531 292400 277424 +rect 273285 275847 273813 276989 +rect 275123 275847 292400 276989 +rect 273285 275531 292400 275847 +rect 273285 275503 287287 275531 rect 291170 275281 292400 275531 rect -400 274721 830 274970 rect 291170 272430 292400 272681 @@ -693,8 +698,13 @@ rect -400 83589 830 83844 rect -400 81696 4990 83589 rect -400 81444 830 81696 +rect 280813 75549 287932 75721 rect 291170 75549 292400 75815 -rect 287122 73656 292400 75549 +rect 280813 75451 292400 75549 +rect 280813 73748 281123 75451 +rect 282980 73748 292400 75451 +rect 280813 73656 292400 73748 +rect 280813 73516 287932 73656 rect 291170 73415 292400 73656 rect 291170 70535 292400 70815 rect 287095 68642 292400 70535 @@ -775,6 +785,9 @@ rect 291760 1363 292400 1419 rect -400 772 240 828 rect 291760 772 292400 828 +<< via3 >> +rect 273813 275847 275123 276989 +rect 281123 73748 282980 75451 << metal4 >> rect 82797 351150 85297 352400 rect 87947 351150 90447 352400 @@ -788,6 +801,32 @@ rect 114054 349155 116090 351150 rect 159668 349191 161704 351150 rect 164874 349155 166910 351150 +rect 86463 78792 88763 338537 +rect 75859 75823 91030 78792 +rect 127056 75823 129356 335568 +rect 164365 77556 166665 337301 +rect 153761 75823 168932 77556 +rect 204552 76938 206852 336683 +rect 231137 77556 233437 337301 +rect 273495 276989 275423 277344 +rect 273495 275847 273813 276989 +rect 275123 275847 275423 276989 +rect 273495 275548 275423 275847 +rect 193948 75823 209119 76938 +rect 220533 75823 235704 77556 +rect 6802 75789 279373 75823 +rect 6802 75451 283186 75789 +rect 6802 73748 281123 75451 +rect 282980 73748 283186 75451 +rect 6802 73413 283186 73748 +rect 86463 6833 88763 73413 +rect 127056 3864 129356 73413 +rect 164365 5597 166665 73413 +rect 204552 4979 206852 73413 +rect 231137 5597 233437 73413 +rect 278502 73408 283186 73413 +<< via4 >> +rect 273813 275847 275123 276989 << metal5 >> rect 82797 351150 85297 352400 rect 87947 351150 90447 352400 @@ -801,31 +840,51 @@ rect 114054 349155 116090 351150 rect 159668 349191 161704 351150 rect 164874 349155 166910 351150 +rect 79150 280881 81491 338780 +rect 75859 277912 91030 280881 +rect 119743 277912 122084 335811 +rect 157052 279645 159393 337544 +rect 153761 277912 168932 279645 +rect 197239 279027 199580 336926 +rect 223824 279645 226165 337544 +rect 193948 277912 209119 279027 +rect 220533 277912 235704 279645 +rect 12023 277906 272994 277912 +rect 12023 276989 275442 277906 +rect 12023 275847 273813 276989 +rect 275123 275847 275442 276989 +rect 12023 275136 275442 275847 +rect 12023 275109 272994 275136 +rect 79150 5833 81491 275109 +rect 119743 2864 122084 275109 +rect 157052 4597 159393 275109 +rect 197239 3979 199580 275109 +rect 223824 4597 226165 275109 << comment >> rect -50 352000 292050 352050 rect -50 0 0 352000 rect 292000 0 292050 352000 rect -50 -50 292050 0 -use cp cp_0 -timestamp 1640911461 -transform 1 0 54462 0 1 195288 -box -415 -1715 4690 2035 -use pll_full pll_full_0 -timestamp 1642811007 -transform 1 0 183060 0 1 147974 -box -5415 -2690 26430 12835 +use pd pd_2 +timestamp 1642897958 +transform 1 0 65676 0 1 170751 +box -215 -855 1685 810 +use pd pd_1 +timestamp 1642897958 +transform 1 0 58362 0 1 223414 +box -215 -855 1685 810 +use divider divider_2 +timestamp 1642897958 +transform 1 0 260331 0 1 239350 +box -490 -235 4690 2150 +use ro_complete ro_complete_0 +timestamp 1642897958 +transform -1 0 245567 0 -1 235887 +box -57 -5330 4455 1440 use pd pd_0 -timestamp 1642811703 +timestamp 1642897958 transform 1 0 103126 0 1 258815 box -215 -855 1685 810 -use filter filter_0 -timestamp 1640983258 -transform 1 0 77692 0 1 317254 -box -1800 -11005 6240 390 -use divider divider_0 -timestamp 1642812614 -transform 1 0 166638 0 1 265093 -box -490 -235 4690 2150 use divbuf divbuf_7 timestamp 1641017053 transform 1 0 245779 0 1 306691 @@ -838,10 +897,6 @@ timestamp 1641017053 transform 1 0 245938 0 1 311543 box -460 -1085 31200 495 -use ro_complete ro_complete_1 -timestamp 1642812614 -transform 1 0 247313 0 1 328719 -box -57 -5330 4455 1440 use divbuf divbuf_2 timestamp 1641017053 transform 1 0 246097 0 1 316394 @@ -862,6 +917,30 @@ timestamp 1641017053 transform 1 0 244347 0 1 337471 box -460 -1085 31200 495 +use ro_complete ro_complete_1 +timestamp 1642897958 +transform 1 0 247313 0 1 328719 +box -57 -5330 4455 1440 +use divider divider_0 +timestamp 1642897958 +transform 1 0 246803 0 1 129340 +box -490 -235 4690 2150 +use divider divider_1 +timestamp 1642897958 +transform 1 0 46099 0 1 170885 +box -490 -235 4690 2150 +use cp cp_1 +timestamp 1640911461 +transform 1 0 52227 0 1 262480 +box -415 -1715 4690 2035 +use filter filter_1 +timestamp 1640983258 +transform 1 0 38025 0 1 41313 +box -1800 -11005 6240 390 +use pll_full pll_full_1 +timestamp 1642897958 +transform 1 0 31292 0 1 318138 +box -5415 -2690 26430 12835 << labels >> flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0] port 0 nsew signal bidirectional
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice index 38cbd75..caa7f83 100644 --- a/netgen/user_analog_project_wrapper.spice +++ b/netgen/user_analog_project_wrapper.spice
@@ -106,863 +106,1485 @@ + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] + wbs_stb_i wbs_we_i -C0 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF -C1 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF -C2 io_clamp_high[2] io_analog[6] 0.53fF +C0 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF +C1 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF +C2 divider_2/nor_0/B divider_2/tspc_2/Z3 0.38fF C3 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF -C4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C5 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C6 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C7 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C8 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF -C9 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF -C10 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF -C11 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.29fF -C12 pll_full_0/pd_0/UP pll_full_0/pd_0/DOWN 4.58fF -C13 divider_0/tspc_1/a_630_n680# divider_0/tspc_0/Q 0.01fF -C14 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar1 0.11fF -C15 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF -C16 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF -C17 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF -C18 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF -C19 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/A 0.15fF -C20 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z3 0.38fF -C21 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C22 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C23 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C24 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF -C25 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF -C26 pll_full_0/pd_0/R pll_full_0/pd_0/DOWN 0.36fF -C27 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF -C28 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF -C29 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C30 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF -C31 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C32 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF -C33 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C34 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C35 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF -C36 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF -C37 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF -C38 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF -C39 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF -C40 pd_0/R pd_0/and_pd_0/Out1 0.33fF -C41 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Z3 0.03fF -C42 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF -C43 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF -C44 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF -C45 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF -C46 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z2 0.30fF -C47 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF -C48 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C49 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C50 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF -C51 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF -C52 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF -C53 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF -C54 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF -C55 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF -C56 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF -C57 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT2 1.37fF -C58 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF -C59 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF -C60 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF -C61 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF -C62 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C63 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C64 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF -C65 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C66 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF -C67 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z1 0.17fF -C68 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF -C69 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C70 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C71 divbuf_2/OUT2 divbuf_2/OUT 0.06fF -C72 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF -C73 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z4 0.65fF -C74 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C75 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF -C76 divbuf_5/OUT2 divbuf_5/OUT 0.06fF -C77 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF -C78 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF -C79 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.32fF -C80 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C81 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C82 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF -C83 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF -C84 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF -C85 io_clamp_low[1] io_analog[5] 0.53fF -C86 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF -C87 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C88 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C89 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF -C90 pd_0/DIV pd_0/R 0.51fF -C91 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF -C92 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF -C93 pd_0/UP pd_0/and_pd_0/Z1 0.06fF -C94 filter_0/a_4216_n2998# filter_0/v 0.31fF -C95 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Z3 0.03fF -C96 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C97 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF -C98 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF -C99 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF -C100 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/A 0.35fF -C101 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C102 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C103 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C104 cp_0/out cp_0/a_1710_n2840# 0.61fF -C105 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF -C106 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF -C107 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF -C108 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C109 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/Out 0.08fF -C110 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF -C111 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF -C112 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C113 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF -C114 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/DIV 0.02fF -C115 divider_0/mc2 divider_0/nor_1/A 0.04fF -C116 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF -C117 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF -C118 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF -C119 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF -C120 divbuf_2/a_492_n240# divbuf_2/OUT5 0.01fF -C121 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF -C122 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF -C123 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF -C124 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C125 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C126 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/A 0.55fF -C127 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C128 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF -C129 pd_0/DOWN pd_0/UP 0.46fF -C130 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF -C131 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF -C132 divbuf_7/OUT3 divbuf_7/OUT 0.26fF -C133 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF -C134 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF -C135 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF -C136 divider_0/tspc_2/Z3 divider_0/Out 0.05fF -C137 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C138 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF -C139 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF -C140 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF -C141 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF -C142 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF -C143 divider_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.45fF -C144 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF -C145 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF -C146 divider_0/and_0/B divider_0/and_0/Z1 0.07fF -C147 divbuf_2/OUT4 divbuf_2/OUT 1.11fF -C148 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C149 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF -C150 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF -C151 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF -C152 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C153 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.04fF -C154 divbuf_5/OUT4 divbuf_5/OUT 1.11fF -C155 divider_0/mc2 divider_0/nor_1/B 0.06fF -C156 divider_0/tspc_0/Z3 divider_0/tspc_0/Z1 0.06fF -C157 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF -C158 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF -C159 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF -C160 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF -C161 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF -C162 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/B 0.22fF -C163 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C164 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.61fF -C165 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF -C166 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF -C167 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF -C168 pll_full_0/divider_0/nor_0/B pll_full_0/divbuf_0/IN 0.29fF -C169 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF -C170 pll_full_0/pd_0/R pll_full_0/pd_0/DIV 0.51fF -C171 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z3 0.09fF -C172 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF -C173 filter_0/a_4216_n5230# filter_0/v 0.19fF -C174 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF -C175 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C176 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF -C177 divbuf_1/OUT divbuf_1/OUT3 0.26fF -C178 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF -C179 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF -C180 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.45fF -C181 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C182 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C183 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF -C184 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF -C185 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF -C186 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF -C187 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C188 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z1 0.06fF -C189 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF -C190 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF -C191 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF -C192 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/Out 0.11fF -C193 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF -C194 pll_full_0/pd_0/UP pll_full_0/pd_0/R 0.46fF -C195 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF -C196 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF -C197 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF -C198 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C199 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF -C200 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/Z3 0.20fF -C201 pll_full_0/pd_0/tspc_r_1/z5 pll_full_0/pd_0/REF 0.04fF -C202 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF -C203 divbuf_3/IN divbuf_3/OUT5 0.00fF -C204 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF -C205 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF -C206 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF -C207 divbuf_7/OUT5 divbuf_7/OUT 43.38fF -C208 cp_0/a_10_n50# cp_0/vbias 0.19fF -C209 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF -C210 pd_0/R pd_0/REF 0.61fF -C211 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF -C212 divider_0/tspc_0/Z4 divider_0/tspc_0/a_630_n680# 0.12fF -C213 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF -C214 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF -C215 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF -C216 divbuf_4/IN divbuf_4/OUT5 0.00fF -C217 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/Z3 0.20fF -C218 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF -C219 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF -C220 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF -C221 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF -C222 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF -C223 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C224 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF -C225 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF -C226 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF -C227 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF -C228 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF -C229 io_clamp_high[0] io_analog[4] 0.53fF -C230 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C231 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF -C232 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C233 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF -C234 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF -C235 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF -C236 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF -C237 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF -C238 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z3 0.25fF -C239 divider_0/tspc_0/Z3 divider_0/nor_1/A 0.38fF -C240 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF -C241 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF -C242 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF -C243 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF -C244 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF -C245 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C246 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF -C247 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C248 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C249 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.01fF -C250 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF -C251 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF -C252 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z1 0.71fF -C253 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF -C254 divider_0/nor_1/B divider_0/nor_1/A 1.21fF -C255 divider_0/mc2 divider_0/and_0/B 0.20fF -C256 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Z3 0.38fF -C257 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF -C258 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C259 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF -C260 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/Out 0.28fF -C261 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF -C262 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z3 0.27fF -C263 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF -C264 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF -C265 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF -C266 divbuf_1/OUT5 divbuf_1/IN 0.00fF -C267 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C268 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/nor_1/A 0.38fF -C269 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF -C270 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF -C271 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF -C272 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/Out 0.91fF -C273 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF -C274 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF -C275 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C276 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF -C277 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C278 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF -C279 divbuf_3/OUT2 divbuf_3/OUT 0.06fF -C280 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF -C281 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF -C282 pll_full_0/cp_0/down pll_full_0/cp_0/upbar 0.02fF -C283 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF -C284 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF -C285 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF -C286 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF -C287 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C288 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF -C289 divbuf_4/OUT2 divbuf_4/OUT 0.06fF -C290 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C291 pll_full_0/pd_0/REF pll_full_0/pd_0/DOWN 1.48fF -C292 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF -C293 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF -C294 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF -C295 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF -C296 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C297 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF -C298 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/Z2 0.14fF -C299 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF -C300 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF -C301 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF -C302 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF -C303 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF -C304 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF -C305 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF -C306 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF -C307 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.01fF -C308 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF -C309 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF -C310 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF -C311 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/DIV 0.19fF -C312 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF -C313 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF -C314 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF -C315 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF -C316 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C317 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF -C318 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF -C319 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF -C320 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF -C321 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF -C322 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF -C323 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF -C324 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C325 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF -C326 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF -C327 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF -C328 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF -C329 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF -C330 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF -C331 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF -C332 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF -C333 divider_0/and_0/out1 divider_0/and_0/A 0.01fF -C334 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF -C335 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF -C336 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF -C337 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF -C338 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF -C339 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF -C340 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF -C341 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF -C342 divbuf_6/OUT3 divbuf_6/OUT 0.26fF -C343 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF -C344 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z2 0.21fF -C345 divider_0/mc2 divider_0/and_0/OUT 0.05fF -C346 divider_0/nor_1/A divider_0/and_0/B 0.08fF -C347 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C348 divbuf_3/OUT4 divbuf_3/OUT 1.11fF -C349 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF -C350 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF -C351 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C352 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF -C353 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF -C354 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF -C355 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF -C356 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C357 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF -C358 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF -C359 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C360 divbuf_4/OUT4 divbuf_4/OUT 1.11fF -C361 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C362 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/Out 0.11fF -C363 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF -C364 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF -C365 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF -C366 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF -C367 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF -C368 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF -C369 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF -C370 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF -C371 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/R 0.21fF -C372 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z3 0.09fF -C373 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF -C374 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF -C375 divider_0/nor_1/B divider_0/and_0/B 0.31fF -C376 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF -C377 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF -C378 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF -C379 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C380 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.20fF -C381 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF -C382 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF -C383 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF -C384 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF -C385 pll_full_0/cp_0/a_1710_0# pll_full_0/pd_0/DOWN 0.04fF -C386 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF -C387 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF -C388 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF -C389 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF -C390 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF -C391 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF -C392 divbuf_2/a_492_n240# divbuf_2/IN 0.13fF -C393 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF -C394 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF -C395 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF -C396 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF -C397 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF -C398 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF -C399 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF -C400 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF -C401 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF -C402 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C403 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF -C404 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF -C405 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF -C406 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C407 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z3 0.25fF -C408 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF -C409 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF -C410 io_clamp_low[2] io_analog[6] 0.53fF -C411 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF -C412 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF -C413 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C414 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF -C415 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF -C416 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF -C417 divbuf_6/OUT5 divbuf_6/OUT 43.38fF -C418 pd_0/UP pd_0/and_pd_0/Out1 0.33fF -C419 divider_0/tspc_0/Z3 divider_0/tspc_0/a_630_n680# 0.05fF -C420 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C421 pd_0/R pd_0/tspc_r_1/Z2 0.21fF -C422 divider_0/nor_1/B divider_0/tspc_0/a_630_n680# 0.01fF -C423 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF -C424 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF -C425 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF -C426 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF -C427 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF -C428 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C429 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF -C430 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C431 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C432 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF -C433 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF -C434 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C435 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF -C436 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/a_630_n680# 0.05fF -C437 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF -C438 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF -C439 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF -C440 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Z3 0.38fF -C441 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF -C442 divider_0/tspc_0/Z3 divider_0/tspc_0/Q 0.05fF -C443 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF -C444 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF -C445 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF -C446 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF -C447 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C448 divbuf_2/a_492_n240# divbuf_2/OUT2 0.42fF -C449 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF -C450 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_1/A 0.01fF -C451 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z1 0.03fF -C452 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF -C453 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.15fF -C454 divbuf_7/IN divbuf_7/OUT5 0.00fF -C455 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF -C456 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF -C457 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF -C458 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF -C459 divider_0/nor_0/B divider_0/Out 0.22fF -C460 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF -C461 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF -C462 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF -C463 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF -C464 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF -C465 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF -C466 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF -C467 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF -C468 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF -C469 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C470 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z4 0.36fF -C471 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Q 0.05fF -C472 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C473 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C474 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF -C475 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF -C476 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF -C477 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF -C478 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF -C479 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF -C480 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF -C481 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF -C482 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C483 divbuf_0/IN divbuf_0/OUT5 0.00fF -C484 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF -C485 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF -C486 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF -C487 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF -C488 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF -C489 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF -C490 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C491 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF -C492 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF -C493 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF -C494 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C495 cp_0/a_1710_0# cp_0/down 0.32fF -C496 cp_0/upbar cp_0/a_1710_n2840# 0.29fF -C497 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF -C498 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF -C499 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF -C500 divider_0/prescaler_0/Out divider_0/clk 0.51fF -C501 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C502 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C503 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF -C504 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF -C505 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF -C506 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/Out 0.12fF -C507 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C508 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/Z2 0.14fF -C509 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C510 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF -C511 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF -C512 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z4 0.00fF -C513 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.05fF -C514 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF -C515 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF -C516 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF -C517 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF -C518 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF -C519 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C520 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF -C521 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF -C522 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF -C523 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF -C524 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C525 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF -C526 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF -C527 divbuf_7/OUT2 divbuf_7/OUT 0.06fF -C528 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C529 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF -C530 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF -C531 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF -C532 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF -C533 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF -C534 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF -C535 pd_0/UP pd_0/tspc_r_1/z5 0.03fF -C536 pll_full_0/pd_0/tspc_r_1/z5 pll_full_0/pd_0/tspc_r_0/z5 0.02fF -C537 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C538 divider_0/tspc_0/Z2 divider_0/prescaler_0/Out 0.11fF -C539 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C540 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF -C541 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C542 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C543 divbuf_2/OUT3 divbuf_2/OUT 0.26fF -C544 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C545 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF -C546 divbuf_5/OUT3 divbuf_5/OUT 0.26fF -C547 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF -C548 io_clamp_low[2] io_clamp_high[2] 0.53fF -C549 divider_0/tspc_0/Z2 divider_0/tspc_0/Z1 1.07fF -C550 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF -C551 io_clamp_high[1] io_analog[5] 0.53fF -C552 divbuf_0/OUT divbuf_0/OUT3 0.26fF -C553 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF -C554 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C555 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF -C556 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C557 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF -C558 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF -C559 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF -C560 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF -C561 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF -C562 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF -C563 divider_0/and_0/OUT divider_0/and_0/B 0.01fF -C564 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF -C565 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF -C566 divbuf_1/OUT divbuf_1/OUT2 0.06fF -C567 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C568 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C569 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF -C570 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/Out 0.11fF -C571 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF -C572 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF -C573 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF -C574 divider_0/mc2 divider_0/and_0/out1 0.06fF -C575 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF -C576 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C577 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF -C578 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C579 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z1 1.07fF -C580 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C581 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/Out 0.19fF -C582 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/R 0.30fF -C583 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C584 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C585 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF -C586 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_0/Q 0.01fF -C587 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF -C588 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF -C589 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF -C590 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF -C591 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.26fF -C592 pd_0/R pd_0/and_pd_0/Z1 0.02fF -C593 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/REF 0.02fF -C594 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF -C595 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C596 divbuf_0/OUT3 divbuf_0/OUT5 0.01fF -C597 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/A 0.21fF -C598 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C599 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF -C600 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF -C601 divbuf_7/OUT4 divbuf_7/OUT 1.11fF -C602 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF -C603 divider_0/mc2 divider_0/nor_0/B 0.15fF -C604 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF -C605 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF -C606 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF -C607 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.45fF -C608 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF -C609 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF -C610 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF -C611 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF -C612 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF -C613 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C614 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF -C615 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.32fF -C616 divbuf_2/OUT5 divbuf_2/OUT 43.38fF -C617 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF -C618 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF -C619 divbuf_5/OUT5 divbuf_5/OUT 43.38fF -C620 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF -C621 io_clamp_low[0] io_analog[4] 0.53fF -C622 divbuf_0/OUT divbuf_0/OUT4 1.11fF -C623 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF -C624 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C625 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF -C626 pd_0/DOWN pd_0/R 0.36fF -C627 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF -C628 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF -C629 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF -C630 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF -C631 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF -C632 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF -C633 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/REF 0.19fF -C634 divider_0/tspc_0/Z2 divider_0/nor_1/A 0.23fF -C635 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF -C636 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF -C637 divbuf_1/OUT divbuf_1/OUT4 1.11fF -C638 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C639 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C640 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF -C641 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF -C642 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF -C643 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF -C644 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF -C645 divider_0/mc2 divider_0/and_0/A 0.16fF -C646 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C647 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C648 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C649 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF -C650 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF -C651 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF -C652 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF -C653 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF -C654 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C655 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_1/A 0.23fF -C656 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF -C657 divbuf_6/IN divbuf_6/OUT5 0.00fF -C658 pll_full_0/pd_0/tspc_r_1/z5 pll_full_0/pd_0/tspc_r_1/Z3 0.11fF -C659 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF -C660 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C661 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF -C662 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF -C663 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF -C664 pd_0/R pd_0/tspc_r_1/Z3 0.29fF -C665 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/DOWN 0.02fF -C666 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C667 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF -C668 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF -C669 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C670 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF -C671 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF -C672 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF -C673 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF -C674 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF -C675 divider_0/mc2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF -C676 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C677 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF -C678 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF -C679 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF -C680 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/Out 0.15fF -C681 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.64fF -C682 io_clamp_low[1] io_clamp_high[1] 0.53fF -C683 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF -C684 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF -C685 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF -C686 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C687 divbuf_0/OUT divbuf_0/OUT5 43.38fF -C688 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/A 0.03fF -C689 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C690 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF -C691 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF -C692 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF -C693 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divbuf_0/IN 0.05fF -C694 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF -C695 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF -C696 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF -C697 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C698 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C699 divbuf_1/a_492_n240# divbuf_1/OUT2 0.42fF -C700 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF -C701 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF -C702 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C703 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C704 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF -C705 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF -C706 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF -C707 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF -C708 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF -C709 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C710 divider_0/nor_1/B divider_0/nor_0/B 0.47fF -C711 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF -C712 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF -C713 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF -C714 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF -C715 divbuf_6/OUT2 divbuf_6/OUT 0.06fF -C716 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF -C717 divider_0/nor_1/A divider_0/and_0/A 0.01fF -C718 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF -C719 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF -C720 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF -C721 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_0/D 0.16fF -C722 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.05fF -C723 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF -C724 divbuf_3/OUT3 divbuf_3/OUT 0.26fF -C725 pd_0/R pd_0/UP 0.45fF -C726 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF -C727 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF -C728 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF -C729 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF -C730 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF -C731 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF -C732 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C733 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF -C734 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF -C735 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C736 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF -C737 divbuf_4/OUT3 divbuf_4/OUT 0.26fF -C738 pll_full_0/cp_0/down pll_full_0/cp_0/a_1710_0# 0.32fF -C739 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C740 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF -C741 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF -C742 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF -C743 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/REF 0.17fF -C744 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF -C745 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C746 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF -C747 divider_0/nor_1/B divider_0/and_0/A 0.26fF -C748 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF -C749 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF -C750 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF -C751 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF -C752 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF -C753 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF -C754 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF -C755 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF -C756 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF -C757 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF -C758 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.44fF -C759 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C760 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF -C761 cp_0/upbar cp_0/down 0.02fF -C762 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF -C763 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF -C764 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF -C765 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF -C766 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF -C767 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF -C768 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF -C769 divider_0/and_0/out1 divider_0/and_0/B 0.18fF -C770 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C771 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C772 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF -C773 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF -C774 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF -C775 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF -C776 divider_0/tspc_0/Z4 divider_0/prescaler_0/Out 0.12fF -C777 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF -C778 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF -C779 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C780 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF -C781 divbuf_6/OUT4 divbuf_6/OUT 1.11fF -C782 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF -C783 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF -C784 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF -C785 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/clk 0.05fF -C786 divider_0/tspc_0/Z2 divider_0/tspc_0/a_630_n680# 0.01fF -C787 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF -C788 divider_0/and_0/OUT divider_0/clk 0.04fF -C789 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF -C790 divbuf_3/OUT5 divbuf_3/OUT 43.38fF -C791 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C792 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_1/A 1.21fF -C793 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF -C794 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF -C795 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF -C796 divider_0/nor_0/B divider_0/and_0/B 0.29fF -C797 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF -C798 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C799 divbuf_4/OUT5 divbuf_4/OUT 43.38fF -C800 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C801 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C802 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF -C803 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF -C804 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF -C805 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF -C806 divbuf_1/OUT5 divbuf_1/OUT 43.38fF -C807 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C808 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF -C809 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF -C810 io_clamp_low[0] io_clamp_high[0] 0.53fF -C811 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/R 0.03fF -C812 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/REF 0.12fF -C813 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF -C814 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF -C815 divbuf_0/OUT divbuf_0/OUT2 0.06fF -C816 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF -C817 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF -C818 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF -C819 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF -C820 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF -C821 cp_0/a_1710_0# cp_0/out 0.84fF -C822 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF -C823 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF -C824 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF -C825 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF -C826 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF -C827 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C828 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF -C829 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C830 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF -C831 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C832 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF -C833 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF -C834 pd_0/REF pd_0/tspc_r_1/z5 0.04fF -C835 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF -C836 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF -C837 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF -C838 divider_0/and_0/A divider_0/and_0/B 0.18fF -C839 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C840 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C841 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C842 divbuf_2/OUT5 divbuf_2/IN 0.00fF -C843 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF -C844 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF -C845 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C846 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.01fF -C847 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.19fF -C848 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.14fF -C849 divbuf_5/IN divbuf_5/OUT5 0.00fF +C4 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF +C5 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C6 divbuf_7/OUT2 divbuf_7/OUT 0.06fF +C7 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF +C8 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF +C9 divider_0/mc2 divider_0/nor_0/B 0.15fF +C10 pd_0/R pd_0/and_pd_0/Z1 0.02fF +C11 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF +C12 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C13 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF +C14 divider_1/tspc_0/Z4 divider_1/tspc_0/Z1 0.00fF +C15 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z3 0.65fF +C16 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C17 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C18 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF +C19 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF +C20 divider_1/tspc_1/Q divider_1/tspc_2/Z2 0.14fF +C21 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF +C22 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z3 0.25fF +C23 divider_2/tspc_1/Z3 divider_2/tspc_0/Q 0.45fF +C24 divbuf_4/OUT3 divbuf_4/OUT 0.26fF +C25 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF +C26 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z2 0.36fF +C27 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C28 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF +C29 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Qbar1 0.38fF +C30 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF +C31 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF +C32 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/a_630_n680# 0.19fF +C33 pd_2/DOWN pd_2/tspc_r_1/Qbar 0.02fF +C34 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF +C35 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF +C36 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF +C37 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF +C38 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF +C39 divider_1/nor_0/B divider_1/tspc_2/Z1 0.03fF +C40 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/a0 0.13fF +C41 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF +C42 divider_2/tspc_1/Q divider_2/nor_0/B 0.22fF +C43 divider_2/and_0/OUT divider_2/prescaler_0/tspc_0/D 0.03fF +C44 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF +C45 divbuf_5/OUT3 divbuf_5/OUT 0.26fF +C46 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF +C47 pd_0/DIV pd_0/R 0.51fF +C48 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF +C49 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/Z2 0.06fF +C50 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF +C51 pd_1/R pd_1/and_pd_0/Out1 0.33fF +C52 pd_1/REF pd_1/tspc_r_1/Z4 0.02fF +C53 pd_1/tspc_r_1/Qbar1 pd_1/UP 0.11fF +C54 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF +C55 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/Out 0.11fF +C56 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF +C57 pd_2/tspc_r_1/Qbar pd_2/and_pd_0/Out1 0.05fF +C58 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF +C59 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF +C60 divbuf_1/OUT5 divbuf_1/OUT 43.38fF +C61 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF +C62 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF +C63 divider_2/nor_1/B divider_2/tspc_0/a_630_n680# 0.01fF +C64 divider_1/and_0/out1 divider_1/and_0/B 0.18fF +C65 ro_complete_1/a1 ro_complete_1/cbank_1/v 0.05fF +C66 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF +C67 pll_full_0/cp_0/down pll_full_0/cp_0/upbar 0.02fF +C68 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF +C69 pd_1/DIV pd_1/tspc_r_0/Qbar1 0.12fF +C70 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF +C71 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF +C72 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF +C73 divider_1/mc2 divider_1/nor_1/A 0.04fF +C74 divider_0/and_0/OUT divider_0/and_0/B 0.01fF +C75 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF +C76 pd_2/tspc_r_0/Z1 pd_2/DIV 0.17fF +C77 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_0/D 0.16fF +C78 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.05fF +C79 divider_1/nor_1/A divider_1/prescaler_0/tspc_1/Q 0.03fF +C80 divider_1/tspc_1/a_630_n680# divider_1/nor_0/B 0.00fF +C81 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF +C82 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF +C83 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF +C84 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF +C85 divider_2/nor_0/B divider_2/and_0/B 0.29fF +C86 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF +C87 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF +C88 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C89 pd_1/DOWN pd_1/tspc_r_0/Z3 0.03fF +C90 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C91 divider_1/tspc_0/Z4 divider_1/tspc_0/Z3 0.65fF +C92 divider_0/prescaler_0/Out divider_0/tspc_0/Z3 0.45fF +C93 pd_2/DOWN pd_2/tspc_r_0/z5 0.03fF +C94 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C95 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C96 ro_complete_1/a4 ro_complete_1/cbank_2/switch_1/vin 0.09fF +C97 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/v 1.30fF +C98 divider_2/mc2 divider_2/and_0/B 0.20fF +C99 divider_0/mc2 divider_0/nor_1/B 0.06fF +C100 pd_1/R pd_1/tspc_r_1/Z3 0.29fF +C101 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF +C102 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C103 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Q 0.05fF +C104 filter_0/a_4216_n5230# filter_0/v 0.19fF +C105 pd_2/DOWN pd_2/and_pd_0/Z1 0.07fF +C106 pd_2/tspc_r_1/Qbar1 pd_2/tspc_r_1/z5 0.20fF +C107 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z2 0.23fF +C108 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF +C109 divider_2/tspc_0/Z3 divider_2/tspc_0/a_630_n680# 0.05fF +C110 divider_2/nor_1/Z1 divider_2/and_0/A 0.80fF +C111 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF +C112 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF +C113 ro_complete_1/a3 ro_complete_1/cbank_2/switch_2/vin 0.09fF +C114 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/Out 0.04fF +C115 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF +C116 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF +C117 pd_0/DOWN pd_0/UP 0.46fF +C118 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF +C119 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z4 0.08fF +C120 pd_2/tspc_r_0/Z2 pd_2/R 0.21fF +C121 pd_1/UP pd_1/and_pd_0/Z1 0.06fF +C122 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF +C123 pd_2/and_pd_0/Out1 pd_2/and_pd_0/Z1 0.18fF +C124 divider_1/tspc_0/Z1 divider_1/tspc_0/Z3 0.06fF +C125 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF +C126 divider_2/nor_1/B divider_2/tspc_1/a_630_n680# 0.35fF +C127 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a3 0.13fF +C128 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF +C129 divbuf_3/OUT3 divbuf_3/OUT 0.26fF +C130 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/v 1.30fF +C131 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF +C132 divider_2/nor_0/B divider_2/tspc_2/Z4 0.22fF +C133 divbuf_7/OUT4 divbuf_7/OUT 1.11fF +C134 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF +C135 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z3 0.09fF +C136 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.44fF +C137 pd_2/R pd_2/REF 0.61fF +C138 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF +C139 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C140 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF +C141 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF +C142 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF +C143 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF +C144 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF +C145 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C146 divider_1/nor_1/B divider_1/nor_0/B 0.47fF +C147 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/Out 0.19fF +C148 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF +C149 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF +C150 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/v 1.30fF +C151 divbuf_4/OUT5 divbuf_4/OUT 43.38fF +C152 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C153 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C154 pd_1/DOWN pd_1/UP 0.46fF +C155 pd_1/tspc_r_0/Z3 pd_1/R 0.27fF +C156 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF +C157 pll_full_0/pd_0/R pll_full_0/pd_0/DOWN 0.36fF +C158 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF +C159 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF +C160 pd_2/REF pd_2/tspc_r_1/Qbar1 0.12fF +C161 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF +C162 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF +C163 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF +C164 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF +C165 divider_1/nor_0/B divider_1/tspc_2/Z3 0.38fF +C166 divider_2/tspc_1/Q divider_2/tspc_2/Z2 0.14fF +C167 divider_2/tspc_0/a_630_n680# divider_2/prescaler_0/Out 0.01fF +C168 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF +C169 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF +C170 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_4/vin 0.20fF +C171 divbuf_5/OUT5 divbuf_5/OUT 43.38fF +C172 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF +C173 pd_1/DIV pd_1/tspc_r_0/Z1 0.17fF +C174 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF +C175 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF +C176 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF +C177 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF +C178 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C179 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF +C180 divider_1/tspc_0/Z4 divider_1/tspc_0/Z2 0.36fF +C181 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z1 0.00fF +C182 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF +C183 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF +C184 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF +C185 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF +C186 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/clk 0.05fF +C187 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF +C188 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF +C189 divider_2/and_0/OUT divider_2/clk 0.04fF +C190 ro_complete_1/a5 ro_complete_1/cbank_2/v 0.08fF +C191 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF +C192 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF +C193 pd_1/DIV pd_1/R 0.51fF +C194 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF +C195 pd_2/tspc_r_0/Z2 pd_2/tspc_r_0/Z3 0.25fF +C196 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/A 0.15fF +C197 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C198 pll_full_0/pd_0/UP pll_full_0/pd_0/DOWN 4.58fF +C199 divider_1/mc2 divider_1/nor_1/B 0.06fF +C200 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF +C201 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF +C202 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DIV 0.12fF +C203 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF +C204 divider_2/tspc_1/Z3 divider_2/tspc_1/Q 0.05fF +C205 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF +C206 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF +C207 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF +C208 divider_0/mc2 divider_0/and_0/A 0.16fF +C209 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C210 pd_2/tspc_r_0/Z4 pd_2/tspc_r_0/z5 0.04fF +C211 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C212 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C213 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF +C214 divider_1/tspc_0/Z2 divider_1/tspc_0/Z1 1.07fF +C215 divider_0/and_0/out1 divider_0/and_0/B 0.18fF +C216 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF +C217 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF +C218 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C219 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF +C220 divider_1/nor_1/A divider_1/and_0/A 0.01fF +C221 ro_complete_1/a2 ro_complete_1/cbank_2/v 0.05fF +C222 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF +C223 divider_1/tspc_1/Z4 divider_1/nor_1/A 0.02fF +C224 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF +C225 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF +C226 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF +C227 pd_1/R pd_1/UP 0.45fF +C228 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF +C229 divider_1/tspc_0/Z4 divider_1/prescaler_0/Out 0.12fF +C230 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF +C231 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF +C232 io_clamp_low[0] io_clamp_high[0] 0.53fF +C233 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF +C234 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF +C235 divider_2/mc2 divider_2/prescaler_0/tspc_0/a_630_n680# 0.33fF +C236 divider_1/nor_0/B divider_1/and_0/B 0.29fF +C237 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF +C238 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/a0 0.09fF +C239 divbuf_6/IN divbuf_6/OUT5 0.00fF +C240 pd_0/R pd_0/REF 0.61fF +C241 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z4 0.12fF +C242 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF +C243 divider_2/nor_1/A divider_2/mc2 0.04fF +C244 divider_0/nor_1/A divider_0/tspc_0/Z3 0.38fF +C245 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF +C246 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C247 divbuf_2/IN divbuf_2/a_492_n240# 0.13fF +C248 divider_2/mc2 divider_2/and_0/OUT 0.05fF +C249 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z2 0.01fF +C250 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.15fF +C251 divbuf_3/OUT5 divbuf_3/OUT 43.38fF +C252 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF +C253 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF +C254 divider_2/tspc_2/Z3 divider_2/Out 0.05fF +C255 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF +C256 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C257 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C258 divider_0/nor_1/B divider_0/nor_1/A 1.21fF +C259 divider_2/tspc_0/Z4 divider_2/tspc_0/Z1 0.00fF +C260 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/a_630_n680# 0.01fF +C261 pd_2/R pd_2/tspc_r_1/Qbar1 0.30fF +C262 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF +C263 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF +C264 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C265 divider_1/nor_1/B divider_1/tspc_2/Z2 0.20fF +C266 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF +C267 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF +C268 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/v 1.30fF +C269 divider_2/tspc_0/Z3 divider_2/prescaler_0/Out 0.45fF +C270 divider_2/and_0/A divider_2/and_0/B 0.18fF +C271 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C272 divider_1/and_0/OUT divider_1/prescaler_0/tspc_0/D 0.03fF +C273 divider_0/mc2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF +C274 pd_1/tspc_r_1/Z1 pd_1/REF 0.17fF +C275 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Z4 0.20fF +C276 divider_1/tspc_1/Z4 divider_1/tspc_1/a_630_n680# 0.12fF +C277 divider_0/tspc_0/Z4 divider_0/tspc_0/Z3 0.65fF +C278 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C279 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C280 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF +C281 divider_2/nor_1/A divider_2/prescaler_0/tspc_1/Q 0.03fF +C282 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.05fF +C283 divider_1/tspc_0/Z2 divider_1/tspc_0/Z3 0.16fF +C284 divider_1/mc2 divider_1/and_0/B 0.20fF +C285 pd_2/tspc_r_1/Z3 pd_2/UP 0.03fF +C286 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.01fF +C287 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.19fF +C288 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.14fF +C289 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF +C290 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF +C291 divider_1/nor_0/B divider_1/tspc_2/Z4 0.22fF +C292 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF +C293 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF +C294 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z1 0.71fF +C295 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_0/z1 0.24fF +C296 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/Out 0.19fF +C297 io_clamp_high[2] io_analog[6] 0.53fF +C298 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF +C299 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C300 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C301 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF +C302 pd_1/UP pd_1/tspc_r_1/z5 0.03fF +C303 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z3 0.05fF +C304 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF +C305 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF +C306 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z3 0.38fF +C307 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C308 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C309 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/Z2 0.14fF +C310 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF +C311 divbuf_0/OUT4 divbuf_0/OUT 1.11fF +C312 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF +C313 pll_full_0/divider_0/nor_0/B pll_full_0/divbuf_0/IN 0.29fF +C314 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.29fF +C315 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF +C316 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF +C317 ro_complete_1/a0 ro_complete_1/cbank_2/switch_4/vin 0.13fF +C318 ro_complete_1/cbank_0/v ro_complete_1/cbank_1/v 1.27fF +C319 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF +C320 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.26fF +C321 pd_1/DIV pd_1/tspc_r_0/Z4 0.02fF +C322 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF +C323 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF +C324 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF +C325 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF +C326 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF +C327 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF +C328 pd_2/tspc_r_0/Qbar pd_2/tspc_r_0/Qbar1 0.01fF +C329 pd_2/R pd_2/tspc_r_0/Z3 0.27fF +C330 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DOWN 0.03fF +C331 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF +C332 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF +C333 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF +C334 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF +C335 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF +C336 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C337 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C338 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C339 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.01fF +C340 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF +C341 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Q 0.04fF +C342 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF +C343 divider_2/tspc_0/Z4 divider_2/nor_1/A 0.21fF +C344 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF +C345 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C346 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/tspc_0/Z3 0.05fF +C347 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF +C348 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C349 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C350 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF +C351 divider_1/tspc_0/Z3 divider_1/prescaler_0/Out 0.45fF +C352 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.64fF +C353 divider_1/nor_1/B divider_1/and_0/A 0.26fF +C354 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF +C355 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/cbank_0/v 1.30fF +C356 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF +C357 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF +C358 divider_1/tspc_1/Z4 divider_1/nor_1/B 0.21fF +C359 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z3 0.05fF +C360 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF +C361 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF +C362 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF +C363 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF +C364 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF +C365 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF +C366 divider_2/tspc_0/Z3 divider_2/tspc_0/Z2 0.16fF +C367 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF +C368 divbuf_6/OUT2 divbuf_6/OUT 0.06fF +C369 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF +C370 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF +C371 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z2 0.71fF +C372 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF +C373 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF +C374 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF +C375 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C376 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C377 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF +C378 divider_0/nor_1/A divider_0/and_0/A 0.01fF +C379 divider_1/nor_1/B divider_1/tspc_1/Z1 0.03fF +C380 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF +C381 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF +C382 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF +C383 divider_2/nor_1/B divider_2/tspc_0/Q 0.22fF +C384 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF +C385 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT2 1.37fF +C386 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF +C387 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF +C388 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF +C389 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF +C390 pd_1/tspc_r_0/Z2 pd_1/R 0.21fF +C391 pd_2/DIV pd_2/tspc_r_0/Qbar1 0.12fF +C392 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C393 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C394 divider_1/tspc_0/Z4 divider_1/nor_1/A 0.21fF +C395 divider_0/nor_0/B divider_0/and_0/B 0.29fF +C396 divbuf_1/OUT2 divbuf_1/OUT 0.06fF +C397 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF +C398 divider_2/mc2 divider_2/and_0/out1 0.06fF +C399 divider_2/tspc_1/a_630_n680# divider_2/tspc_0/Q 0.01fF +C400 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF +C401 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Q 0.04fF +C402 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C403 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C404 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z3 0.25fF +C405 pd_1/tspc_r_0/Qbar1 pd_1/tspc_r_0/z5 0.20fF +C406 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C407 pd_2/tspc_r_1/Z3 pd_2/tspc_r_1/Z1 0.09fF +C408 pd_2/REF pd_2/tspc_r_1/Z2 0.19fF +C409 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF +C410 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.32fF +C411 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C412 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF +C413 divider_1/tspc_0/Q divider_1/tspc_1/Z3 0.45fF +C414 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF +C415 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF +C416 divider_1/tspc_2/Z3 divider_1/Out 0.05fF +C417 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF +C418 divider_2/tspc_0/Z2 divider_2/prescaler_0/Out 0.11fF +C419 divider_2/and_0/OUT divider_2/prescaler_0/tspc_0/Q 0.04fF +C420 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF +C421 io_clamp_low[1] io_analog[5] 0.53fF +C422 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF +C423 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF +C424 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF +C425 divider_1/nor_0/Z1 divider_1/nor_1/B 0.18fF +C426 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF +C427 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF +C428 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C429 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C430 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF +C431 divbuf_0/OUT5 divbuf_0/OUT 43.38fF +C432 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF +C433 divider_2/nor_1/Z1 divider_2/nor_1/B 0.06fF +C434 divider_2/nor_1/A divider_2/and_0/A 0.01fF +C435 divider_1/tspc_0/Z2 divider_1/prescaler_0/Out 0.11fF +C436 divider_1/tspc_0/Z1 divider_1/nor_1/A 0.03fF +C437 divider_1/prescaler_0/tspc_1/Z4 divider_1/prescaler_0/tspc_2/a_740_n680# 0.01fF +C438 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF +C439 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF +C440 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF +C441 divider_2/nor_1/B divider_2/tspc_1/Z2 0.30fF +C442 divider_2/tspc_0/Z3 divider_2/tspc_0/Q 0.05fF +C443 divider_1/and_0/A divider_1/and_0/B 0.18fF +C444 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF +C445 divider_2/tspc_2/a_630_n680# divider_2/nor_0/B 0.35fF +C446 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF +C447 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C448 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF +C449 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z2 0.01fF +C450 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF +C451 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF +C452 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF +C453 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF +C454 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF +C455 pd_2/R pd_2/DOWN 0.36fF +C456 pd_2/tspc_r_0/Z2 pd_2/tspc_r_0/Z4 0.14fF +C457 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF +C458 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/A 0.35fF +C459 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C460 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C461 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C462 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF +C463 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF +C464 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF +C465 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF +C466 divider_2/tspc_1/Z2 divider_2/tspc_1/a_630_n680# 0.01fF +C467 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF +C468 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF +C469 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF +C470 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF +C471 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF +C472 pd_1/DOWN pd_1/tspc_r_0/z5 0.03fF +C473 pd_2/R pd_2/and_pd_0/Out1 0.33fF +C474 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF +C475 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C476 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/Out 0.08fF +C477 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF +C478 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF +C479 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/DIV 0.19fF +C480 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF +C481 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/switch_5/vin 0.20fF +C482 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF +C483 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C484 cp_0/a_1710_0# cp_0/out 0.84fF +C485 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF +C486 divider_0/nor_1/B divider_0/and_0/B 0.31fF +C487 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF +C488 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF +C489 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF +C490 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF +C491 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C492 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C493 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/v 1.30fF +C494 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.64fF +C495 divbuf_6/OUT4 divbuf_6/OUT 1.11fF +C496 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C497 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF +C498 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/Z1 1.07fF +C499 divider_1/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.01fF +C500 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.01fF +C501 divider_0/and_0/OUT divider_0/clk 0.04fF +C502 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF +C503 divider_1/nor_1/A divider_1/tspc_0/Z3 0.38fF +C504 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF +C505 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF +C506 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a2 0.09fF +C507 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a4 0.12fF +C508 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF +C509 divider_2/nor_1/B divider_2/tspc_1/Z4 0.21fF +C510 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF +C511 ro_complete_1/a0 ro_complete_1/cbank_2/switch_5/vin 0.09fF +C512 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C513 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z4 0.14fF +C514 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF +C515 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF +C516 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF +C517 pd_2/R pd_2/tspc_r_1/Z2 0.21fF +C518 pd_2/tspc_r_0/Z3 pd_2/DOWN 0.03fF +C519 divider_1/nor_0/Z1 divider_1/and_0/B 0.78fF +C520 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF +C521 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF +C522 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF +C523 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF +C524 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF +C525 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF +C526 divider_2/and_0/B divider_2/and_0/Z1 0.07fF +C527 pd_1/tspc_r_1/Qbar pd_1/tspc_r_1/Qbar1 0.01fF +C528 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF +C529 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C530 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF +C531 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF +C532 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF +C533 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF +C534 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C535 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.04fF +C536 divbuf_0/OUT5 divbuf_0/IN 0.00fF +C537 ro_complete_1/a4 ro_complete_1/cbank_1/v 0.05fF +C538 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C539 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF +C540 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF +C541 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF +C542 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF +C543 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF +C544 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C545 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.61fF +C546 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF +C547 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF +C548 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Q 0.20fF +C549 divider_1/tspc_1/Z2 divider_1/nor_1/A 0.15fF +C550 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF +C551 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF +C552 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF +C553 divider_2/nor_1/B divider_2/tspc_1/Q 0.51fF +C554 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF +C555 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF +C556 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF +C557 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF +C558 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF +C559 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF +C560 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF +C561 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF +C562 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C563 pd_0/R pd_0/and_pd_0/Out1 0.33fF +C564 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF +C565 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF +C566 divider_0/nor_1/B divider_0/tspc_0/a_630_n680# 0.01fF +C567 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF +C568 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/Out 0.12fF +C569 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C570 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C571 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF +C572 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF +C573 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF +C574 divider_0/tspc_2/Z3 divider_0/Out 0.05fF +C575 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Z3 0.03fF +C576 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF +C577 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.03fF +C578 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF +C579 divider_2/tspc_1/Q divider_2/tspc_1/a_630_n680# 0.04fF +C580 divider_2/mc2 divider_2/nor_0/B 0.15fF +C581 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF +C582 divbuf_4/IN divbuf_4/OUT5 0.00fF +C583 ro_complete_1/cbank_1/v ro_complete_1/cbank_2/v 1.36fF +C584 divider_2/and_0/out1 divider_2/and_0/A 0.01fF +C585 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_1/A 0.01fF +C586 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C587 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF +C588 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF +C589 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF +C590 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF +C591 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/Out 0.11fF +C592 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF +C593 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF +C594 divider_1/mc2 divider_1/and_0/out1 0.06fF +C595 divider_1/tspc_0/Z2 divider_1/nor_1/A 0.23fF +C596 divider_0/and_0/A divider_0/and_0/B 0.18fF +C597 divider_1/tspc_2/a_630_n680# divider_1/nor_0/B 0.35fF +C598 divider_2/nor_1/B divider_2/and_0/B 0.31fF +C599 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF +C600 ro_complete_1/a5 ro_complete_1/cbank_1/switch_0/vin 0.09fF +C601 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/v 1.30fF +C602 divbuf_5/IN divbuf_5/OUT5 0.00fF +C603 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF +C604 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF +C605 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF +C606 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF +C607 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF +C608 cp_0/a_1710_0# cp_0/down 0.32fF +C609 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF +C610 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Z1 0.02fF +C611 pd_1/REF pd_1/tspc_r_1/Qbar1 0.12fF +C612 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF +C613 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C614 pd_2/tspc_r_1/Z4 pd_2/tspc_r_1/z5 0.04fF +C615 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF +C616 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z2 0.01fF +C617 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF +C618 divider_1/nor_1/Z1 divider_1/nor_1/B 0.06fF +C619 ro_complete_1/a2 ro_complete_1/cbank_0/switch_3/vin 0.09fF +C620 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF +C621 ro_complete_1/cbank_1/switch_2/vin ro_complete_1/cbank_1/v 1.30fF +C622 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF +C623 pd_0/R pd_0/tspc_r_1/Z2 0.21fF +C624 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF +C625 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF +C626 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a2 0.09fF +C627 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C628 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF +C629 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF +C630 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF +C631 divbuf_2/OUT5 divbuf_2/a_492_n240# 0.01fF +C632 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/v 1.30fF +C633 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF +C634 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF +C635 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C636 ro_complete_1/a0 ro_complete_1/cbank_2/v 0.05fF +C637 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF +C638 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF +C639 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF +C640 pd_1/DOWN pd_1/tspc_r_1/Qbar 0.02fF +C641 pd_0/UP pd_0/and_pd_0/Z1 0.06fF +C642 pd_2/tspc_r_0/Z3 pd_2/tspc_r_0/Z4 0.20fF +C643 pd_2/DIV pd_2/tspc_r_0/z5 0.04fF +C644 divider_1/nor_1/A divider_1/prescaler_0/Out 0.15fF +C645 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.14fF +C646 divbuf_2/OUT3 divbuf_2/OUT 0.26fF +C647 divider_2/nor_1/B divider_2/tspc_2/Z4 0.02fF +C648 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF +C649 divider_1/tspc_0/a_630_n680# divider_1/nor_1/A 0.35fF +C650 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF +C651 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF +C652 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF +C653 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/a_630_n680# 0.19fF +C654 pd_2/DOWN pd_2/and_pd_0/Out1 0.12fF +C655 pd_2/REF pd_2/tspc_r_1/Z4 0.02fF +C656 pd_2/UP pd_2/tspc_r_1/Qbar 0.21fF +C657 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C658 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF +C659 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF +C660 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF +C661 divbuf_3/OUT2 divbuf_3/a_492_n240# 0.42fF +C662 io_clamp_high[0] io_analog[4] 0.53fF +C663 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF +C664 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C665 pd_2/tspc_r_0/Z1 pd_2/tspc_r_0/Z2 0.71fF +C666 pd_1/UP pd_1/and_pd_0/Out1 0.33fF +C667 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C668 divider_1/tspc_1/Z2 divider_1/nor_1/B 0.30fF +C669 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF +C670 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF +C671 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF +C672 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF +C673 divider_1/and_0/B divider_1/and_0/Z1 0.07fF +C674 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF +C675 ro_complete_1/a3 ro_complete_1/cbank_2/v 0.05fF +C676 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF +C677 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF +C678 divider_2/tspc_2/a_630_n680# divider_2/Out 0.04fF +C679 divider_2/nor_0/B divider_2/tspc_2/Z2 0.40fF +C680 divider_2/prescaler_0/tspc_0/Q divider_2/clk 0.05fF +C681 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C682 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF +C683 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF +C684 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF +C685 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z3 0.27fF +C686 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF +C687 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF +C688 divider_2/nor_1/A divider_2/tspc_0/a_630_n680# 0.35fF +C689 divider_1/and_0/OUT divider_1/and_0/B 0.01fF +C690 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF +C691 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF +C692 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/Z3 0.05fF +C693 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C694 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C695 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.01fF +C696 divider_1/tspc_1/Q divider_1/tspc_2/Z1 0.01fF +C697 divider_1/nor_1/Z1 divider_1/and_0/B 0.18fF +C698 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF +C699 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF +C700 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF +C701 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF +C702 divbuf_1/OUT divbuf_1/OUT3 0.26fF +C703 ro_complete_1/a4 ro_complete_1/cbank_1/switch_1/vin 0.09fF +C704 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF +C705 divider_2/tspc_1/Z2 divider_2/tspc_0/Q 0.14fF +C706 divbuf_4/OUT2 divbuf_4/OUT 0.06fF +C707 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF +C708 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF +C709 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF +C710 pd_1/tspc_r_1/Qbar pd_1/R 0.03fF +C711 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/B 0.22fF +C712 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C713 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z3 0.09fF +C714 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF +C715 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_0/D 0.16fF +C716 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/Out 0.28fF +C717 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF +C718 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF +C719 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF +C720 ro_complete_1/a3 ro_complete_1/cbank_1/switch_2/vin 0.09fF +C721 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF +C722 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.03fF +C723 divbuf_5/OUT2 divbuf_5/OUT 0.06fF +C724 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF +C725 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF +C726 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C727 pd_1/tspc_r_1/Z3 pd_1/UP 0.03fF +C728 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/A 0.21fF +C729 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Q 0.20fF +C730 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF +C731 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF +C732 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Q 0.04fF +C733 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF +C734 divbuf_0/OUT2 divbuf_0/OUT5 0.02fF +C735 pd_2/UP pd_2/and_pd_0/Z1 0.06fF +C736 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF +C737 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/Out 0.91fF +C738 divider_2/tspc_0/Z3 divider_2/tspc_0/Z1 0.06fF +C739 divider_1/and_0/out1 divider_1/and_0/A 0.01fF +C740 ro_complete_1/a2 ro_complete_1/cbank_2/switch_3/vin 0.09fF +C741 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF +C742 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/switch_5/vin 0.20fF +C743 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C744 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C745 pd_1/DIV pd_1/tspc_r_0/Z3 0.65fF +C746 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF +C747 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF +C748 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C749 divider_2/nor_1/A divider_2/nor_1/B 1.21fF +C750 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF +C751 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF +C752 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF +C753 divbuf_0/OUT4 divbuf_0/OUT3 5.16fF +C754 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z3 0.45fF +C755 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a5 0.09fF +C756 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF +C757 divider_1/tspc_1/Z4 divider_1/tspc_0/Q 0.15fF +C758 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF +C759 pd_2/tspc_r_0/Qbar1 pd_2/tspc_r_0/z5 0.20fF +C760 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF +C761 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C762 divider_1/mc2 divider_1/nor_0/B 0.15fF +C763 divider_0/prescaler_0/Out divider_0/tspc_0/Z2 0.11fF +C764 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF +C765 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF +C766 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/REF 0.12fF +C767 divider_2/mc2 divider_2/and_0/A 0.16fF +C768 divider_2/tspc_0/Q divider_2/tspc_1/Z4 0.15fF +C769 divbuf_2/OUT5 divbuf_2/OUT 43.38fF +C770 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF +C771 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF +C772 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF +C773 cp_0/a_1710_n2840# cp_0/upbar 0.29fF +C774 pd_1/R pd_1/REF 0.61fF +C775 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF +C776 divider_1/tspc_0/a_630_n680# divider_1/nor_1/B 0.01fF +C777 divider_1/tspc_1/Z4 divider_1/tspc_1/Z3 0.65fF +C778 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF +C779 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF +C780 pd_2/tspc_r_1/Z3 pd_2/tspc_r_1/z5 0.11fF +C781 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C782 divider_1/tspc_0/Q divider_1/tspc_1/Z1 0.01fF +C783 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF +C784 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/Q 0.19fF +C785 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.14fF +C786 ro_complete_1/a5 ro_complete_1/cbank_1/v 0.10fF +C787 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/cbank_0/v 1.30fF +C788 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF +C789 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF +C790 divider_0/mc2 divider_0/nor_1/A 0.04fF +C791 cp_0/upbar cp_0/down 0.02fF +C792 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.01fF +C793 divider_2/nor_1/A divider_2/tspc_0/Z3 0.38fF +C794 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z3 0.65fF +C795 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF +C796 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF +C797 divider_1/tspc_1/Z3 divider_1/tspc_1/Z1 0.06fF +C798 divider_1/tspc_1/Q divider_1/nor_1/B 0.51fF +C799 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF +C800 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF +C801 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF +C802 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF +C803 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF +C804 divider_2/nor_0/B divider_2/Out 0.22fF +C805 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.29fF +C806 divbuf_7/OUT3 divbuf_7/OUT 0.26fF +C807 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF +C808 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C809 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C810 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF +C811 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF +C812 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF +C813 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF +C814 pd_0/UP pd_0/tspc_r_1/z5 0.03fF +C815 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C816 divider_2/nor_0/Z1 divider_2/nor_1/B 0.18fF +C817 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF +C818 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF +C819 divider_1/tspc_1/Q divider_1/tspc_2/Z3 0.45fF +C820 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF +C821 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/Out 0.08fF +C822 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF +C823 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF +C824 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF +C825 ro_complete_1/a2 ro_complete_1/cbank_1/v 0.05fF +C826 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF +C827 divbuf_4/OUT4 divbuf_4/OUT 1.11fF +C828 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z3 0.65fF +C829 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z4 0.12fF +C830 divider_0/tspc_0/Z4 divider_0/prescaler_0/Out 0.12fF +C831 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF +C832 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF +C833 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF +C834 pd_2/REF pd_2/tspc_r_1/Z3 0.65fF +C835 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF +C836 divider_0/and_0/B divider_0/and_0/Z1 0.07fF +C837 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF +C838 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF +C839 divider_1/tspc_2/a_630_n680# divider_1/Out 0.04fF +C840 divider_1/nor_0/B divider_1/tspc_2/Z2 0.40fF +C841 divider_1/prescaler_0/tspc_0/Q divider_1/clk 0.05fF +C842 divider_2/tspc_1/Q divider_2/tspc_2/Z1 0.01fF +C843 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF +C844 ro_complete_1/a3 ro_complete_1/cbank_2/switch_1/vin 0.13fF +C845 divbuf_5/OUT4 divbuf_5/OUT 1.11fF +C846 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF +C847 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF +C848 divider_0/tspc_0/Z4 divider_0/tspc_0/Z1 0.00fF +C849 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF +C850 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z3 0.11fF +C851 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF +C852 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF +C853 pd_1/REF pd_1/tspc_r_1/z5 0.04fF +C854 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF +C855 divbuf_0/OUT2 divbuf_0/OUT 0.06fF +C856 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF +C857 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF +C858 divider_2/nor_1/A divider_2/prescaler_0/Out 0.15fF +C859 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF +C860 ro_complete_1/a2 ro_complete_1/cbank_0/switch_2/vin 0.14fF +C861 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a4 0.09fF +C862 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF +C863 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF +C864 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/v 1.30fF +C865 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF +C866 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/tspc_0/Z4 0.11fF +C867 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C868 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z4 0.04fF +C869 pll_full_0/pd_0/R pll_full_0/pd_0/DIV 0.51fF +C870 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF +C871 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF +C872 pd_2/tspc_r_0/Z1 pd_2/tspc_r_0/Z3 0.09fF +C873 pd_2/tspc_r_0/Z2 pd_2/DIV 0.19fF +C874 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF +C875 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF +C876 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF +C877 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF +C878 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF +C879 divider_2/tspc_0/Z2 divider_2/tspc_0/Z1 1.07fF +C880 divider_2/prescaler_0/tspc_1/Z4 divider_2/prescaler_0/tspc_2/a_740_n680# 0.01fF +C881 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF +C882 ro_complete_1/cbank_2/switch_2/vin ro_complete_1/cbank_2/v 1.30fF +C883 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF +C884 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF +C885 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C886 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF +C887 pd_1/DOWN pd_1/tspc_r_0/Qbar1 0.11fF +C888 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF +C889 divider_1/and_0/OUT divider_1/prescaler_0/tspc_0/Z2 0.05fF +C890 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF +C891 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF +C892 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF +C893 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF +C894 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/DIV 0.17fF +C895 divider_0/and_0/out1 divider_0/and_0/A 0.01fF +C896 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C897 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C898 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/Out 0.11fF +C899 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF +C900 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF +C901 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.06fF +C902 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF +C903 pd_1/R pd_1/tspc_r_1/Qbar1 0.30fF +C904 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF +C905 pd_2/UP pd_2/tspc_r_1/z5 0.03fF +C906 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z3 0.38fF +C907 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF +C908 divider_2/nor_1/Z1 divider_2/and_0/B 0.18fF +C909 divider_2/nor_1/B divider_2/tspc_1/Z1 0.03fF +C910 divbuf_3/IN divbuf_3/OUT5 0.00fF +C911 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/D 0.32fF +C912 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF +C913 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF +C914 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF +C915 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF +C916 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C917 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.20fF +C918 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_1/A 1.21fF +C919 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar1 0.11fF +C920 divider_1/nor_1/A divider_1/nor_1/B 1.21fF +C921 divbuf_0/a_492_n240# divbuf_0/IN 0.13fF +C922 divbuf_3/OUT4 divbuf_3/OUT 1.11fF +C923 ro_complete_1/a1 ro_complete_1/cbank_2/v 0.05fF +C924 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF +C925 divbuf_7/OUT5 divbuf_7/OUT 43.38fF +C926 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z3 0.25fF +C927 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF +C928 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF +C929 pd_2/R pd_2/tspc_r_1/Z3 0.29fF +C930 divider_2/nor_1/A divider_2/tspc_0/Z2 0.23fF +C931 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF +C932 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF +C933 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z3 0.16fF +C934 divider_1/tspc_1/Q divider_1/tspc_2/Z4 0.15fF +C935 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/Q 0.19fF +C936 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/Out 0.11fF +C937 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF +C938 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF +C939 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF +C940 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF +C941 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF +C942 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF +C943 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C944 pd_1/tspc_r_0/Qbar1 pd_1/R 0.01fF +C945 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF +C946 divider_0/nor_1/B divider_0/nor_0/B 0.47fF +C947 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF +C948 divider_0/tspc_0/Q divider_0/tspc_0/Z3 0.05fF +C949 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF +C950 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF +C951 pd_2/tspc_r_1/Z3 pd_2/tspc_r_1/Qbar1 0.38fF +C952 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar1 0.11fF +C953 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF +C954 divider_1/mc2 divider_1/and_0/A 0.16fF +C955 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF +C956 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF +C957 divider_1/nor_0/B divider_1/Out 0.22fF +C958 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.29fF +C959 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF +C960 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF +C961 divider_2/tspc_1/Q divider_2/tspc_2/Z3 0.45fF +C962 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF +C963 io_clamp_low[2] io_analog[6] 0.53fF +C964 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF +C965 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF +C966 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF +C967 pd_1/DIV pd_1/tspc_r_0/Z2 0.19fF +C968 pd_0/DOWN pd_0/R 0.36fF +C969 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF +C970 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF +C971 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF +C972 pd_1/R pd_1/and_pd_0/Z1 0.02fF +C973 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF +C974 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z2 0.30fF +C975 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C976 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF +C977 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z2 0.01fF +C978 pd_2/tspc_r_1/Qbar pd_2/and_pd_0/Z1 0.02fF +C979 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF +C980 divider_1/tspc_1/a_630_n680# divider_1/nor_1/B 0.35fF +C981 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_2/a_740_n680# 0.01fF +C982 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF +C983 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF +C984 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF +C985 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF +C986 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF +C987 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/v 1.45fF +C988 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF +C989 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF +C990 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF +C991 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF +C992 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF +C993 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF +C994 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF +C995 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C996 pd_2/R pd_2/DIV 0.51fF +C997 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF +C998 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF +C999 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF +C1000 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF +C1001 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF +C1002 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF +C1003 divbuf_0/OUT divbuf_0/OUT3 0.26fF +C1004 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF +C1005 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/switch_5/vin 0.20fF +C1006 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF +C1007 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/tspc_0/Z2 0.09fF +C1008 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF +C1009 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF +C1010 divider_0/mc2 divider_0/and_0/B 0.20fF +C1011 pd_1/DOWN pd_1/R 0.36fF +C1012 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C1013 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C1014 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF +C1015 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C1016 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C1017 divider_2/nor_1/A divider_2/tspc_0/Q 0.55fF +C1018 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF +C1019 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF +C1020 divider_1/nor_1/A divider_1/and_0/B 0.08fF +C1021 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/Out 0.05fF +C1022 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF +C1023 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF +C1024 divbuf_1/OUT5 divbuf_1/IN 0.00fF +C1025 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF +C1026 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF +C1027 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C1028 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF +C1029 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF +C1030 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF +C1031 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z1 0.03fF +C1032 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF +C1033 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF +C1034 pd_2/tspc_r_1/Z2 pd_2/tspc_r_1/Z4 0.14fF +C1035 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF +C1036 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF +C1037 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DIV 0.04fF +C1038 divider_1/tspc_0/Q divider_1/tspc_0/Z3 0.05fF +C1039 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF +C1040 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF +C1041 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF +C1042 divider_2/prescaler_0/tspc_0/Q divider_2/prescaler_0/tspc_2/D 0.04fF +C1043 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF +C1044 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF +C1045 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF +C1046 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF +C1047 pd_0/R pd_0/tspc_r_1/Z3 0.29fF +C1048 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1049 cp_0/a_10_n50# cp_0/vbias 0.19fF +C1050 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_1/A 0.01fF +C1051 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF +C1052 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF +C1053 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.15fF +C1054 divbuf_1/OUT2 divbuf_1/OUT5 0.02fF +C1055 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF +C1056 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF +C1057 divbuf_2/OUT2 divbuf_2/a_492_n240# 0.42fF +C1058 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF +C1059 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF +C1060 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF +C1061 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF +C1062 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF +C1063 ro_complete_1/cbank_1/switch_5/vin ro_complete_1/cbank_1/v 1.30fF +C1064 vdda1 vssa1 732.18fF +C1065 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z3 0.33fF +C1066 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF +C1067 pd_1/tspc_r_0/Qbar pd_1/tspc_r_0/Qbar1 0.01fF +C1068 divider_2/nor_1/A divider_2/tspc_1/Z2 0.15fF +C1069 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF +C1070 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_630_n680# 0.05fF +C1071 pd_2/R pd_2/UP 0.45fF +C1072 pd_2/DIV pd_2/tspc_r_0/Z3 0.65fF +C1073 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/D 0.32fF +C1074 divider_1/prescaler_0/tspc_1/Z4 divider_1/prescaler_0/Out 0.28fF +C1075 divbuf_1/OUT4 divbuf_1/OUT3 5.16fF +C1076 divider_2/nor_1/B divider_2/nor_0/B 0.47fF +C1077 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF +C1078 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF +C1079 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF +C1080 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF +C1081 divider_1/and_0/OUT divider_1/prescaler_0/m1_2700_2190# 0.14fF +C1082 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF +C1083 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF +C1084 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF +C1085 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z3 0.09fF +C1086 pd_1/tspc_r_1/Z2 pd_1/REF 0.19fF +C1087 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/z5 0.11fF +C1088 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C1089 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF +C1090 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF +C1091 divider_1/tspc_0/Q divider_1/tspc_1/Z2 0.14fF +C1092 pd_2/tspc_r_0/Z4 pd_2/tspc_r_1/Z4 0.02fF +C1093 pd_2/REF pd_2/tspc_r_1/Z1 0.17fF +C1094 pd_2/tspc_r_1/Qbar1 pd_2/UP 0.11fF +C1095 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF +C1096 divider_2/mc2 divider_2/nor_1/B 0.06fF +C1097 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF +C1098 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.00fF +C1099 divider_2/tspc_1/Q divider_2/tspc_2/Z4 0.15fF +C1100 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/Out 0.11fF +C1101 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF +C1102 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF +C1103 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF +C1104 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C1105 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF +C1106 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF +C1107 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF +C1108 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF +C1109 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF +C1110 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF +C1111 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF +C1112 cp_0/a_1710_n2840# cp_0/out 0.61fF +C1113 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF +C1114 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF +C1115 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF +C1116 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF +C1117 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF +C1118 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF +C1119 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF +C1120 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF +C1121 ro_complete_1/a0 ro_complete_1/cbank_1/switch_5/vin 0.09fF +C1122 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF +C1123 pd_1/DIV pd_1/tspc_r_0/z5 0.04fF +C1124 pd_1/tspc_r_0/Qbar pd_1/DOWN 0.21fF +C1125 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF +C1126 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF +C1127 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF +C1128 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF +C1129 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF +C1130 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF +C1131 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF +C1132 divider_2/tspc_0/Z4 divider_2/tspc_0/a_630_n680# 0.12fF +C1133 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_630_n680# 0.12fF +C1134 divider_1/and_0/OUT divider_1/clk 0.04fF +C1135 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z3 0.06fF +C1136 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF +C1137 divider_0/nor_0/B divider_0/Out 0.22fF +C1138 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF +C1139 pd_2/R pd_2/tspc_r_0/Qbar1 0.01fF +C1140 pd_2/tspc_r_0/Qbar pd_2/DOWN 0.21fF +C1141 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF +C1142 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C1143 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF +C1144 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF +C1145 ro_complete_1/a2 ro_complete_1/cbank_2/switch_2/vin 0.14fF +C1146 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/REF 0.19fF +C1147 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF +C1148 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/v 1.30fF +C1149 divider_2/prescaler_0/Out divider_2/clk 0.51fF +C1150 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C1151 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1152 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF +C1153 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF +C1154 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF +C1155 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF +C1156 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF +C1157 divider_2/nor_1/A divider_2/tspc_1/Z4 0.02fF +C1158 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF +C1159 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF +C1160 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF +C1161 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C1162 divider_1/nor_1/B divider_1/and_0/B 0.31fF +C1163 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1164 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_0/vin 0.19fF +C1165 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Z3 0.38fF +C1166 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF +C1167 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1168 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Out1 0.05fF +C1169 divider_1/tspc_1/Z4 divider_1/tspc_1/Z1 0.00fF +C1170 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF +C1171 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF +C1172 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF +C1173 divider_0/nor_1/B divider_0/and_0/A 0.26fF +C1174 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.05fF +C1175 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF +C1176 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF +C1177 divider_2/prescaler_0/tspc_0/Q divider_2/prescaler_0/nand_1/z1 0.01fF +C1178 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/Out 0.05fF +C1179 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF +C1180 divbuf_6/OUT3 divbuf_6/OUT 0.26fF +C1181 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF +C1182 pd_0/R pd_0/UP 0.45fF +C1183 divider_0/mc2 divider_0/and_0/OUT 0.05fF +C1184 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF +C1185 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C1186 divider_0/nor_1/A divider_0/and_0/B 0.08fF +C1187 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF +C1188 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.45fF +C1189 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/tspc_r_1/Qbar1 0.01fF +C1190 divider_2/tspc_1/Z1 divider_2/tspc_0/Q 0.01fF +C1191 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF +C1192 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF +C1193 ro_complete_1/cbank_0/v ro_complete_1/cbank_2/v 0.04fF +C1194 pd_0/UP pd_0/and_pd_0/Out1 0.33fF +C1195 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Q 0.04fF +C1196 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/tspc_0/Z1 0.15fF +C1197 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF +C1198 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C1199 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF +C1200 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF +C1201 pd_2/tspc_r_0/Z3 pd_2/tspc_r_0/Qbar1 0.38fF +C1202 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF +C1203 divider_1/nor_1/B divider_1/tspc_2/Z4 0.02fF +C1204 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF +C1205 divider_1/prescaler_0/tspc_0/Q divider_1/prescaler_0/tspc_2/D 0.04fF +C1206 divider_2/nor_1/B divider_2/tspc_2/Z2 0.20fF +C1207 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF +C1208 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF +C1209 divbuf_2/OUT2 divbuf_2/OUT 0.06fF +C1210 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF +C1211 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C1212 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1213 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF +C1214 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C1215 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF +C1216 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/m1_2700_2190# 0.16fF +C1217 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF +C1218 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF +C1219 pd_2/tspc_r_0/z5 pd_2/tspc_r_1/z5 0.02fF +C1220 pd_2/tspc_r_1/Z3 pd_2/tspc_r_1/Z2 0.25fF +C1221 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF +C1222 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF +C1223 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF +C1224 io_clamp_low[2] io_clamp_high[2] 0.53fF +C1225 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF +C1226 divider_2/prescaler_0/tspc_1/Z4 divider_2/prescaler_0/Out 0.28fF +C1227 ro_complete_1/a4 ro_complete_1/cbank_2/switch_0/vin 0.12fF +C1228 io_clamp_high[1] io_analog[5] 0.53fF +C1229 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_740_n680# 0.33fF +C1230 divider_1/and_0/OUT divider_1/mc2 0.05fF +C1231 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF +C1232 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF +C1233 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1234 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C1235 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C1236 divider_2/tspc_0/Z4 divider_2/tspc_0/Z3 0.65fF +C1237 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_0/z1 0.24fF +C1238 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF +C1239 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF +C1240 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF +C1241 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF +C1242 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divbuf_0/IN 0.05fF +C1243 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C1244 divider_2/nor_1/A divider_2/and_0/B 0.08fF +C1245 divider_1/tspc_1/Z3 divider_1/tspc_1/Q 0.05fF +C1246 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF +C1247 divider_2/nor_1/B divider_2/tspc_1/Z3 0.38fF +C1248 divbuf_2/IN divbuf_2/OUT5 0.00fF +C1249 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF +C1250 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF +C1251 divider_2/and_0/OUT divider_2/and_0/B 0.01fF +C1252 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/Out 0.91fF +C1253 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF +C1254 ro_complete_1/a0 ro_complete_1/cbank_1/v 0.05fF +C1255 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF +C1256 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF +C1257 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF +C1258 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF +C1259 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1260 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF +C1261 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Qbar1 0.20fF +C1262 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.26fF +C1263 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF +C1264 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF +C1265 divider_1/tspc_1/Q divider_1/tspc_2/a_630_n680# 0.01fF +C1266 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/Out 0.11fF +C1267 divider_2/tspc_1/Z3 divider_2/tspc_1/a_630_n680# 0.05fF +C1268 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF +C1269 divbuf_1/OUT divbuf_1/OUT4 1.11fF +C1270 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_4/vin 0.20fF +C1271 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF +C1272 ro_complete_1/cbank_2/switch_0/vin ro_complete_1/cbank_2/v 1.44fF +C1273 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C1274 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF +C1275 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF +C1276 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF +C1277 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF +C1278 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF +C1279 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF +C1280 pd_2/DOWN pd_2/UP 0.46fF +C1281 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C1282 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/Out 0.19fF +C1283 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF +C1284 ro_complete_1/a2 ro_complete_1/cbank_1/switch_3/vin 0.09fF +C1285 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF +C1286 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C1287 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF +C1288 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF +C1289 divider_2/nor_1/B divider_2/and_0/A 0.26fF +C1290 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF +C1291 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF +C1292 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_740_n680# 0.08fF +C1293 divider_0/tspc_0/Q divider_0/tspc_1/a_630_n680# 0.01fF +C1294 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C1295 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C1296 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF +C1297 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF +C1298 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF +C1299 pd_1/REF pd_1/tspc_r_1/Z3 0.65fF +C1300 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF +C1301 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF +C1302 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF +C1303 pd_2/UP pd_2/and_pd_0/Out1 0.33fF +C1304 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.26fF +C1305 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DIV 0.65fF +C1306 divider_2/tspc_0/Z4 divider_2/prescaler_0/Out 0.12fF +C1307 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF +C1308 divider_1/prescaler_0/Out divider_1/clk 0.51fF +C1309 divbuf_3/OUT2 divbuf_3/OUT 0.06fF +C1310 ro_complete_1/a3 ro_complete_1/cbank_1/v 0.05fF +C1311 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_1/z1 0.21fF +C1312 divbuf_6/OUT5 divbuf_6/OUT 43.38fF +C1313 divider_0/tspc_0/Z4 divider_0/tspc_0/a_630_n680# 0.12fF +C1314 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1315 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z1 0.06fF +C1316 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C1317 divbuf_0/OUT2 divbuf_0/OUT3 1.37fF +C1318 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/DIV 0.02fF +C1319 divider_2/nor_0/Z1 divider_2/and_0/B 0.78fF +C1320 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_4/vin 0.20fF +C1321 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF +C1322 divider_1/mc2 divider_1/prescaler_0/tspc_0/a_630_n680# 0.33fF +C1323 divider_0/mc2 divider_0/and_0/out1 0.06fF +C1324 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF +C1325 divider_2/nor_1/A divider_2/tspc_0/Z1 0.03fF +C1326 pd_2/R pd_2/tspc_r_1/Qbar 0.03fF +C1327 pd_2/DIV pd_2/tspc_r_0/Z4 0.02fF +C1328 pd_2/tspc_r_0/Qbar1 pd_2/DOWN 0.11fF +C1329 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.45fF +C1330 divider_1/prescaler_0/tspc_0/Q divider_1/prescaler_0/nand_1/z1 0.01fF +C1331 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/Out 0.21fF +C1332 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a1 0.14fF +C1333 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/a3 0.09fF +C1334 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF +C1335 ro_complete_1/cbank_2/switch_5/vin ro_complete_1/cbank_2/v 1.30fF +C1336 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF +C1337 pd_1/tspc_r_1/Qbar pd_1/UP 0.21fF +C1338 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF +C1339 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C1340 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.32fF +C1341 divider_1/tspc_0/Q divider_1/nor_1/A 0.55fF +C1342 pd_2/tspc_r_1/Qbar1 pd_2/tspc_r_1/Qbar 0.01fF +C1343 divbuf_3/IN divbuf_3/a_492_n240# 0.13fF +C1344 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/v 1.30fF +C1345 io_clamp_low[0] io_analog[4] 0.53fF +C1346 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF +C1347 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF +C1348 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF +C1349 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z2 0.21fF +C1350 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z1 0.00fF +C1351 divider_1/and_0/OUT divider_1/prescaler_0/tspc_0/Q 0.04fF +C1352 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF +C1353 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF +C1354 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF +C1355 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C1356 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF +C1357 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.45fF +C1358 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF +C1359 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF +C1360 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF +C1361 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF +C1362 divider_2/nor_0/B divider_2/tspc_2/Z1 0.03fF +C1363 divbuf_7/IN divbuf_7/OUT5 0.00fF +C1364 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF +C1365 pd_0/REF pd_0/tspc_r_1/z5 0.04fF +C1366 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF +C1367 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C1368 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF +C1369 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF +C1370 divider_2/tspc_0/Z4 divider_2/tspc_0/Z2 0.36fF +C1371 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF +C1372 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C1373 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF +C1374 divider_1/tspc_1/Q divider_1/nor_0/B 0.22fF +C1375 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF +C1376 divider_1/nor_1/Z1 divider_1/and_0/A 0.80fF +C1377 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF +C1378 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF +C1379 divider_2/and_0/out1 divider_2/and_0/B 0.18fF +C1380 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1381 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C1382 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1383 pd_1/tspc_r_1/Z2 pd_1/R 0.21fF +C1384 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF +C1385 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF +C1386 filter_0/a_4216_n2998# filter_0/v 0.31fF +C1387 pd_2/R pd_2/and_pd_0/Z1 0.02fF +C1388 divider_1/tspc_0/Q divider_1/tspc_1/a_630_n680# 0.01fF +C1389 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF +C1390 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF +C1391 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/Out 0.91fF +C1392 divider_2/tspc_1/Q divider_2/tspc_2/a_630_n680# 0.01fF +C1393 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/Out 0.08fF +C1394 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF +C1395 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF +C1396 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF +C1397 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF +C1398 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF +C1399 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1400 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF +C1401 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF +C1402 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/A 0.55fF +C1403 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF +C1404 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF +C1405 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF +C1406 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF +C1407 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_1/A 0.01fF +C1408 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z3 0.05fF +C1409 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF +C1410 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Q 0.05fF +C1411 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF +C1412 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF +C1413 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C1414 ro_complete_1/a4 ro_complete_1/cbank_2/v 0.05fF +C1415 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_0/vin 0.19fF +C1416 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF +C1417 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1418 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF +C1419 pd_1/and_pd_0/Out1 pd_1/and_pd_0/Z1 0.18fF +C1420 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF +C1421 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF +C1422 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z2 0.11fF +C1423 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_2/a_740_n680# 0.01fF +C1424 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF +C1425 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C1426 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF +C1427 pd_2/tspc_r_0/Z3 pd_2/tspc_r_0/z5 0.11fF +C1428 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF +C1429 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF +C1430 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Q 0.04fF +C1431 divider_0/prescaler_0/Out divider_0/clk 0.51fF +C1432 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_1/z1 0.21fF +C1433 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/Out 0.04fF +C1434 divbuf_2/OUT4 divbuf_2/OUT 1.11fF +C1435 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a1 0.14fF +C1436 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF +C1437 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/Z3 0.16fF +C1438 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C1439 divider_1/tspc_1/Z4 divider_1/tspc_1/Z2 0.36fF +C1440 divider_1/and_0/OUT divider_1/prescaler_0/tspc_1/Z2 0.06fF +C1441 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF +C1442 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF +C1443 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF +C1444 pd_2/tspc_r_1/Z3 pd_2/tspc_r_1/Z4 0.20fF +C1445 pd_2/REF pd_2/tspc_r_1/z5 0.04fF +C1446 pd_2/tspc_r_1/Z1 pd_2/tspc_r_1/Z2 0.71fF +C1447 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/Out 0.15fF +C1448 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.64fF +C1449 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF +C1450 divider_1/tspc_0/Q divider_1/nor_1/B 0.22fF +C1451 io_clamp_low[1] io_clamp_high[1] 0.53fF +C1452 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_0/vin 0.19fF +C1453 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF +C1454 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF +C1455 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/Out 0.21fF +C1456 ro_complete_1/a5 ro_complete_1/cbank_2/switch_0/vin 0.09fF +C1457 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF +C1458 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C1459 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z2 0.36fF +C1460 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF +C1461 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF +C1462 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF +C1463 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/A 0.03fF +C1464 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C1465 divider_1/tspc_1/Z2 divider_1/tspc_1/Z1 1.07fF +C1466 divider_1/tspc_1/Z3 divider_1/nor_1/B 0.38fF +C1467 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF Xpd_0 VDD gnd pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd +Xpd_1 VDD gnd pd_1/REF pd_1/DIV pd_1/UP pd_1/DOWN pd_1/R pd Xcp_0 cp_0/vbias vdd gnd cp_0/out cp_0/down cp_0/upbar cp +Xpd_2 VDD gnd pd_2/REF pd_2/DIV pd_2/UP pd_2/DOWN pd_2/R pd Xfilter_0 gnd filter_0/v filter Xro_complete_0 ro_complete_0/a0 ro_complete_0/a1 ro_complete_0/a5 ro_complete_0/a4 + ro_complete_0/a3 ro_complete_0/a2 ro_complete Xdivbuf_0 VDD divbuf_0/IN divbuf_0/OUT divbuf_0/OUT2 divbuf_0/OUT3 divbuf_0/OUT4 divbuf_0/OUT5 + gnd divbuf +Xro_complete_1 ro_complete_1/a0 ro_complete_1/a1 ro_complete_1/a5 ro_complete_1/a4 ++ ro_complete_1/a3 ro_complete_1/a2 ro_complete Xdivbuf_1 VDD divbuf_1/IN divbuf_1/OUT divbuf_1/OUT2 divbuf_1/OUT3 divbuf_1/OUT4 divbuf_1/OUT5 + gnd divbuf Xdivbuf_2 VDD divbuf_2/IN divbuf_2/OUT divbuf_2/OUT2 divbuf_2/OUT3 divbuf_2/OUT4 divbuf_2/OUT5 @@ -978,966 +1600,1148 @@ Xdivbuf_7 VDD divbuf_7/IN divbuf_7/OUT divbuf_7/OUT2 divbuf_7/OUT3 divbuf_7/OUT4 divbuf_7/OUT5 + gnd divbuf Xdivider_0 gnd vdd divider_0/Out divider_0/clk divider_0/mc2 divider +Xdivider_1 gnd vdd divider_1/Out divider_1/clk divider_1/mc2 divider +Xdivider_2 gnd vdd divider_2/Out divider_2/clk divider_2/mc2 divider Xpll_full_0 vdd pll_full -C850 io_analog[4] vdd 43.96fF -C851 io_analog[5] vdd 44.13fF -C852 io_analog[6] vdd 43.46fF -C853 io_in_3v3[0] vdd 0.61fF -C854 io_oeb[26] vdd 0.61fF -C855 io_in[0] vdd 0.61fF -C856 io_out[26] vdd 0.61fF -C857 io_out[0] vdd 0.61fF -C858 io_in[26] vdd 0.61fF -C859 io_oeb[0] vdd 0.61fF -C860 io_in_3v3[26] vdd 0.61fF -C861 io_in_3v3[1] vdd 0.61fF -C862 io_oeb[25] vdd 0.61fF -C863 io_in[1] vdd 0.61fF -C864 io_out[25] vdd 0.61fF -C865 io_out[1] vdd 0.61fF -C866 io_in[25] vdd 0.61fF -C867 io_oeb[1] vdd 0.61fF -C868 io_in_3v3[25] vdd 0.61fF -C869 io_in_3v3[2] vdd 0.61fF -C870 io_oeb[24] vdd 0.61fF -C871 io_in[2] vdd 0.61fF -C872 io_out[24] vdd 0.61fF -C873 io_out[2] vdd 0.61fF -C874 io_in[24] vdd 0.61fF -C875 io_oeb[2] vdd 0.61fF -C876 io_in_3v3[24] vdd 0.61fF -C877 io_in_3v3[3] vdd 0.61fF -C878 gpio_noesd[17] vdd 2.32fF -C879 io_in[3] vdd 0.61fF -C880 gpio_analog[17] vdd 2.30fF -C881 io_out[3] vdd 0.61fF -C882 io_oeb[3] vdd 0.61fF -C883 io_in_3v3[4] vdd 0.61fF -C884 io_in[4] vdd 0.61fF -C885 io_out[4] vdd 0.61fF -C886 io_oeb[4] vdd 0.61fF -C887 io_oeb[23] vdd 0.61fF -C888 io_out[23] vdd 0.61fF -C889 io_in[23] vdd 0.61fF -C890 io_in_3v3[23] vdd 0.61fF -C891 gpio_noesd[16] vdd 2.30fF -C892 gpio_analog[16] vdd 2.30fF -C893 io_in_3v3[5] vdd 0.61fF -C894 io_in[5] vdd 0.61fF -C895 io_out[5] vdd 0.61fF -C896 io_oeb[5] vdd 0.61fF -C897 io_oeb[22] vdd 0.61fF -C898 io_out[22] vdd 0.61fF -C899 io_in[22] vdd 0.61fF -C900 io_in_3v3[22] vdd 0.61fF -C901 gpio_noesd[15] vdd 2.31fF -C902 gpio_analog[15] vdd 2.30fF -C903 io_in_3v3[6] vdd 0.61fF -C904 io_in[6] vdd 0.61fF -C905 io_out[6] vdd 0.61fF -C906 io_oeb[6] vdd 0.61fF -C907 io_oeb[21] vdd 0.61fF -C908 io_out[21] vdd 0.61fF -C909 io_in[21] vdd 0.61fF -C910 io_in_3v3[21] vdd 0.61fF -C911 gpio_noesd[14] vdd 2.30fF -C912 gpio_analog[14] vdd 2.29fF -C913 vssa1 vdd 63.32fF -C914 vssd2 vdd 38.54fF -C915 vssd1 vdd 13.04fF -C916 vdda2 vdd 38.30fF -C917 vdda1 vdd 51.85fF -C918 io_oeb[20] vdd 0.61fF -C919 io_out[20] vdd 0.61fF -C920 io_in[20] vdd 0.61fF -C921 io_in_3v3[20] vdd 0.61fF -C922 gpio_noesd[13] vdd 2.31fF -C923 gpio_analog[13] vdd 2.30fF -C924 gpio_analog[0] vdd 0.61fF -C925 gpio_noesd[0] vdd 0.61fF -C926 io_in_3v3[7] vdd 0.61fF -C927 io_in[7] vdd 0.61fF -C928 io_out[7] vdd 0.61fF -C929 io_oeb[7] vdd 0.61fF -C930 io_oeb[19] vdd 0.61fF -C931 io_out[19] vdd 0.61fF -C932 io_in[19] vdd 0.61fF -C933 io_in_3v3[19] vdd 0.61fF -C934 gpio_noesd[12] vdd 2.32fF -C935 gpio_analog[12] vdd 2.30fF -C936 gpio_analog[1] vdd 0.61fF -C937 gpio_noesd[1] vdd 0.61fF -C938 io_in_3v3[8] vdd 0.61fF -C939 io_in[8] vdd 0.61fF -C940 io_out[8] vdd 0.61fF -C941 io_oeb[8] vdd 0.61fF -C942 io_oeb[18] vdd 0.61fF -C943 io_out[18] vdd 0.61fF -C944 io_in[18] vdd 0.61fF -C945 io_in_3v3[18] vdd 0.61fF -C946 gpio_noesd[11] vdd 2.30fF -C947 gpio_analog[11] vdd 2.29fF -C948 gpio_analog[2] vdd 0.61fF -C949 gpio_noesd[2] vdd 0.61fF -C950 io_in_3v3[9] vdd 0.61fF -C951 io_in[9] vdd 0.61fF -C952 io_out[9] vdd 0.61fF -C953 io_oeb[9] vdd 0.61fF -C954 io_oeb[17] vdd 0.61fF -C955 io_out[17] vdd 0.61fF -C956 io_in[17] vdd 0.61fF -C957 io_in_3v3[17] vdd 0.61fF -C958 gpio_noesd[10] vdd 2.31fF -C959 gpio_analog[10] vdd 2.29fF -C960 gpio_analog[3] vdd 0.61fF -C961 gpio_noesd[3] vdd 0.61fF -C962 io_in_3v3[10] vdd 0.61fF -C963 io_in[10] vdd 0.61fF -C964 io_out[10] vdd 0.61fF -C965 io_oeb[10] vdd 0.61fF -C966 io_oeb[16] vdd 0.61fF -C967 io_out[16] vdd 0.61fF -C968 io_in[16] vdd 0.61fF -C969 io_in_3v3[16] vdd 0.61fF -C970 gpio_noesd[9] vdd 2.28fF -C971 gpio_analog[9] vdd 2.28fF -C972 gpio_analog[4] vdd 0.61fF -C973 gpio_noesd[4] vdd 0.61fF -C974 io_in_3v3[11] vdd 0.61fF -C975 io_in[11] vdd 0.61fF -C976 io_out[11] vdd 0.61fF -C977 io_oeb[11] vdd 0.61fF -C978 io_oeb[15] vdd 0.61fF -C979 io_out[15] vdd 0.61fF -C980 io_in[15] vdd 0.61fF -C981 io_in_3v3[15] vdd 0.61fF -C982 gpio_noesd[8] vdd 2.28fF -C983 gpio_analog[8] vdd 2.26fF -C984 gpio_analog[5] vdd 0.61fF -C985 gpio_noesd[5] vdd 0.61fF -C986 io_in_3v3[12] vdd 0.61fF -C987 io_in[12] vdd 0.61fF -C988 io_out[12] vdd 0.61fF -C989 io_oeb[12] vdd 0.61fF -C990 io_oeb[14] vdd 0.61fF -C991 io_out[14] vdd 0.61fF -C992 io_in[14] vdd 0.61fF -C993 io_in_3v3[14] vdd 0.61fF -C994 gpio_noesd[7] vdd 2.30fF -C995 gpio_analog[7] vdd 2.28fF -C996 vssa2 vdd 38.35fF -C997 gpio_analog[6] vdd 5.71fF -C998 gpio_noesd[6] vdd 5.70fF -C999 io_in_3v3[13] vdd 0.61fF -C1000 io_in[13] vdd 0.61fF -C1001 io_out[13] vdd 0.61fF -C1002 io_oeb[13] vdd 0.61fF -C1003 vccd1 vdd 39.84fF -C1004 vccd2 vdd 38.46fF -C1005 io_analog[0] vdd 19.99fF -C1006 io_analog[10] vdd 19.36fF -C1007 io_analog[1] vdd 13.17fF -C1008 io_analog[2] vdd 12.57fF -C1009 io_analog[3] vdd 12.83fF -C1010 io_clamp_high[0] vdd 3.58fF -C1011 io_clamp_low[0] vdd 3.58fF -C1012 io_clamp_high[1] vdd 3.58fF -C1013 io_clamp_low[1] vdd 3.58fF -C1014 io_clamp_high[2] vdd 3.58fF -C1015 io_clamp_low[2] vdd 3.58fF -C1016 io_analog[7] vdd 12.74fF -C1017 io_analog[8] vdd 13.08fF -C1018 io_analog[9] vdd 13.08fF -C1019 user_irq[2] vdd 0.63fF -C1020 user_irq[1] vdd 0.63fF -C1021 user_irq[0] vdd 0.63fF -C1022 user_clock2 vdd 0.63fF -C1023 la_oenb[127] vdd 0.63fF -C1024 la_data_out[127] vdd 0.63fF -C1025 la_data_in[127] vdd 0.63fF -C1026 la_oenb[126] vdd 0.63fF -C1027 la_data_out[126] vdd 0.63fF -C1028 la_data_in[126] vdd 0.63fF -C1029 la_oenb[125] vdd 0.63fF -C1030 la_data_out[125] vdd 0.63fF -C1031 la_data_in[125] vdd 0.63fF -C1032 la_oenb[124] vdd 0.63fF -C1033 la_data_out[124] vdd 0.63fF -C1034 la_data_in[124] vdd 0.63fF -C1035 la_oenb[123] vdd 0.63fF -C1036 la_data_out[123] vdd 0.63fF -C1037 la_data_in[123] vdd 0.63fF -C1038 la_oenb[122] vdd 0.63fF -C1039 la_data_out[122] vdd 0.63fF -C1040 la_data_in[122] vdd 0.63fF -C1041 la_oenb[121] vdd 0.63fF -C1042 la_data_out[121] vdd 0.63fF -C1043 la_data_in[121] vdd 0.63fF -C1044 la_oenb[120] vdd 0.63fF -C1045 la_data_out[120] vdd 0.63fF -C1046 la_data_in[120] vdd 0.63fF -C1047 la_oenb[119] vdd 0.63fF -C1048 la_data_out[119] vdd 0.63fF -C1049 la_data_in[119] vdd 0.63fF -C1050 la_oenb[118] vdd 0.63fF -C1051 la_data_out[118] vdd 0.63fF -C1052 la_data_in[118] vdd 0.63fF -C1053 la_oenb[117] vdd 0.63fF -C1054 la_data_out[117] vdd 0.63fF -C1055 la_data_in[117] vdd 0.63fF -C1056 la_oenb[116] vdd 0.63fF -C1057 la_data_out[116] vdd 0.63fF -C1058 la_data_in[116] vdd 0.63fF -C1059 la_oenb[115] vdd 0.63fF -C1060 la_data_out[115] vdd 0.63fF -C1061 la_data_in[115] vdd 0.63fF -C1062 la_oenb[114] vdd 0.63fF -C1063 la_data_out[114] vdd 0.63fF -C1064 la_data_in[114] vdd 0.63fF -C1065 la_oenb[113] vdd 0.63fF -C1066 la_data_out[113] vdd 0.63fF -C1067 la_data_in[113] vdd 0.63fF -C1068 la_oenb[112] vdd 0.63fF -C1069 la_data_out[112] vdd 0.63fF -C1070 la_data_in[112] vdd 0.63fF -C1071 la_oenb[111] vdd 0.63fF -C1072 la_data_out[111] vdd 0.63fF -C1073 la_data_in[111] vdd 0.63fF -C1074 la_oenb[110] vdd 0.63fF -C1075 la_data_out[110] vdd 0.63fF -C1076 la_data_in[110] vdd 0.63fF -C1077 la_oenb[109] vdd 0.63fF -C1078 la_data_out[109] vdd 0.63fF -C1079 la_data_in[109] vdd 0.63fF -C1080 la_oenb[108] vdd 0.63fF -C1081 la_data_out[108] vdd 0.63fF -C1082 la_data_in[108] vdd 0.63fF -C1083 la_oenb[107] vdd 0.63fF -C1084 la_data_out[107] vdd 0.63fF -C1085 la_data_in[107] vdd 0.63fF -C1086 la_oenb[106] vdd 0.63fF -C1087 la_data_out[106] vdd 0.63fF -C1088 la_data_in[106] vdd 0.63fF -C1089 la_oenb[105] vdd 0.63fF -C1090 la_data_out[105] vdd 0.63fF -C1091 la_data_in[105] vdd 0.63fF -C1092 la_oenb[104] vdd 0.63fF -C1093 la_data_out[104] vdd 0.63fF -C1094 la_data_in[104] vdd 0.63fF -C1095 la_oenb[103] vdd 0.63fF -C1096 la_data_out[103] vdd 0.63fF -C1097 la_data_in[103] vdd 0.63fF -C1098 la_oenb[102] vdd 0.63fF -C1099 la_data_out[102] vdd 0.63fF -C1100 la_data_in[102] vdd 0.63fF -C1101 la_oenb[101] vdd 0.63fF -C1102 la_data_out[101] vdd 0.63fF -C1103 la_data_in[101] vdd 0.63fF -C1104 la_oenb[100] vdd 0.63fF -C1105 la_data_out[100] vdd 0.63fF -C1106 la_data_in[100] vdd 0.63fF -C1107 la_oenb[99] vdd 0.63fF -C1108 la_data_out[99] vdd 0.63fF -C1109 la_data_in[99] vdd 0.63fF -C1110 la_oenb[98] vdd 0.63fF -C1111 la_data_out[98] vdd 0.63fF -C1112 la_data_in[98] vdd 0.63fF -C1113 la_oenb[97] vdd 0.63fF -C1114 la_data_out[97] vdd 0.63fF -C1115 la_data_in[97] vdd 0.63fF -C1116 la_oenb[96] vdd 0.63fF -C1117 la_data_out[96] vdd 0.63fF -C1118 la_data_in[96] vdd 0.63fF -C1119 la_oenb[95] vdd 0.63fF -C1120 la_data_out[95] vdd 0.63fF -C1121 la_data_in[95] vdd 0.63fF -C1122 la_oenb[94] vdd 0.63fF -C1123 la_data_out[94] vdd 0.63fF -C1124 la_data_in[94] vdd 0.63fF -C1125 la_oenb[93] vdd 0.63fF -C1126 la_data_out[93] vdd 0.63fF -C1127 la_data_in[93] vdd 0.63fF -C1128 la_oenb[92] vdd 0.63fF -C1129 la_data_out[92] vdd 0.63fF -C1130 la_data_in[92] vdd 0.63fF -C1131 la_oenb[91] vdd 0.63fF -C1132 la_data_out[91] vdd 0.63fF -C1133 la_data_in[91] vdd 0.63fF -C1134 la_oenb[90] vdd 0.63fF -C1135 la_data_out[90] vdd 0.63fF -C1136 la_data_in[90] vdd 0.63fF -C1137 la_oenb[89] vdd 0.63fF -C1138 la_data_out[89] vdd 0.63fF -C1139 la_data_in[89] vdd 0.63fF -C1140 la_oenb[88] vdd 0.63fF -C1141 la_data_out[88] vdd 0.63fF -C1142 la_data_in[88] vdd 0.63fF -C1143 la_oenb[87] vdd 0.63fF -C1144 la_data_out[87] vdd 0.63fF -C1145 la_data_in[87] vdd 0.63fF -C1146 la_oenb[86] vdd 0.63fF -C1147 la_data_out[86] vdd 0.63fF -C1148 la_data_in[86] vdd 0.63fF -C1149 la_oenb[85] vdd 0.63fF -C1150 la_data_out[85] vdd 0.63fF -C1151 la_data_in[85] vdd 0.63fF -C1152 la_oenb[84] vdd 0.63fF -C1153 la_data_out[84] vdd 0.63fF -C1154 la_data_in[84] vdd 0.63fF -C1155 la_oenb[83] vdd 0.63fF -C1156 la_data_out[83] vdd 0.63fF -C1157 la_data_in[83] vdd 0.63fF -C1158 la_oenb[82] vdd 0.63fF -C1159 la_data_out[82] vdd 0.63fF -C1160 la_data_in[82] vdd 0.63fF -C1161 la_oenb[81] vdd 0.63fF -C1162 la_data_out[81] vdd 0.63fF -C1163 la_data_in[81] vdd 0.63fF -C1164 la_oenb[80] vdd 0.63fF -C1165 la_data_out[80] vdd 0.63fF -C1166 la_data_in[80] vdd 0.63fF -C1167 la_oenb[79] vdd 0.63fF -C1168 la_data_out[79] vdd 0.63fF -C1169 la_data_in[79] vdd 0.63fF -C1170 la_oenb[78] vdd 0.63fF -C1171 la_data_out[78] vdd 0.63fF -C1172 la_data_in[78] vdd 0.63fF -C1173 la_oenb[77] vdd 0.63fF -C1174 la_data_out[77] vdd 0.63fF -C1175 la_data_in[77] vdd 0.63fF -C1176 la_oenb[76] vdd 0.63fF -C1177 la_data_out[76] vdd 0.63fF -C1178 la_data_in[76] vdd 0.63fF -C1179 la_oenb[75] vdd 0.63fF -C1180 la_data_out[75] vdd 0.63fF -C1181 la_data_in[75] vdd 0.63fF -C1182 la_oenb[74] vdd 0.63fF -C1183 la_data_out[74] vdd 0.63fF -C1184 la_data_in[74] vdd 0.63fF -C1185 la_oenb[73] vdd 0.63fF -C1186 la_data_out[73] vdd 0.63fF -C1187 la_data_in[73] vdd 0.63fF -C1188 la_oenb[72] vdd 0.63fF -C1189 la_data_out[72] vdd 0.63fF -C1190 la_data_in[72] vdd 0.63fF -C1191 la_oenb[71] vdd 0.63fF -C1192 la_data_out[71] vdd 0.63fF -C1193 la_data_in[71] vdd 0.63fF -C1194 la_oenb[70] vdd 0.63fF -C1195 la_data_out[70] vdd 0.63fF -C1196 la_data_in[70] vdd 0.63fF -C1197 la_oenb[69] vdd 0.63fF -C1198 la_data_out[69] vdd 0.63fF -C1199 la_data_in[69] vdd 0.63fF -C1200 la_oenb[68] vdd 0.63fF -C1201 la_data_out[68] vdd 0.63fF -C1202 la_data_in[68] vdd 0.63fF -C1203 la_oenb[67] vdd 0.63fF -C1204 la_data_out[67] vdd 0.63fF -C1205 la_data_in[67] vdd 0.63fF -C1206 la_oenb[66] vdd 0.63fF -C1207 la_data_out[66] vdd 0.63fF -C1208 la_data_in[66] vdd 0.63fF -C1209 la_oenb[65] vdd 0.63fF -C1210 la_data_out[65] vdd 0.63fF -C1211 la_data_in[65] vdd 0.63fF -C1212 la_oenb[64] vdd 0.63fF -C1213 la_data_out[64] vdd 0.63fF -C1214 la_data_in[64] vdd 0.63fF -C1215 la_oenb[63] vdd 0.63fF -C1216 la_data_out[63] vdd 0.63fF -C1217 la_data_in[63] vdd 0.63fF -C1218 la_oenb[62] vdd 0.63fF -C1219 la_data_out[62] vdd 0.63fF -C1220 la_data_in[62] vdd 0.63fF -C1221 la_oenb[61] vdd 0.63fF -C1222 la_data_out[61] vdd 0.63fF -C1223 la_data_in[61] vdd 0.63fF -C1224 la_oenb[60] vdd 0.63fF -C1225 la_data_out[60] vdd 0.63fF -C1226 la_data_in[60] vdd 0.63fF -C1227 la_oenb[59] vdd 0.63fF -C1228 la_data_out[59] vdd 0.63fF -C1229 la_data_in[59] vdd 0.63fF -C1230 la_oenb[58] vdd 0.63fF -C1231 la_data_out[58] vdd 0.63fF -C1232 la_data_in[58] vdd 0.63fF -C1233 la_oenb[57] vdd 0.63fF -C1234 la_data_out[57] vdd 0.63fF -C1235 la_data_in[57] vdd 0.63fF -C1236 la_oenb[56] vdd 0.63fF -C1237 la_data_out[56] vdd 0.63fF -C1238 la_data_in[56] vdd 0.63fF -C1239 la_oenb[55] vdd 0.63fF -C1240 la_data_out[55] vdd 0.63fF -C1241 la_data_in[55] vdd 0.63fF -C1242 la_oenb[54] vdd 0.63fF -C1243 la_data_out[54] vdd 0.63fF -C1244 la_data_in[54] vdd 0.63fF -C1245 la_oenb[53] vdd 0.63fF -C1246 la_data_out[53] vdd 0.63fF -C1247 la_data_in[53] vdd 0.63fF -C1248 la_oenb[52] vdd 0.63fF -C1249 la_data_out[52] vdd 0.63fF -C1250 la_data_in[52] vdd 0.63fF -C1251 la_oenb[51] vdd 0.63fF -C1252 la_data_out[51] vdd 0.63fF -C1253 la_data_in[51] vdd 0.63fF -C1254 la_oenb[50] vdd 0.63fF -C1255 la_data_out[50] vdd 0.63fF -C1256 la_data_in[50] vdd 0.63fF -C1257 la_oenb[49] vdd 0.63fF -C1258 la_data_out[49] vdd 0.63fF -C1259 la_data_in[49] vdd 0.63fF -C1260 la_oenb[48] vdd 0.63fF -C1261 la_data_out[48] vdd 0.63fF -C1262 la_data_in[48] vdd 0.63fF -C1263 la_oenb[47] vdd 0.63fF -C1264 la_data_out[47] vdd 0.63fF -C1265 la_data_in[47] vdd 0.63fF -C1266 la_oenb[46] vdd 0.63fF -C1267 la_data_out[46] vdd 0.63fF -C1268 la_data_in[46] vdd 0.63fF -C1269 la_oenb[45] vdd 0.63fF -C1270 la_data_out[45] vdd 0.63fF -C1271 la_data_in[45] vdd 0.63fF -C1272 la_oenb[44] vdd 0.63fF -C1273 la_data_out[44] vdd 0.63fF -C1274 la_data_in[44] vdd 0.63fF -C1275 la_oenb[43] vdd 0.63fF -C1276 la_data_out[43] vdd 0.63fF -C1277 la_data_in[43] vdd 0.63fF -C1278 la_oenb[42] vdd 0.63fF -C1279 la_data_out[42] vdd 0.63fF -C1280 la_data_in[42] vdd 0.63fF -C1281 la_oenb[41] vdd 0.63fF -C1282 la_data_out[41] vdd 0.63fF -C1283 la_data_in[41] vdd 0.63fF -C1284 la_oenb[40] vdd 0.63fF -C1285 la_data_out[40] vdd 0.63fF -C1286 la_data_in[40] vdd 0.63fF -C1287 la_oenb[39] vdd 0.63fF -C1288 la_data_out[39] vdd 0.63fF -C1289 la_data_in[39] vdd 0.63fF -C1290 la_oenb[38] vdd 0.63fF -C1291 la_data_out[38] vdd 0.63fF -C1292 la_data_in[38] vdd 0.63fF -C1293 la_oenb[37] vdd 0.63fF -C1294 la_data_out[37] vdd 0.63fF -C1295 la_data_in[37] vdd 0.63fF -C1296 la_oenb[36] vdd 0.63fF -C1297 la_data_out[36] vdd 0.63fF -C1298 la_data_in[36] vdd 0.63fF -C1299 la_oenb[35] vdd 0.63fF -C1300 la_data_out[35] vdd 0.63fF -C1301 la_data_in[35] vdd 0.63fF -C1302 la_oenb[34] vdd 0.63fF -C1303 la_data_out[34] vdd 0.63fF -C1304 la_data_in[34] vdd 0.63fF -C1305 la_oenb[33] vdd 0.63fF -C1306 la_data_out[33] vdd 0.63fF -C1307 la_data_in[33] vdd 0.63fF -C1308 la_oenb[32] vdd 0.63fF -C1309 la_data_out[32] vdd 0.63fF -C1310 la_data_in[32] vdd 0.63fF -C1311 la_oenb[31] vdd 0.63fF -C1312 la_data_out[31] vdd 0.63fF -C1313 la_data_in[31] vdd 0.63fF -C1314 la_oenb[30] vdd 0.63fF -C1315 la_data_out[30] vdd 0.63fF -C1316 la_data_in[30] vdd 0.63fF -C1317 la_oenb[29] vdd 0.63fF -C1318 la_data_out[29] vdd 0.63fF -C1319 la_data_in[29] vdd 0.63fF -C1320 la_oenb[28] vdd 0.63fF -C1321 la_data_out[28] vdd 0.63fF -C1322 la_data_in[28] vdd 0.63fF -C1323 la_oenb[27] vdd 0.63fF -C1324 la_data_out[27] vdd 0.63fF -C1325 la_data_in[27] vdd 0.63fF -C1326 la_oenb[26] vdd 0.63fF -C1327 la_data_out[26] vdd 0.63fF -C1328 la_data_in[26] vdd 0.63fF -C1329 la_oenb[25] vdd 0.63fF -C1330 la_data_out[25] vdd 0.63fF -C1331 la_data_in[25] vdd 0.63fF -C1332 la_oenb[24] vdd 0.63fF -C1333 la_data_out[24] vdd 0.63fF -C1334 la_data_in[24] vdd 0.63fF -C1335 la_oenb[23] vdd 0.63fF -C1336 la_data_out[23] vdd 0.63fF -C1337 la_data_in[23] vdd 0.63fF -C1338 la_oenb[22] vdd 0.63fF -C1339 la_data_out[22] vdd 0.63fF -C1340 la_data_in[22] vdd 0.63fF -C1341 la_oenb[21] vdd 0.63fF -C1342 la_data_out[21] vdd 0.63fF -C1343 la_data_in[21] vdd 0.63fF -C1344 la_oenb[20] vdd 0.63fF -C1345 la_data_out[20] vdd 0.63fF -C1346 la_data_in[20] vdd 0.63fF -C1347 la_oenb[19] vdd 0.63fF -C1348 la_data_out[19] vdd 0.63fF -C1349 la_data_in[19] vdd 0.63fF -C1350 la_oenb[18] vdd 0.63fF -C1351 la_data_out[18] vdd 0.63fF -C1352 la_data_in[18] vdd 0.63fF -C1353 la_oenb[17] vdd 0.63fF -C1354 la_data_out[17] vdd 0.63fF -C1355 la_data_in[17] vdd 0.63fF -C1356 la_oenb[16] vdd 0.63fF -C1357 la_data_out[16] vdd 0.63fF -C1358 la_data_in[16] vdd 0.63fF -C1359 la_oenb[15] vdd 0.63fF -C1360 la_data_out[15] vdd 0.63fF -C1361 la_data_in[15] vdd 0.63fF -C1362 la_oenb[14] vdd 0.63fF -C1363 la_data_out[14] vdd 0.63fF -C1364 la_data_in[14] vdd 0.63fF -C1365 la_oenb[13] vdd 0.63fF -C1366 la_data_out[13] vdd 0.63fF -C1367 la_data_in[13] vdd 0.63fF -C1368 la_oenb[12] vdd 0.63fF -C1369 la_data_out[12] vdd 0.63fF -C1370 la_data_in[12] vdd 0.63fF -C1371 la_oenb[11] vdd 0.63fF -C1372 la_data_out[11] vdd 0.63fF -C1373 la_data_in[11] vdd 0.63fF -C1374 la_oenb[10] vdd 0.63fF -C1375 la_data_out[10] vdd 0.63fF -C1376 la_data_in[10] vdd 0.63fF -C1377 la_oenb[9] vdd 0.63fF -C1378 la_data_out[9] vdd 0.63fF -C1379 la_data_in[9] vdd 0.63fF -C1380 la_oenb[8] vdd 0.63fF -C1381 la_data_out[8] vdd 0.63fF -C1382 la_data_in[8] vdd 0.63fF -C1383 la_oenb[7] vdd 0.63fF -C1384 la_data_out[7] vdd 0.63fF -C1385 la_data_in[7] vdd 0.63fF -C1386 la_oenb[6] vdd 0.63fF -C1387 la_data_out[6] vdd 0.63fF -C1388 la_data_in[6] vdd 0.63fF -C1389 la_oenb[5] vdd 0.63fF -C1390 la_data_out[5] vdd 0.63fF -C1391 la_data_in[5] vdd 0.63fF -C1392 la_oenb[4] vdd 0.63fF -C1393 la_data_out[4] vdd 0.63fF -C1394 la_data_in[4] vdd 0.63fF -C1395 la_oenb[3] vdd 0.63fF -C1396 la_data_out[3] vdd 0.63fF -C1397 la_data_in[3] vdd 0.63fF -C1398 la_oenb[2] vdd 0.63fF -C1399 la_data_out[2] vdd 0.63fF -C1400 la_data_in[2] vdd 0.63fF -C1401 la_oenb[1] vdd 0.63fF -C1402 la_data_out[1] vdd 0.63fF -C1403 la_data_in[1] vdd 0.63fF -C1404 la_oenb[0] vdd 0.63fF -C1405 la_data_out[0] vdd 0.63fF -C1406 la_data_in[0] vdd 0.63fF -C1407 wbs_dat_o[31] vdd 0.63fF -C1408 wbs_dat_i[31] vdd 0.63fF -C1409 wbs_adr_i[31] vdd 0.63fF -C1410 wbs_dat_o[30] vdd 0.63fF -C1411 wbs_dat_i[30] vdd 0.63fF -C1412 wbs_adr_i[30] vdd 0.63fF -C1413 wbs_dat_o[29] vdd 0.63fF -C1414 wbs_dat_i[29] vdd 0.63fF -C1415 wbs_adr_i[29] vdd 0.63fF -C1416 wbs_dat_o[28] vdd 0.63fF -C1417 wbs_dat_i[28] vdd 0.63fF -C1418 wbs_adr_i[28] vdd 0.63fF -C1419 wbs_dat_o[27] vdd 0.63fF -C1420 wbs_dat_i[27] vdd 0.63fF -C1421 wbs_adr_i[27] vdd 0.63fF -C1422 wbs_dat_o[26] vdd 0.63fF -C1423 wbs_dat_i[26] vdd 0.63fF -C1424 wbs_adr_i[26] vdd 0.63fF -C1425 wbs_dat_o[25] vdd 0.63fF -C1426 wbs_dat_i[25] vdd 0.63fF -C1427 wbs_adr_i[25] vdd 0.63fF -C1428 wbs_dat_o[24] vdd 0.63fF -C1429 wbs_dat_i[24] vdd 0.63fF -C1430 wbs_adr_i[24] vdd 0.63fF -C1431 wbs_dat_o[23] vdd 0.63fF -C1432 wbs_dat_i[23] vdd 0.63fF -C1433 wbs_adr_i[23] vdd 0.63fF -C1434 wbs_dat_o[22] vdd 0.63fF -C1435 wbs_dat_i[22] vdd 0.63fF -C1436 wbs_adr_i[22] vdd 0.63fF -C1437 wbs_dat_o[21] vdd 0.63fF -C1438 wbs_dat_i[21] vdd 0.63fF -C1439 wbs_adr_i[21] vdd 0.63fF -C1440 wbs_dat_o[20] vdd 0.63fF -C1441 wbs_dat_i[20] vdd 0.63fF -C1442 wbs_adr_i[20] vdd 0.63fF -C1443 wbs_dat_o[19] vdd 0.63fF -C1444 wbs_dat_i[19] vdd 0.63fF -C1445 wbs_adr_i[19] vdd 0.63fF -C1446 wbs_dat_o[18] vdd 0.63fF -C1447 wbs_dat_i[18] vdd 0.63fF -C1448 wbs_adr_i[18] vdd 0.63fF -C1449 wbs_dat_o[17] vdd 0.63fF -C1450 wbs_dat_i[17] vdd 0.63fF -C1451 wbs_adr_i[17] vdd 0.63fF -C1452 wbs_dat_o[16] vdd 0.63fF -C1453 wbs_dat_i[16] vdd 0.63fF -C1454 wbs_adr_i[16] vdd 0.63fF -C1455 wbs_dat_o[15] vdd 0.63fF -C1456 wbs_dat_i[15] vdd 0.63fF -C1457 wbs_adr_i[15] vdd 0.63fF -C1458 wbs_dat_o[14] vdd 0.63fF -C1459 wbs_dat_i[14] vdd 0.63fF -C1460 wbs_adr_i[14] vdd 0.63fF -C1461 wbs_dat_o[13] vdd 0.63fF -C1462 wbs_dat_i[13] vdd 0.63fF -C1463 wbs_adr_i[13] vdd 0.63fF -C1464 wbs_dat_o[12] vdd 0.63fF -C1465 wbs_dat_i[12] vdd 0.63fF -C1466 wbs_adr_i[12] vdd 0.63fF -C1467 wbs_dat_o[11] vdd 0.63fF -C1468 wbs_dat_i[11] vdd 0.63fF -C1469 wbs_adr_i[11] vdd 0.63fF -C1470 wbs_dat_o[10] vdd 0.63fF -C1471 wbs_dat_i[10] vdd 0.63fF -C1472 wbs_adr_i[10] vdd 0.63fF -C1473 wbs_dat_o[9] vdd 0.63fF -C1474 wbs_dat_i[9] vdd 0.63fF -C1475 wbs_adr_i[9] vdd 0.63fF -C1476 wbs_dat_o[8] vdd 0.63fF -C1477 wbs_dat_i[8] vdd 0.63fF -C1478 wbs_adr_i[8] vdd 0.63fF -C1479 wbs_dat_o[7] vdd 0.63fF -C1480 wbs_dat_i[7] vdd 0.63fF -C1481 wbs_adr_i[7] vdd 0.63fF -C1482 wbs_dat_o[6] vdd 0.63fF -C1483 wbs_dat_i[6] vdd 0.63fF -C1484 wbs_adr_i[6] vdd 0.63fF -C1485 wbs_dat_o[5] vdd 0.63fF -C1486 wbs_dat_i[5] vdd 0.63fF -C1487 wbs_adr_i[5] vdd 0.63fF -C1488 wbs_dat_o[4] vdd 0.63fF -C1489 wbs_dat_i[4] vdd 0.63fF -C1490 wbs_adr_i[4] vdd 0.63fF -C1491 wbs_sel_i[3] vdd 0.63fF -C1492 wbs_dat_o[3] vdd 0.63fF -C1493 wbs_dat_i[3] vdd 0.63fF -C1494 wbs_adr_i[3] vdd 0.63fF -C1495 wbs_sel_i[2] vdd 0.63fF -C1496 wbs_dat_o[2] vdd 0.63fF -C1497 wbs_dat_i[2] vdd 0.63fF -C1498 wbs_adr_i[2] vdd 0.63fF -C1499 wbs_sel_i[1] vdd 0.63fF -C1500 wbs_dat_o[1] vdd 0.63fF -C1501 wbs_dat_i[1] vdd 0.63fF -C1502 wbs_adr_i[1] vdd 0.63fF -C1503 wbs_sel_i[0] vdd 0.63fF -C1504 wbs_dat_o[0] vdd 0.63fF -C1505 wbs_dat_i[0] vdd 0.63fF -C1506 wbs_adr_i[0] vdd 0.63fF -C1507 wbs_we_i vdd 0.63fF -C1508 wbs_stb_i vdd 0.63fF -C1509 wbs_cyc_i vdd 0.63fF -C1510 wbs_ack_o vdd 0.63fF -C1511 wb_rst_i vdd 0.63fF -C1512 wb_clk_i vdd 0.63fF -C1513 pll_full_0/divider_0/and_0/Z1 vdd 0.65fF -C1514 pll_full_0/divider_0/and_0/B vdd 2.45fF -C1515 pll_full_0/divider_0/and_0/A vdd 2.35fF -C1516 pll_full_0/divider_0/and_0/out1 vdd 2.99fF -C1517 pll_full_0/divider_0/tspc_2/Z4 vdd 0.86fF -C1518 pll_full_0/divbuf_0/IN vdd 9.95fF -C1519 pll_full_0/divider_0/tspc_2/Z3 vdd 2.26fF -C1520 pll_full_0/divider_0/tspc_2/Z2 vdd 1.46fF -C1521 pll_full_0/divider_0/tspc_2/Z1 vdd 0.99fF -C1522 pll_full_0/divider_0/nor_0/B vdd 6.48fF -C1523 pll_full_0/divider_0/tspc_2/a_630_n680# vdd 1.14fF **FLOATING -C1524 pll_full_0/divider_0/tspc_1/Z4 vdd 0.86fF -C1525 pll_full_0/divider_0/tspc_1/Q vdd 3.12fF -C1526 pll_full_0/divider_0/tspc_1/Z3 vdd 2.26fF -C1527 pll_full_0/divider_0/tspc_1/Z2 vdd 1.46fF -C1528 pll_full_0/divider_0/tspc_1/Z1 vdd 0.99fF -C1529 pll_full_0/divider_0/nor_1/B vdd 7.12fF -C1530 pll_full_0/divider_0/tspc_1/a_630_n680# vdd 1.15fF **FLOATING -C1531 pll_full_0/divider_0/tspc_0/Z4 vdd 0.86fF -C1532 pll_full_0/divider_0/tspc_0/Q vdd 3.14fF -C1533 pll_full_0/divider_0/tspc_0/Z3 vdd 2.26fF -C1534 pll_full_0/divider_0/tspc_0/Z2 vdd 1.46fF -C1535 pll_full_0/divider_0/tspc_0/Z1 vdd 0.99fF -C1536 pll_full_0/divider_0/nor_1/A vdd 7.08fF -C1537 pll_full_0/divider_0/tspc_0/a_630_n680# vdd 1.15fF **FLOATING -C1538 pll_full_0/divider_0/clk vdd 31.85fF -C1539 pll_full_0/divider_0/prescaler_0/Out vdd 4.59fF -C1540 pll_full_0/divider_0/prescaler_0/nand_1/z1 vdd 0.36fF -C1541 pll_full_0/divider_0/prescaler_0/tspc_2/D vdd 2.64fF -C1542 pll_full_0/divider_0/prescaler_0/tspc_0/Q vdd 3.64fF -C1543 pll_full_0/divider_0/prescaler_0/tspc_1/Q vdd 3.61fF -C1544 pll_full_0/divider_0/prescaler_0/nand_0/z1 vdd 0.36fF -C1545 pll_full_0/divider_0/prescaler_0/tspc_0/D vdd 3.12fF -C1546 pll_full_0/divider_0/and_0/OUT vdd 5.67fF -C1547 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 vdd 0.86fF -C1548 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 vdd 2.26fF -C1549 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 vdd 1.46fF -C1550 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF -C1551 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING -C1552 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING -C1553 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 vdd 0.86fF -C1554 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 vdd 2.26fF -C1555 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 vdd 1.48fF -C1556 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF -C1557 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING -C1558 pll_full_0/divider_0/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING -C1559 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 vdd 0.86fF -C1560 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 vdd 2.26fF -C1561 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 vdd 1.19fF -C1562 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF -C1563 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# vdd 1.47fF **FLOATING -C1564 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING -C1565 pll_full_0/divider_0/nor_1/Z1 vdd 1.34fF -C1566 pll_full_0/divider_0/nor_0/Z1 vdd 1.34fF -C1567 pll_full_0/divbuf_1/OUT vdd 363.82fF -C1568 pll_full_0/divbuf_1/OUT5 vdd 350.37fF -C1569 pll_full_0/divbuf_1/OUT4 vdd 133.72fF -C1570 pll_full_0/divbuf_1/OUT3 vdd 34.03fF -C1571 pll_full_0/divbuf_1/OUT2 vdd 8.71fF -C1572 pll_full_0/divbuf_1/a_492_n240# vdd 2.46fF **FLOATING -C1573 pll_full_0/divbuf_0/OUT5 vdd 350.37fF -C1574 pll_full_0/divbuf_0/OUT4 vdd 133.72fF -C1575 pll_full_0/divbuf_0/OUT3 vdd 34.03fF -C1576 pll_full_0/divbuf_0/OUT2 vdd 8.71fF -C1577 pll_full_0/divbuf_0/a_492_n240# vdd 2.46fF **FLOATING -C1578 pll_full_0/ro_complete_0/cbank_2/v vdd 17.88fF -C1579 pll_full_0/ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF -C1580 pll_full_0/ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF -C1581 pll_full_0/ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF -C1582 pll_full_0/ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF -C1583 pll_full_0/ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF -C1584 pll_full_0/ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF -C1585 pll_full_0/ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF -C1586 pll_full_0/ro_complete_0/a0 vdd 7.88fF -C1587 pll_full_0/ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF -C1588 pll_full_0/ro_complete_0/a1 vdd 5.39fF -C1589 pll_full_0/ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF -C1590 pll_full_0/ro_complete_0/a3 vdd 6.85fF -C1591 pll_full_0/ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF -C1592 pll_full_0/ro_complete_0/a2 vdd 5.48fF -C1593 pll_full_0/ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF -C1594 pll_full_0/ro_complete_0/a4 vdd 5.36fF -C1595 pll_full_0/ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF -C1596 pll_full_0/ro_complete_0/a5 vdd 5.19fF -C1597 pll_full_0/ro_complete_0/cbank_0/v vdd 15.02fF -C1598 pll_full_0/ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF -C1599 pll_full_0/ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF -C1600 pll_full_0/ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF -C1601 pll_full_0/ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF -C1602 pll_full_0/ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF -C1603 pll_full_0/ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF -C1604 pll_full_0/ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF -C1605 pll_full_0/filter_0/a_4216_n5230# vdd 419.25fF **FLOATING -C1606 pll_full_0/filter_0/a_4216_n2998# vdd 1.39fF **FLOATING -C1607 pll_full_0/cp_0/down vdd 1.54fF -C1608 pll_full_0/cp_0/upbar vdd 1.79fF -C1609 pll_full_0/cp_0/a_7110_n2840# vdd 0.17fF **FLOATING -C1610 pll_full_0/cp_0/a_3060_n2840# vdd 1.71fF **FLOATING -C1611 pll_full_0/cp_0/a_7110_0# vdd 0.17fF **FLOATING -C1612 pll_full_0/cp_0/a_6370_0# vdd 0.40fF **FLOATING -C1613 pll_full_0/cp_0/a_3060_0# vdd 2.49fF **FLOATING -C1614 pll_full_0/cp_0/a_1710_0# vdd 7.47fF **FLOATING -C1615 pll_full_0/pd_0/and_pd_0/Z1 vdd 0.39fF -C1616 pll_full_0/pd_0/and_pd_0/Out1 vdd 2.22fF -C1617 pll_full_0/pd_0/tspc_r_1/z5 vdd 1.10fF -C1618 pll_full_0/pd_0/tspc_r_1/Z4 vdd 1.07fF -C1619 pll_full_0/pd_0/tspc_r_1/Qbar vdd 0.88fF -C1620 pll_full_0/pd_0/tspc_r_1/Z2 vdd 1.22fF -C1621 pll_full_0/pd_0/tspc_r_1/Z1 vdd 0.67fF -C1622 pll_full_0/pd_0/UP vdd 6.61fF -C1623 pll_full_0/pd_0/tspc_r_1/Qbar1 vdd 1.34fF -C1624 pll_full_0/pd_0/tspc_r_1/Z3 vdd 2.12fF -C1625 pll_full_0/pd_0/REF vdd 6.44fF -C1626 pll_full_0/pd_0/tspc_r_0/z5 vdd 1.10fF -C1627 pll_full_0/pd_0/tspc_r_0/Z4 vdd 1.07fF -C1628 pll_full_0/pd_0/R vdd 3.05fF -C1629 pll_full_0/pd_0/tspc_r_0/Qbar vdd 0.79fF -C1630 pll_full_0/pd_0/tspc_r_0/Z2 vdd 1.22fF -C1631 pll_full_0/pd_0/tspc_r_0/Z1 vdd 0.67fF -C1632 pll_full_0/pd_0/DOWN vdd 7.24fF -C1633 pll_full_0/pd_0/tspc_r_0/Qbar1 vdd 1.34fF -C1634 pll_full_0/pd_0/tspc_r_0/Z3 vdd 2.12fF -C1635 pll_full_0/pd_0/DIV vdd 371.87fF -C1636 divider_0/and_0/Z1 vdd 0.74fF -C1637 divider_0/and_0/B vdd 2.25fF -C1638 divider_0/and_0/A vdd 2.19fF -C1639 divider_0/and_0/out1 vdd 2.93fF -C1640 divider_0/tspc_2/Z4 vdd 0.86fF -C1641 divider_0/Out vdd 1.60fF -C1642 divider_0/tspc_2/Z3 vdd 2.26fF -C1643 divider_0/tspc_2/Z2 vdd 1.46fF -C1644 divider_0/tspc_2/Z1 vdd 0.99fF -C1645 divider_0/nor_0/B vdd 6.33fF -C1646 divider_0/tspc_2/a_630_n680# vdd 1.14fF **FLOATING -C1647 divider_0/tspc_1/Z4 vdd 0.86fF -C1648 divider_0/tspc_1/Q vdd 3.12fF -C1649 divider_0/tspc_1/Z3 vdd 2.26fF -C1650 divider_0/tspc_1/Z2 vdd 1.46fF -C1651 divider_0/tspc_1/Z1 vdd 0.99fF -C1652 divider_0/nor_1/B vdd 7.05fF -C1653 divider_0/tspc_1/a_630_n680# vdd 1.15fF **FLOATING -C1654 divider_0/tspc_0/Z4 vdd 0.86fF -C1655 divider_0/tspc_0/Q vdd 3.14fF -C1656 divider_0/tspc_0/Z3 vdd 2.26fF -C1657 divider_0/tspc_0/Z2 vdd 1.46fF -C1658 divider_0/tspc_0/Z1 vdd 0.99fF -C1659 divider_0/nor_1/A vdd 7.04fF -C1660 divider_0/tspc_0/a_630_n680# vdd 1.15fF **FLOATING -C1661 divider_0/clk vdd 5.63fF -C1662 divider_0/prescaler_0/Out vdd 4.59fF -C1663 divider_0/prescaler_0/nand_1/z1 vdd 0.36fF -C1664 divider_0/prescaler_0/tspc_2/D vdd 2.64fF -C1665 divider_0/prescaler_0/tspc_0/Q vdd 3.64fF -C1666 divider_0/prescaler_0/tspc_1/Q vdd 3.61fF -C1667 divider_0/prescaler_0/nand_0/z1 vdd 0.36fF -C1668 divider_0/prescaler_0/tspc_0/D vdd 3.12fF -C1669 divider_0/and_0/OUT vdd 5.62fF -C1670 divider_0/prescaler_0/tspc_2/Z4 vdd 0.86fF -C1671 divider_0/prescaler_0/tspc_2/Z3 vdd 2.26fF -C1672 divider_0/prescaler_0/tspc_2/Z2 vdd 1.46fF -C1673 divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF -C1674 divider_0/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING -C1675 divider_0/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING -C1676 divider_0/prescaler_0/tspc_1/Z4 vdd 0.86fF -C1677 divider_0/prescaler_0/tspc_1/Z3 vdd 2.26fF -C1678 divider_0/prescaler_0/tspc_1/Z2 vdd 1.48fF -C1679 divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF -C1680 divider_0/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING -C1681 divider_0/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING -C1682 divider_0/prescaler_0/tspc_0/Z4 vdd 0.86fF -C1683 divider_0/prescaler_0/tspc_0/Z3 vdd 2.26fF -C1684 divider_0/prescaler_0/tspc_0/Z2 vdd 1.46fF -C1685 divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF -C1686 divider_0/prescaler_0/tspc_0/a_630_n680# vdd 1.14fF **FLOATING -C1687 divider_0/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING -C1688 divider_0/nor_1/Z1 vdd 1.34fF -C1689 divider_0/nor_0/Z1 vdd 1.34fF -C1690 divider_0/mc2 vdd 5.29fF -C1691 divbuf_7/OUT vdd 363.82fF -C1692 divbuf_7/OUT5 vdd 350.37fF -C1693 divbuf_7/OUT4 vdd 133.72fF -C1694 divbuf_7/OUT3 vdd 34.03fF -C1695 divbuf_7/OUT2 vdd 8.71fF -C1696 divbuf_7/IN vdd 0.89fF -C1697 divbuf_7/a_492_n240# vdd 2.46fF **FLOATING -C1698 divbuf_6/OUT vdd 363.82fF -C1699 divbuf_6/OUT5 vdd 350.37fF -C1700 divbuf_6/OUT4 vdd 133.72fF -C1701 divbuf_6/OUT3 vdd 34.03fF -C1702 divbuf_6/OUT2 vdd 8.71fF -C1703 divbuf_6/IN vdd 0.89fF -C1704 divbuf_6/a_492_n240# vdd 2.46fF **FLOATING -C1705 divbuf_5/OUT vdd 363.82fF -C1706 divbuf_5/OUT5 vdd 350.37fF -C1707 divbuf_5/OUT4 vdd 133.72fF -C1708 divbuf_5/OUT3 vdd 34.03fF -C1709 divbuf_5/OUT2 vdd 8.71fF -C1710 divbuf_5/IN vdd 0.89fF -C1711 divbuf_5/a_492_n240# vdd 2.46fF **FLOATING -C1712 divbuf_4/OUT vdd 363.82fF -C1713 divbuf_4/OUT5 vdd 350.37fF -C1714 divbuf_4/OUT4 vdd 133.72fF -C1715 divbuf_4/OUT3 vdd 34.03fF -C1716 divbuf_4/OUT2 vdd 8.71fF -C1717 divbuf_4/IN vdd 0.89fF -C1718 divbuf_4/a_492_n240# vdd 2.46fF **FLOATING -C1719 divbuf_3/OUT vdd 363.82fF -C1720 divbuf_3/OUT5 vdd 350.37fF -C1721 divbuf_3/OUT4 vdd 133.72fF -C1722 divbuf_3/OUT3 vdd 34.03fF -C1723 divbuf_3/OUT2 vdd 8.71fF -C1724 divbuf_3/IN vdd 0.89fF -C1725 divbuf_3/a_492_n240# vdd 2.46fF **FLOATING -C1726 divbuf_2/OUT vdd 363.82fF -C1727 divbuf_2/OUT5 vdd 350.37fF -C1728 divbuf_2/OUT4 vdd 133.72fF -C1729 divbuf_2/OUT3 vdd 34.03fF -C1730 divbuf_2/OUT2 vdd 8.71fF -C1731 divbuf_2/IN vdd 0.89fF -C1732 divbuf_2/a_492_n240# vdd 2.46fF **FLOATING -C1733 divbuf_1/OUT vdd 363.82fF -C1734 divbuf_1/OUT5 vdd 350.37fF -C1735 divbuf_1/OUT4 vdd 133.72fF -C1736 divbuf_1/OUT3 vdd 34.03fF -C1737 divbuf_1/OUT2 vdd 8.71fF -C1738 divbuf_1/IN vdd 0.89fF -C1739 divbuf_1/a_492_n240# vdd 2.46fF **FLOATING -C1740 divbuf_0/OUT vdd 363.82fF -C1741 divbuf_0/OUT5 vdd 350.37fF -C1742 divbuf_0/OUT4 vdd 133.72fF -C1743 divbuf_0/OUT3 vdd 34.03fF -C1744 divbuf_0/OUT2 vdd 8.71fF -C1745 divbuf_0/IN vdd 0.89fF -C1746 divbuf_0/a_492_n240# vdd 2.46fF **FLOATING -C1747 ro_complete_0/cbank_2/v vdd 17.84fF -C1748 ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF -C1749 ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF -C1750 ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF -C1751 ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF -C1752 ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF -C1753 ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF -C1754 ro_complete_0/cbank_1/v vdd 16.34fF -C1755 ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF -C1756 ro_complete_0/a0 vdd 7.88fF -C1757 ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF -C1758 ro_complete_0/a1 vdd 5.39fF -C1759 ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF -C1760 ro_complete_0/a3 vdd 6.85fF -C1761 ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF -C1762 ro_complete_0/a2 vdd 5.48fF -C1763 ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF -C1764 ro_complete_0/a4 vdd 5.36fF -C1765 ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF -C1766 ro_complete_0/a5 vdd 5.19fF -C1767 ro_complete_0/cbank_0/v vdd 14.98fF -C1768 ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF -C1769 ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF -C1770 ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF -C1771 ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF -C1772 ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF -C1773 ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF -C1774 ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF -C1775 filter_0/v vdd 85.69fF -C1776 filter_0/a_4216_n5230# vdd 418.47fF **FLOATING -C1777 filter_0/a_4216_n2998# vdd 1.03fF **FLOATING -C1778 cp_0/down vdd 1.54fF -C1779 cp_0/vbias vdd 2.41fF -C1780 cp_0/out vdd 5.26fF -C1781 cp_0/upbar vdd 1.50fF -C1782 cp_0/a_7110_n2840# vdd 0.17fF **FLOATING -C1783 cp_0/a_3060_n2840# vdd 1.71fF **FLOATING -C1784 cp_0/a_7110_0# vdd 0.17fF **FLOATING -C1785 cp_0/a_6370_0# vdd 0.40fF **FLOATING -C1786 cp_0/a_3060_0# vdd 1.65fF **FLOATING -C1787 cp_0/a_1710_0# vdd 5.76fF **FLOATING -C1788 cp_0/a_1710_n2840# vdd 4.89fF **FLOATING -C1789 cp_0/a_10_n50# vdd 2.96fF **FLOATING -C1790 pd_0/and_pd_0/Z1 vdd 0.39fF -C1791 pd_0/and_pd_0/Out1 vdd 2.22fF -C1792 pd_0/tspc_r_1/z5 vdd 1.10fF -C1793 pd_0/tspc_r_1/Z4 vdd 1.07fF -C1794 pd_0/tspc_r_1/Qbar vdd 0.88fF -C1795 pd_0/tspc_r_1/Z2 vdd 1.22fF -C1796 pd_0/tspc_r_1/Z1 vdd 0.67fF -C1797 pd_0/UP vdd 2.21fF -C1798 pd_0/tspc_r_1/Qbar1 vdd 1.34fF -C1799 pd_0/tspc_r_1/Z3 vdd 2.12fF -C1800 pd_0/REF vdd 1.80fF -C1801 pd_0/tspc_r_0/z5 vdd 1.10fF -C1802 pd_0/tspc_r_0/Z4 vdd 1.07fF -C1803 pd_0/R vdd 3.05fF -C1804 pd_0/tspc_r_0/Qbar vdd 0.79fF -C1805 pd_0/tspc_r_0/Z2 vdd 1.22fF -C1806 pd_0/tspc_r_0/Z1 vdd 0.67fF -C1807 pd_0/DOWN vdd 3.08fF -C1808 pd_0/tspc_r_0/Qbar1 vdd 1.34fF -C1809 pd_0/tspc_r_0/Z3 vdd 2.12fF -C1810 pd_0/DIV vdd 1.82fF +C1468 io_analog[4] vdd 43.96fF +C1469 io_analog[5] vdd 44.13fF +C1470 io_analog[6] vdd 43.46fF +C1471 io_in_3v3[0] vdd 0.61fF +C1472 io_oeb[26] vdd 0.61fF +C1473 io_in[0] vdd 0.61fF +C1474 io_out[26] vdd 0.61fF +C1475 io_out[0] vdd 0.61fF +C1476 io_in[26] vdd 0.61fF +C1477 io_oeb[0] vdd 0.61fF +C1478 io_in_3v3[26] vdd 0.61fF +C1479 io_in_3v3[1] vdd 0.61fF +C1480 io_oeb[25] vdd 0.61fF +C1481 io_in[1] vdd 0.61fF +C1482 io_out[25] vdd 0.61fF +C1483 io_out[1] vdd 0.61fF +C1484 io_in[25] vdd 0.61fF +C1485 io_oeb[1] vdd 0.61fF +C1486 io_in_3v3[25] vdd 0.61fF +C1487 io_in_3v3[2] vdd 0.61fF +C1488 io_oeb[24] vdd 0.61fF +C1489 io_in[2] vdd 0.61fF +C1490 io_out[24] vdd 0.61fF +C1491 io_out[2] vdd 0.61fF +C1492 io_in[24] vdd 0.61fF +C1493 io_oeb[2] vdd 0.61fF +C1494 io_in_3v3[24] vdd 0.61fF +C1495 io_in_3v3[3] vdd 0.61fF +C1496 gpio_noesd[17] vdd 2.32fF +C1497 io_in[3] vdd 0.61fF +C1498 gpio_analog[17] vdd 2.30fF +C1499 io_out[3] vdd 0.61fF +C1500 io_oeb[3] vdd 0.61fF +C1501 io_in_3v3[4] vdd 0.61fF +C1502 io_in[4] vdd 0.61fF +C1503 io_out[4] vdd 0.61fF +C1504 io_oeb[4] vdd 0.61fF +C1505 io_oeb[23] vdd 0.61fF +C1506 io_out[23] vdd 0.61fF +C1507 io_in[23] vdd 0.61fF +C1508 io_in_3v3[23] vdd 0.61fF +C1509 gpio_noesd[16] vdd 2.30fF +C1510 gpio_analog[16] vdd 2.30fF +C1511 io_in_3v3[5] vdd 0.61fF +C1512 io_in[5] vdd 0.61fF +C1513 io_out[5] vdd 0.61fF +C1514 io_oeb[5] vdd 0.61fF +C1515 io_oeb[22] vdd 0.61fF +C1516 io_out[22] vdd 0.61fF +C1517 io_in[22] vdd 0.61fF +C1518 io_in_3v3[22] vdd 0.61fF +C1519 gpio_noesd[15] vdd 2.31fF +C1520 gpio_analog[15] vdd 2.30fF +C1521 io_in_3v3[6] vdd 0.61fF +C1522 io_in[6] vdd 0.61fF +C1523 io_out[6] vdd 0.61fF +C1524 io_oeb[6] vdd 0.61fF +C1525 io_oeb[21] vdd 0.61fF +C1526 io_out[21] vdd 0.61fF +C1527 io_in[21] vdd 0.61fF +C1528 io_in_3v3[21] vdd 0.61fF +C1529 gpio_noesd[14] vdd 2.30fF +C1530 gpio_analog[14] vdd 2.29fF +C1531 vssa1 vdd 5145.48fF +C1532 vssd2 vdd 38.54fF +C1533 vssd1 vdd 13.04fF +C1534 vdda2 vdd 38.30fF +C1535 vdda1 vdd 4325.70fF +C1536 io_oeb[20] vdd 0.61fF +C1537 io_out[20] vdd 0.61fF +C1538 io_in[20] vdd 0.61fF +C1539 io_in_3v3[20] vdd 0.61fF +C1540 gpio_noesd[13] vdd 2.31fF +C1541 gpio_analog[13] vdd 2.30fF +C1542 gpio_analog[0] vdd 0.61fF +C1543 gpio_noesd[0] vdd 0.61fF +C1544 io_in_3v3[7] vdd 0.61fF +C1545 io_in[7] vdd 0.61fF +C1546 io_out[7] vdd 0.61fF +C1547 io_oeb[7] vdd 0.61fF +C1548 io_oeb[19] vdd 0.61fF +C1549 io_out[19] vdd 0.61fF +C1550 io_in[19] vdd 0.61fF +C1551 io_in_3v3[19] vdd 0.61fF +C1552 gpio_noesd[12] vdd 2.32fF +C1553 gpio_analog[12] vdd 2.30fF +C1554 gpio_analog[1] vdd 0.61fF +C1555 gpio_noesd[1] vdd 0.61fF +C1556 io_in_3v3[8] vdd 0.61fF +C1557 io_in[8] vdd 0.61fF +C1558 io_out[8] vdd 0.61fF +C1559 io_oeb[8] vdd 0.61fF +C1560 io_oeb[18] vdd 0.61fF +C1561 io_out[18] vdd 0.61fF +C1562 io_in[18] vdd 0.61fF +C1563 io_in_3v3[18] vdd 0.61fF +C1564 gpio_noesd[11] vdd 2.30fF +C1565 gpio_analog[11] vdd 2.29fF +C1566 gpio_analog[2] vdd 0.61fF +C1567 gpio_noesd[2] vdd 0.61fF +C1568 io_in_3v3[9] vdd 0.61fF +C1569 io_in[9] vdd 0.61fF +C1570 io_out[9] vdd 0.61fF +C1571 io_oeb[9] vdd 0.61fF +C1572 io_oeb[17] vdd 0.61fF +C1573 io_out[17] vdd 0.61fF +C1574 io_in[17] vdd 0.61fF +C1575 io_in_3v3[17] vdd 0.61fF +C1576 gpio_noesd[10] vdd 2.31fF +C1577 gpio_analog[10] vdd 2.29fF +C1578 gpio_analog[3] vdd 0.61fF +C1579 gpio_noesd[3] vdd 0.61fF +C1580 io_in_3v3[10] vdd 0.61fF +C1581 io_in[10] vdd 0.61fF +C1582 io_out[10] vdd 0.61fF +C1583 io_oeb[10] vdd 0.61fF +C1584 io_oeb[16] vdd 0.61fF +C1585 io_out[16] vdd 0.61fF +C1586 io_in[16] vdd 0.61fF +C1587 io_in_3v3[16] vdd 0.61fF +C1588 gpio_noesd[9] vdd 2.28fF +C1589 gpio_analog[9] vdd 2.28fF +C1590 gpio_analog[4] vdd 0.61fF +C1591 gpio_noesd[4] vdd 0.61fF +C1592 io_in_3v3[11] vdd 0.61fF +C1593 io_in[11] vdd 0.61fF +C1594 io_out[11] vdd 0.61fF +C1595 io_oeb[11] vdd 0.61fF +C1596 io_oeb[15] vdd 0.61fF +C1597 io_out[15] vdd 0.61fF +C1598 io_in[15] vdd 0.61fF +C1599 io_in_3v3[15] vdd 0.61fF +C1600 gpio_noesd[8] vdd 2.28fF +C1601 gpio_analog[8] vdd 2.26fF +C1602 gpio_analog[5] vdd 0.61fF +C1603 gpio_noesd[5] vdd 0.61fF +C1604 io_in_3v3[12] vdd 0.61fF +C1605 io_in[12] vdd 0.61fF +C1606 io_out[12] vdd 0.61fF +C1607 io_oeb[12] vdd 0.61fF +C1608 io_oeb[14] vdd 0.61fF +C1609 io_out[14] vdd 0.61fF +C1610 io_in[14] vdd 0.61fF +C1611 io_in_3v3[14] vdd 0.61fF +C1612 gpio_noesd[7] vdd 2.30fF +C1613 gpio_analog[7] vdd 2.28fF +C1614 vssa2 vdd 38.35fF +C1615 gpio_analog[6] vdd 5.71fF +C1616 gpio_noesd[6] vdd 5.70fF +C1617 io_in_3v3[13] vdd 0.61fF +C1618 io_in[13] vdd 0.61fF +C1619 io_out[13] vdd 0.61fF +C1620 io_oeb[13] vdd 0.61fF +C1621 vccd1 vdd 39.84fF +C1622 vccd2 vdd 38.46fF +C1623 io_analog[0] vdd 19.99fF +C1624 io_analog[10] vdd 19.36fF +C1625 io_analog[1] vdd 13.17fF +C1626 io_analog[2] vdd 12.57fF +C1627 io_analog[3] vdd 12.83fF +C1628 io_clamp_high[0] vdd 3.58fF +C1629 io_clamp_low[0] vdd 3.58fF +C1630 io_clamp_high[1] vdd 3.58fF +C1631 io_clamp_low[1] vdd 3.58fF +C1632 io_clamp_high[2] vdd 3.58fF +C1633 io_clamp_low[2] vdd 3.58fF +C1634 io_analog[7] vdd 12.74fF +C1635 io_analog[8] vdd 13.08fF +C1636 io_analog[9] vdd 13.08fF +C1637 user_irq[2] vdd 0.63fF +C1638 user_irq[1] vdd 0.63fF +C1639 user_irq[0] vdd 0.63fF +C1640 user_clock2 vdd 0.63fF +C1641 la_oenb[127] vdd 0.63fF +C1642 la_data_out[127] vdd 0.63fF +C1643 la_data_in[127] vdd 0.63fF +C1644 la_oenb[126] vdd 0.63fF +C1645 la_data_out[126] vdd 0.63fF +C1646 la_data_in[126] vdd 0.63fF +C1647 la_oenb[125] vdd 0.63fF +C1648 la_data_out[125] vdd 0.63fF +C1649 la_data_in[125] vdd 0.63fF +C1650 la_oenb[124] vdd 0.63fF +C1651 la_data_out[124] vdd 0.63fF +C1652 la_data_in[124] vdd 0.63fF +C1653 la_oenb[123] vdd 0.63fF +C1654 la_data_out[123] vdd 0.63fF +C1655 la_data_in[123] vdd 0.63fF +C1656 la_oenb[122] vdd 0.63fF +C1657 la_data_out[122] vdd 0.63fF +C1658 la_data_in[122] vdd 0.63fF +C1659 la_oenb[121] vdd 0.63fF +C1660 la_data_out[121] vdd 0.63fF +C1661 la_data_in[121] vdd 0.63fF +C1662 la_oenb[120] vdd 0.63fF +C1663 la_data_out[120] vdd 0.63fF +C1664 la_data_in[120] vdd 0.63fF +C1665 la_oenb[119] vdd 0.63fF +C1666 la_data_out[119] vdd 0.63fF +C1667 la_data_in[119] vdd 0.63fF +C1668 la_oenb[118] vdd 0.63fF +C1669 la_data_out[118] vdd 0.63fF +C1670 la_data_in[118] vdd 0.63fF +C1671 la_oenb[117] vdd 0.63fF +C1672 la_data_out[117] vdd 0.63fF +C1673 la_data_in[117] vdd 0.63fF +C1674 la_oenb[116] vdd 0.63fF +C1675 la_data_out[116] vdd 0.63fF +C1676 la_data_in[116] vdd 0.63fF +C1677 la_oenb[115] vdd 0.63fF +C1678 la_data_out[115] vdd 0.63fF +C1679 la_data_in[115] vdd 0.63fF +C1680 la_oenb[114] vdd 0.63fF +C1681 la_data_out[114] vdd 0.63fF +C1682 la_data_in[114] vdd 0.63fF +C1683 la_oenb[113] vdd 0.63fF +C1684 la_data_out[113] vdd 0.63fF +C1685 la_data_in[113] vdd 0.63fF +C1686 la_oenb[112] vdd 0.63fF +C1687 la_data_out[112] vdd 0.63fF +C1688 la_data_in[112] vdd 0.63fF +C1689 la_oenb[111] vdd 0.63fF +C1690 la_data_out[111] vdd 0.63fF +C1691 la_data_in[111] vdd 0.63fF +C1692 la_oenb[110] vdd 0.63fF +C1693 la_data_out[110] vdd 0.63fF +C1694 la_data_in[110] vdd 0.63fF +C1695 la_oenb[109] vdd 0.63fF +C1696 la_data_out[109] vdd 0.63fF +C1697 la_data_in[109] vdd 0.63fF +C1698 la_oenb[108] vdd 0.63fF +C1699 la_data_out[108] vdd 0.63fF +C1700 la_data_in[108] vdd 0.63fF +C1701 la_oenb[107] vdd 0.63fF +C1702 la_data_out[107] vdd 0.63fF +C1703 la_data_in[107] vdd 0.63fF +C1704 la_oenb[106] vdd 0.63fF +C1705 la_data_out[106] vdd 0.63fF +C1706 la_data_in[106] vdd 0.63fF +C1707 la_oenb[105] vdd 0.63fF +C1708 la_data_out[105] vdd 0.63fF +C1709 la_data_in[105] vdd 0.63fF +C1710 la_oenb[104] vdd 0.63fF +C1711 la_data_out[104] vdd 0.63fF +C1712 la_data_in[104] vdd 0.63fF +C1713 la_oenb[103] vdd 0.63fF +C1714 la_data_out[103] vdd 0.63fF +C1715 la_data_in[103] vdd 0.63fF +C1716 la_oenb[102] vdd 0.63fF +C1717 la_data_out[102] vdd 0.63fF +C1718 la_data_in[102] vdd 0.63fF +C1719 la_oenb[101] vdd 0.63fF +C1720 la_data_out[101] vdd 0.63fF +C1721 la_data_in[101] vdd 0.63fF +C1722 la_oenb[100] vdd 0.63fF +C1723 la_data_out[100] vdd 0.63fF +C1724 la_data_in[100] vdd 0.63fF +C1725 la_oenb[99] vdd 0.63fF +C1726 la_data_out[99] vdd 0.63fF +C1727 la_data_in[99] vdd 0.63fF +C1728 la_oenb[98] vdd 0.63fF +C1729 la_data_out[98] vdd 0.63fF +C1730 la_data_in[98] vdd 0.63fF +C1731 la_oenb[97] vdd 0.63fF +C1732 la_data_out[97] vdd 0.63fF +C1733 la_data_in[97] vdd 0.63fF +C1734 la_oenb[96] vdd 0.63fF +C1735 la_data_out[96] vdd 0.63fF +C1736 la_data_in[96] vdd 0.63fF +C1737 la_oenb[95] vdd 0.63fF +C1738 la_data_out[95] vdd 0.63fF +C1739 la_data_in[95] vdd 0.63fF +C1740 la_oenb[94] vdd 0.63fF +C1741 la_data_out[94] vdd 0.63fF +C1742 la_data_in[94] vdd 0.63fF +C1743 la_oenb[93] vdd 0.63fF +C1744 la_data_out[93] vdd 0.63fF +C1745 la_data_in[93] vdd 0.63fF +C1746 la_oenb[92] vdd 0.63fF +C1747 la_data_out[92] vdd 0.63fF +C1748 la_data_in[92] vdd 0.63fF +C1749 la_oenb[91] vdd 0.63fF +C1750 la_data_out[91] vdd 0.63fF +C1751 la_data_in[91] vdd 0.63fF +C1752 la_oenb[90] vdd 0.63fF +C1753 la_data_out[90] vdd 0.63fF +C1754 la_data_in[90] vdd 0.63fF +C1755 la_oenb[89] vdd 0.63fF +C1756 la_data_out[89] vdd 0.63fF +C1757 la_data_in[89] vdd 0.63fF +C1758 la_oenb[88] vdd 0.63fF +C1759 la_data_out[88] vdd 0.63fF +C1760 la_data_in[88] vdd 0.63fF +C1761 la_oenb[87] vdd 0.63fF +C1762 la_data_out[87] vdd 0.63fF +C1763 la_data_in[87] vdd 0.63fF +C1764 la_oenb[86] vdd 0.63fF +C1765 la_data_out[86] vdd 0.63fF +C1766 la_data_in[86] vdd 0.63fF +C1767 la_oenb[85] vdd 0.63fF +C1768 la_data_out[85] vdd 0.63fF +C1769 la_data_in[85] vdd 0.63fF +C1770 la_oenb[84] vdd 0.63fF +C1771 la_data_out[84] vdd 0.63fF +C1772 la_data_in[84] vdd 0.63fF +C1773 la_oenb[83] vdd 0.63fF +C1774 la_data_out[83] vdd 0.63fF +C1775 la_data_in[83] vdd 0.63fF +C1776 la_oenb[82] vdd 0.63fF +C1777 la_data_out[82] vdd 0.63fF +C1778 la_data_in[82] vdd 0.63fF +C1779 la_oenb[81] vdd 0.63fF +C1780 la_data_out[81] vdd 0.63fF +C1781 la_data_in[81] vdd 0.63fF +C1782 la_oenb[80] vdd 0.63fF +C1783 la_data_out[80] vdd 0.63fF +C1784 la_data_in[80] vdd 0.63fF +C1785 la_oenb[79] vdd 0.63fF +C1786 la_data_out[79] vdd 0.63fF +C1787 la_data_in[79] vdd 0.63fF +C1788 la_oenb[78] vdd 0.63fF +C1789 la_data_out[78] vdd 0.63fF +C1790 la_data_in[78] vdd 0.63fF +C1791 la_oenb[77] vdd 0.63fF +C1792 la_data_out[77] vdd 0.63fF +C1793 la_data_in[77] vdd 0.63fF +C1794 la_oenb[76] vdd 0.63fF +C1795 la_data_out[76] vdd 0.63fF +C1796 la_data_in[76] vdd 0.63fF +C1797 la_oenb[75] vdd 0.63fF +C1798 la_data_out[75] vdd 0.63fF +C1799 la_data_in[75] vdd 0.63fF +C1800 la_oenb[74] vdd 0.63fF +C1801 la_data_out[74] vdd 0.63fF +C1802 la_data_in[74] vdd 0.63fF +C1803 la_oenb[73] vdd 0.63fF +C1804 la_data_out[73] vdd 0.63fF +C1805 la_data_in[73] vdd 0.63fF +C1806 la_oenb[72] vdd 0.63fF +C1807 la_data_out[72] vdd 0.63fF +C1808 la_data_in[72] vdd 0.63fF +C1809 la_oenb[71] vdd 0.63fF +C1810 la_data_out[71] vdd 0.63fF +C1811 la_data_in[71] vdd 0.63fF +C1812 la_oenb[70] vdd 0.63fF +C1813 la_data_out[70] vdd 0.63fF +C1814 la_data_in[70] vdd 0.63fF +C1815 la_oenb[69] vdd 0.63fF +C1816 la_data_out[69] vdd 0.63fF +C1817 la_data_in[69] vdd 0.63fF +C1818 la_oenb[68] vdd 0.63fF +C1819 la_data_out[68] vdd 0.63fF +C1820 la_data_in[68] vdd 0.63fF +C1821 la_oenb[67] vdd 0.63fF +C1822 la_data_out[67] vdd 0.63fF +C1823 la_data_in[67] vdd 0.63fF +C1824 la_oenb[66] vdd 0.63fF +C1825 la_data_out[66] vdd 0.63fF +C1826 la_data_in[66] vdd 0.63fF +C1827 la_oenb[65] vdd 0.63fF +C1828 la_data_out[65] vdd 0.63fF +C1829 la_data_in[65] vdd 0.63fF +C1830 la_oenb[64] vdd 0.63fF +C1831 la_data_out[64] vdd 0.63fF +C1832 la_data_in[64] vdd 0.63fF +C1833 la_oenb[63] vdd 0.63fF +C1834 la_data_out[63] vdd 0.63fF +C1835 la_data_in[63] vdd 0.63fF +C1836 la_oenb[62] vdd 0.63fF +C1837 la_data_out[62] vdd 0.63fF +C1838 la_data_in[62] vdd 0.63fF +C1839 la_oenb[61] vdd 0.63fF +C1840 la_data_out[61] vdd 0.63fF +C1841 la_data_in[61] vdd 0.63fF +C1842 la_oenb[60] vdd 0.63fF +C1843 la_data_out[60] vdd 0.63fF +C1844 la_data_in[60] vdd 0.63fF +C1845 la_oenb[59] vdd 0.63fF +C1846 la_data_out[59] vdd 0.63fF +C1847 la_data_in[59] vdd 0.63fF +C1848 la_oenb[58] vdd 0.63fF +C1849 la_data_out[58] vdd 0.63fF +C1850 la_data_in[58] vdd 0.63fF +C1851 la_oenb[57] vdd 0.63fF +C1852 la_data_out[57] vdd 0.63fF +C1853 la_data_in[57] vdd 0.63fF +C1854 la_oenb[56] vdd 0.63fF +C1855 la_data_out[56] vdd 0.63fF +C1856 la_data_in[56] vdd 0.63fF +C1857 la_oenb[55] vdd 0.63fF +C1858 la_data_out[55] vdd 0.63fF +C1859 la_data_in[55] vdd 0.63fF +C1860 la_oenb[54] vdd 0.63fF +C1861 la_data_out[54] vdd 0.63fF +C1862 la_data_in[54] vdd 0.63fF +C1863 la_oenb[53] vdd 0.63fF +C1864 la_data_out[53] vdd 0.63fF +C1865 la_data_in[53] vdd 0.63fF +C1866 la_oenb[52] vdd 0.63fF +C1867 la_data_out[52] vdd 0.63fF +C1868 la_data_in[52] vdd 0.63fF +C1869 la_oenb[51] vdd 0.63fF +C1870 la_data_out[51] vdd 0.63fF +C1871 la_data_in[51] vdd 0.63fF +C1872 la_oenb[50] vdd 0.63fF +C1873 la_data_out[50] vdd 0.63fF +C1874 la_data_in[50] vdd 0.63fF +C1875 la_oenb[49] vdd 0.63fF +C1876 la_data_out[49] vdd 0.63fF +C1877 la_data_in[49] vdd 0.63fF +C1878 la_oenb[48] vdd 0.63fF +C1879 la_data_out[48] vdd 0.63fF +C1880 la_data_in[48] vdd 0.63fF +C1881 la_oenb[47] vdd 0.63fF +C1882 la_data_out[47] vdd 0.63fF +C1883 la_data_in[47] vdd 0.63fF +C1884 la_oenb[46] vdd 0.63fF +C1885 la_data_out[46] vdd 0.63fF +C1886 la_data_in[46] vdd 0.63fF +C1887 la_oenb[45] vdd 0.63fF +C1888 la_data_out[45] vdd 0.63fF +C1889 la_data_in[45] vdd 0.63fF +C1890 la_oenb[44] vdd 0.63fF +C1891 la_data_out[44] vdd 0.63fF +C1892 la_data_in[44] vdd 0.63fF +C1893 la_oenb[43] vdd 0.63fF +C1894 la_data_out[43] vdd 0.63fF +C1895 la_data_in[43] vdd 0.63fF +C1896 la_oenb[42] vdd 0.63fF +C1897 la_data_out[42] vdd 0.63fF +C1898 la_data_in[42] vdd 0.63fF +C1899 la_oenb[41] vdd 0.63fF +C1900 la_data_out[41] vdd 0.63fF +C1901 la_data_in[41] vdd 0.63fF +C1902 la_oenb[40] vdd 0.63fF +C1903 la_data_out[40] vdd 0.63fF +C1904 la_data_in[40] vdd 0.63fF +C1905 la_oenb[39] vdd 0.63fF +C1906 la_data_out[39] vdd 0.63fF +C1907 la_data_in[39] vdd 0.63fF +C1908 la_oenb[38] vdd 0.63fF +C1909 la_data_out[38] vdd 0.63fF +C1910 la_data_in[38] vdd 0.63fF +C1911 la_oenb[37] vdd 0.63fF +C1912 la_data_out[37] vdd 0.63fF +C1913 la_data_in[37] vdd 0.63fF +C1914 la_oenb[36] vdd 0.63fF +C1915 la_data_out[36] vdd 0.63fF +C1916 la_data_in[36] vdd 0.63fF +C1917 la_oenb[35] vdd 0.63fF +C1918 la_data_out[35] vdd 0.63fF +C1919 la_data_in[35] vdd 0.63fF +C1920 la_oenb[34] vdd 0.63fF +C1921 la_data_out[34] vdd 0.63fF +C1922 la_data_in[34] vdd 0.63fF +C1923 la_oenb[33] vdd 0.63fF +C1924 la_data_out[33] vdd 0.63fF +C1925 la_data_in[33] vdd 0.63fF +C1926 la_oenb[32] vdd 0.63fF +C1927 la_data_out[32] vdd 0.63fF +C1928 la_data_in[32] vdd 0.63fF +C1929 la_oenb[31] vdd 0.63fF +C1930 la_data_out[31] vdd 0.63fF +C1931 la_data_in[31] vdd 0.63fF +C1932 la_oenb[30] vdd 0.63fF +C1933 la_data_out[30] vdd 0.63fF +C1934 la_data_in[30] vdd 0.63fF +C1935 la_oenb[29] vdd 0.63fF +C1936 la_data_out[29] vdd 0.63fF +C1937 la_data_in[29] vdd 0.63fF +C1938 la_oenb[28] vdd 0.63fF +C1939 la_data_out[28] vdd 0.63fF +C1940 la_data_in[28] vdd 0.63fF +C1941 la_oenb[27] vdd 0.63fF +C1942 la_data_out[27] vdd 0.63fF +C1943 la_data_in[27] vdd 0.63fF +C1944 la_oenb[26] vdd 0.63fF +C1945 la_data_out[26] vdd 0.63fF +C1946 la_data_in[26] vdd 0.63fF +C1947 la_oenb[25] vdd 0.63fF +C1948 la_data_out[25] vdd 0.63fF +C1949 la_data_in[25] vdd 0.63fF +C1950 la_oenb[24] vdd 0.63fF +C1951 la_data_out[24] vdd 0.63fF +C1952 la_data_in[24] vdd 0.63fF +C1953 la_oenb[23] vdd 0.63fF +C1954 la_data_out[23] vdd 0.63fF +C1955 la_data_in[23] vdd 0.63fF +C1956 la_oenb[22] vdd 0.63fF +C1957 la_data_out[22] vdd 0.63fF +C1958 la_data_in[22] vdd 0.63fF +C1959 la_oenb[21] vdd 0.63fF +C1960 la_data_out[21] vdd 0.63fF +C1961 la_data_in[21] vdd 0.63fF +C1962 la_oenb[20] vdd 0.63fF +C1963 la_data_out[20] vdd 0.63fF +C1964 la_data_in[20] vdd 0.63fF +C1965 la_oenb[19] vdd 0.63fF +C1966 la_data_out[19] vdd 0.63fF +C1967 la_data_in[19] vdd 0.63fF +C1968 la_oenb[18] vdd 0.63fF +C1969 la_data_out[18] vdd 0.63fF +C1970 la_data_in[18] vdd 0.63fF +C1971 la_oenb[17] vdd 0.63fF +C1972 la_data_out[17] vdd 0.63fF +C1973 la_data_in[17] vdd 0.63fF +C1974 la_oenb[16] vdd 0.63fF +C1975 la_data_out[16] vdd 0.63fF +C1976 la_data_in[16] vdd 0.63fF +C1977 la_oenb[15] vdd 0.63fF +C1978 la_data_out[15] vdd 0.63fF +C1979 la_data_in[15] vdd 0.63fF +C1980 la_oenb[14] vdd 0.63fF +C1981 la_data_out[14] vdd 0.63fF +C1982 la_data_in[14] vdd 0.63fF +C1983 la_oenb[13] vdd 0.63fF +C1984 la_data_out[13] vdd 0.63fF +C1985 la_data_in[13] vdd 0.63fF +C1986 la_oenb[12] vdd 0.63fF +C1987 la_data_out[12] vdd 0.63fF +C1988 la_data_in[12] vdd 0.63fF +C1989 la_oenb[11] vdd 0.63fF +C1990 la_data_out[11] vdd 0.63fF +C1991 la_data_in[11] vdd 0.63fF +C1992 la_oenb[10] vdd 0.63fF +C1993 la_data_out[10] vdd 0.63fF +C1994 la_data_in[10] vdd 0.63fF +C1995 la_oenb[9] vdd 0.63fF +C1996 la_data_out[9] vdd 0.63fF +C1997 la_data_in[9] vdd 0.63fF +C1998 la_oenb[8] vdd 0.63fF +C1999 la_data_out[8] vdd 0.63fF +C2000 la_data_in[8] vdd 0.63fF +C2001 la_oenb[7] vdd 0.63fF +C2002 la_data_out[7] vdd 0.63fF +C2003 la_data_in[7] vdd 0.63fF +C2004 la_oenb[6] vdd 0.63fF +C2005 la_data_out[6] vdd 0.63fF +C2006 la_data_in[6] vdd 0.63fF +C2007 la_oenb[5] vdd 0.63fF +C2008 la_data_out[5] vdd 0.63fF +C2009 la_data_in[5] vdd 0.63fF +C2010 la_oenb[4] vdd 0.63fF +C2011 la_data_out[4] vdd 0.63fF +C2012 la_data_in[4] vdd 0.63fF +C2013 la_oenb[3] vdd 0.63fF +C2014 la_data_out[3] vdd 0.63fF +C2015 la_data_in[3] vdd 0.63fF +C2016 la_oenb[2] vdd 0.63fF +C2017 la_data_out[2] vdd 0.63fF +C2018 la_data_in[2] vdd 0.63fF +C2019 la_oenb[1] vdd 0.63fF +C2020 la_data_out[1] vdd 0.63fF +C2021 la_data_in[1] vdd 0.63fF +C2022 la_oenb[0] vdd 0.63fF +C2023 la_data_out[0] vdd 0.63fF +C2024 la_data_in[0] vdd 0.63fF +C2025 wbs_dat_o[31] vdd 0.63fF +C2026 wbs_dat_i[31] vdd 0.63fF +C2027 wbs_adr_i[31] vdd 0.63fF +C2028 wbs_dat_o[30] vdd 0.63fF +C2029 wbs_dat_i[30] vdd 0.63fF +C2030 wbs_adr_i[30] vdd 0.63fF +C2031 wbs_dat_o[29] vdd 0.63fF +C2032 wbs_dat_i[29] vdd 0.63fF +C2033 wbs_adr_i[29] vdd 0.63fF +C2034 wbs_dat_o[28] vdd 0.63fF +C2035 wbs_dat_i[28] vdd 0.63fF +C2036 wbs_adr_i[28] vdd 0.63fF +C2037 wbs_dat_o[27] vdd 0.63fF +C2038 wbs_dat_i[27] vdd 0.63fF +C2039 wbs_adr_i[27] vdd 0.63fF +C2040 wbs_dat_o[26] vdd 0.63fF +C2041 wbs_dat_i[26] vdd 0.63fF +C2042 wbs_adr_i[26] vdd 0.63fF +C2043 wbs_dat_o[25] vdd 0.63fF +C2044 wbs_dat_i[25] vdd 0.63fF +C2045 wbs_adr_i[25] vdd 0.63fF +C2046 wbs_dat_o[24] vdd 0.63fF +C2047 wbs_dat_i[24] vdd 0.63fF +C2048 wbs_adr_i[24] vdd 0.63fF +C2049 wbs_dat_o[23] vdd 0.63fF +C2050 wbs_dat_i[23] vdd 0.63fF +C2051 wbs_adr_i[23] vdd 0.63fF +C2052 wbs_dat_o[22] vdd 0.63fF +C2053 wbs_dat_i[22] vdd 0.63fF +C2054 wbs_adr_i[22] vdd 0.63fF +C2055 wbs_dat_o[21] vdd 0.63fF +C2056 wbs_dat_i[21] vdd 0.63fF +C2057 wbs_adr_i[21] vdd 0.63fF +C2058 wbs_dat_o[20] vdd 0.63fF +C2059 wbs_dat_i[20] vdd 0.63fF +C2060 wbs_adr_i[20] vdd 0.63fF +C2061 wbs_dat_o[19] vdd 0.63fF +C2062 wbs_dat_i[19] vdd 0.63fF +C2063 wbs_adr_i[19] vdd 0.63fF +C2064 wbs_dat_o[18] vdd 0.63fF +C2065 wbs_dat_i[18] vdd 0.63fF +C2066 wbs_adr_i[18] vdd 0.63fF +C2067 wbs_dat_o[17] vdd 0.63fF +C2068 wbs_dat_i[17] vdd 0.63fF +C2069 wbs_adr_i[17] vdd 0.63fF +C2070 wbs_dat_o[16] vdd 0.63fF +C2071 wbs_dat_i[16] vdd 0.63fF +C2072 wbs_adr_i[16] vdd 0.63fF +C2073 wbs_dat_o[15] vdd 0.63fF +C2074 wbs_dat_i[15] vdd 0.63fF +C2075 wbs_adr_i[15] vdd 0.63fF +C2076 wbs_dat_o[14] vdd 0.63fF +C2077 wbs_dat_i[14] vdd 0.63fF +C2078 wbs_adr_i[14] vdd 0.63fF +C2079 wbs_dat_o[13] vdd 0.63fF +C2080 wbs_dat_i[13] vdd 0.63fF +C2081 wbs_adr_i[13] vdd 0.63fF +C2082 wbs_dat_o[12] vdd 0.63fF +C2083 wbs_dat_i[12] vdd 0.63fF +C2084 wbs_adr_i[12] vdd 0.63fF +C2085 wbs_dat_o[11] vdd 0.63fF +C2086 wbs_dat_i[11] vdd 0.63fF +C2087 wbs_adr_i[11] vdd 0.63fF +C2088 wbs_dat_o[10] vdd 0.63fF +C2089 wbs_dat_i[10] vdd 0.63fF +C2090 wbs_adr_i[10] vdd 0.63fF +C2091 wbs_dat_o[9] vdd 0.63fF +C2092 wbs_dat_i[9] vdd 0.63fF +C2093 wbs_adr_i[9] vdd 0.63fF +C2094 wbs_dat_o[8] vdd 0.63fF +C2095 wbs_dat_i[8] vdd 0.63fF +C2096 wbs_adr_i[8] vdd 0.63fF +C2097 wbs_dat_o[7] vdd 0.63fF +C2098 wbs_dat_i[7] vdd 0.63fF +C2099 wbs_adr_i[7] vdd 0.63fF +C2100 wbs_dat_o[6] vdd 0.63fF +C2101 wbs_dat_i[6] vdd 0.63fF +C2102 wbs_adr_i[6] vdd 0.63fF +C2103 wbs_dat_o[5] vdd 0.63fF +C2104 wbs_dat_i[5] vdd 0.63fF +C2105 wbs_adr_i[5] vdd 0.63fF +C2106 wbs_dat_o[4] vdd 0.63fF +C2107 wbs_dat_i[4] vdd 0.63fF +C2108 wbs_adr_i[4] vdd 0.63fF +C2109 wbs_sel_i[3] vdd 0.63fF +C2110 wbs_dat_o[3] vdd 0.63fF +C2111 wbs_dat_i[3] vdd 0.63fF +C2112 wbs_adr_i[3] vdd 0.63fF +C2113 wbs_sel_i[2] vdd 0.63fF +C2114 wbs_dat_o[2] vdd 0.63fF +C2115 wbs_dat_i[2] vdd 0.63fF +C2116 wbs_adr_i[2] vdd 0.63fF +C2117 wbs_sel_i[1] vdd 0.63fF +C2118 wbs_dat_o[1] vdd 0.63fF +C2119 wbs_dat_i[1] vdd 0.63fF +C2120 wbs_adr_i[1] vdd 0.63fF +C2121 wbs_sel_i[0] vdd 0.63fF +C2122 wbs_dat_o[0] vdd 0.63fF +C2123 wbs_dat_i[0] vdd 0.63fF +C2124 wbs_adr_i[0] vdd 0.63fF +C2125 wbs_we_i vdd 0.63fF +C2126 wbs_stb_i vdd 0.63fF +C2127 wbs_cyc_i vdd 0.63fF +C2128 wbs_ack_o vdd 0.63fF +C2129 wb_rst_i vdd 0.63fF +C2130 wb_clk_i vdd 0.63fF +C2131 pll_full_0/divider_0/and_0/Z1 vdd 0.65fF +C2132 pll_full_0/divider_0/and_0/B vdd 2.45fF +C2133 pll_full_0/divider_0/and_0/A vdd 2.35fF +C2134 pll_full_0/divider_0/and_0/out1 vdd 2.99fF +C2135 pll_full_0/divider_0/tspc_2/Z4 vdd 0.86fF +C2136 pll_full_0/divbuf_0/IN vdd 9.95fF +C2137 pll_full_0/divider_0/tspc_2/Z3 vdd 2.26fF +C2138 pll_full_0/divider_0/tspc_2/Z2 vdd 1.46fF +C2139 pll_full_0/divider_0/tspc_2/Z1 vdd 0.99fF +C2140 pll_full_0/divider_0/nor_0/B vdd 6.48fF +C2141 pll_full_0/divider_0/tspc_2/a_630_n680# vdd 1.14fF **FLOATING +C2142 pll_full_0/divider_0/tspc_1/Z4 vdd 0.86fF +C2143 pll_full_0/divider_0/tspc_1/Q vdd 3.12fF +C2144 pll_full_0/divider_0/tspc_1/Z3 vdd 2.26fF +C2145 pll_full_0/divider_0/tspc_1/Z2 vdd 1.46fF +C2146 pll_full_0/divider_0/tspc_1/Z1 vdd 0.99fF +C2147 pll_full_0/divider_0/nor_1/B vdd 7.12fF +C2148 pll_full_0/divider_0/tspc_1/a_630_n680# vdd 1.15fF **FLOATING +C2149 pll_full_0/divider_0/tspc_0/Z4 vdd 0.86fF +C2150 pll_full_0/divider_0/tspc_0/Q vdd 3.14fF +C2151 pll_full_0/divider_0/tspc_0/Z3 vdd 2.26fF +C2152 pll_full_0/divider_0/tspc_0/Z2 vdd 1.46fF +C2153 pll_full_0/divider_0/tspc_0/Z1 vdd 0.99fF +C2154 pll_full_0/divider_0/nor_1/A vdd 7.08fF +C2155 pll_full_0/divider_0/tspc_0/a_630_n680# vdd 1.15fF **FLOATING +C2156 pll_full_0/divider_0/clk vdd 31.85fF +C2157 pll_full_0/divider_0/prescaler_0/Out vdd 4.59fF +C2158 pll_full_0/divider_0/prescaler_0/nand_1/z1 vdd 0.36fF +C2159 pll_full_0/divider_0/prescaler_0/tspc_2/D vdd 2.64fF +C2160 pll_full_0/divider_0/prescaler_0/tspc_0/Q vdd 3.64fF +C2161 pll_full_0/divider_0/prescaler_0/tspc_1/Q vdd 3.61fF +C2162 pll_full_0/divider_0/prescaler_0/nand_0/z1 vdd 0.36fF +C2163 pll_full_0/divider_0/prescaler_0/tspc_0/D vdd 3.12fF +C2164 pll_full_0/divider_0/and_0/OUT vdd 5.67fF +C2165 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 vdd 0.86fF +C2166 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 vdd 2.26fF +C2167 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 vdd 1.46fF +C2168 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF +C2169 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING +C2170 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING +C2171 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 vdd 0.86fF +C2172 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 vdd 2.26fF +C2173 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 vdd 1.48fF +C2174 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF +C2175 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING +C2176 pll_full_0/divider_0/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING +C2177 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 vdd 0.86fF +C2178 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 vdd 2.26fF +C2179 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 vdd 1.19fF +C2180 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF +C2181 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# vdd 1.47fF **FLOATING +C2182 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING +C2183 pll_full_0/divider_0/nor_1/Z1 vdd 1.34fF +C2184 pll_full_0/divider_0/nor_0/Z1 vdd 1.34fF +C2185 pll_full_0/divbuf_1/OUT vdd 363.82fF +C2186 pll_full_0/divbuf_1/OUT5 vdd 350.37fF +C2187 pll_full_0/divbuf_1/OUT4 vdd 133.72fF +C2188 pll_full_0/divbuf_1/OUT3 vdd 34.03fF +C2189 pll_full_0/divbuf_1/OUT2 vdd 8.71fF +C2190 pll_full_0/divbuf_1/a_492_n240# vdd 2.46fF **FLOATING +C2191 pll_full_0/divbuf_0/OUT5 vdd 350.37fF +C2192 pll_full_0/divbuf_0/OUT4 vdd 133.72fF +C2193 pll_full_0/divbuf_0/OUT3 vdd 34.03fF +C2194 pll_full_0/divbuf_0/OUT2 vdd 8.71fF +C2195 pll_full_0/divbuf_0/a_492_n240# vdd 2.46fF **FLOATING +C2196 pll_full_0/ro_complete_0/cbank_2/v vdd 17.88fF +C2197 pll_full_0/ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF +C2198 pll_full_0/ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF +C2199 pll_full_0/ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF +C2200 pll_full_0/ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF +C2201 pll_full_0/ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF +C2202 pll_full_0/ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF +C2203 pll_full_0/ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF +C2204 pll_full_0/ro_complete_0/a0 vdd 7.88fF +C2205 pll_full_0/ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF +C2206 pll_full_0/ro_complete_0/a1 vdd 5.39fF +C2207 pll_full_0/ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF +C2208 pll_full_0/ro_complete_0/a3 vdd 6.85fF +C2209 pll_full_0/ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF +C2210 pll_full_0/ro_complete_0/a2 vdd 5.48fF +C2211 pll_full_0/ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF +C2212 pll_full_0/ro_complete_0/a4 vdd 5.36fF +C2213 pll_full_0/ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF +C2214 pll_full_0/ro_complete_0/a5 vdd 5.19fF +C2215 pll_full_0/ro_complete_0/cbank_0/v vdd 15.02fF +C2216 pll_full_0/ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF +C2217 pll_full_0/ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF +C2218 pll_full_0/ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF +C2219 pll_full_0/ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF +C2220 pll_full_0/ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF +C2221 pll_full_0/ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF +C2222 pll_full_0/ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF +C2223 pll_full_0/filter_0/a_4216_n5230# vdd 419.25fF **FLOATING +C2224 pll_full_0/filter_0/a_4216_n2998# vdd 1.39fF **FLOATING +C2225 pll_full_0/cp_0/down vdd 1.54fF +C2226 pll_full_0/cp_0/upbar vdd 1.79fF +C2227 pll_full_0/cp_0/a_7110_n2840# vdd 0.17fF **FLOATING +C2228 pll_full_0/cp_0/a_3060_n2840# vdd 1.71fF **FLOATING +C2229 pll_full_0/cp_0/a_7110_0# vdd 0.17fF **FLOATING +C2230 pll_full_0/cp_0/a_6370_0# vdd 0.40fF **FLOATING +C2231 pll_full_0/cp_0/a_3060_0# vdd 2.49fF **FLOATING +C2232 pll_full_0/cp_0/a_1710_0# vdd 7.47fF **FLOATING +C2233 pll_full_0/pd_0/and_pd_0/Z1 vdd 0.39fF +C2234 pll_full_0/pd_0/and_pd_0/Out1 vdd 2.22fF +C2235 pll_full_0/pd_0/tspc_r_1/z5 vdd 1.10fF +C2236 pll_full_0/pd_0/tspc_r_1/Z4 vdd 1.07fF +C2237 pll_full_0/pd_0/tspc_r_1/Qbar vdd 0.88fF +C2238 pll_full_0/pd_0/tspc_r_1/Z2 vdd 1.22fF +C2239 pll_full_0/pd_0/tspc_r_1/Z1 vdd 0.67fF +C2240 pll_full_0/pd_0/UP vdd 6.61fF +C2241 pll_full_0/pd_0/tspc_r_1/Qbar1 vdd 1.34fF +C2242 pll_full_0/pd_0/tspc_r_1/Z3 vdd 2.12fF +C2243 pll_full_0/pd_0/REF vdd 6.44fF +C2244 pll_full_0/pd_0/tspc_r_0/z5 vdd 1.10fF +C2245 pll_full_0/pd_0/tspc_r_0/Z4 vdd 1.07fF +C2246 pll_full_0/pd_0/R vdd 3.05fF +C2247 pll_full_0/pd_0/tspc_r_0/Qbar vdd 0.79fF +C2248 pll_full_0/pd_0/tspc_r_0/Z2 vdd 1.22fF +C2249 pll_full_0/pd_0/tspc_r_0/Z1 vdd 0.67fF +C2250 pll_full_0/pd_0/DOWN vdd 7.24fF +C2251 pll_full_0/pd_0/tspc_r_0/Qbar1 vdd 1.34fF +C2252 pll_full_0/pd_0/tspc_r_0/Z3 vdd 2.12fF +C2253 pll_full_0/pd_0/DIV vdd 371.87fF +C2254 divider_2/and_0/Z1 vdd 0.74fF +C2255 divider_2/and_0/B vdd 2.25fF +C2256 divider_2/and_0/A vdd 2.19fF +C2257 divider_2/and_0/out1 vdd 2.93fF +C2258 divider_2/tspc_2/Z4 vdd 0.86fF +C2259 divider_2/Out vdd 1.60fF +C2260 divider_2/tspc_2/Z3 vdd 2.26fF +C2261 divider_2/tspc_2/Z2 vdd 1.46fF +C2262 divider_2/tspc_2/Z1 vdd 0.99fF +C2263 divider_2/nor_0/B vdd 6.33fF +C2264 divider_2/tspc_2/a_630_n680# vdd 1.14fF **FLOATING +C2265 divider_2/tspc_1/Z4 vdd 0.86fF +C2266 divider_2/tspc_1/Q vdd 3.12fF +C2267 divider_2/tspc_1/Z3 vdd 2.26fF +C2268 divider_2/tspc_1/Z2 vdd 1.46fF +C2269 divider_2/tspc_1/Z1 vdd 0.99fF +C2270 divider_2/nor_1/B vdd 7.05fF +C2271 divider_2/tspc_1/a_630_n680# vdd 1.15fF **FLOATING +C2272 divider_2/tspc_0/Z4 vdd 0.86fF +C2273 divider_2/tspc_0/Q vdd 3.14fF +C2274 divider_2/tspc_0/Z3 vdd 2.26fF +C2275 divider_2/tspc_0/Z2 vdd 1.46fF +C2276 divider_2/tspc_0/Z1 vdd 0.99fF +C2277 divider_2/nor_1/A vdd 7.04fF +C2278 divider_2/tspc_0/a_630_n680# vdd 1.15fF **FLOATING +C2279 divider_2/clk vdd 5.63fF +C2280 divider_2/prescaler_0/Out vdd 4.59fF +C2281 divider_2/prescaler_0/nand_1/z1 vdd 0.36fF +C2282 divider_2/prescaler_0/tspc_2/D vdd 2.64fF +C2283 divider_2/prescaler_0/tspc_0/Q vdd 3.64fF +C2284 divider_2/prescaler_0/tspc_1/Q vdd 3.61fF +C2285 divider_2/prescaler_0/nand_0/z1 vdd 0.36fF +C2286 divider_2/prescaler_0/tspc_0/D vdd 3.12fF +C2287 divider_2/and_0/OUT vdd 5.62fF +C2288 divider_2/prescaler_0/tspc_2/Z4 vdd 0.86fF +C2289 divider_2/prescaler_0/tspc_2/Z3 vdd 2.26fF +C2290 divider_2/prescaler_0/tspc_2/Z2 vdd 1.46fF +C2291 divider_2/prescaler_0/tspc_2/Z1 vdd 0.99fF +C2292 divider_2/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING +C2293 divider_2/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING +C2294 divider_2/prescaler_0/tspc_1/Z4 vdd 0.86fF +C2295 divider_2/prescaler_0/tspc_1/Z3 vdd 2.26fF +C2296 divider_2/prescaler_0/tspc_1/Z2 vdd 1.48fF +C2297 divider_2/prescaler_0/tspc_1/Z1 vdd 0.99fF +C2298 divider_2/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING +C2299 divider_2/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING +C2300 divider_2/prescaler_0/tspc_0/Z4 vdd 0.86fF +C2301 divider_2/prescaler_0/tspc_0/Z3 vdd 2.26fF +C2302 divider_2/prescaler_0/tspc_0/Z2 vdd 1.46fF +C2303 divider_2/prescaler_0/tspc_0/Z1 vdd 0.99fF +C2304 divider_2/prescaler_0/tspc_0/a_630_n680# vdd 1.14fF **FLOATING +C2305 divider_2/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING +C2306 divider_2/nor_1/Z1 vdd 1.34fF +C2307 divider_2/nor_0/Z1 vdd 1.34fF +C2308 divider_2/mc2 vdd 5.29fF +C2309 divider_1/and_0/Z1 vdd 0.74fF +C2310 divider_1/and_0/B vdd 2.25fF +C2311 divider_1/and_0/A vdd 2.19fF +C2312 divider_1/and_0/out1 vdd 2.93fF +C2313 divider_1/tspc_2/Z4 vdd 0.86fF +C2314 divider_1/Out vdd 1.60fF +C2315 divider_1/tspc_2/Z3 vdd 2.26fF +C2316 divider_1/tspc_2/Z2 vdd 1.46fF +C2317 divider_1/tspc_2/Z1 vdd 0.99fF +C2318 divider_1/nor_0/B vdd 6.33fF +C2319 divider_1/tspc_2/a_630_n680# vdd 1.14fF **FLOATING +C2320 divider_1/tspc_1/Z4 vdd 0.86fF +C2321 divider_1/tspc_1/Q vdd 3.12fF +C2322 divider_1/tspc_1/Z3 vdd 2.26fF +C2323 divider_1/tspc_1/Z2 vdd 1.46fF +C2324 divider_1/tspc_1/Z1 vdd 0.99fF +C2325 divider_1/nor_1/B vdd 7.05fF +C2326 divider_1/tspc_1/a_630_n680# vdd 1.15fF **FLOATING +C2327 divider_1/tspc_0/Z4 vdd 0.86fF +C2328 divider_1/tspc_0/Q vdd 3.14fF +C2329 divider_1/tspc_0/Z3 vdd 2.26fF +C2330 divider_1/tspc_0/Z2 vdd 1.46fF +C2331 divider_1/tspc_0/Z1 vdd 0.99fF +C2332 divider_1/nor_1/A vdd 7.04fF +C2333 divider_1/tspc_0/a_630_n680# vdd 1.15fF **FLOATING +C2334 divider_1/clk vdd 5.63fF +C2335 divider_1/prescaler_0/Out vdd 4.59fF +C2336 divider_1/prescaler_0/nand_1/z1 vdd 0.36fF +C2337 divider_1/prescaler_0/tspc_2/D vdd 2.64fF +C2338 divider_1/prescaler_0/tspc_0/Q vdd 3.64fF +C2339 divider_1/prescaler_0/tspc_1/Q vdd 3.61fF +C2340 divider_1/prescaler_0/nand_0/z1 vdd 0.36fF +C2341 divider_1/prescaler_0/tspc_0/D vdd 3.12fF +C2342 divider_1/and_0/OUT vdd 5.62fF +C2343 divider_1/prescaler_0/tspc_2/Z4 vdd 0.86fF +C2344 divider_1/prescaler_0/tspc_2/Z3 vdd 2.26fF +C2345 divider_1/prescaler_0/tspc_2/Z2 vdd 1.46fF +C2346 divider_1/prescaler_0/tspc_2/Z1 vdd 0.99fF +C2347 divider_1/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING +C2348 divider_1/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING +C2349 divider_1/prescaler_0/tspc_1/Z4 vdd 0.86fF +C2350 divider_1/prescaler_0/tspc_1/Z3 vdd 2.26fF +C2351 divider_1/prescaler_0/tspc_1/Z2 vdd 1.48fF +C2352 divider_1/prescaler_0/tspc_1/Z1 vdd 0.99fF +C2353 divider_1/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING +C2354 divider_1/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING +C2355 divider_1/prescaler_0/tspc_0/Z4 vdd 0.86fF +C2356 divider_1/prescaler_0/tspc_0/Z3 vdd 2.26fF +C2357 divider_1/prescaler_0/tspc_0/Z2 vdd 1.46fF +C2358 divider_1/prescaler_0/tspc_0/Z1 vdd 0.99fF +C2359 divider_1/prescaler_0/tspc_0/a_630_n680# vdd 1.14fF **FLOATING +C2360 divider_1/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING +C2361 divider_1/nor_1/Z1 vdd 1.34fF +C2362 divider_1/nor_0/Z1 vdd 1.34fF +C2363 divider_1/mc2 vdd 5.29fF +C2364 divider_0/and_0/Z1 vdd 0.74fF +C2365 divider_0/and_0/B vdd 2.25fF +C2366 divider_0/and_0/A vdd 2.19fF +C2367 divider_0/and_0/out1 vdd 2.93fF +C2368 divider_0/tspc_2/Z4 vdd 0.86fF +C2369 divider_0/Out vdd 1.60fF +C2370 divider_0/tspc_2/Z3 vdd 2.26fF +C2371 divider_0/tspc_2/Z2 vdd 1.46fF +C2372 divider_0/tspc_2/Z1 vdd 0.99fF +C2373 divider_0/nor_0/B vdd 6.33fF +C2374 divider_0/tspc_2/a_630_n680# vdd 1.14fF **FLOATING +C2375 divider_0/tspc_1/Z4 vdd 0.86fF +C2376 divider_0/tspc_1/Q vdd 3.12fF +C2377 divider_0/tspc_1/Z3 vdd 2.26fF +C2378 divider_0/tspc_1/Z2 vdd 1.46fF +C2379 divider_0/tspc_1/Z1 vdd 0.99fF +C2380 divider_0/nor_1/B vdd 7.05fF +C2381 divider_0/tspc_1/a_630_n680# vdd 1.15fF **FLOATING +C2382 divider_0/tspc_0/Z4 vdd 0.86fF +C2383 divider_0/tspc_0/Q vdd 3.14fF +C2384 divider_0/tspc_0/Z3 vdd 2.26fF +C2385 divider_0/tspc_0/Z2 vdd 1.46fF +C2386 divider_0/tspc_0/Z1 vdd 0.99fF +C2387 divider_0/nor_1/A vdd 7.04fF +C2388 divider_0/tspc_0/a_630_n680# vdd 1.15fF **FLOATING +C2389 divider_0/clk vdd 5.63fF +C2390 divider_0/prescaler_0/Out vdd 4.59fF +C2391 divider_0/prescaler_0/nand_1/z1 vdd 0.36fF +C2392 divider_0/prescaler_0/tspc_2/D vdd 2.64fF +C2393 divider_0/prescaler_0/tspc_0/Q vdd 3.64fF +C2394 divider_0/prescaler_0/tspc_1/Q vdd 3.61fF +C2395 divider_0/prescaler_0/nand_0/z1 vdd 0.36fF +C2396 divider_0/prescaler_0/tspc_0/D vdd 3.12fF +C2397 divider_0/and_0/OUT vdd 5.62fF +C2398 divider_0/prescaler_0/tspc_2/Z4 vdd 0.86fF +C2399 divider_0/prescaler_0/tspc_2/Z3 vdd 2.26fF +C2400 divider_0/prescaler_0/tspc_2/Z2 vdd 1.46fF +C2401 divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF +C2402 divider_0/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING +C2403 divider_0/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING +C2404 divider_0/prescaler_0/tspc_1/Z4 vdd 0.86fF +C2405 divider_0/prescaler_0/tspc_1/Z3 vdd 2.26fF +C2406 divider_0/prescaler_0/tspc_1/Z2 vdd 1.48fF +C2407 divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF +C2408 divider_0/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING +C2409 divider_0/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING +C2410 divider_0/prescaler_0/tspc_0/Z4 vdd 0.86fF +C2411 divider_0/prescaler_0/tspc_0/Z3 vdd 2.26fF +C2412 divider_0/prescaler_0/tspc_0/Z2 vdd 1.46fF +C2413 divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF +C2414 divider_0/prescaler_0/tspc_0/a_630_n680# vdd 1.14fF **FLOATING +C2415 divider_0/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING +C2416 divider_0/nor_1/Z1 vdd 1.34fF +C2417 divider_0/nor_0/Z1 vdd 1.34fF +C2418 divider_0/mc2 vdd 5.29fF +C2419 divbuf_7/OUT vdd 363.82fF +C2420 divbuf_7/OUT5 vdd 350.37fF +C2421 divbuf_7/OUT4 vdd 133.72fF +C2422 divbuf_7/OUT3 vdd 34.03fF +C2423 divbuf_7/OUT2 vdd 8.71fF +C2424 divbuf_7/IN vdd 0.89fF +C2425 divbuf_7/a_492_n240# vdd 2.46fF **FLOATING +C2426 divbuf_6/OUT vdd 363.82fF +C2427 divbuf_6/OUT5 vdd 350.37fF +C2428 divbuf_6/OUT4 vdd 133.72fF +C2429 divbuf_6/OUT3 vdd 34.03fF +C2430 divbuf_6/OUT2 vdd 8.71fF +C2431 divbuf_6/IN vdd 0.89fF +C2432 divbuf_6/a_492_n240# vdd 2.46fF **FLOATING +C2433 divbuf_5/OUT vdd 363.82fF +C2434 divbuf_5/OUT5 vdd 350.37fF +C2435 divbuf_5/OUT4 vdd 133.72fF +C2436 divbuf_5/OUT3 vdd 34.03fF +C2437 divbuf_5/OUT2 vdd 8.71fF +C2438 divbuf_5/IN vdd 0.89fF +C2439 divbuf_5/a_492_n240# vdd 2.46fF **FLOATING +C2440 divbuf_4/OUT vdd 363.82fF +C2441 divbuf_4/OUT5 vdd 350.37fF +C2442 divbuf_4/OUT4 vdd 133.72fF +C2443 divbuf_4/OUT3 vdd 34.03fF +C2444 divbuf_4/OUT2 vdd 8.71fF +C2445 divbuf_4/IN vdd 0.89fF +C2446 divbuf_4/a_492_n240# vdd 2.46fF **FLOATING +C2447 divbuf_3/OUT vdd 363.82fF +C2448 divbuf_3/OUT5 vdd 350.37fF +C2449 divbuf_3/OUT4 vdd 133.72fF +C2450 divbuf_3/OUT3 vdd 34.03fF +C2451 divbuf_3/OUT2 vdd 8.71fF +C2452 divbuf_3/IN vdd 0.89fF +C2453 divbuf_3/a_492_n240# vdd 2.46fF **FLOATING +C2454 divbuf_2/OUT vdd 363.82fF +C2455 divbuf_2/OUT5 vdd 350.37fF +C2456 divbuf_2/OUT4 vdd 133.72fF +C2457 divbuf_2/OUT3 vdd 34.03fF +C2458 divbuf_2/OUT2 vdd 8.71fF +C2459 divbuf_2/IN vdd 0.89fF +C2460 divbuf_2/a_492_n240# vdd 2.46fF **FLOATING +C2461 divbuf_1/OUT vdd 363.82fF +C2462 divbuf_1/OUT5 vdd 350.37fF +C2463 divbuf_1/OUT4 vdd 133.72fF +C2464 divbuf_1/OUT3 vdd 34.03fF +C2465 divbuf_1/OUT2 vdd 8.71fF +C2466 divbuf_1/IN vdd 0.89fF +C2467 divbuf_1/a_492_n240# vdd 2.46fF **FLOATING +C2468 ro_complete_1/cbank_2/v vdd 17.84fF +C2469 ro_complete_1/cbank_2/switch_5/vin vdd 0.78fF +C2470 ro_complete_1/cbank_2/switch_4/vin vdd 1.50fF +C2471 ro_complete_1/cbank_2/switch_2/vin vdd 1.30fF +C2472 ro_complete_1/cbank_2/switch_3/vin vdd 0.56fF +C2473 ro_complete_1/cbank_2/switch_1/vin vdd 1.14fF +C2474 ro_complete_1/cbank_2/switch_0/vin vdd 1.02fF +C2475 ro_complete_1/cbank_1/v vdd 16.34fF +C2476 ro_complete_1/cbank_1/switch_5/vin vdd 0.78fF +C2477 ro_complete_1/a0 vdd 7.88fF +C2478 ro_complete_1/cbank_1/switch_4/vin vdd 1.50fF +C2479 ro_complete_1/a1 vdd 5.39fF +C2480 ro_complete_1/cbank_1/switch_2/vin vdd 1.30fF +C2481 ro_complete_1/a3 vdd 6.85fF +C2482 ro_complete_1/cbank_1/switch_3/vin vdd 0.56fF +C2483 ro_complete_1/a2 vdd 5.48fF +C2484 ro_complete_1/cbank_1/switch_1/vin vdd 1.14fF +C2485 ro_complete_1/a4 vdd 5.36fF +C2486 ro_complete_1/cbank_1/switch_0/vin vdd 1.02fF +C2487 ro_complete_1/a5 vdd 5.19fF +C2488 ro_complete_1/cbank_0/v vdd 14.98fF +C2489 ro_complete_1/cbank_0/switch_5/vin vdd 0.78fF +C2490 ro_complete_1/cbank_0/switch_4/vin vdd 1.50fF +C2491 ro_complete_1/cbank_0/switch_2/vin vdd 1.30fF +C2492 ro_complete_1/cbank_0/switch_3/vin vdd 0.56fF +C2493 ro_complete_1/cbank_0/switch_1/vin vdd 1.14fF +C2494 ro_complete_1/cbank_0/switch_0/vin vdd 1.02fF +C2495 ro_complete_1/ro_var_extend_0/vcont vdd 0.27fF +C2496 divbuf_0/OUT vdd 363.82fF +C2497 divbuf_0/OUT5 vdd 350.37fF +C2498 divbuf_0/OUT4 vdd 133.72fF +C2499 divbuf_0/OUT3 vdd 34.03fF +C2500 divbuf_0/OUT2 vdd 8.71fF +C2501 divbuf_0/IN vdd 0.89fF +C2502 divbuf_0/a_492_n240# vdd 2.46fF **FLOATING +C2503 ro_complete_0/cbank_2/v vdd 17.84fF +C2504 ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF +C2505 ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF +C2506 ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF +C2507 ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF +C2508 ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF +C2509 ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF +C2510 ro_complete_0/cbank_1/v vdd 16.34fF +C2511 ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF +C2512 ro_complete_0/a0 vdd 7.88fF +C2513 ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF +C2514 ro_complete_0/a1 vdd 5.39fF +C2515 ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF +C2516 ro_complete_0/a3 vdd 6.85fF +C2517 ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF +C2518 ro_complete_0/a2 vdd 5.48fF +C2519 ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF +C2520 ro_complete_0/a4 vdd 5.36fF +C2521 ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF +C2522 ro_complete_0/a5 vdd 5.19fF +C2523 ro_complete_0/cbank_0/v vdd 14.98fF +C2524 ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF +C2525 ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF +C2526 ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF +C2527 ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF +C2528 ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF +C2529 ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF +C2530 ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF +C2531 filter_0/v vdd 85.69fF +C2532 filter_0/a_4216_n5230# vdd 418.47fF **FLOATING +C2533 filter_0/a_4216_n2998# vdd 1.03fF **FLOATING +C2534 pd_2/and_pd_0/Z1 vdd 0.39fF +C2535 pd_2/and_pd_0/Out1 vdd 2.22fF +C2536 pd_2/tspc_r_1/z5 vdd 1.10fF +C2537 pd_2/tspc_r_1/Z4 vdd 1.07fF +C2538 pd_2/tspc_r_1/Qbar vdd 0.88fF +C2539 pd_2/tspc_r_1/Z2 vdd 1.22fF +C2540 pd_2/tspc_r_1/Z1 vdd 0.67fF +C2541 pd_2/UP vdd 2.21fF +C2542 pd_2/tspc_r_1/Qbar1 vdd 1.34fF +C2543 pd_2/tspc_r_1/Z3 vdd 2.12fF +C2544 pd_2/REF vdd 1.80fF +C2545 pd_2/tspc_r_0/z5 vdd 1.10fF +C2546 pd_2/tspc_r_0/Z4 vdd 1.07fF +C2547 pd_2/R vdd 3.05fF +C2548 pd_2/tspc_r_0/Qbar vdd 0.79fF +C2549 pd_2/tspc_r_0/Z2 vdd 1.22fF +C2550 pd_2/tspc_r_0/Z1 vdd 0.67fF +C2551 pd_2/DOWN vdd 3.08fF +C2552 pd_2/tspc_r_0/Qbar1 vdd 1.34fF +C2553 pd_2/tspc_r_0/Z3 vdd 2.12fF +C2554 pd_2/DIV vdd 1.82fF +C2555 cp_0/down vdd 1.54fF +C2556 cp_0/vbias vdd 2.41fF +C2557 cp_0/out vdd 5.26fF +C2558 cp_0/upbar vdd 1.50fF +C2559 cp_0/a_7110_n2840# vdd 0.17fF **FLOATING +C2560 cp_0/a_3060_n2840# vdd 1.71fF **FLOATING +C2561 cp_0/a_7110_0# vdd 0.17fF **FLOATING +C2562 cp_0/a_6370_0# vdd 0.40fF **FLOATING +C2563 cp_0/a_3060_0# vdd 1.65fF **FLOATING +C2564 cp_0/a_1710_0# vdd 5.76fF **FLOATING +C2565 cp_0/a_1710_n2840# vdd 4.89fF **FLOATING +C2566 cp_0/a_10_n50# vdd 2.96fF **FLOATING +C2567 pd_1/and_pd_0/Z1 vdd 0.39fF +C2568 pd_1/and_pd_0/Out1 vdd 2.22fF +C2569 pd_1/tspc_r_1/z5 vdd 1.10fF +C2570 pd_1/tspc_r_1/Z4 vdd 1.07fF +C2571 pd_1/tspc_r_1/Qbar vdd 0.88fF +C2572 pd_1/tspc_r_1/Z2 vdd 1.22fF +C2573 pd_1/tspc_r_1/Z1 vdd 0.67fF +C2574 pd_1/UP vdd 2.21fF +C2575 pd_1/tspc_r_1/Qbar1 vdd 1.34fF +C2576 pd_1/tspc_r_1/Z3 vdd 2.12fF +C2577 pd_1/REF vdd 1.80fF +C2578 pd_1/tspc_r_0/z5 vdd 1.10fF +C2579 pd_1/tspc_r_0/Z4 vdd 1.07fF +C2580 pd_1/R vdd 3.05fF +C2581 pd_1/tspc_r_0/Qbar vdd 0.79fF +C2582 pd_1/tspc_r_0/Z2 vdd 1.22fF +C2583 pd_1/tspc_r_0/Z1 vdd 0.67fF +C2584 pd_1/DOWN vdd 3.08fF +C2585 pd_1/tspc_r_0/Qbar1 vdd 1.34fF +C2586 pd_1/tspc_r_0/Z3 vdd 2.12fF +C2587 pd_1/DIV vdd 1.82fF +C2588 pd_0/and_pd_0/Z1 vdd 0.39fF +C2589 pd_0/and_pd_0/Out1 vdd 2.22fF +C2590 pd_0/tspc_r_1/z5 vdd 1.10fF +C2591 pd_0/tspc_r_1/Z4 vdd 1.07fF +C2592 pd_0/tspc_r_1/Qbar vdd 0.88fF +C2593 pd_0/tspc_r_1/Z2 vdd 1.22fF +C2594 pd_0/tspc_r_1/Z1 vdd 0.67fF +C2595 pd_0/UP vdd 2.21fF +C2596 pd_0/tspc_r_1/Qbar1 vdd 1.34fF +C2597 pd_0/tspc_r_1/Z3 vdd 2.12fF +C2598 pd_0/REF vdd 1.80fF +C2599 pd_0/tspc_r_0/z5 vdd 1.10fF +C2600 pd_0/tspc_r_0/Z4 vdd 1.07fF +C2601 pd_0/R vdd 3.05fF +C2602 pd_0/tspc_r_0/Qbar vdd 0.79fF +C2603 pd_0/tspc_r_0/Z2 vdd 1.22fF +C2604 pd_0/tspc_r_0/Z1 vdd 0.67fF +C2605 pd_0/DOWN vdd 3.08fF +C2606 pd_0/tspc_r_0/Qbar1 vdd 1.34fF +C2607 pd_0/tspc_r_0/Z3 vdd 2.12fF +C2608 pd_0/DIV vdd 1.82fF .ends