pin extension
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds index 072b453..7ef325e 100644 --- a/gds/user_analog_project_wrapper.gds +++ b/gds/user_analog_project_wrapper.gds Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag index 18b6423..19a717e 100644 --- a/mag/user_analog_project_wrapper.mag +++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@ magic tech sky130A -timestamp 1642892036 +timestamp 1642892719 << metal2 >> rect 262 -400 318 240 rect 853 -400 909 240 @@ -531,22 +531,46 @@ rect 260451 349303 262487 351170 rect 283297 351150 285797 352400 rect 283588 349206 285624 351150 -rect -400 340121 850 342621 -rect 291150 338992 292400 341492 -rect -400 321921 830 324321 -rect 291170 319892 292400 322292 -rect -400 316921 830 319321 -rect 291170 314892 292400 317292 +rect -400 342364 850 342621 +rect -400 340471 4906 342364 +rect 291150 341209 292400 341492 +rect -400 340121 850 340471 +rect 287117 339172 292400 341209 +rect 291150 338992 292400 339172 +rect -400 324049 830 324321 +rect -400 322156 4976 324049 +rect -400 321921 830 322156 +rect 291170 322092 292400 322292 +rect 287015 320055 292400 322092 +rect 291170 319892 292400 320055 +rect -400 319125 830 319321 +rect -400 317232 4906 319125 +rect -400 316921 830 317232 +rect 291170 317127 292400 317292 +rect 287114 315090 292400 317127 +rect 291170 314892 292400 315090 rect 291760 294736 292400 294792 rect 291760 294145 292400 294201 rect 291760 293554 292400 293610 rect 291760 292963 292400 293019 -rect 291760 292372 292400 292428 -rect 291760 291781 292400 291837 -rect -400 279721 830 282121 -rect -400 274721 830 277121 -rect 291170 275281 292400 277681 -rect 291170 270281 292400 272681 +rect 287531 292428 291858 292545 +rect 287531 292372 292400 292428 +rect 287531 292267 291858 292372 +rect 287523 291837 291850 291977 +rect 287523 291781 292400 291837 +rect 287523 291699 291850 291781 +rect -400 281893 830 282121 +rect -400 280000 4941 281893 +rect -400 279721 830 280000 +rect 291170 277424 292400 277681 +rect -400 276863 830 277121 +rect -400 274970 4906 276863 +rect 287005 275531 292400 277424 +rect 291170 275281 292400 275531 +rect -400 274721 830 274970 +rect 291170 272430 292400 272681 +rect 286997 270537 292400 272430 +rect 291170 270281 292400 270537 rect -400 255765 240 255821 rect -400 255174 240 255230 rect -400 254583 240 254639 @@ -627,14 +651,26 @@ rect -400 123244 240 123300 rect 291170 117615 292400 120015 rect 291170 112615 292400 115015 -rect -400 107444 830 109844 -rect -400 102444 830 104844 +rect -400 109532 830 109844 +rect -400 107639 4916 109532 +rect -400 107444 830 107639 +rect -400 104575 830 104844 +rect -400 102682 4916 104575 +rect -400 102444 830 102682 rect 291170 95715 292400 98115 rect 291170 90715 292400 93115 -rect -400 86444 830 88844 -rect -400 81444 830 83844 -rect 291170 73415 292400 75815 -rect 291170 68415 292400 70815 +rect -400 88533 830 88844 +rect -400 86640 4920 88533 +rect -400 86444 830 86640 +rect -400 83589 830 83844 +rect -400 81696 4990 83589 +rect -400 81444 830 81696 +rect 291170 75549 292400 75815 +rect 287122 73656 292400 75549 +rect 291170 73415 292400 73656 +rect 291170 70535 292400 70815 +rect 287095 68642 292400 70535 +rect 291170 68415 292400 68642 rect -400 62388 240 62444 rect -400 61797 240 61853 rect -400 61206 240 61262 @@ -738,6 +774,10 @@ timestamp 1642811703 transform 1 0 103126 0 1 258815 box -215 -855 1685 810 +use filter filter_0 +timestamp 1640983258 +transform 1 0 77692 0 1 317254 +box -1800 -11005 6240 390 use divider divider_0 timestamp 1642812614 transform 1 0 166638 0 1 265093 @@ -746,10 +786,6 @@ timestamp 1641017053 transform 1 0 245779 0 1 306691 box -460 -1085 31200 495 -use filter filter_0 -timestamp 1640983258 -transform 1 0 77692 0 1 317254 -box -1800 -11005 6240 390 use divbuf divbuf_6 timestamp 1641017053 transform 1 0 245858 0 1 309157
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice index 561133c..1ec0b28 100644 --- a/netgen/user_analog_project_wrapper.spice +++ b/netgen/user_analog_project_wrapper.spice
@@ -106,856 +106,856 @@ + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] + wbs_stb_i wbs_we_i -C0 divider_0/nor_1/A divider_0/tspc_0/Q 0.55fF -C1 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF -C2 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF -C3 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF -C4 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF -C5 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF -C6 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF -C7 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C8 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF -C9 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF -C10 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF -C11 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF -C12 divbuf_0/OUT5 divbuf_0/OUT4 20.26fF -C13 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF -C14 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF -C15 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF -C16 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF -C17 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF -C18 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF -C19 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF -C20 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF -C21 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C22 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF -C23 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF -C24 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF -C25 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.01fF -C26 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF -C27 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF -C28 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF -C29 divbuf_1/OUT2 divbuf_1/OUT 0.06fF -C30 divbuf_1/OUT3 divbuf_1/OUT5 0.01fF -C31 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF -C32 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF -C33 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF -C34 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF -C35 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF -C36 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C37 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF -C38 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF -C39 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF -C40 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C41 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C42 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF -C43 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF -C44 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF -C45 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF -C46 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF -C47 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF -C48 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF -C49 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF -C50 divbuf_6/OUT5 divbuf_6/OUT 43.38fF -C51 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF -C52 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF -C53 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF -C54 cp_0/a_1710_0# cp_0/out 0.84fF -C55 pd_0/R pd_0/and_pd_0/Out1 0.33fF -C56 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF -C57 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF -C58 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF -C59 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF -C60 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF -C61 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF -C62 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF -C63 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF -C64 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF -C65 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/R 0.33fF -C66 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF -C67 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF -C68 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C69 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF -C70 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF -C71 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF -C72 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF -C73 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF -C74 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF -C75 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF -C76 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C77 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF -C78 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF -C79 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C80 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C81 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/Out 0.11fF -C82 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF -C83 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF -C84 pd_0/R pd_0/tspc_r_1/Z2 0.21fF -C85 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF -C86 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF -C87 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF -C88 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C89 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF -C90 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF -C91 divbuf_7/IN divbuf_7/OUT5 0.00fF -C92 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF -C93 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z3 0.38fF -C94 pd_0/UP pd_0/and_pd_0/Z1 0.06fF -C95 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF -C96 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF -C97 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF -C98 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF -C99 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF -C100 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C101 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.20fF -C102 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_1/A 1.21fF -C103 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF -C104 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF -C105 divbuf_1/OUT4 divbuf_1/OUT 1.11fF -C106 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z2 0.19fF -C107 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C108 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF -C109 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF -C110 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF -C111 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF -C112 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF -C113 divbuf_0/OUT5 divbuf_0/OUT 43.38fF -C114 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF -C115 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF -C116 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF -C117 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C118 divider_0/prescaler_0/Out divider_0/tspc_0/a_630_n680# 0.01fF -C119 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C120 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF -C121 cp_0/a_1710_0# cp_0/down 0.32fF -C122 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF -C123 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF -C124 io_clamp_low[2] io_analog[6] 0.53fF -C125 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF -C126 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z2 0.30fF -C127 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C128 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF -C129 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF -C130 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF -C131 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF -C132 divider_0/prescaler_0/Out divider_0/clk 0.51fF -C133 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF -C134 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF -C135 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C136 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF -C137 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF -C138 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF -C139 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF -C140 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF -C141 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C142 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF -C143 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C144 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C145 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF -C146 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF -C147 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF -C148 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF -C149 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF -C150 divbuf_0/OUT5 divbuf_0/IN 0.00fF -C151 divbuf_0/OUT2 divbuf_0/OUT3 1.37fF -C152 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C153 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF -C154 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF -C155 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF -C156 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C157 divider_0/and_0/OUT divider_0/and_0/B 0.01fF -C158 divbuf_7/OUT2 divbuf_7/OUT 0.06fF -C159 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF -C160 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z1 0.03fF -C161 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF -C162 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF -C163 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF -C164 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF -C165 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF -C166 divider_0/nor_0/B divider_0/Out 0.22fF -C167 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF -C168 cp_0/a_1710_n2840# cp_0/out 0.61fF -C169 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF -C170 divider_0/mc2 divider_0/and_0/out1 0.06fF -C171 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C172 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_1/A 0.01fF -C173 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF -C174 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF -C175 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.15fF -C176 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF -C177 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C178 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF -C179 pll_full_0/pd_0/DIV pll_full_0/pd_0/R 0.51fF -C180 divbuf_2/OUT3 divbuf_2/OUT 0.26fF -C181 divbuf_5/OUT3 divbuf_5/OUT 0.26fF -C182 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF -C183 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF -C184 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF -C185 divider_0/mc2 divider_0/nor_1/A 0.04fF -C186 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF -C187 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C188 divider_0/prescaler_0/Out divider_0/nor_1/A 0.15fF -C189 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C190 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF -C191 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF -C192 pd_0/UP pd_0/tspc_r_1/z5 0.03fF -C193 pll_full_0/divbuf_1/OUT5 pll_full_0/pd_0/REF 0.00fF -C194 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF -C195 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C196 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF -C197 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C198 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF -C199 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C200 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF -C201 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF -C202 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF -C203 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C204 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF -C205 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF -C206 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF -C207 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF -C208 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C209 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C210 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF -C211 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF -C212 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C213 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C214 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C215 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF -C216 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF -C217 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF -C218 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF -C219 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF -C220 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C221 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF -C222 cp_0/upbar cp_0/a_1710_n2840# 0.29fF -C223 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF -C224 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF -C225 divider_0/mc2 divider_0/nor_1/B 0.06fF -C226 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C227 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF -C228 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF -C229 divbuf_7/OUT4 divbuf_7/OUT 1.11fF -C230 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.05fF -C231 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF -C232 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF -C233 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF -C234 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF -C235 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF -C236 divider_0/mc2 divider_0/and_0/A 0.16fF -C237 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF -C238 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF -C239 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C240 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF -C241 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C242 divbuf_2/OUT5 divbuf_2/OUT 43.38fF -C243 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF -C244 divbuf_5/OUT5 divbuf_5/OUT 43.38fF -C245 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF -C246 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF -C247 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF -C248 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C249 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C250 divider_0/prescaler_0/Out divider_0/tspc_0/Z2 0.11fF -C251 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C252 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF -C253 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF -C254 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF -C255 io_clamp_low[2] io_clamp_high[2] 0.53fF -C256 cp_0/a_10_n50# cp_0/vbias 0.19fF -C257 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF -C258 io_clamp_high[1] io_analog[5] 0.53fF -C259 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF -C260 divider_0/mc2 divider_0/nor_0/B 0.15fF -C261 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF -C262 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF -C263 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C264 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C265 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C266 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF -C267 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divbuf_0/IN 0.05fF -C268 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Z3 0.03fF -C269 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF -C270 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C271 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF -C272 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF -C273 pd_0/DOWN pd_0/R 0.36fF -C274 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF -C275 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF -C276 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF -C277 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF -C278 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C279 divbuf_6/IN divbuf_6/OUT5 0.00fF -C280 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF -C281 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C282 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/Out 0.19fF -C283 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF -C284 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF -C285 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF -C286 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF -C287 divbuf_2/a_492_n240# divbuf_2/OUT5 0.01fF -C288 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF -C289 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C290 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF -C291 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF -C292 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C293 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF -C294 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF -C295 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF -C296 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.26fF -C297 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C298 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF -C299 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/UP 0.06fF -C300 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF -C301 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF -C302 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF -C303 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF -C304 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF -C305 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF -C306 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C307 divider_0/mc2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF -C308 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C309 divider_0/nor_1/A divider_0/tspc_0/Z1 0.03fF -C310 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF -C311 filter_0/a_4216_n2998# filter_0/v 0.31fF -C312 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/R 0.01fF -C313 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF -C314 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF -C315 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.45fF -C316 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF -C317 pd_0/R pd_0/tspc_r_1/Z3 0.29fF -C318 divbuf_0/OUT divbuf_0/OUT2 0.06fF -C319 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF -C320 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF -C321 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF -C322 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C323 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.32fF -C324 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF -C325 divbuf_1/OUT5 divbuf_1/IN 0.00fF -C326 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF -C327 io_clamp_low[0] io_analog[4] 0.53fF -C328 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF -C329 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF -C330 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C331 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF -C332 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z3 0.09fF -C333 divider_0/and_0/out1 divider_0/and_0/B 0.18fF -C334 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF -C335 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C336 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C337 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF -C338 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF -C339 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF -C340 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF -C341 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF -C342 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF -C343 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C344 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C345 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF -C346 divbuf_6/OUT2 divbuf_6/OUT 0.06fF -C347 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF -C348 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C349 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF -C350 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF -C351 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF -C352 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/DOWN 0.07fF -C353 divider_0/nor_1/A divider_0/and_0/B 0.08fF -C354 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF -C355 divbuf_3/OUT3 divbuf_3/OUT 0.26fF -C356 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF -C357 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C358 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF -C359 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/A 0.55fF -C360 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF -C361 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF -C362 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF -C363 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF -C364 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF -C365 divbuf_4/OUT3 divbuf_4/OUT 0.26fF -C366 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF -C367 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF -C368 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z2 0.11fF -C369 divider_0/nor_1/A divider_0/tspc_0/Z3 0.38fF -C370 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF -C371 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF -C372 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF -C373 filter_0/a_4216_n5230# filter_0/v 0.19fF -C374 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF -C375 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF -C376 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF -C377 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF -C378 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C379 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF -C380 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF -C381 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF -C382 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF -C383 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/and_pd_0/Out1 0.18fF -C384 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF -C385 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF -C386 pd_0/R pd_0/UP 0.45fF -C387 divbuf_0/OUT divbuf_0/OUT3 0.26fF -C388 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF -C389 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C390 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF -C391 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF -C392 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF -C393 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/Out 0.15fF -C394 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.64fF -C395 io_clamp_low[1] io_clamp_high[1] 0.53fF -C396 divider_0/nor_1/B divider_0/and_0/B 0.31fF -C397 pd_0/UP pd_0/and_pd_0/Out1 0.33fF -C398 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF -C399 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C400 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/A 0.03fF -C401 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C402 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF -C403 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/UP 0.33fF -C404 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF -C405 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF -C406 divider_0/and_0/A divider_0/and_0/B 0.18fF -C407 divbuf_1/OUT2 divbuf_1/OUT5 0.02fF -C408 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF -C409 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF -C410 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C411 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF -C412 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C413 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z3 0.65fF -C414 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C415 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C416 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF -C417 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF -C418 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF -C419 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF -C420 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF -C421 divbuf_6/OUT4 divbuf_6/OUT 1.11fF -C422 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF -C423 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF -C424 divider_0/and_0/OUT divider_0/clk 0.04fF -C425 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF -C426 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C427 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF -C428 divbuf_3/OUT5 divbuf_3/OUT 43.38fF -C429 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF -C430 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF -C431 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF -C432 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF -C433 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF -C434 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF -C435 divider_0/nor_0/B divider_0/and_0/B 0.29fF -C436 divbuf_4/OUT5 divbuf_4/OUT 43.38fF -C437 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF -C438 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF -C439 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_0/D 0.16fF -C440 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.05fF -C441 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF -C442 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF -C443 divider_0/nor_1/A divider_0/tspc_0/Z4 0.21fF -C444 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF -C445 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF -C446 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C447 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF -C448 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF -C449 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C450 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF -C451 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF -C452 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF -C453 divbuf_0/OUT divbuf_0/OUT4 1.11fF -C454 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF -C455 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF -C456 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C457 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF -C458 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF -C459 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF -C460 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF -C461 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF -C462 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z2 0.23fF -C463 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF -C464 cp_0/upbar cp_0/down 0.02fF -C465 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/DOWN 0.12fF -C466 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF -C467 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF -C468 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF -C469 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C470 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF -C471 divbuf_1/OUT3 divbuf_1/OUT 0.26fF -C472 divbuf_1/OUT4 divbuf_1/OUT5 20.26fF -C473 divbuf_2/OUT5 divbuf_2/IN 0.00fF -C474 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF -C475 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF -C476 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF -C477 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.44fF -C478 divbuf_5/IN divbuf_5/OUT5 0.00fF -C479 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF -C480 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C481 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF -C482 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF -C483 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF -C484 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF -C485 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF -C486 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF -C487 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF -C488 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF -C489 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C490 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C491 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF -C492 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF -C493 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF -C494 pd_0/REF pd_0/tspc_r_1/z5 0.04fF -C495 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF -C496 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF -C497 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF -C498 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C499 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF -C500 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF -C501 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF -C502 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF -C503 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF -C504 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/clk 0.05fF -C505 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF -C506 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/A 0.15fF -C507 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C508 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF -C509 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF -C510 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF -C511 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF -C512 divider_0/tspc_0/Z3 divider_0/tspc_0/Q 0.05fF -C513 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF -C514 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF -C515 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF -C516 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C517 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF -C518 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C519 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C520 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF -C521 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF -C522 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF -C523 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF -C524 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF -C525 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF -C526 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF -C527 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF -C528 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF -C529 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF -C530 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF -C531 io_clamp_low[0] io_clamp_high[0] 0.53fF -C532 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF -C533 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF -C534 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF -C535 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF -C536 divbuf_2/a_492_n240# divbuf_2/IN 0.13fF -C537 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF -C538 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF -C539 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF -C540 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF -C541 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF -C542 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF -C543 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/tspc_r_1/Qbar 0.05fF -C544 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF -C545 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF -C546 divider_0/and_0/B divider_0/and_0/Z1 0.07fF -C547 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF -C548 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C549 divbuf_2/OUT2 divbuf_2/OUT 0.06fF -C550 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF -C551 divbuf_5/OUT2 divbuf_5/OUT 0.06fF -C552 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF -C553 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF -C554 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF -C555 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C556 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF -C557 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF -C558 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF -C559 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF -C560 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF -C561 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C562 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C563 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C564 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.01fF -C565 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.19fF -C566 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.14fF -C567 pd_0/R pd_0/and_pd_0/Z1 0.02fF -C568 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF -C569 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF -C570 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF -C571 io_clamp_high[2] io_analog[6] 0.53fF -C572 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C573 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C574 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z3 0.38fF -C575 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF -C576 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C577 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C578 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF -C579 pll_full_0/divider_0/nor_0/B pll_full_0/divbuf_0/IN 0.29fF -C580 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF -C581 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.29fF -C582 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF -C583 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF -C584 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C585 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C586 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C587 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF -C588 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF -C589 pd_0/DIV pd_0/R 0.51fF -C590 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF -C591 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C592 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF -C593 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF -C594 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C595 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C596 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF -C597 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF -C598 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF -C599 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF -C600 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF -C601 divbuf_2/a_492_n240# divbuf_2/OUT2 0.42fF -C602 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF -C603 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF -C604 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF -C605 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF -C606 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF -C607 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF -C608 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF -C609 divbuf_7/OUT3 divbuf_7/OUT 0.26fF -C610 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF -C611 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF -C612 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF -C613 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF -C614 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF -C615 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF -C616 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF -C617 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C618 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C619 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF -C620 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF -C621 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF -C622 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF -C623 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF -C624 divbuf_2/OUT4 divbuf_2/OUT 1.11fF -C625 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT2 1.37fF -C626 divbuf_5/OUT4 divbuf_5/OUT 1.11fF -C627 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C628 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C629 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF -C630 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF -C631 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF -C632 pd_0/DOWN pd_0/UP 0.46fF -C633 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF -C634 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF -C635 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF -C636 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C637 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C638 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C639 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF -C640 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.32fF -C641 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C642 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF -C643 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF -C644 io_clamp_low[1] io_analog[5] 0.53fF -C645 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF -C646 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C647 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C648 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF -C649 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF -C650 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF -C651 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF -C652 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/DIV 0.17fF -C653 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C654 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF -C655 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF -C656 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF -C657 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/A 0.35fF -C658 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C659 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C660 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C661 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF -C662 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF -C663 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF -C664 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF -C665 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.01fF -C666 divbuf_1/OUT5 divbuf_1/OUT 43.38fF -C667 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF -C668 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF -C669 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF -C670 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C671 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/Out 0.08fF -C672 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF -C673 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF -C674 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF -C675 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF -C676 divbuf_3/IN divbuf_3/OUT5 0.00fF -C677 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF -C678 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C679 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF -C680 divbuf_7/OUT5 divbuf_7/OUT 43.38fF -C681 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF -C682 divider_0/tspc_2/Z3 divider_0/Out 0.05fF -C683 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF -C684 divider_0/mc2 divider_0/and_0/B 0.20fF -C685 divbuf_4/IN divbuf_4/OUT5 0.00fF -C686 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C687 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C688 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF -C689 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF -C690 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF -C691 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF -C692 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C693 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF -C694 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/R 0.27fF -C695 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C696 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF -C697 divider_0/prescaler_0/tspc_1/Q divider_0/nor_1/A 0.03fF -C698 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF -C699 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF -C700 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF -C701 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF -C702 pd_0/R pd_0/REF 0.61fF -C703 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF -C704 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF -C705 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C706 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF -C707 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF -C708 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF -C709 divider_0/prescaler_0/Out divider_0/tspc_0/Z3 0.45fF -C710 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF -C711 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF -C712 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C713 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF -C714 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF -C715 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.04fF -C716 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C717 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF -C718 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF -C719 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF -C720 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C721 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.61fF -C722 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF -C723 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF -C724 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF -C725 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar1 0.11fF -C726 divider_0/and_0/out1 divider_0/and_0/A 0.01fF -C727 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF -C728 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF -C729 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C730 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/Out 0.12fF -C731 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C732 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C733 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF -C734 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF -C735 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF -C736 divider_0/nor_1/A divider_0/nor_1/B 1.21fF -C737 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF -C738 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF -C739 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF -C740 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF -C741 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C742 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF -C743 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF -C744 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF -C745 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF -C746 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF -C747 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/Out 0.11fF -C748 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF -C749 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF -C750 divider_0/nor_1/A divider_0/and_0/A 0.01fF -C751 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF -C752 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF -C753 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF -C754 divbuf_3/OUT2 divbuf_3/OUT 0.06fF -C755 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF -C756 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF -C757 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF -C758 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C759 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF -C760 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF -C761 divbuf_4/OUT2 divbuf_4/OUT 0.06fF -C762 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF -C763 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF -C764 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF -C765 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF -C766 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF -C767 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF -C768 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Q 0.04fF -C769 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF -C770 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF -C771 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF -C772 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF -C773 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF -C774 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF -C775 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF -C776 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF -C777 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF -C778 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF -C779 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF -C780 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF -C781 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF -C782 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF -C783 divider_0/prescaler_0/Out divider_0/tspc_0/Z4 0.12fF -C784 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF -C785 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF -C786 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C787 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF -C788 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF -C789 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF -C790 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/R 0.02fF -C791 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF -C792 divider_0/nor_1/B divider_0/and_0/A 0.26fF -C793 io_clamp_high[0] io_analog[4] 0.53fF -C794 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF -C795 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF -C796 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF -C797 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF -C798 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF -C799 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF -C800 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C801 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C802 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF -C803 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF -C804 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF -C805 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C806 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF -C807 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF -C808 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF -C809 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF -C810 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF -C811 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/Z3 0.05fF -C812 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C813 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C814 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.01fF -C815 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF -C816 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF -C817 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF -C818 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF -C819 divider_0/nor_1/A divider_0/tspc_1/Z2 0.15fF -C820 divider_0/tspc_0/Q divider_0/tspc_1/a_630_n680# 0.01fF -C821 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF -C822 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF -C823 divbuf_6/OUT3 divbuf_6/OUT 0.26fF -C824 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF -C825 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/B 0.22fF -C826 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C827 divider_0/mc2 divider_0/and_0/OUT 0.05fF -C828 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/Out 0.28fF -C829 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF -C830 divider_0/nor_1/B divider_0/nor_0/B 0.47fF -C831 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF -C832 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF -C833 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C834 divbuf_3/OUT4 divbuf_3/OUT 1.11fF -C835 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/A 0.21fF -C836 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C837 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF -C838 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF -C839 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF -C840 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/Out 0.91fF -C841 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF -C842 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C843 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C844 divbuf_4/OUT4 divbuf_4/OUT 1.11fF -C845 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C846 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF -C847 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF -C848 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z3 0.45fF -C849 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF +C0 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF +C1 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF +C2 io_clamp_low[0] io_clamp_high[0] 0.53fF +C3 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF +C4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF +C5 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C6 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF +C7 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C8 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF +C9 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF +C10 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF +C11 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF +C12 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF +C13 pd_0/DOWN pd_0/R 0.36fF +C14 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF +C15 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF +C16 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF +C17 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z3 0.27fF +C18 divider_0/nor_1/B divider_0/tspc_0/a_630_n680# 0.01fF +C19 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF +C20 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF +C21 divider_0/tspc_2/Z3 divider_0/Out 0.05fF +C22 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF +C23 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF +C24 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF +C25 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C26 pll_full_0/pd_0/REF pll_full_0/pd_0/R 0.61fF +C27 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF +C28 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF +C29 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF +C30 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF +C31 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF +C32 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF +C33 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C34 divider_0/and_0/A divider_0/and_0/B 0.18fF +C35 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C36 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF +C37 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C38 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C39 divbuf_5/IN divbuf_5/OUT5 0.00fF +C40 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.01fF +C41 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.19fF +C42 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.14fF +C43 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF +C44 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF +C45 io_clamp_high[2] io_analog[6] 0.53fF +C46 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF +C47 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z3 0.38fF +C48 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C49 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C50 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF +C51 pll_full_0/divider_0/nor_0/B pll_full_0/divbuf_0/IN 0.29fF +C52 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.29fF +C53 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF +C54 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF +C55 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF +C56 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF +C57 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF +C58 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C59 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C60 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C61 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF +C62 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF +C63 pd_0/R pd_0/tspc_r_1/Z3 0.29fF +C64 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF +C65 divbuf_0/OUT divbuf_0/OUT5 43.38fF +C66 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C67 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF +C68 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C69 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C70 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF +C71 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF +C72 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF +C73 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF +C74 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C75 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF +C76 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF +C77 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF +C78 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF +C79 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF +C80 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF +C81 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C82 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C83 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF +C84 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF +C85 pll_full_0/pd_0/R pll_full_0/pd_0/DOWN 0.36fF +C86 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF +C87 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF +C88 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF +C89 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF +C90 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF +C91 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF +C92 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C93 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C94 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF +C95 cp_0/a_10_n50# cp_0/vbias 0.19fF +C96 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF +C97 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF +C98 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF +C99 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF +C100 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C101 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C102 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C103 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF +C104 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.32fF +C105 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C106 divbuf_5/OUT2 divbuf_5/OUT 0.06fF +C107 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF +C108 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z1 0.09fF +C109 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF +C110 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF +C111 io_clamp_low[1] io_analog[5] 0.53fF +C112 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT5 0.01fF +C113 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF +C114 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C115 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C116 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF +C117 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF +C118 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF +C119 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF +C120 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF +C121 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C122 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C123 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C124 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DIV 0.65fF +C125 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF +C126 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF +C127 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/A 0.35fF +C128 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C129 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C130 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C131 divbuf_2/OUT5 divbuf_2/IN 0.00fF +C132 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF +C133 pd_0/R pd_0/UP 0.45fF +C134 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF +C135 divider_0/prescaler_0/Out divider_0/tspc_0/Z2 0.11fF +C136 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF +C137 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF +C138 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF +C139 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C140 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/Out 0.08fF +C141 pd_0/UP pd_0/and_pd_0/Out1 0.33fF +C142 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C143 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF +C144 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF +C145 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF +C146 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF +C147 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C148 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF +C149 divider_0/mc2 divider_0/nor_1/A 0.04fF +C150 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/Z2 0.14fF +C151 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF +C152 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF +C153 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C154 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF +C155 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF +C156 divbuf_7/OUT3 divbuf_7/OUT 0.26fF +C157 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF +C158 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF +C159 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Z3 0.38fF +C160 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF +C161 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF +C162 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF +C163 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF +C164 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF +C165 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF +C166 divider_0/tspc_0/Z4 divider_0/prescaler_0/Out 0.12fF +C167 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF +C168 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF +C169 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF +C170 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C171 divider_0/and_0/B divider_0/and_0/Z1 0.07fF +C172 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF +C173 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C174 divbuf_5/OUT4 divbuf_5/OUT 1.11fF +C175 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.04fF +C176 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C177 divider_0/tspc_0/Z4 divider_0/tspc_0/Z1 0.00fF +C178 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF +C179 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF +C180 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT4 20.26fF +C181 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C182 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF +C183 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C184 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF +C185 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF +C186 divbuf_1/OUT5 divbuf_1/OUT 43.38fF +C187 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF +C188 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF +C189 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/Out 0.12fF +C190 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C191 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C192 divbuf_2/OUT2 divbuf_2/OUT 0.06fF +C193 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF +C194 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF +C195 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF +C196 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF +C197 divbuf_0/OUT divbuf_0/OUT2 0.06fF +C198 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF +C199 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF +C200 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF +C201 divider_0/and_0/out1 divider_0/and_0/A 0.01fF +C202 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT5 43.38fF +C203 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C204 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C205 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF +C206 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF +C207 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF +C208 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF +C209 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF +C210 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/Out 0.11fF +C211 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF +C212 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C213 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF +C214 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF +C215 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C216 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF +C217 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT5 0.02fF +C218 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF +C219 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF +C220 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C221 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF +C222 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF +C223 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C224 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF +C225 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF +C226 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF +C227 divbuf_3/IN divbuf_3/OUT5 0.00fF +C228 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF +C229 divbuf_7/OUT5 divbuf_7/OUT 43.38fF +C230 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF +C231 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF +C232 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z3 0.25fF +C233 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF +C234 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.19fF +C235 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF +C236 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF +C237 divbuf_4/IN divbuf_4/OUT5 0.00fF +C238 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF +C239 pd_0/REF pd_0/tspc_r_1/z5 0.04fF +C240 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF +C241 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF +C242 pll_full_0/pd_0/R pll_full_0/pd_0/DIV 0.51fF +C243 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF +C244 divider_0/nor_1/B divider_0/nor_0/B 0.47fF +C245 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF +C246 divider_0/tspc_0/Q divider_0/tspc_0/Z3 0.05fF +C247 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF +C248 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF +C249 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF +C250 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF +C251 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C252 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF +C253 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF +C254 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF +C255 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF +C256 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF +C257 io_clamp_high[0] io_analog[4] 0.53fF +C258 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C259 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF +C260 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C261 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF +C262 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF +C263 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF +C264 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF +C265 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF +C266 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF +C267 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C268 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF +C269 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF +C270 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF +C271 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF +C272 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF +C273 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF +C274 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF +C275 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF +C276 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/Z3 0.05fF +C277 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C278 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C279 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.01fF +C280 divbuf_2/OUT4 divbuf_2/OUT 1.11fF +C281 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF +C282 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z3 0.11fF +C283 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF +C284 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF +C285 divider_0/mc2 divider_0/and_0/B 0.20fF +C286 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF +C287 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/B 0.22fF +C288 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C289 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/Out 0.28fF +C290 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF +C291 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF +C292 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF +C293 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF +C294 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF +C295 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF +C296 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF +C297 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF +C298 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF +C299 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/A 0.21fF +C300 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF +C301 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF +C302 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF +C303 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/Out 0.91fF +C304 divbuf_1/OUT divbuf_1/OUT3 0.26fF +C305 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF +C306 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF +C307 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF +C308 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF +C309 divbuf_3/OUT2 divbuf_3/OUT 0.06fF +C310 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF +C311 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C312 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z3 0.45fF +C313 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF +C314 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF +C315 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF +C316 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF +C317 divbuf_4/OUT2 divbuf_4/OUT 0.06fF +C318 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF +C319 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF +C320 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C321 cp_0/upbar cp_0/down 0.02fF +C322 pd_0/R pd_0/and_pd_0/Z1 0.02fF +C323 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF +C324 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF +C325 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF +C326 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF +C327 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF +C328 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF +C329 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF +C330 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF +C331 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C332 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF +C333 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF +C334 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF +C335 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF +C336 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C337 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF +C338 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF +C339 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF +C340 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF +C341 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.01fF +C342 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF +C343 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF +C344 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF +C345 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF +C346 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF +C347 pd_0/DIV pd_0/R 0.51fF +C348 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF +C349 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/DIV 0.17fF +C350 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF +C351 divider_0/nor_0/B divider_0/Out 0.22fF +C352 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF +C353 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C354 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF +C355 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF +C356 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF +C357 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DOWN 0.03fF +C358 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF +C359 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF +C360 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF +C361 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF +C362 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF +C363 divbuf_2/a_492_n240# divbuf_2/OUT5 0.01fF +C364 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF +C365 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF +C366 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF +C367 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.44fF +C368 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF +C369 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF +C370 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF +C371 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF +C372 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z2 0.21fF +C373 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF +C374 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF +C375 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF +C376 divider_0/nor_1/B divider_0/and_0/A 0.26fF +C377 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF +C378 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C379 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF +C380 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF +C381 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF +C382 divbuf_6/OUT3 divbuf_6/OUT 0.26fF +C383 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF +C384 divider_0/mc2 divider_0/and_0/OUT 0.05fF +C385 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF +C386 divider_0/nor_1/A divider_0/and_0/B 0.08fF +C387 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C388 divbuf_3/OUT4 divbuf_3/OUT 1.11fF +C389 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF +C390 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF +C391 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF +C392 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF +C393 pd_0/DOWN pd_0/UP 0.46fF +C394 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF +C395 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF +C396 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C397 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF +C398 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF +C399 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C400 divbuf_4/OUT4 divbuf_4/OUT 1.11fF +C401 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C402 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C403 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/Out 0.11fF +C404 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF +C405 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DIV 0.12fF +C406 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF +C407 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF +C408 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF +C409 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z3 0.38fF +C410 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF +C411 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF +C412 filter_0/a_4216_n2998# filter_0/v 0.31fF +C413 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/OUT5 0.01fF +C414 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF +C415 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF +C416 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF +C417 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF +C418 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF +C419 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF +C420 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C421 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.20fF +C422 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_1/A 1.21fF +C423 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF +C424 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF +C425 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF +C426 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF +C427 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF +C428 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF +C429 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF +C430 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF +C431 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C432 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF +C433 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF +C434 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF +C435 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF +C436 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF +C437 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF +C438 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF +C439 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF +C440 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF +C441 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF +C442 divider_0/tspc_0/Q divider_0/tspc_1/a_630_n680# 0.01fF +C443 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C444 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF +C445 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF +C446 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF +C447 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF +C448 io_clamp_low[2] io_analog[6] 0.53fF +C449 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C450 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z2 0.30fF +C451 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C452 divbuf_6/OUT5 divbuf_6/OUT 43.38fF +C453 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF +C454 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF +C455 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF +C456 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF +C457 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF +C458 divider_0/tspc_0/Z4 divider_0/tspc_0/a_630_n680# 0.12fF +C459 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C460 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF +C461 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z1 0.71fF +C462 divider_0/mc2 divider_0/and_0/out1 0.06fF +C463 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF +C464 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF +C465 pd_0/R pd_0/REF 0.61fF +C466 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C467 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C468 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF +C469 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C470 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C471 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/DIV 0.19fF +C472 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF +C473 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z1 0.03fF +C474 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF +C475 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF +C476 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF +C477 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF +C478 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF +C479 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF +C480 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF +C481 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF +C482 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C483 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF +C484 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF +C485 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C486 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.20fF +C487 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_1/A 0.01fF +C488 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF +C489 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF +C490 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.15fF +C491 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF +C492 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF +C493 divbuf_7/IN divbuf_7/OUT5 0.00fF +C494 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C495 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF +C496 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/DOWN 0.21fF +C497 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF +C498 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF +C499 divbuf_1/OUT5 divbuf_1/IN 0.00fF +C500 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C501 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF +C502 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF +C503 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C504 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/R 0.29fF +C505 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF +C506 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF +C507 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF +C508 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF +C509 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF +C510 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF +C511 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF +C512 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF +C513 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF +C514 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C515 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF +C516 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF +C517 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF +C518 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_0/switch_0/vin 0.09fF +C519 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DIV 0.04fF +C520 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF +C521 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF +C522 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF +C523 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF +C524 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF +C525 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C526 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF +C527 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF +C528 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF +C529 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF +C530 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF +C531 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF +C532 divbuf_2/a_492_n240# divbuf_2/IN 0.13fF +C533 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF +C534 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF +C535 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C536 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF +C537 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C538 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF +C539 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF +C540 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF +C541 divider_0/prescaler_0/Out divider_0/clk 0.51fF +C542 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF +C543 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF +C544 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF +C545 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C546 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF +C547 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF +C548 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF +C549 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C550 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C551 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF +C552 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.05fF +C553 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF +C554 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C555 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF +C556 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF +C557 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF +C558 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF +C559 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF +C560 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF +C561 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C562 divbuf_7/OUT2 divbuf_7/OUT 0.06fF +C563 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF +C564 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF +C565 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF +C566 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF +C567 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF +C568 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF +C569 divider_0/mc2 divider_0/nor_0/B 0.15fF +C570 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF +C571 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF +C572 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF +C573 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C574 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF +C575 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT5 0.01fF +C576 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C577 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C578 divbuf_5/OUT3 divbuf_5/OUT 0.26fF +C579 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF +C580 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF +C581 io_clamp_low[2] io_clamp_high[2] 0.53fF +C582 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF +C583 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_0/vin 0.19fF +C584 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF +C585 io_clamp_high[1] io_analog[5] 0.53fF +C586 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF +C587 pll_full_0/divbuf_1/OUT4 pll_full_0/divbuf_1/OUT5 20.26fF +C588 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C589 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C590 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF +C591 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF +C592 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divbuf_0/IN 0.05fF +C593 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF +C594 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF +C595 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_0/Z4 0.02fF +C596 divider_0/and_0/OUT divider_0/and_0/B 0.01fF +C597 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF +C598 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF +C599 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/OUT3 1.37fF +C600 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C601 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF +C602 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C603 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C604 divider_0/prescaler_0/Out divider_0/tspc_0/Z3 0.45fF +C605 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF +C606 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF +C607 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF +C608 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF +C609 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C610 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/Out 0.19fF +C611 divider_0/mc2 divider_0/nor_1/B 0.06fF +C612 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF +C613 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF +C614 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF +C615 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C616 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF +C617 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF +C618 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF +C619 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.61fF +C620 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.26fF +C621 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF +C622 filter_0/a_4216_n5230# filter_0/v 0.19fF +C623 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C624 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF +C625 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C626 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF +C627 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF +C628 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C629 divbuf_7/OUT4 divbuf_7/OUT 1.11fF +C630 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF +C631 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF +C632 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF +C633 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF +C634 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.45fF +C635 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF +C636 pd_0/R pd_0/and_pd_0/Out1 0.33fF +C637 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF +C638 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF +C639 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF +C640 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF +C641 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF +C642 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C643 divbuf_5/OUT5 divbuf_5/OUT 43.38fF +C644 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF +C645 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z4 0.04fF +C646 io_clamp_low[0] io_analog[4] 0.53fF +C647 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF +C648 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C649 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF +C650 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF +C651 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF +C652 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF +C653 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF +C654 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF +C655 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF +C656 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF +C657 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/OUT5 0.02fF +C658 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C659 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF +C660 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C661 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF +C662 divbuf_2/OUT3 divbuf_2/OUT 0.26fF +C663 pd_0/R pd_0/tspc_r_1/Z2 0.21fF +C664 divider_0/mc2 divider_0/and_0/A 0.16fF +C665 divbuf_2/a_492_n240# divbuf_2/OUT2 0.42fF +C666 divider_0/and_0/out1 divider_0/and_0/B 0.18fF +C667 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF +C668 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF +C669 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF +C670 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF +C671 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF +C672 pd_0/UP pd_0/and_pd_0/Z1 0.06fF +C673 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/OUT2 0.42fF +C674 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF +C675 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF +C676 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF +C677 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF +C678 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C679 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF +C680 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/A 0.55fF +C681 divbuf_6/IN divbuf_6/OUT5 0.00fF +C682 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF +C683 divbuf_1/OUT divbuf_1/OUT2 0.06fF +C684 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF +C685 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF +C686 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C687 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF +C688 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF +C689 divider_0/nor_1/A divider_0/tspc_0/Z3 0.38fF +C690 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF +C691 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF +C692 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF +C693 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF +C694 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z2 0.11fF +C695 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF +C696 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C697 divider_0/nor_1/B divider_0/nor_1/A 1.21fF +C698 divbuf_0/IN divbuf_0/OUT5 0.00fF +C699 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF +C700 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF +C701 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF +C702 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF +C703 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF +C704 divider_0/mc2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF +C705 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF +C706 divider_0/tspc_0/Z4 divider_0/tspc_0/Z3 0.65fF +C707 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF +C708 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF +C709 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF +C710 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF +C711 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/Out 0.15fF +C712 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.64fF +C713 io_clamp_low[1] io_clamp_high[1] 0.53fF +C714 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF +C715 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF +C716 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF +C717 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF +C718 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C719 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/A 0.03fF +C720 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C721 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF +C722 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF +C723 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF +C724 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF +C725 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF +C726 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF +C727 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF +C728 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF +C729 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF +C730 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF +C731 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF +C732 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF +C733 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C734 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z3 0.65fF +C735 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C736 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C737 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF +C738 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF +C739 divbuf_2/OUT5 divbuf_2/OUT 43.38fF +C740 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF +C741 cp_0/a_1710_0# cp_0/out 0.84fF +C742 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF +C743 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF +C744 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF +C745 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C746 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF +C747 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF +C748 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C749 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF +C750 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF +C751 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF +C752 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF +C753 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF +C754 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF +C755 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF +C756 divbuf_6/OUT2 divbuf_6/OUT 0.06fF +C757 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF +C758 divbuf_1/OUT divbuf_1/OUT4 1.11fF +C759 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF +C760 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C761 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF +C762 divider_0/nor_1/A divider_0/and_0/A 0.01fF +C763 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF +C764 divbuf_3/OUT3 divbuf_3/OUT 0.26fF +C765 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF +C766 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_0/D 0.16fF +C767 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.05fF +C768 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF +C769 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF +C770 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF +C771 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF +C772 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF +C773 divbuf_0/OUT divbuf_0/OUT3 0.26fF +C774 divider_0/nor_0/B divider_0/and_0/B 0.29fF +C775 divbuf_4/OUT3 divbuf_4/OUT 0.26fF +C776 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF +C777 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C778 pd_0/UP pd_0/tspc_r_1/z5 0.03fF +C779 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C780 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.32fF +C781 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z2 0.23fF +C782 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF +C783 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF +C784 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF +C785 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a2 0.09fF +C786 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF +C787 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF +C788 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF +C789 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF +C790 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF +C791 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF +C792 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF +C793 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF +C794 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF +C795 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF +C796 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF +C797 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF +C798 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF +C799 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C800 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF +C801 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C802 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF +C803 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF +C804 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF +C805 cp_0/upbar cp_0/a_1710_n2840# 0.29fF +C806 cp_0/a_1710_0# cp_0/down 0.32fF +C807 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF +C808 pll_full_0/divbuf_0/a_492_n240# pll_full_0/pd_0/DIV 0.00fF +C809 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF +C810 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF +C811 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF +C812 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF +C813 divbuf_0/OUT3 divbuf_0/OUT5 0.01fF +C814 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C815 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF +C816 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF +C817 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF +C818 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF +C819 divider_0/nor_1/B divider_0/and_0/B 0.31fF +C820 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF +C821 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF +C822 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF +C823 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C824 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF +C825 divbuf_6/OUT4 divbuf_6/OUT 1.11fF +C826 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF +C827 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF +C828 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF +C829 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/clk 0.05fF +C830 divbuf_1/a_492_n240# divbuf_1/OUT2 0.42fF +C831 pll_full_0/pd_0/REF pll_full_0/pd_0/DOWN 1.48fF +C832 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF +C833 divider_0/and_0/OUT divider_0/clk 0.04fF +C834 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/A 0.15fF +C835 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C836 divbuf_3/OUT5 divbuf_3/OUT 43.38fF +C837 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF +C838 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF +C839 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF +C840 divbuf_0/OUT divbuf_0/OUT4 1.11fF +C841 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C842 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C843 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C844 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF +C845 divbuf_4/OUT5 divbuf_4/OUT 43.38fF +C846 cp_0/a_1710_n2840# cp_0/out 0.61fF +C847 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF +C848 pll_full_0/pd_0/UP pll_full_0/pd_0/DOWN 4.58fF +C849 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF Xpd_0 VDD gnd pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd Xcp_0 cp_0/vbias vdd gnd cp_0/out cp_0/down cp_0/upbar cp Xfilter_0 gnd filter_0/v filter @@ -1042,11 +1042,11 @@ C910 io_in_3v3[21] vdd 0.61fF C911 gpio_noesd[14] vdd 0.61fF C912 gpio_analog[14] vdd 0.61fF -C913 vssa1 vdd 38.21fF -C914 vssd2 vdd 13.04fF +C913 vssa1 vdd 63.32fF +C914 vssd2 vdd 38.54fF C915 vssd1 vdd 13.04fF -C916 vdda2 vdd 13.04fF -C917 vdda1 vdd 26.08fF +C916 vdda2 vdd 38.30fF +C917 vdda1 vdd 51.85fF C918 io_oeb[20] vdd 0.61fF C919 io_out[20] vdd 0.61fF C920 io_in[20] vdd 0.61fF @@ -1125,17 +1125,17 @@ C993 io_in_3v3[14] vdd 0.61fF C994 gpio_noesd[7] vdd 0.61fF C995 gpio_analog[7] vdd 0.61fF -C996 vssa2 vdd 13.04fF -C997 gpio_analog[6] vdd 0.61fF -C998 gpio_noesd[6] vdd 0.61fF +C996 vssa2 vdd 38.35fF +C997 gpio_analog[6] vdd 5.71fF +C998 gpio_noesd[6] vdd 5.70fF C999 io_in_3v3[13] vdd 0.61fF C1000 io_in[13] vdd 0.61fF C1001 io_out[13] vdd 0.61fF C1002 io_oeb[13] vdd 0.61fF -C1003 vccd1 vdd 13.04fF -C1004 vccd2 vdd 13.04fF -C1005 io_analog[0] vdd 6.83fF -C1006 io_analog[10] vdd 6.83fF +C1003 vccd1 vdd 39.84fF +C1004 vccd2 vdd 38.46fF +C1005 io_analog[0] vdd 19.99fF +C1006 io_analog[10] vdd 19.36fF C1007 io_analog[1] vdd 13.17fF C1008 io_analog[2] vdd 12.57fF C1009 io_analog[3] vdd 12.83fF