vco+div+buffers
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index bde7dc3..57f4268 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -106,481 +106,481 @@
+ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
+ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
+ wbs_stb_i wbs_we_i
-C0 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C2 ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF
-C3 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF
-C4 ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C5 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF
-C6 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF
-C7 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/tspc_0/Z1 0.06fF
-C8 ro_div_new_0/divider_0/tspc_1/Z3 ro_div_new_0/divider_0/tspc_1/Z4 0.65fF
-C9 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 ro_div_new_0/divider_0/clk 0.12fF
-C10 divbuf_3/OUT divbuf_3/OUT3 0.26fF
-C11 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
-C12 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C13 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_0/Q 0.05fF
-C14 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/tspc_2/Z2 0.14fF
-C15 ro_div_new_0/divider_0/prescaler_0/tspc_0/Q ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.04fF
-C16 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C17 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF
-C18 divbuf_4/OUT2 divbuf_4/OUT 0.06fF
-C19 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF
-C20 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C21 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF
-C22 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C23 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/Out 0.22fF
-C24 ro_div_new_0/divider_0/tspc_2/Z1 ro_div_new_0/divider_0/tspc_2/Z3 0.06fF
-C25 ro_div_new_0/divider_0/tspc_1/Z2 ro_div_new_0/divider_0/tspc_1/Z4 0.36fF
-C26 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C27 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C28 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a2 0.09fF
-C29 ro_div_new_0/divider_0/and_0/out1 ro_div_new_0/divider_0/and_0/Z1 0.36fF
-C30 ro_div_new_0/ro_complete_0/cbank_1/switch_3/vin ro_div_new_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C31 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/switch_1/vin 0.19fF
-C32 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a2 0.14fF
-C33 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_2/Z4 0.02fF
-C34 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 ro_div_new_0/divider_0/prescaler_0/Out 0.11fF
-C35 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/clk 0.11fF
-C36 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF
-C37 ro_div_new_0/ro_complete_0/cbank_1/switch_1/vin ro_div_new_0/divider_0/clk 1.30fF
-C38 divbuf_0/OUT divbuf_0/OUT4 1.11fF
-C39 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF
-C40 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/tspc_0/Z4 0.65fF
-C41 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF
-C42 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
-C43 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.16fF
-C44 ro_div_new_0/divider_0/prescaler_0/Out ro_div_new_0/divider_0/clk 0.51fF
-C45 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C46 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/and_0/OUT 0.05fF
-C47 divbuf_6/OUT3 divbuf_6/OUT 0.26fF
-C48 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF
-C49 ro_div_new_0/divider_0/nor_0/Z1 ro_div_new_0/divider_0/and_0/B 0.78fF
-C50 ro_div_new_0/divider_0/prescaler_0/tspc_0/Q ro_div_new_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C51 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/clk 0.11fF
-C52 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 ro_div_new_0/divider_0/prescaler_0/Out 0.05fF
-C53 divbuf_2/OUT2 divbuf_2/OUT 0.06fF
-C54 divbuf_4/OUT4 divbuf_4/OUT 1.11fF
-C55 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C56 divbuf_1/OUT4 divbuf_1/OUT3 5.16fF
-C57 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF
-C58 ro_div_new_0/divider_0/tspc_2/Z1 ro_div_new_0/divider_0/tspc_2/Z4 0.00fF
-C59 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C60 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C61 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C62 io_clamp_high[1] io_analog[5] 0.53fF
-C63 ro_div_new_0/ro_complete_0/cbank_1/switch_1/vin ro_div_new_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C64 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF
-C65 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/and_0/OUT 0.05fF
-C66 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF
-C67 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 ro_div_new_0/divider_0/prescaler_0/Out 0.28fF
-C68 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF
-C69 ro_div_new_0/ro_complete_0/cbank_0/v ro_div_new_0/ro_complete_0/cbank_0/switch_0/vin 1.30fF
-C70 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
-C71 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C72 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/and_0/B 0.01fF
-C73 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/prescaler_0/Out 0.91fF
-C74 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF
-C75 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C76 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C77 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C78 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C79 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C80 ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF
-C81 ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C82 divbuf_6/OUT5 divbuf_6/OUT 43.38fF
-C83 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF
-C84 divbuf_0/OUT2 divbuf_0/OUT3 1.37fF
-C85 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF
-C86 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/prescaler_0/Out 0.15fF
-C87 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C88 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/clk 0.01fF
-C89 divbuf_2/a_492_n240# divbuf_2/OUT2 0.42fF
-C90 ro_complete_0/a5 ro_complete_0/cbank_0/switch_0/vin 0.09fF
-C91 ro_div_new_0/ro_complete_0/cbank_1/switch_4/vin ro_div_new_0/divider_0/clk 1.30fF
-C92 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/divider_0/clk 0.05fF
-C93 ro_div_new_0/divider_0/prescaler_0/tspc_2/D ro_div_new_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C94 divbuf_2/OUT3 divbuf_2/OUT 0.26fF
-C95 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF
-C96 ro_div_new_0/divider_0/tspc_2/Z3 ro_div_new_0/divider_0/tspc_2/Z4 0.65fF
-C97 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF
-C98 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF
-C99 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/nor_0/B 0.00fF
-C100 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C101 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C102 io_clamp_low[0] io_analog[4] 0.53fF
-C103 divbuf_7/IN divbuf_7/OUT5 0.00fF
-C104 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C105 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C106 divbuf_1/OUT4 divbuf_1/OUT 1.11fF
-C107 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF
-C108 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/tspc_0/Z2 0.23fF
-C109 ro_div_new_0/divider_0/tspc_0/Z4 ro_div_new_0/divider_0/tspc_0/Z1 0.00fF
-C110 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C111 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C112 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF
-C113 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/nor_1/A 0.35fF
-C114 ro_div_new_0/ro_complete_0/cbank_2/switch_0/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.44fF
-C115 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C116 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF
-C117 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF
-C118 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C119 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF
-C120 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF
-C121 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C122 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF
-C123 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C124 ro_div_new_0/ro_complete_0/cbank_0/switch_4/vin ro_div_new_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C125 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/clk 0.01fF
-C126 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF
-C127 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/nor_1/A 0.01fF
-C128 divbuf_2/OUT5 divbuf_2/OUT 43.38fF
-C129 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/tspc_1/Q 0.04fF
-C130 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/tspc_0/Q 0.55fF
-C131 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
-C132 ro_div_new_0/ro_complete_0/a5 ro_div_new_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C133 ro_div_new_0/ro_complete_0/cbank_1/switch_3/vin ro_div_new_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C134 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C135 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF
-C136 io_clamp_low[1] io_clamp_high[1] 0.53fF
-C137 divbuf_3/OUT divbuf_3/a_492_n240# 0.00fF
-C138 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF
-C139 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF
-C140 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C141 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C142 divbuf_7/OUT2 divbuf_7/OUT 0.06fF
-C143 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF
-C144 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/Out 0.21fF
-C145 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF
-C146 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C147 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF
-C148 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C149 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/clk 0.11fF
-C150 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C151 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C152 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/nor_1/B 1.21fF
-C153 ro_div_new_0/ro_complete_0/cbank_2/switch_5/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF
-C154 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF
-C155 divbuf_5/OUT3 divbuf_5/OUT 0.26fF
-C156 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF
-C157 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/nor_1/A 0.38fF
-C158 divbuf_0/a_492_n240# divbuf_0/IN 0.13fF
-C159 ro_div_new_0/divider_0/tspc_1/Z1 ro_div_new_0/divider_0/tspc_0/Q 0.01fF
-C160 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C161 divbuf_0/OUT divbuf_0/OUT3 0.26fF
-C162 ro_div_new_0/ro_complete_0/cbank_0/switch_4/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF
-C163 ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin ro_div_new_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C164 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
-C165 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/nor_0/B 0.47fF
-C166 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C167 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C168 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z1 ro_div_new_0/divider_0/prescaler_0/Out 0.08fF
-C169 divbuf_2/a_492_n240# divbuf_2/OUT5 0.01fF
-C170 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C171 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/and_0/out1 0.06fF
-C172 ro_div_new_0/divider_0/nor_1/Z1 ro_div_new_0/divider_0/nor_1/B 0.06fF
-C173 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/nor_1/A 0.04fF
-C174 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Z1 0.03fF
-C175 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C176 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF
-C177 divbuf_3/OUT5 divbuf_3/IN 0.00fF
-C178 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C179 ro_div_new_0/ro_complete_0/cbank_1/switch_1/vin ro_div_new_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C180 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/nor_0/B 0.15fF
-C181 divbuf_7/OUT4 divbuf_7/OUT 1.11fF
-C182 ro_complete_0/a1 ro_complete_0/cbank_2/switch_3/vin 0.14fF
-C183 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/prescaler_0/Out 0.04fF
-C184 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/and_0/A 0.26fF
-C185 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF
-C186 ro_div_new_0/ro_complete_0/cbank_1/switch_4/vin ro_div_new_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C187 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF
-C188 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C189 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/divider_0/clk 0.05fF
-C190 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF
-C191 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/tspc_1/Z2 0.15fF
-C192 ro_div_new_0/divider_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/tspc_2/Z3 0.05fF
-C193 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/tspc_2/Z1 0.03fF
-C194 ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF
-C195 divbuf_5/OUT5 divbuf_5/OUT 43.38fF
-C196 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF
-C197 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
-C198 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF
-C199 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Q 0.51fF
-C200 ro_div_new_0/divider_0/tspc_1/Z1 ro_div_new_0/divider_0/tspc_1/Z3 0.06fF
-C201 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C202 ro_div_new_0/divider_0/and_0/out1 ro_div_new_0/divider_0/and_0/B 0.18fF
-C203 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_div_new_0/divider_0/clk 0.01fF
-C204 ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin ro_div_new_0/ro_complete_0/a3 0.13fF
-C205 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF
-C206 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF
-C207 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
-C208 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_2/Z2 0.20fF
-C209 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/and_0/B 0.08fF
-C210 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C211 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
-C212 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/and_0/A 0.16fF
-C213 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/divider_0/clk 0.05fF
-C214 divbuf_3/OUT4 divbuf_3/OUT 1.11fF
-C215 divbuf_0/OUT4 divbuf_0/OUT3 5.16fF
-C216 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/clk 0.04fF
-C217 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF
-C218 divbuf_1/a_492_n240# divbuf_1/OUT5 0.01fF
-C219 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF
-C220 ro_div_new_0/ro_complete_0/a5 ro_div_new_0/ro_complete_0/cbank_2/v 0.08fF
-C221 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
-C222 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/tspc_1/Z4 0.02fF
-C223 ro_div_new_0/divider_0/tspc_1/Z1 ro_div_new_0/divider_0/tspc_1/Z2 1.07fF
-C224 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/and_0/B 0.29fF
-C225 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C226 divbuf_6/IN divbuf_6/OUT5 0.00fF
-C227 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C228 ro_div_new_0/divider_0/nor_1/Z1 ro_div_new_0/divider_0/and_0/B 0.18fF
-C229 ro_div_new_0/divider_0/tspc_1/Z3 ro_div_new_0/divider_0/tspc_1/Q 0.05fF
-C230 divbuf_3/OUT divbuf_3/OUT2 0.06fF
-C231 divbuf_3/OUT5 divbuf_3/OUT3 0.01fF
-C232 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C233 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/tspc_2/Z1 0.01fF
-C234 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF
-C235 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF
-C236 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF
-C237 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
-C238 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/tspc_0/Z1 0.03fF
-C239 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C240 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/tspc_2/Z3 0.38fF
-C241 ro_div_new_0/divider_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/tspc_2/Z4 0.12fF
-C242 ro_div_new_0/divider_0/tspc_2/Z1 ro_div_new_0/divider_0/tspc_2/Z2 1.07fF
-C243 ro_div_new_0/ro_complete_0/cbank_2/switch_4/vin ro_div_new_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C244 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C245 ro_div_new_0/divider_0/tspc_1/Z1 ro_div_new_0/divider_0/tspc_1/Z4 0.00fF
-C246 ro_div_new_0/divider_0/nor_0/Z1 ro_div_new_0/divider_0/nor_0/B 0.06fF
-C247 ro_div_new_0/divider_0/and_0/A ro_div_new_0/divider_0/and_0/B 0.18fF
-C248 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C249 io_clamp_high[2] io_analog[6] 0.53fF
-C250 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF
-C251 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C252 ro_div_new_0/divider_0/prescaler_0/tspc_0/D ro_div_new_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C253 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/Out 0.19fF
-C254 ro_div_new_0/ro_complete_0/cbank_2/v ro_div_new_0/divider_0/clk 1.36fF
-C255 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/divider_0/clk 0.05fF
-C256 divbuf_1/OUT5 divbuf_1/OUT 43.38fF
-C257 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/and_0/out1 0.31fF
-C258 ro_div_new_0/divider_0/prescaler_0/tspc_0/D ro_div_new_0/divider_0/clk 0.26fF
-C259 ro_div_new_0/ro_complete_0/a1 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF
-C260 divbuf_1/IN divbuf_1/OUT5 0.00fF
-C261 ro_div_new_0/ro_complete_0/cbank_0/switch_5/vin ro_div_new_0/ro_complete_0/a0 0.09fF
-C262 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/a5 0.09fF
-C263 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C264 ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin ro_div_new_0/ro_complete_0/a4 0.09fF
-C265 divbuf_6/OUT2 divbuf_6/OUT 0.06fF
-C266 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF
-C267 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C268 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C269 ro_div_new_0/ro_complete_0/a5 ro_div_new_0/divider_0/clk 0.10fF
-C270 ro_div_new_0/divider_0/tspc_0/Z4 ro_div_new_0/divider_0/nor_1/A 0.21fF
-C271 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/tspc_2/Z3 0.45fF
-C272 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/switch_1/vin 0.20fF
-C273 divbuf_4/OUT3 divbuf_4/OUT 0.26fF
-C274 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF
-C275 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C276 ro_div_new_0/divider_0/tspc_2/Z2 ro_div_new_0/divider_0/tspc_2/Z3 0.16fF
-C277 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/tspc_2/Z4 0.22fF
-C278 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/Q 0.20fF
-C279 ro_div_new_0/ro_complete_0/cbank_2/switch_4/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF
-C280 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
-C281 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C282 io_clamp_low[1] io_analog[5] 0.53fF
-C283 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF
-C284 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
-C285 ro_div_new_0/divider_0/tspc_0/Z2 ro_div_new_0/divider_0/prescaler_0/Out 0.11fF
-C286 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/prescaler_0/tspc_0/Q 0.04fF
-C287 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 ro_div_new_0/divider_0/clk 0.45fF
-C288 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C289 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/prescaler_0/Out 0.01fF
-C290 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/clk 0.01fF
-C291 divbuf_0/OUT5 divbuf_0/OUT 43.38fF
-C292 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a2 0.09fF
-C293 divbuf_1/OUT3 divbuf_1/OUT2 1.37fF
-C294 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF
-C295 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
-C296 ro_div_new_0/ro_complete_0/a5 ro_div_new_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C297 divbuf_6/OUT4 divbuf_6/OUT 1.11fF
-C298 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/Out 0.11fF
-C299 divbuf_2/a_492_n240# divbuf_2/IN 0.13fF
-C300 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF
-C301 ro_div_new_0/ro_complete_0/a1 ro_div_new_0/divider_0/clk 0.05fF
-C302 divbuf_1/a_492_n240# divbuf_1/OUT2 0.42fF
-C303 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/tspc_2/Z4 0.15fF
-C304 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 ro_div_new_0/divider_0/clk 0.64fF
-C305 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C306 divbuf_4/OUT5 divbuf_4/OUT 43.38fF
-C307 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C308 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/tspc_0/Q 0.01fF
-C309 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C310 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF
-C311 ro_div_new_0/divider_0/tspc_2/Z2 ro_div_new_0/divider_0/tspc_2/Z4 0.36fF
-C312 ro_div_new_0/divider_0/tspc_2/Z3 ro_div_new_0/divider_0/Out 0.05fF
-C313 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/tspc_0/Z2 0.01fF
-C314 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF
-C315 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
-C316 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C317 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C318 ro_div_new_0/divider_0/and_0/B ro_div_new_0/divider_0/and_0/Z1 0.07fF
-C319 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF
-C320 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.15fF
-C321 divbuf_1/OUT4 divbuf_1/OUT5 20.26fF
-C322 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 ro_div_new_0/divider_0/clk 0.12fF
-C323 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF
-C324 ro_complete_0/a4 ro_complete_0/cbank_0/switch_0/vin 0.12fF
-C325 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/Out 0.45fF
-C326 ro_div_new_0/ro_complete_0/cbank_1/switch_0/vin ro_div_new_0/divider_0/clk 1.45fF
-C327 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF
-C328 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/nor_1/B 0.35fF
-C329 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C330 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/clk 0.60fF
-C331 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF
-C332 ro_div_new_0/ro_complete_0/cbank_0/v ro_div_new_0/ro_complete_0/cbank_2/v 0.04fF
-C333 divbuf_5/IN divbuf_5/OUT5 0.00fF
-C334 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C335 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF
-C336 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF
-C337 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/tspc_0/Q 0.04fF
-C338 divbuf_0/OUT5 divbuf_0/OUT4 20.26fF
-C339 divbuf_1/OUT divbuf_1/OUT2 0.06fF
-C340 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C341 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C342 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C343 ro_div_new_0/ro_complete_0/cbank_1/switch_3/vin ro_div_new_0/divider_0/clk 1.30fF
-C344 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 ro_div_new_0/divider_0/clk 0.12fF
-C345 divbuf_2/OUT4 divbuf_2/OUT 1.11fF
-C346 ro_complete_0/a4 ro_complete_0/cbank_0/switch_1/vin 0.09fF
-C347 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/tspc_1/Z3 0.05fF
-C348 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/nor_1/B 0.01fF
-C349 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/tspc_0/Z2 0.16fF
-C350 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C351 divbuf_3/OUT5 divbuf_3/a_492_n240# 0.01fF
-C352 io_clamp_high[0] io_analog[4] 0.53fF
-C353 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/tspc_0/a_630_n680# 0.05fF
-C354 ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin ro_div_new_0/ro_complete_0/a3 0.09fF
-C355 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/Q 0.04fF
-C356 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF
-C357 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF
-C358 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C359 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF
-C360 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/tspc_1/Z2 0.01fF
-C361 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/and_0/Z1 0.04fF
-C362 ro_div_new_0/divider_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/nor_0/B 0.35fF
-C363 ro_div_new_0/divider_0/prescaler_0/tspc_0/Q ro_div_new_0/divider_0/clk 0.05fF
-C364 divbuf_5/OUT2 divbuf_5/OUT 0.06fF
-C365 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF
-C366 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF
-C367 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF
-C368 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C369 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C370 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_0/Q 0.22fF
-C371 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C372 divbuf_0/OUT5 divbuf_0/IN 0.00fF
-C373 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/tspc_0/Q 0.05fF
-C374 divbuf_0/OUT divbuf_0/OUT2 0.06fF
-C375 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C376 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C377 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C378 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C379 ro_div_new_0/ro_complete_0/cbank_0/v ro_div_new_0/divider_0/clk 1.27fF
-C380 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C381 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C382 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF
-C383 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF
-C384 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/tspc_1/Z4 0.12fF
-C385 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin ro_div_new_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C386 ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin ro_div_new_0/ro_complete_0/a1 0.14fF
-C387 ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF
-C388 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF
-C389 ro_div_new_0/divider_0/tspc_0/Q ro_div_new_0/divider_0/tspc_1/Z3 0.45fF
-C390 ro_div_new_0/ro_complete_0/cbank_1/switch_5/vin ro_div_new_0/divider_0/clk 1.30fF
-C391 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C392 divbuf_7/OUT3 divbuf_7/OUT 0.26fF
-C393 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF
-C394 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C395 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/prescaler_0/tspc_0/Q 0.19fF
-C396 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/clk 0.14fF
-C397 divbuf_2/IN divbuf_2/OUT5 0.00fF
-C398 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C399 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/clk 0.45fF
-C400 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/cbank_0/switch_0/vin 0.12fF
-C401 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF
-C402 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C403 ro_div_new_0/divider_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/tspc_2/Z2 0.01fF
-C404 ro_div_new_0/divider_0/prescaler_0/tspc_2/D ro_div_new_0/divider_0/clk 0.29fF
-C405 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/nor_1/B 0.06fF
-C406 divbuf_5/OUT4 divbuf_5/OUT 1.11fF
-C407 ro_div_new_0/divider_0/tspc_1/Z2 ro_div_new_0/divider_0/tspc_0/Q 0.14fF
-C408 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Z3 0.38fF
-C409 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/and_0/OUT 0.06fF
-C410 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C411 ro_div_new_0/divider_0/and_0/out1 ro_div_new_0/divider_0/and_0/A 0.01fF
-C412 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C413 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C414 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/and_0/A 0.01fF
-C415 ro_div_new_0/ro_complete_0/a5 ro_div_new_0/ro_complete_0/cbank_0/switch_0/vin 0.09fF
-C416 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/a2 0.09fF
-C417 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF
-C418 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF
-C419 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Z2 0.30fF
-C420 ro_div_new_0/divider_0/tspc_0/Z2 ro_div_new_0/divider_0/tspc_0/Z1 1.07fF
-C421 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
-C422 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C423 ro_div_new_0/ro_complete_0/cbank_0/switch_5/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF
-C424 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin ro_div_new_0/ro_complete_0/a1 0.14fF
-C425 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF
-C426 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_0/vin 0.19fF
-C427 ro_div_new_0/divider_0/tspc_0/Q ro_div_new_0/divider_0/tspc_1/Z4 0.15fF
-C428 ro_div_new_0/divider_0/tspc_0/Z4 ro_div_new_0/divider_0/prescaler_0/Out 0.12fF
-C429 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C430 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/and_0/OUT 0.06fF
-C431 ro_div_new_0/divider_0/nor_1/Z1 ro_div_new_0/divider_0/and_0/A 0.80fF
-C432 divbuf_3/OUT5 divbuf_3/OUT2 0.02fF
-C433 divbuf_3/OUT4 divbuf_3/OUT3 5.16fF
-C434 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C435 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF
-C436 divbuf_7/OUT5 divbuf_7/OUT 43.38fF
-C437 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/and_0/B 0.31fF
-C438 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/nor_0/B 0.22fF
-C439 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.32fF
-C440 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/clk 0.01fF
-C441 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF
-C442 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF
-C443 divbuf_4/IN divbuf_4/OUT5 0.00fF
-C444 ro_div_new_0/ro_complete_0/cbank_1/switch_2/vin ro_div_new_0/divider_0/clk 1.30fF
-C445 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C446 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/tspc_2/Z2 0.40fF
-C447 ro_div_new_0/divider_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/Out 0.04fF
-C448 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF
-C449 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF
-C450 divbuf_1/OUT divbuf_1/OUT3 0.26fF
-C451 ro_div_new_0/divider_0/tspc_1/Z2 ro_div_new_0/divider_0/tspc_1/Z3 0.16fF
-C452 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Z4 0.21fF
-C453 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C454 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C455 io_clamp_low[2] io_analog[6] 0.53fF
-C456 ro_div_new_0/ro_complete_0/cbank_0/switch_4/vin ro_div_new_0/ro_complete_0/a0 0.13fF
-C457 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin ro_div_new_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C458 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C459 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF
-C460 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C461 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C462 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/switch_1/vin 0.19fF
-C463 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/and_0/B 0.20fF
-C464 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF
-C465 ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin ro_div_new_0/ro_complete_0/cbank_0/switch_0/vin 0.19fF
-C466 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF
-C467 ro_div_new_0/divider_0/nor_0/Z1 ro_div_new_0/divider_0/nor_1/B 0.18fF
-C468 ro_div_new_0/divider_0/tspc_0/Z4 ro_div_new_0/divider_0/tspc_0/Z2 0.36fF
-C469 divbuf_3/OUT5 divbuf_3/OUT 43.38fF
-C470 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/tspc_0/Z4 0.12fF
-C471 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C472 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF
-C473 divbuf_1/a_492_n240# divbuf_1/OUT 0.00fF
-C474 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/and_0/OUT 0.14fF
+C0 divbuf_0/OUT5 divbuf_0/OUT4 20.26fF
+C1 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C2 divbuf_5/IN divbuf_5/OUT5 0.00fF
+C3 ro_div_new_0/divider_0/tspc_0/Q ro_div_new_0/divider_0/tspc_1/Z1 0.01fF
+C4 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/clk 0.01fF
+C5 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF
+C6 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.15fF
+C7 ro_div_new_0/ro_complete_0/cbank_2/switch_0/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.44fF
+C8 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF
+C9 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
+C10 divbuf_2/OUT5 divbuf_2/OUT 43.38fF
+C11 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C12 ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF
+C13 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/tspc_1/Q 0.04fF
+C14 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/tspc_0/Z2 0.01fF
+C15 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
+C16 ro_div_new_0/ro_complete_0/a5 ro_div_new_0/divider_0/clk 0.10fF
+C17 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
+C18 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C19 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_0/vin 0.19fF
+C20 divbuf_3/OUT divbuf_3/a_492_n240# 0.00fF
+C21 divbuf_2/a_492_n240# divbuf_2/OUT2 0.42fF
+C22 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF
+C23 io_clamp_high[0] io_analog[4] 0.53fF
+C24 divbuf_0/OUT divbuf_0/OUT4 1.11fF
+C25 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/Out 0.21fF
+C26 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/and_0/A 0.01fF
+C27 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF
+C28 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C29 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF
+C30 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF
+C31 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF
+C32 ro_div_new_0/ro_complete_0/cbank_1/switch_3/vin ro_div_new_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C33 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/nor_1/B 0.01fF
+C34 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C35 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C36 ro_div_new_0/ro_complete_0/cbank_2/switch_5/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF
+C37 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C38 ro_div_new_0/ro_complete_0/cbank_0/v ro_div_new_0/divider_0/clk 1.27fF
+C39 divbuf_5/OUT2 divbuf_5/OUT 0.06fF
+C40 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF
+C41 ro_div_new_0/divider_0/tspc_0/Z1 ro_div_new_0/divider_0/nor_1/A 0.03fF
+C42 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C43 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/nor_0/B 0.47fF
+C44 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C45 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C46 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z1 ro_div_new_0/divider_0/prescaler_0/Out 0.08fF
+C47 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C48 ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C49 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C50 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/Q 0.20fF
+C51 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF
+C52 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C53 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
+C54 ro_div_new_0/ro_complete_0/cbank_0/switch_4/vin ro_div_new_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C55 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C56 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Z1 0.03fF
+C57 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/Q 0.04fF
+C58 divbuf_0/OUT divbuf_0/OUT5 43.38fF
+C59 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin ro_div_new_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C60 divbuf_3/OUT5 divbuf_3/IN 0.00fF
+C61 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF
+C62 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF
+C63 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/nor_1/A 0.04fF
+C64 ro_div_new_0/divider_0/tspc_0/Z1 ro_div_new_0/divider_0/tspc_0/Z2 1.07fF
+C65 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/prescaler_0/Out 0.04fF
+C66 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/and_0/A 0.26fF
+C67 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
+C68 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF
+C69 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF
+C70 divbuf_7/OUT3 divbuf_7/OUT 0.26fF
+C71 ro_div_new_0/ro_complete_0/cbank_1/switch_1/vin ro_div_new_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C72 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF
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+C217 divbuf_1/OUT4 divbuf_1/OUT 1.11fF
+C218 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF
+C219 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/tspc_1/Z3 0.05fF
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+C227 divbuf_2/a_492_n240# divbuf_2/IN 0.13fF
+C228 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF
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+C231 io_clamp_low[0] io_analog[4] 0.53fF
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+C234 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/tspc_1/Z2 0.01fF
+C235 divbuf_0/a_492_n240# divbuf_0/OUT2 0.42fF
+C236 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/and_0/Z1 0.04fF
+C237 ro_div_new_0/divider_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/nor_0/B 0.35fF
+C238 ro_div_new_0/divider_0/prescaler_0/tspc_0/Q ro_div_new_0/divider_0/clk 0.05fF
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+C240 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
+C241 ro_div_new_0/ro_complete_0/cbank_1/switch_0/vin ro_div_new_0/divider_0/clk 1.45fF
+C242 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF
+C243 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF
+C244 divbuf_0/OUT divbuf_0/OUT3 0.26fF
+C245 ro_div_new_0/divider_0/tspc_0/Q ro_div_new_0/divider_0/tspc_1/Z2 0.14fF
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+C251 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C252 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.09fF
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+C254 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C255 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/tspc_1/Z2 0.15fF
+C256 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/tspc_1/Z4 0.12fF
+C257 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C258 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF
+C259 ro_div_new_0/ro_complete_0/cbank_1/switch_5/vin ro_div_new_0/divider_0/clk 1.30fF
+C260 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C261 io_clamp_low[1] io_clamp_high[1] 0.53fF
+C262 ro_div_new_0/divider_0/tspc_0/Q ro_div_new_0/divider_0/tspc_1/Z4 0.15fF
+C263 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF
+C264 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a2 0.09fF
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+C266 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C267 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/prescaler_0/tspc_0/Q 0.19fF
+C268 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/clk 0.14fF
+C269 divbuf_2/IN divbuf_2/OUT5 0.00fF
+C270 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
+C271 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C272 divbuf_7/OUT2 divbuf_7/OUT 0.06fF
+C273 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF
+C274 ro_div_new_0/divider_0/tspc_0/Z4 ro_div_new_0/divider_0/tspc_0/Z1 0.00fF
+C275 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin ro_div_new_0/ro_complete_0/a1 0.14fF
+C276 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C277 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/divider_0/clk 0.05fF
+C278 ro_div_new_0/divider_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/tspc_2/Z2 0.01fF
+C279 ro_div_new_0/divider_0/prescaler_0/tspc_2/D ro_div_new_0/divider_0/clk 0.29fF
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+C281 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Z3 0.38fF
+C282 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/and_0/OUT 0.06fF
+C283 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C284 ro_div_new_0/divider_0/and_0/out1 ro_div_new_0/divider_0/and_0/A 0.01fF
+C285 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF
+C286 divbuf_5/OUT3 divbuf_5/OUT 0.26fF
+C287 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF
+C288 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF
+C289 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C290 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF
+C291 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C292 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Z2 0.30fF
+C293 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
+C294 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/clk 0.11fF
+C295 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C296 ro_div_new_0/ro_complete_0/cbank_1/switch_4/vin ro_div_new_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C297 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/Out 0.45fF
+C298 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C299 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/and_0/OUT 0.06fF
+C300 divbuf_3/OUT5 divbuf_3/OUT2 0.02fF
+C301 divbuf_3/OUT4 divbuf_3/OUT3 5.16fF
+C302 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C303 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF
+C304 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF
+C305 ro_div_new_0/ro_complete_0/cbank_0/switch_0/vin ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C306 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
+C307 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/and_0/B 0.31fF
+C308 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/nor_0/B 0.22fF
+C309 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.32fF
+C310 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/clk 0.01fF
+C311 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C312 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF
+C313 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF
+C314 divbuf_7/OUT4 divbuf_7/OUT 1.11fF
+C315 ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin ro_div_new_0/ro_complete_0/a1 0.14fF
+C316 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C317 ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF
+C318 ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin ro_div_new_0/ro_complete_0/a3 0.09fF
+C319 divbuf_1/OUT2 divbuf_1/OUT5 0.02fF
+C320 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF
+C321 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C322 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/divider_0/clk 0.05fF
+C323 ro_div_new_0/divider_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/Out 0.04fF
+C324 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/tspc_2/Z2 0.40fF
+C325 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF
+C326 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF
+C327 ro_div_new_0/divider_0/tspc_0/Q ro_div_new_0/divider_0/tspc_0/Z3 0.05fF
+C328 ro_div_new_0/ro_complete_0/cbank_0/switch_5/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF
+C329 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/and_0/out1 0.06fF
+C330 ro_div_new_0/divider_0/tspc_1/Z2 ro_div_new_0/divider_0/tspc_1/Z3 0.16fF
+C331 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Z4 0.21fF
+C332 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C333 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C334 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/divider_0/clk 0.05fF
+C335 divbuf_5/OUT5 divbuf_5/OUT 43.38fF
+C336 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C337 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C338 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF
+C339 ro_div_new_0/ro_complete_0/cbank_0/switch_0/vin ro_div_new_0/ro_complete_0/a5 0.09fF
+C340 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/nor_1/A 0.38fF
+C341 ro_div_new_0/divider_0/nor_0/Z1 ro_div_new_0/divider_0/nor_0/B 0.06fF
+C342 divbuf_3/OUT5 divbuf_3/OUT 43.38fF
+C343 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
+C344 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF
+C345 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C346 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin ro_div_new_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C347 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C348 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/and_0/OUT 0.14fF
+C349 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/nor_0/B 0.15fF
+C350 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/divider_0/clk 0.05fF
+C351 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF
+C352 divbuf_1/OUT5 divbuf_1/OUT 43.38fF
+C353 ro_div_new_0/divider_0/tspc_1/Z3 ro_div_new_0/divider_0/tspc_1/Z4 0.65fF
+C354 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 ro_div_new_0/divider_0/clk 0.12fF
+C355 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF
+C356 divbuf_3/OUT divbuf_3/OUT3 0.26fF
+C357 divbuf_6/IN divbuf_6/OUT5 0.00fF
+C358 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C359 ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF
+C360 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF
+C361 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/tspc_2/Z2 0.14fF
+C362 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C363 ro_div_new_0/divider_0/prescaler_0/tspc_0/Q ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.04fF
+C364 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF
+C365 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF
+C366 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF
+C367 ro_div_new_0/ro_complete_0/cbank_0/switch_0/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF
+C368 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/tspc_0/Z2 0.16fF
+C369 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C370 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/Out 0.22fF
+C371 ro_div_new_0/divider_0/tspc_2/Z1 ro_div_new_0/divider_0/tspc_2/Z3 0.06fF
+C372 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF
+C373 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF
+C374 divbuf_0/IN divbuf_0/OUT5 0.00fF
+C375 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C376 ro_div_new_0/ro_complete_0/a5 ro_div_new_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C377 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/and_0/A 0.16fF
+C378 ro_div_new_0/divider_0/tspc_1/Z2 ro_div_new_0/divider_0/tspc_1/Z4 0.36fF
+C379 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C380 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C381 ro_div_new_0/divider_0/and_0/out1 ro_div_new_0/divider_0/and_0/Z1 0.36fF
+C382 ro_div_new_0/ro_complete_0/a1 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF
+C383 io_clamp_high[2] io_analog[6] 0.53fF
+C384 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_2/Z4 0.02fF
+C385 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 ro_div_new_0/divider_0/prescaler_0/Out 0.11fF
+C386 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/clk 0.11fF
+C387 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C388 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
+C389 ro_div_new_0/ro_complete_0/cbank_0/switch_4/vin ro_div_new_0/ro_complete_0/a0 0.13fF
+C390 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.16fF
+C391 ro_div_new_0/divider_0/prescaler_0/Out ro_div_new_0/divider_0/clk 0.51fF
+C392 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C393 ro_complete_0/a1 ro_complete_0/cbank_0/switch_3/vin 0.14fF
+C394 ro_complete_0/a4 ro_complete_0/cbank_0/switch_0/vin 0.12fF
+C395 divbuf_6/OUT2 divbuf_6/OUT 0.06fF
+C396 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF
+C397 ro_div_new_0/divider_0/nor_1/Z1 ro_div_new_0/divider_0/nor_1/B 0.06fF
+C398 ro_div_new_0/ro_complete_0/cbank_2/switch_4/vin ro_div_new_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C399 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
+C400 ro_div_new_0/divider_0/prescaler_0/tspc_0/Q ro_div_new_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C401 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 ro_div_new_0/divider_0/prescaler_0/Out 0.05fF
+C402 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/clk 0.11fF
+C403 divbuf_2/OUT2 divbuf_2/OUT 0.06fF
+C404 ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF
+C405 ro_div_new_0/divider_0/tspc_0/Z4 ro_div_new_0/divider_0/prescaler_0/Out 0.12fF
+C406 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C407 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF
+C408 ro_div_new_0/divider_0/tspc_2/Z1 ro_div_new_0/divider_0/tspc_2/Z4 0.00fF
+C409 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF
+C410 divbuf_4/OUT3 divbuf_4/OUT 0.26fF
+C411 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C412 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C413 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C414 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF
+C415 io_clamp_low[1] io_analog[5] 0.53fF
+C416 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 ro_div_new_0/divider_0/prescaler_0/Out 0.28fF
+C417 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF
+C418 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF
+C419 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF
+C420 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C421 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/and_0/B 0.01fF
+C422 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/prescaler_0/Out 0.91fF
+C423 divbuf_1/IN divbuf_1/a_492_n240# 0.13fF
+C424 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C425 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C426 ro_div_new_0/ro_complete_0/a1 ro_div_new_0/divider_0/clk 0.05fF
+C427 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF
+C428 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/a2 0.09fF
+C429 ro_div_new_0/divider_0/tspc_0/Z4 ro_div_new_0/divider_0/nor_1/A 0.21fF
+C430 ro_div_new_0/ro_complete_0/a5 ro_div_new_0/ro_complete_0/cbank_2/v 0.08fF
+C431 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C432 ro_complete_0/a5 ro_complete_0/cbank_0/switch_0/vin 0.09fF
+C433 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/prescaler_0/Out 0.01fF
+C434 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C435 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/clk 0.01fF
+C436 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF
+C437 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF
+C438 divbuf_6/OUT4 divbuf_6/OUT 1.11fF
+C439 ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C440 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/switch_1/vin 0.20fF
+C441 ro_div_new_0/ro_complete_0/cbank_2/switch_4/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF
+C442 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF
+C443 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C444 ro_div_new_0/divider_0/prescaler_0/tspc_2/D ro_div_new_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C445 divbuf_2/OUT3 divbuf_2/OUT 0.26fF
+C446 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
+C447 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C448 divbuf_1/OUT4 divbuf_1/OUT5 20.26fF
+C449 divbuf_1/OUT3 divbuf_1/OUT 0.26fF
+C450 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF
+C451 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_div_new_0/divider_0/clk 0.01fF
+C452 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF
+C453 ro_div_new_0/divider_0/tspc_2/Z3 ro_div_new_0/divider_0/tspc_2/Z4 0.65fF
+C454 divbuf_4/OUT5 divbuf_4/OUT 43.38fF
+C455 ro_div_new_0/divider_0/tspc_0/Q ro_div_new_0/divider_0/tspc_0/a_630_n680# 0.04fF
+C456 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF
+C457 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C458 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/nor_0/B 0.00fF
+C459 ro_div_new_0/divider_0/nor_1/Z1 ro_div_new_0/divider_0/and_0/B 0.18fF
+C460 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C461 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/clk 0.01fF
+C462 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF
+C463 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF
+C464 divbuf_0/a_492_n240# divbuf_0/IN 0.13fF
+C465 divbuf_1/OUT5 divbuf_1/IN 0.00fF
+C466 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/switch_1/vin 0.19fF
+C467 ro_div_new_0/divider_0/tspc_0/Z4 ro_div_new_0/divider_0/tspc_0/Z2 0.36fF
+C468 ro_div_new_0/ro_complete_0/cbank_0/v ro_div_new_0/ro_complete_0/cbank_2/v 0.04fF
+C469 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
+C470 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF
+C471 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/nor_1/A 0.35fF
+C472 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C473 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C474 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF
Xro_div_new_0/ro_complete_0 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/ro_complete_0/a1
+ ro_div_new_0/ro_complete_0/a5 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/a3
+ ro_div_new_0/ro_complete_0/a2 ro_complete
