fix consistency check error
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds index 451f7ef..c5ffe4a 100644 --- a/gds/user_analog_project_wrapper.gds +++ b/gds/user_analog_project_wrapper.gds Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag index 3218621..bdf9cc8 100644 --- a/mag/user_analog_project_wrapper.mag +++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@ magic tech sky130A -timestamp 1643059293 +timestamp 1643079693 << nwell >> rect 26424 264625 26589 264812 rect 23497 264291 23832 264611 @@ -1976,7 +1976,7 @@ rect 22523 267082 24124 274937 rect 157010 272682 159389 274937 rect 157010 272524 159393 272682 -rect 157052 270231 159393 272524 +rect 157052 270890 159393 272524 rect 22903 266651 23075 267082 rect 22903 266518 22917 266651 rect 23059 266518 23075 266651 @@ -1986,6 +1986,7 @@ rect 23582 266522 23603 266657 rect 22903 266504 23070 266505 rect 23424 266499 23603 266522 +rect 157000 264416 159401 270890 rect 229206 266148 231073 274937 rect 229206 266001 230173 266148 rect 230330 266144 231073 266148 @@ -1998,7 +1999,7 @@ rect 230806 265995 230895 266139 rect 229206 265992 230895 265995 rect 231052 265992 231073 266139 -rect 157052 245000 159393 265511 +rect 157052 245000 159393 264416 rect 229206 263775 231073 265992 rect 229206 263772 230409 263775 rect 229206 263625 230168 263772 @@ -2065,6 +2066,7 @@ rect 10000 225022 36608 225144 rect 36727 225022 275000 225144 rect 10000 225000 275000 225022 +rect 157052 207700 159393 225000 rect 27342 187275 28458 187920 rect 27342 187145 27672 187275 rect 27843 187271 28458 187275 @@ -2091,7 +2093,7 @@ rect 28130 180039 28209 180169 rect 28380 180039 28458 180169 rect 27342 177000 28458 180039 -rect 157052 177000 159393 225000 +rect 157052 177000 159393 204482 rect 12000 175000 277000 177000 rect 27364 171169 28450 175000 rect 27362 170817 28452 171169
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice index e37ceea..fb464d1 100644 --- a/netgen/user_analog_project_wrapper.spice +++ b/netgen/user_analog_project_wrapper.spice
@@ -88,7 +88,7 @@ + la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] + la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] + la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2] -+ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] ++ vccd1 vccd2 vssa1 vdda2 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] + wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] + wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] + wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] @@ -106,1725 +106,1725 @@ + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] + wbs_stb_i wbs_we_i -C0 ro_complete_1/a2 ro_complete_1/cbank_1/v 0.05fF -C1 divbuf_14/OUT divbuf_14/OUT3 0.26fF -C2 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF -C3 pd_1/R pd_1/tspc_r_1/Qbar 0.03fF -C4 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF -C5 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z1 0.00fF -C6 divider_1/tspc_0/Z1 divider_1/tspc_0/Z4 0.00fF -C7 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z2 0.19fF -C8 pd_1/REF pd_1/tspc_r_1/Z4 0.02fF -C9 pd_1/UP pd_1/tspc_r_1/Qbar 0.21fF -C10 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z2 0.01fF -C11 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF -C12 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.26fF -C13 pd_1/tspc_r_0/Z1 pd_1/DIV 0.17fF -C14 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C15 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF -C16 divbuf_1/a_492_n240# divbuf_1/OUT 0.00fF -C17 ro_complete_1/a5 ro_complete_1/cbank_2/v 0.08fF -C18 pd_0/tspc_r_1/z5 pd_0/UP 0.03fF -C19 divider_2/tspc_1/Q divider_2/tspc_0/Z1 0.01fF -C20 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF -C21 divider_2/nor_0/B divider_2/tspc_1/Z3 0.38fF -C22 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF -C23 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF -C24 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF -C25 divbuf_12/OUT3 divbuf_12/OUT 0.26fF -C26 divbuf_12/OUT4 divbuf_12/OUT5 20.26fF -C27 pd_1/and_pd_0/Z1 pd_1/tspc_r_1/Qbar 0.02fF -C28 io_clamp_high[2] io_analog[6] 0.53fF -C29 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF -C30 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF -C31 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF -C32 divbuf_14/OUT2 divbuf_14/a_492_n240# 0.42fF -C33 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF -C34 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF -C35 divbuf_3/OUT2 divbuf_3/OUT 0.06fF -C36 ro_complete_1/a3 ro_complete_1/cbank_1/v 0.05fF -C37 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C38 divbuf_6/OUT5 divbuf_6/OUT 43.38fF -C39 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C40 divider_1/tspc_1/Q divider_1/tspc_1/Z3 0.05fF -C41 divider_1/tspc_1/Z1 divider_1/tspc_1/Z4 0.00fF -C42 divider_1/Out divider_1/nor_1/B 0.22fF -C43 divbuf_11/a_492_n240# divbuf_11/OUT 0.00fF -C44 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF -C45 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF -C46 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF -C47 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF -C48 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF -C49 divbuf_18/OUT5 divbuf_18/OUT 43.38fF -C50 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF -C51 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF -C52 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF -C53 ro_complete_1/a2 ro_complete_1/cbank_0/switch_2/vin 0.14fF -C54 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF -C55 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C56 divider_2/tspc_0/Z4 divider_2/tspc_1/Q 0.15fF -C57 divbuf_20/a_492_n240# divbuf_20/IN 0.13fF -C58 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C59 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C60 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.14fF -C61 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.78fF -C62 divider_1/tspc_1/Z2 divider_1/tspc_1/Z4 0.36fF -C63 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF -C64 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.64fF -C65 divbuf_22/OUT4 divbuf_22/OUT 1.11fF -C66 pd_1/R pd_1/tspc_r_0/Z2 0.21fF -C67 pd_0/tspc_r_1/Z4 pd_0/REF 0.02fF -C68 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z3 0.05fF -C69 divider_2/tspc_0/Z3 divider_2/tspc_0/a_630_n680# 0.05fF -C70 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF -C71 divbuf_13/a_492_n240# divbuf_13/OUT5 0.01fF -C72 divider_0/tspc_0/a_630_n680# divider_0/Out 0.04fF -C73 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF -C74 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.45fF -C75 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a1 0.14fF -C76 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/a3 0.09fF -C77 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF -C78 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Z4 0.65fF -C79 ro_complete_1/cbank_2/switch_5/vin ro_complete_1/cbank_2/v 1.30fF -C80 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C81 divbuf_21/OUT2 divbuf_21/OUT3 1.37fF -C82 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF -C83 divider_2/prescaler_0/Out divider_2/tspc_2/Z3 0.45fF -C84 divider_1/tspc_1/Z4 divider_1/nor_0/A 0.02fF -C85 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF -C86 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF -C87 divider_2/nor_0/A divider_2/and_0/B 0.08fF -C88 divbuf_24/OUT3 divbuf_24/OUT 0.26fF -C89 divbuf_24/OUT4 divbuf_24/OUT5 20.26fF -C90 cp_0/a_1710_n2840# cp_0/upbar 0.29fF -C91 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF -C92 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF -C93 divider_0/nor_0/A divider_0/tspc_2/Z4 0.21fF -C94 divbuf_3/IN divbuf_3/a_492_n240# 0.13fF -C95 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/v 1.30fF -C96 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C97 divider_1/nor_0/B divider_1/tspc_0/Z4 0.02fF -C98 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF -C99 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF -C100 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z3 0.45fF -C101 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_1/B 0.40fF -C102 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z4 0.12fF -C103 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF -C104 pd_1/and_pd_0/Out1 pd_1/tspc_r_1/Qbar 0.05fF -C105 divbuf_7/OUT5 divbuf_7/OUT 43.38fF -C106 pd_0/tspc_r_1/Z4 pd_0/tspc_r_0/Z4 0.02fF -C107 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF -C108 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF -C109 divider_1/nor_0/A divider_1/tspc_2/Z3 0.38fF -C110 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF -C111 divbuf_23/a_492_n240# divbuf_23/OUT 0.00fF -C112 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Q 0.20fF -C113 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF -C114 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF -C115 divbuf_15/OUT divbuf_15/OUT2 0.06fF -C116 divbuf_15/OUT5 divbuf_15/OUT3 0.01fF -C117 divider_0/prescaler_0/Out divider_0/tspc_2/a_630_n680# 0.01fF -C118 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF -C119 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF -C120 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C121 divbuf_25/OUT5 divbuf_25/OUT 43.38fF -C122 divider_0/and_0/B divider_0/and_0/Z1 0.07fF -C123 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF -C124 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF -C125 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z4 0.12fF -C126 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF -C127 divbuf_10/IN divbuf_10/OUT5 0.00fF -C128 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF -C129 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C130 divbuf_22/a_492_n240# divbuf_22/IN 0.13fF -C131 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a4 0.09fF -C132 divbuf_0/a_492_n240# divbuf_0/IN 0.13fF -C133 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF -C134 divbuf_9/OUT4 divbuf_9/OUT 1.11fF -C135 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/tspc_0/D 0.04fF -C136 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF -C137 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF -C138 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C139 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF -C140 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF -C141 divbuf_2/IN divbuf_2/a_492_n240# 0.13fF -C142 divbuf_0/OUT5 divbuf_0/OUT 43.38fF -C143 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C144 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF -C145 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF -C146 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF -C147 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF -C148 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/Q 0.04fF -C149 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF -C150 divbuf_8/OUT2 divbuf_8/OUT3 1.37fF -C151 divbuf_18/OUT3 divbuf_18/OUT5 0.01fF -C152 divider_2/tspc_0/Z3 divider_2/tspc_1/Q 0.45fF -C153 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF -C154 io_clamp_low[2] io_clamp_high[2] 0.53fF -C155 divider_2/nor_0/A divider_2/tspc_2/Z2 0.23fF -C156 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF -C157 pd_1/R pd_1/UP 0.45fF -C158 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF -C159 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF -C160 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF -C161 pd_1/R pd_1/and_pd_0/Z1 0.02fF -C162 pd_1/and_pd_0/Z1 pd_1/UP 0.06fF -C163 divider_1/nor_1/Z1 divider_1/nor_1/B 0.06fF -C164 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF -C165 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF -C166 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF -C167 pd_0/REF pd_0/R 0.61fF -C168 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF -C169 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF -C170 divbuf_17/OUT4 divbuf_17/OUT5 20.26fF -C171 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF -C172 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C173 divbuf_12/OUT5 divbuf_12/OUT 43.38fF -C174 io_clamp_low[1] io_analog[5] 0.53fF -C175 divider_2/nor_0/B divider_2/tspc_1/Z4 0.21fF -C176 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF -C177 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF -C178 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF -C179 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF -C180 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF -C181 divbuf_15/OUT5 divbuf_15/a_492_n240# 0.01fF -C182 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF -C183 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_2/D 0.16fF -C184 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.03fF -C185 ro_complete_1/a4 ro_complete_1/cbank_2/v 0.05fF -C186 divbuf_25/OUT2 divbuf_25/OUT5 0.02fF -C187 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF -C188 divider_1/prescaler_0/m1_2700_2190# divider_1/and_0/OUT 0.14fF -C189 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z4 0.15fF -C190 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C191 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.11fF -C192 divbuf_17/OUT3 divbuf_17/OUT5 0.01fF -C193 divbuf_11/IN divbuf_11/OUT5 0.00fF -C194 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF -C195 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF -C196 divbuf_9/a_492_n240# divbuf_9/IN 0.13fF -C197 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF -C198 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF -C199 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF -C200 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.45fF -C201 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF -C202 ro_complete_0/a4 ro_complete_0/cbank_0/switch_1/vin 0.09fF -C203 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C204 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF -C205 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF -C206 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF -C207 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF -C208 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C209 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/Z2 0.14fF -C210 pd_0/tspc_r_1/z5 pd_0/tspc_r_1/Z3 0.11fF -C211 divbuf_17/OUT4 divbuf_17/OUT 1.11fF -C212 divider_2/mc2 divider_2/prescaler_0/tspc_2/a_630_n680# 0.33fF -C213 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF -C214 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF -C215 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF -C216 divbuf_13/OUT2 divbuf_13/OUT3 1.37fF -C217 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF -C218 pd_1/DOWN pd_1/tspc_r_0/Qbar1 0.11fF -C219 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF -C220 divider_0/mc2 divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF -C221 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a1 0.14fF -C222 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF -C223 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF -C224 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF -C225 divider_1/tspc_0/a_630_n680# divider_1/Out 0.04fF -C226 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF -C227 divider_2/prescaler_0/Out divider_2/tspc_2/Z4 0.12fF -C228 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.45fF -C229 divbuf_21/OUT2 divbuf_21/OUT5 0.02fF -C230 divbuf_21/OUT3 divbuf_21/OUT4 5.16fF -C231 divbuf_17/OUT3 divbuf_17/OUT 0.26fF -C232 divbuf_12/a_492_n240# divbuf_12/OUT2 0.42fF -C233 divbuf_24/OUT5 divbuf_24/OUT 43.38fF -C234 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF -C235 pd_1/R pd_1/and_pd_0/Out1 0.33fF -C236 pd_1/UP pd_1/and_pd_0/Out1 0.33fF -C237 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF -C238 pd_1/and_pd_0/Z1 pd_1/and_pd_0/Out1 0.18fF -C239 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF -C240 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF -C241 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF -C242 divider_1/nor_0/A divider_1/tspc_2/Z4 0.21fF -C243 pd_0/tspc_r_1/z5 pd_0/tspc_r_0/z5 0.02fF -C244 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF -C245 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Q 0.04fF -C246 divbuf_23/IN divbuf_23/OUT5 0.00fF -C247 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF -C248 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C249 divider_0/prescaler_0/Out divider_0/nor_0/A 0.15fF -C250 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF -C251 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.14fF -C252 divider_0/nor_1/Z1 divider_0/and_0/B 0.78fF -C253 divbuf_1/a_492_n240# divbuf_1/OUT5 0.01fF -C254 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C255 divbuf_10/OUT2 divbuf_10/OUT 0.06fF -C256 divbuf_10/OUT3 divbuf_10/OUT5 0.01fF -C257 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C258 divider_1/prescaler_0/Out divider_1/tspc_2/a_630_n680# 0.01fF -C259 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF -C260 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF -C261 ro_complete_1/a5 ro_complete_1/cbank_1/switch_0/vin 0.09fF -C262 divbuf_19/OUT5 divbuf_19/OUT 43.38fF -C263 divider_1/and_0/B divider_1/and_0/Z1 0.07fF -C264 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z3 0.09fF -C265 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/nand_1/z1 0.01fF -C266 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF -C267 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF -C268 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF -C269 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF -C270 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF -C271 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF -C272 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF -C273 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C274 divbuf_4/OUT3 divbuf_4/OUT 0.26fF -C275 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF -C276 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF -C277 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C278 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z3 0.33fF -C279 divbuf_16/OUT2 divbuf_16/OUT5 0.02fF -C280 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF -C281 divbuf_18/IN divbuf_18/a_492_n240# 0.13fF -C282 divider_2/tspc_0/a_630_n680# divider_2/tspc_1/Q 0.01fF -C283 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF -C284 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF -C285 divbuf_8/OUT2 divbuf_8/OUT5 0.02fF -C286 divbuf_8/OUT3 divbuf_8/OUT4 5.16fF -C287 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF -C288 divbuf_24/a_492_n240# divbuf_24/OUT2 0.42fF -C289 divider_0/tspc_0/Z3 divider_0/Out 0.05fF -C290 divider_0/tspc_0/Z2 divider_0/nor_1/B 0.40fF -C291 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF -C292 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF -C293 divider_0/prescaler_0/tspc_2/Q divider_0/clk 0.05fF -C294 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF -C295 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/a0 0.13fF -C296 divbuf_5/OUT3 divbuf_5/OUT 0.26fF -C297 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF -C298 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF -C299 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF -C300 divbuf_16/OUT3 divbuf_16/OUT2 1.37fF -C301 pd_1/UP pd_1/tspc_r_1/z5 0.03fF -C302 divbuf_16/IN divbuf_16/OUT5 0.00fF -C303 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF -C304 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF -C305 pd_0/tspc_r_0/Z3 pd_0/DIV 0.65fF -C306 divbuf_1/OUT5 divbuf_1/OUT 43.38fF -C307 pd_0/and_pd_0/Out1 pd_0/R 0.33fF -C308 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF -C309 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF -C310 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/switch_1/vin 0.19fF -C311 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF -C312 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF -C313 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF -C314 divider_1/mc2 divider_1/and_0/out1 0.06fF -C315 divbuf_14/OUT4 divbuf_14/OUT3 5.16fF -C316 ro_complete_1/a1 ro_complete_1/cbank_1/v 0.05fF -C317 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_1/B 0.47fF -C318 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z4 0.65fF -C319 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z2 0.19fF -C320 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF -C321 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_2/D 0.16fF -C322 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/D 0.03fF -C323 divbuf_11/OUT2 divbuf_11/OUT 0.06fF -C324 divbuf_11/OUT3 divbuf_11/OUT5 0.01fF -C325 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF -C326 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF -C327 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF -C328 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF -C329 divider_1/mc2 divider_1/nor_0/B 0.06fF -C330 divbuf_14/OUT2 divbuf_14/OUT3 1.37fF -C331 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Q 0.05fF -C332 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF -C333 divbuf_20/a_492_n240# divbuf_20/OUT5 0.01fF -C334 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C335 divbuf_16/OUT3 divbuf_16/OUT5 0.01fF -C336 divbuf_18/OUT2 divbuf_18/a_492_n240# 0.42fF -C337 divider_2/and_0/OUT divider_2/and_0/B 0.01fF -C338 divbuf_13/OUT2 divbuf_13/OUT5 0.02fF -C339 divbuf_13/OUT3 divbuf_13/OUT4 5.16fF -C340 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF -C341 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z4 0.01fF -C342 ro_complete_1/a2 ro_complete_1/cbank_2/switch_2/vin 0.14fF -C343 ro_complete_1/a4 ro_complete_1/cbank_2/switch_1/vin 0.09fF -C344 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/v 1.30fF -C345 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C346 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_1/Q 0.14fF -C347 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF -C348 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF -C349 divbuf_21/OUT3 divbuf_21/OUT 0.26fF -C350 divbuf_21/OUT4 divbuf_21/OUT5 20.26fF -C351 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.64fF -C352 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF -C353 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF -C354 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF -C355 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF -C356 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF -C357 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.06fF -C358 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF -C359 ro_complete_1/a3 ro_complete_1/cbank_2/switch_2/vin 0.09fF -C360 divbuf_17/OUT2 divbuf_17/a_492_n240# 0.42fF -C361 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF -C362 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.18fF -C363 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C364 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF -C365 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF -C366 divbuf_19/OUT2 divbuf_19/a_492_n240# 0.42fF -C367 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF -C368 divbuf_23/OUT2 divbuf_23/OUT 0.06fF -C369 divbuf_23/OUT3 divbuf_23/OUT5 0.01fF -C370 cp_0/a_1710_0# cp_0/out 0.84fF -C371 pd_1/tspc_r_0/z5 pd_1/DIV 0.04fF -C372 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF -C373 divbuf_15/OUT2 divbuf_15/OUT3 1.37fF -C374 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF -C375 divbuf_15/IN divbuf_15/a_492_n240# 0.13fF -C376 divbuf_25/OUT3 divbuf_25/OUT5 0.01fF -C377 divbuf_25/a_492_n240# divbuf_25/IN 0.13fF -C378 divider_0/prescaler_0/Out divider_0/tspc_2/Z2 0.11fF -C379 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF -C380 divbuf_3/OUT3 divbuf_3/OUT 0.26fF -C381 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/v 1.30fF -C382 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF -C383 divider_2/Out divider_2/nor_1/B 0.22fF -C384 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF -C385 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C386 divider_1/prescaler_0/Out divider_1/nor_0/A 0.15fF -C387 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF -C388 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.14fF -C389 divider_1/nor_1/Z1 divider_1/and_0/B 0.78fF -C390 divbuf_10/OUT4 divbuf_10/OUT 1.11fF -C391 divbuf_22/a_492_n240# divbuf_22/OUT5 0.01fF -C392 divbuf_0/OUT5 divbuf_0/IN 0.00fF -C393 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF -C394 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_1/z1 0.21fF -C395 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF -C396 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF -C397 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C398 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/Q 0.19fF -C399 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.01fF -C400 divbuf_4/OUT5 divbuf_4/OUT 43.38fF -C401 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z3 0.05fF -C402 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z4 0.08fF -C403 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C404 divbuf_17/OUT2 divbuf_17/OUT5 0.02fF -C405 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.04fF -C406 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C407 divbuf_8/OUT3 divbuf_8/OUT 0.26fF -C408 divbuf_8/OUT4 divbuf_8/OUT5 20.26fF -C409 io_clamp_low[1] io_clamp_high[1] 0.53fF -C410 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF -C411 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF -C412 divider_0/nor_0/B divider_0/tspc_2/Q 0.22fF -C413 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.35fF -C414 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF -C415 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF -C416 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_4/vin 0.20fF -C417 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C418 divider_0/tspc_2/a_630_n680# divider_0/nor_0/A 0.35fF -C419 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.29fF -C420 divbuf_5/OUT5 divbuf_5/OUT 43.38fF -C421 cp_0/a_10_n50# cp_0/vbias 0.19fF -C422 divider_1/tspc_0/Z3 divider_1/Out 0.05fF -C423 divider_1/tspc_0/Z2 divider_1/nor_1/B 0.40fF -C424 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF -C425 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF -C426 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z1 0.03fF -C427 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.01fF -C428 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF -C429 divider_1/prescaler_0/tspc_2/Q divider_1/clk 0.05fF -C430 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF -C431 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/nor_0/A 0.03fF -C432 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF -C433 io_clamp_high[0] io_analog[4] 0.53fF -C434 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF -C435 pd_1/DIV pd_1/tspc_r_0/Z3 0.65fF -C436 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF -C437 divbuf_15/OUT2 divbuf_15/a_492_n240# 0.42fF -C438 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.00fF -C439 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF -C440 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF -C441 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF -C442 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF -C443 divider_0/nor_0/Z1 divider_0/and_0/A 0.80fF -C444 divbuf_2/OUT5 divbuf_2/IN 0.00fF -C445 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF -C446 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF -C447 cp_0/a_1710_0# cp_0/down 0.32fF -C448 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C449 divider_1/mc2 divider_1/and_0/A 0.16fF -C450 divider_0/and_0/out1 divider_0/and_0/A 0.01fF -C451 divbuf_10/a_492_n240# divbuf_10/IN 0.13fF -C452 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF -C453 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/D 0.05fF -C454 divbuf_0/OUT4 divbuf_0/OUT3 5.16fF -C455 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z2 0.30fF -C456 divbuf_18/OUT2 divbuf_18/OUT 0.06fF -C457 divbuf_17/OUT2 divbuf_17/OUT 0.06fF -C458 divbuf_16/OUT5 divbuf_16/OUT4 20.26fF -C459 divbuf_11/OUT4 divbuf_11/OUT 1.11fF -C460 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF -C461 divbuf_9/a_492_n240# divbuf_9/OUT5 0.01fF -C462 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF -C463 divider_0/tspc_0/Z2 divider_0/tspc_0/a_630_n680# 0.01fF -C464 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF -C465 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF -C466 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF -C467 divider_0/nor_0/B divider_0/and_0/A 0.26fF -C468 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF -C469 divbuf_20/OUT2 divbuf_20/OUT3 1.37fF -C470 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF -C471 divbuf_16/OUT3 divbuf_16/OUT4 5.16fF -C472 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Q 0.05fF -C473 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF -C474 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z3 0.45fF -C475 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_0/A 1.21fF -C476 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF -C477 divider_2/tspc_0/Z2 divider_2/nor_1/B 0.40fF -C478 divbuf_13/OUT3 divbuf_13/OUT 0.26fF -C479 divbuf_13/OUT4 divbuf_13/OUT5 20.26fF -C480 pd_1/R pd_1/tspc_r_0/Qbar1 0.01fF -C481 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/Out 0.05fF -C482 divider_0/nor_1/B divider_0/and_0/B 0.29fF -C483 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C484 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF -C485 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF -C486 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C487 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_630_n680# 0.05fF -C488 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z4 0.01fF -C489 divbuf_21/OUT5 divbuf_21/OUT 43.38fF -C490 pd_1/REF pd_1/tspc_r_1/Z1 0.17fF -C491 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF -C492 divbuf_2/OUT3 divbuf_2/OUT 0.26fF -C493 pd_0/tspc_r_1/Qbar pd_0/tspc_r_1/Qbar1 0.01fF -C494 divbuf_12/a_492_n240# divbuf_12/OUT 0.00fF -C495 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF -C496 pd_0/UP pd_0/and_pd_0/Z1 0.06fF -C497 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF -C498 divider_0/nor_0/B divider_0/tspc_1/Z3 0.38fF -C499 divider_0/tspc_1/Q divider_0/nor_1/B 0.22fF -C500 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF -C501 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF -C502 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/a0 0.09fF -C503 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF -C504 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C505 divbuf_6/IN divbuf_6/OUT5 0.00fF -C506 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF -C507 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_2/Q 0.01fF -C508 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/a_630_n680# 0.35fF -C509 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF -C510 divider_1/nor_0/Z1 divider_1/and_0/B 0.18fF -C511 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF -C512 divider_1/prescaler_0/tspc_0/Z2 divider_1/and_0/OUT 0.06fF -C513 divbuf_11/a_492_n240# divbuf_11/IN 0.13fF -C514 divbuf_23/OUT4 divbuf_23/OUT 1.11fF -C515 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF -C516 divbuf_25/OUT4 divbuf_25/OUT 1.11fF -C517 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.05fF -C518 divbuf_3/OUT5 divbuf_3/OUT 43.38fF -C519 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF -C520 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C521 divbuf_19/IN divbuf_19/OUT5 0.00fF -C522 divbuf_17/OUT4 divbuf_17/OUT3 5.16fF -C523 divider_1/prescaler_0/Out divider_1/tspc_2/Z2 0.11fF -C524 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF -C525 divbuf_22/OUT2 divbuf_22/OUT3 1.37fF -C526 divider_2/mc2 divider_2/nor_1/B 0.15fF -C527 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF -C528 divider_0/tspc_0/Z2 divider_0/tspc_1/Q 0.14fF -C529 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF -C530 divbuf_16/a_492_n240# divbuf_16/OUT2 0.42fF -C531 divider_0/tspc_1/Z2 divider_0/nor_0/A 0.15fF -C532 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/D 0.32fF -C533 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF -C534 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_4/vin 0.20fF -C535 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C536 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C537 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF -C538 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF -C539 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z4 0.12fF -C540 divbuf_21/a_492_n240# divbuf_21/OUT2 0.42fF -C541 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.31fF -C542 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/nor_0/A 0.55fF -C543 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C544 divbuf_18/OUT2 divbuf_18/OUT3 1.37fF -C545 divider_2/nor_1/Z1 divider_2/nor_0/B 0.18fF -C546 divider_2/prescaler_0/Out divider_2/tspc_2/a_630_n680# 0.01fF -C547 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/Q 0.19fF -C548 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.01fF -C549 divbuf_8/OUT5 divbuf_8/OUT 43.38fF -C550 divider_2/nor_1/B divider_2/nor_0/B 0.47fF -C551 divider_2/tspc_0/Z2 divider_2/tspc_0/Z1 1.07fF -C552 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF -C553 divbuf_24/a_492_n240# divbuf_24/OUT 0.00fF -C554 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF -C555 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z3 0.33fF -C556 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF -C557 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF -C558 divbuf_16/a_492_n240# divbuf_16/IN 0.13fF -C559 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF -C560 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C561 divider_1/nor_0/B divider_1/tspc_2/Q 0.22fF -C562 divider_1/tspc_0/a_630_n680# divider_1/nor_1/B 0.35fF -C563 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF -C564 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF -C565 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Q 0.51fF -C566 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z4 0.36fF -C567 divbuf_7/IN divbuf_7/OUT5 0.00fF -C568 pd_0/tspc_r_1/Qbar pd_0/R 0.03fF -C569 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.06fF -C570 divider_1/tspc_2/a_630_n680# divider_1/nor_0/A 0.35fF -C571 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.29fF -C572 divbuf_23/a_492_n240# divbuf_23/IN 0.13fF -C573 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF -C574 divbuf_15/OUT4 divbuf_15/OUT 1.11fF -C575 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF -C576 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF -C577 divider_0/tspc_2/Q divider_0/tspc_1/Z3 0.45fF -C578 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF -C579 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF -C580 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF -C581 divider_2/tspc_0/Z4 divider_2/tspc_0/Z2 0.36fF -C582 divider_2/Out divider_2/tspc_0/Z3 0.05fF -C583 divbuf_16/a_492_n240# divbuf_16/OUT5 0.01fF -C584 ro_complete_1/a0 ro_complete_1/cbank_2/switch_4/vin 0.13fF -C585 ro_complete_1/cbank_0/v ro_complete_1/cbank_1/v 1.27fF -C586 divider_1/tspc_1/a_630_n680# divider_1/nor_1/B 0.00fF -C587 divider_1/prescaler_0/tspc_1/Z2 divider_1/and_0/OUT 0.06fF -C588 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF -C589 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF -C590 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/D 0.11fF -C591 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF -C592 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF -C593 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/A 0.01fF -C594 divbuf_18/IN divbuf_18/OUT5 0.00fF -C595 divider_2/tspc_1/a_630_n680# divider_2/nor_1/B 0.00fF -C596 divider_1/and_0/out1 divider_1/and_0/A 0.01fF -C597 divbuf_9/OUT2 divbuf_9/OUT3 1.37fF -C598 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C599 divbuf_2/OUT5 divbuf_2/OUT 43.38fF -C600 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF -C601 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF -C602 divider_1/tspc_0/Z2 divider_1/tspc_0/a_630_n680# 0.01fF -C603 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF -C604 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF -C605 divider_1/nor_0/B divider_1/and_0/A 0.26fF -C606 divbuf_20/OUT2 divbuf_20/OUT5 0.02fF -C607 divbuf_20/OUT3 divbuf_20/OUT4 5.16fF -C608 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_0/A 0.01fF -C609 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z4 0.12fF -C610 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF -C611 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF -C612 divbuf_8/a_492_n240# divbuf_8/OUT2 0.42fF -C613 ro_complete_1/a5 ro_complete_1/cbank_2/switch_0/vin 0.09fF -C614 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF -C615 divbuf_13/OUT5 divbuf_13/OUT 43.38fF -C616 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Z3 0.11fF -C617 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF -C618 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF -C619 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF -C620 pd_0/DIV pd_0/R 0.51fF -C621 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z1 0.08fF -C622 divider_0/mc2 divider_0/nor_1/B 0.15fF -C623 pd_1/REF pd_1/tspc_r_1/Z3 0.65fF -C624 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/cbank_0/v 1.30fF -C625 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C626 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C627 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_630_n680# 0.12fF -C628 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C629 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z2 0.25fF -C630 divider_1/nor_1/B divider_1/and_0/B 0.29fF -C631 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z1 0.71fF -C632 divbuf_12/IN divbuf_12/OUT5 0.00fF -C633 divider_0/nor_0/B divider_0/tspc_1/Z4 0.21fF -C634 divider_0/tspc_0/Z3 divider_0/nor_1/B 0.38fF -C635 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF -C636 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C637 divider_0/nor_0/A divider_0/and_0/B 0.08fF -C638 divider_1/tspc_1/Z1 divider_1/tspc_1/Z2 1.07fF -C639 divider_1/nor_0/B divider_1/tspc_1/Z3 0.38fF -C640 divider_1/tspc_1/Q divider_1/nor_1/B 0.22fF -C641 divbuf_6/OUT2 divbuf_6/OUT 0.06fF -C642 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF -C643 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C644 divbuf_18/OUT2 divbuf_18/OUT5 0.02fF -C645 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF -C646 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF -C647 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z1 0.03fF -C648 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF -C649 divbuf_19/OUT5 divbuf_19/OUT3 0.01fF -C650 divider_2/nor_0/B divider_2/tspc_2/a_630_n680# 0.01fF -C651 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/D 0.03fF -C652 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF -C653 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Q 0.20fF -C654 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF -C655 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF -C656 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C657 divider_2/tspc_0/Z4 divider_2/nor_0/B 0.02fF -C658 divbuf_19/OUT2 divbuf_19/OUT 0.06fF -C659 divider_1/prescaler_0/tspc_2/Z2 divider_1/and_0/OUT 0.05fF -C660 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF -C661 pd_1/DOWN pd_1/tspc_r_0/Qbar 0.21fF -C662 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z3 0.25fF -C663 divider_2/tspc_0/Z2 divider_2/tspc_0/Z3 0.16fF -C664 divbuf_22/OUT2 divbuf_22/OUT5 0.02fF -C665 divbuf_22/OUT3 divbuf_22/OUT4 5.16fF -C666 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF -C667 divbuf_13/a_492_n240# divbuf_13/OUT2 0.42fF -C668 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/R 0.27fF -C669 divider_2/prescaler_0/tspc_1/Q divider_2/nor_0/A 0.03fF -C670 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF -C671 divider_0/tspc_0/a_630_n680# divider_0/tspc_1/Q 0.01fF -C672 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF -C673 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.05fF -C674 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C675 pd_0/DOWN pd_0/UP 0.46fF -C676 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C0 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF +C1 ro_complete_1/a4 ro_complete_1/cbank_1/v 0.05fF +C2 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C3 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF +C4 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF +C5 divbuf_17/OUT3 divbuf_17/OUT2 1.37fF +C6 divbuf_17/a_492_n240# divbuf_17/OUT 0.00fF +C7 divider_2/nor_1/B divider_2/Out 0.22fF +C8 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF +C9 divider_1/tspc_1/Z2 divider_1/tspc_1/a_630_n680# 0.01fF +C10 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF +C11 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/nor_0/B 0.22fF +C12 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/nor_1/B 0.38fF +C13 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF +C14 divbuf_7/OUT4 divbuf_7/OUT 1.11fF +C15 pd_1/DOWN pd_1/tspc_r_1/Qbar 0.02fF +C16 pd_0/UP pd_0/and_pd_0/Z1 0.06fF +C17 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.15fF +C18 divbuf_23/a_492_n240# divbuf_23/OUT5 0.01fF +C19 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF +C20 divbuf_14/OUT2 divbuf_14/OUT5 0.02fF +C21 divider_0/tspc_2/Q divider_0/tspc_2/Z3 0.05fF +C22 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C23 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF +C24 divider_0/mc2 divider_0/and_0/B 0.20fF +C25 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF +C26 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF +C27 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF +C28 divider_1/nor_0/Z1 divider_1/and_0/B 0.18fF +C29 divbuf_10/OUT2 divbuf_10/OUT3 1.37fF +C30 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF +C31 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF +C32 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C33 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF +C34 divider_2/tspc_0/Z2 divider_2/tspc_0/a_630_n680# 0.01fF +C35 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF +C36 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF +C37 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z4 0.12fF +C38 divbuf_9/OUT4 divbuf_9/OUT5 20.26fF +C39 divbuf_9/OUT3 divbuf_9/OUT 0.26fF +C40 divbuf_0/OUT5 divbuf_0/IN 0.00fF +C41 divbuf_0/OUT2 divbuf_0/OUT3 1.37fF +C42 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C43 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF +C44 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF +C45 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF +C46 divbuf_25/a_492_n240# divbuf_25/IN 0.13fF +C47 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF +C48 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C49 divbuf_4/IN divbuf_4/OUT5 0.00fF +C50 ro_complete_1/cbank_1/v ro_complete_1/cbank_2/v 1.36fF +C51 divider_2/nor_1/B divider_2/tspc_0/Z3 0.38fF +C52 divbuf_20/OUT5 divbuf_20/OUT 43.38fF +C53 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C54 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF +C55 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF +C56 divbuf_18/IN divbuf_18/a_492_n240# 0.13fF +C57 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF +C58 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.03fF +C59 divbuf_8/a_492_n240# divbuf_8/OUT 0.00fF +C60 pd_1/UP pd_1/and_pd_0/Out1 0.33fF +C61 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF +C62 divider_2/nor_0/A divider_2/tspc_2/Z4 0.21fF +C63 divider_0/tspc_1/Q divider_0/tspc_0/Z4 0.15fF +C64 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z4 0.28fF +C65 io_clamp_low[1] io_analog[5] 0.53fF +C66 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF +C67 divider_0/and_0/OUT divider_0/and_0/B 0.01fF +C68 ro_complete_1/a5 ro_complete_1/cbank_1/switch_0/vin 0.09fF +C69 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/v 1.30fF +C70 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C71 divbuf_5/IN divbuf_5/OUT5 0.00fF +C72 divider_1/tspc_0/Z4 divider_1/nor_0/B 0.02fF +C73 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF +C74 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.45fF +C75 divbuf_19/OUT4 divbuf_19/OUT3 5.16fF +C76 divbuf_19/OUT5 divbuf_19/OUT2 0.02fF +C77 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF +C78 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF +C79 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF +C80 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF +C81 divbuf_12/OUT4 divbuf_12/OUT 1.11fF +C82 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF +C83 divider_2/and_0/A divider_2/and_0/B 0.18fF +C84 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Q 0.91fF +C85 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C86 ro_complete_1/a2 ro_complete_1/cbank_0/switch_3/vin 0.09fF +C87 divbuf_19/OUT5 divbuf_19/a_492_n240# 0.01fF +C88 divbuf_16/OUT5 divbuf_16/OUT3 0.01fF +C89 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF +C90 divbuf_25/IN divbuf_25/OUT5 0.00fF +C91 ro_complete_1/cbank_1/switch_2/vin ro_complete_1/cbank_1/v 1.30fF +C92 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF +C93 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C94 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C95 divider_1/tspc_1/Z1 divider_1/tspc_1/Z4 0.00fF +C96 divbuf_11/OUT2 divbuf_11/OUT3 1.37fF +C97 divider_2/mc2 divider_2/and_0/OUT 0.05fF +C98 divider_2/nor_1/Z1 divider_2/nor_0/B 0.18fF +C99 pd_1/tspc_r_1/Qbar pd_1/R 0.03fF +C100 divbuf_19/OUT divbuf_19/OUT3 0.26fF +C101 divider_2/nor_0/B divider_2/tspc_2/a_630_n680# 0.01fF +C102 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_0/z1 0.24fF +C103 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF +C104 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF +C105 divbuf_2/OUT5 divbuf_2/a_492_n240# 0.01fF +C106 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/v 1.30fF +C107 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF +C108 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/OUT3 1.37fF +C109 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C110 divider_2/tspc_1/Q divider_2/tspc_0/Z1 0.01fF +C111 ro_complete_1/a0 ro_complete_1/cbank_2/v 0.05fF +C112 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C113 divbuf_20/a_492_n240# divbuf_20/OUT2 0.42fF +C114 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/nor_0/A 0.15fF +C115 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C116 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C117 divider_1/prescaler_0/Out divider_1/tspc_2/Z4 0.12fF +C118 divider_1/nor_1/B divider_1/Out 0.22fF +C119 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Q 0.04fF +C120 divbuf_22/OUT5 divbuf_22/OUT 43.38fF +C121 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF +C122 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF +C123 pd_1/tspc_r_1/Z3 pd_1/UP 0.03fF +C124 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.26fF +C125 divbuf_13/a_492_n240# divbuf_13/OUT 0.00fF +C126 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C127 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF +C128 divbuf_25/a_492_n240# divbuf_25/OUT5 0.01fF +C129 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_1/z1 0.21fF +C130 divbuf_2/OUT3 divbuf_2/OUT 0.26fF +C131 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z3 0.33fF +C132 divbuf_21/IN divbuf_21/OUT5 0.00fF +C133 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF +C134 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/nand_1/z1 0.01fF +C135 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF +C136 divbuf_12/a_492_n240# divbuf_12/IN 0.13fF +C137 pd_1/DIV pd_1/tspc_r_0/Z3 0.65fF +C138 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF +C139 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z1 0.17fF +C140 divbuf_24/OUT4 divbuf_24/OUT 1.11fF +C141 divbuf_3/OUT2 divbuf_3/a_492_n240# 0.42fF +C142 divider_1/tspc_1/Z2 divider_1/nor_0/B 0.30fF +C143 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF +C144 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/A 0.35fF +C145 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF +C146 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF +C147 divbuf_23/OUT2 divbuf_23/OUT3 1.37fF +C148 pll_full_0/pd_0/DIV pll_full_0/pd_0/R 0.51fF +C149 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF +C150 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF +C151 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF +C152 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/Out 0.04fF +C153 divbuf_14/OUT2 divbuf_14/a_492_n240# 0.42fF +C154 divider_0/tspc_0/Z3 divider_0/tspc_0/Z1 0.06fF +C155 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF +C156 divbuf_17/a_492_n240# divbuf_17/IN 0.13fF +C157 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF +C158 ro_complete_1/a3 ro_complete_1/cbank_2/v 0.05fF +C159 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF +C160 divbuf_16/OUT divbuf_16/OUT4 1.11fF +C161 divider_1/tspc_2/Q divider_1/tspc_2/a_630_n680# 0.04fF +C162 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF +C163 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF +C164 divbuf_10/OUT3 divbuf_10/OUT4 5.16fF +C165 divbuf_10/OUT2 divbuf_10/OUT5 0.02fF +C166 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C167 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF +C168 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C169 divbuf_22/a_492_n240# divbuf_22/OUT2 0.42fF +C170 divbuf_9/OUT5 divbuf_9/OUT 43.38fF +C171 cp_0/a_1710_n2840# cp_0/upbar 0.29fF +C172 pd_1/R pd_1/REF 0.61fF +C173 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF +C174 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF +C175 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/Out 0.21fF +C176 ro_complete_1/a4 ro_complete_1/cbank_1/switch_1/vin 0.09fF +C177 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.45fF +C178 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C179 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF +C180 divider_2/tspc_1/Q divider_2/tspc_0/Z3 0.45fF +C181 divider_1/nor_1/Z1 divider_1/nor_1/B 0.06fF +C182 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF +C183 divbuf_4/OUT2 divbuf_4/OUT 0.06fF +C184 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/a_630_n680# 0.05fF +C185 divbuf_8/IN divbuf_8/OUT5 0.00fF +C186 divider_2/tspc_2/Q divider_2/tspc_1/Z2 0.14fF +C187 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF +C188 divbuf_24/a_492_n240# divbuf_24/IN 0.13fF +C189 cp_0/upbar cp_0/down 0.02fF +C190 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF +C191 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF +C192 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF +C193 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF +C194 divider_0/mc2 divider_0/and_0/OUT 0.05fF +C195 divider_0/tspc_0/Z3 divider_0/nor_1/B 0.38fF +C196 ro_complete_1/a3 ro_complete_1/cbank_1/switch_2/vin 0.09fF +C197 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF +C198 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF +C199 divbuf_5/OUT2 divbuf_5/OUT 0.06fF +C200 divider_1/tspc_0/Z4 divider_1/tspc_0/a_630_n680# 0.12fF +C201 divider_1/and_0/OUT divider_1/and_0/B 0.01fF +C202 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/Z1 0.03fF +C203 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF +C204 pd_0/UP pd_0/tspc_r_1/z5 0.03fF +C205 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF +C206 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF +C207 ro_complete_1/a2 ro_complete_1/cbank_2/switch_3/vin 0.09fF +C208 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF +C209 divbuf_25/a_492_n240# divbuf_25/OUT 0.00fF +C210 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF +C211 divbuf_1/OUT4 divbuf_1/OUT3 5.16fF +C212 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/switch_5/vin 0.20fF +C213 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/a_740_n680# 0.19fF +C214 divider_0/and_0/out1 divider_0/and_0/A 0.01fF +C215 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF +C216 divider_1/tspc_1/Z3 divider_1/tspc_1/Z4 0.65fF +C217 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF +C218 divbuf_18/OUT2 divbuf_18/OUT3 1.37fF +C219 divbuf_11/OUT3 divbuf_11/OUT4 5.16fF +C220 divbuf_11/OUT2 divbuf_11/OUT5 0.02fF +C221 divbuf_9/a_492_n240# divbuf_9/OUT2 0.42fF +C222 divbuf_18/OUT3 divbuf_18/OUT5 0.01fF +C223 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/Q 0.04fF +C224 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF +C225 divider_2/nor_0/B divider_2/nor_0/A 1.21fF +C226 divider_0/tspc_0/Z3 divider_0/Out 0.05fF +C227 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF +C228 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/Out 0.11fF +C229 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.45fF +C230 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z1 0.08fF +C231 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z2 0.11fF +C232 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C233 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF +C234 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF +C235 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF +C236 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.06fF +C237 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF +C238 pd_1/REF pd_1/tspc_r_1/z5 0.04fF +C239 divbuf_13/IN divbuf_13/OUT5 0.00fF +C240 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF +C241 divider_0/prescaler_0/Out divider_0/prescaler_0/m1_2700_2190# 0.11fF +C242 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a4 0.12fF +C243 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF +C244 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF +C245 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C246 divbuf_2/OUT5 divbuf_2/OUT 43.38fF +C247 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF +C248 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF +C249 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C250 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C251 divbuf_25/OUT divbuf_25/OUT5 43.38fF +C252 divider_0/prescaler_0/tspc_1/Q divider_0/nor_0/A 0.03fF +C253 divider_0/nor_1/B divider_0/tspc_0/Z2 0.40fF +C254 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF +C255 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_1/Q 0.45fF +C256 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF +C257 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z4 0.08fF +C258 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z3 0.05fF +C259 divbuf_21/OUT3 divbuf_21/OUT5 0.01fF +C260 divbuf_21/OUT2 divbuf_21/OUT 0.06fF +C261 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_1/z1 0.21fF +C262 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF +C263 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF +C264 divider_2/tspc_2/Q divider_2/tspc_1/Z4 0.15fF +C265 divider_2/tspc_1/Z1 divider_2/nor_0/B 0.03fF +C266 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF +C267 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF +C268 ro_complete_1/a5 ro_complete_1/cbank_1/v 0.10fF +C269 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/cbank_0/v 1.30fF +C270 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z2 0.01fF +C271 divbuf_14/OUT4 divbuf_14/OUT3 5.16fF +C272 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF +C273 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C274 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/A 0.80fF +C275 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF +C276 divider_2/nor_1/B divider_2/and_0/B 0.29fF +C277 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF +C278 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF +C279 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/clk 0.05fF +C280 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF +C281 pd_1/DOWN pd_1/tspc_r_0/Qbar1 0.11fF +C282 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF +C283 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF +C284 divbuf_18/OUT4 divbuf_18/OUT3 5.16fF +C285 divider_2/tspc_2/Q divider_2/tspc_2/Z3 0.05fF +C286 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF +C287 divbuf_23/OUT3 divbuf_23/OUT4 5.16fF +C288 divbuf_23/OUT2 divbuf_23/OUT5 0.02fF +C289 divider_0/tspc_1/Z2 divider_0/nor_0/A 0.15fF +C290 divider_0/prescaler_0/Out divider_0/tspc_2/Z3 0.45fF +C291 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF +C292 divbuf_10/OUT4 divbuf_10/OUT5 20.26fF +C293 divbuf_10/OUT3 divbuf_10/OUT 0.26fF +C294 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.00fF +C295 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C296 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C297 divbuf_16/OUT2 divbuf_16/a_492_n240# 0.42fF +C298 divider_1/tspc_2/Q divider_1/nor_0/A 0.55fF +C299 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF +C300 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF +C301 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF +C302 pd_1/R pd_1/tspc_r_1/Qbar1 0.30fF +C303 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.45fF +C304 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF +C305 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C306 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.04fF +C307 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF +C308 ro_complete_1/a2 ro_complete_1/cbank_1/v 0.05fF +C309 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF +C310 divbuf_4/OUT4 divbuf_4/OUT 1.11fF +C311 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C312 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C313 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF +C314 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF +C315 divbuf_8/OUT3 divbuf_8/OUT5 0.01fF +C316 divbuf_8/OUT2 divbuf_8/OUT 0.06fF +C317 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z3 0.05fF +C318 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF +C319 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF +C320 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF +C321 divider_0/tspc_1/Z2 divider_0/tspc_1/a_630_n680# 0.01fF +C322 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF +C323 io_clamp_high[0] io_analog[4] 0.53fF +C324 divbuf_15/OUT divbuf_15/OUT3 0.26fF +C325 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF +C326 divider_0/nor_0/A divider_0/tspc_2/Z1 0.03fF +C327 ro_complete_1/a3 ro_complete_1/cbank_2/switch_1/vin 0.13fF +C328 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF +C329 divbuf_16/OUT divbuf_16/OUT2 0.06fF +C330 divider_1/tspc_1/Z1 divider_1/tspc_1/Z3 0.06fF +C331 divider_1/tspc_2/Q divider_1/tspc_1/a_630_n680# 0.01fF +C332 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z2 0.19fF +C333 divbuf_5/OUT4 divbuf_5/OUT 1.11fF +C334 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF +C335 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF +C336 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z3 0.25fF +C337 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF +C338 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF +C339 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF +C340 filter_0/a_4216_n2998# filter_0/v 0.31fF +C341 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF +C342 divbuf_19/OUT2 divbuf_19/OUT3 1.37fF +C343 divider_2/and_0/B divider_2/and_0/Z1 0.07fF +C344 ro_complete_1/a2 ro_complete_1/cbank_0/switch_2/vin 0.14fF +C345 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a4 0.09fF +C346 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF +C347 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF +C348 divbuf_15/OUT2 divbuf_15/OUT3 1.37fF +C349 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/v 1.30fF +C350 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C351 divbuf_11/OUT4 divbuf_11/OUT5 20.26fF +C352 divbuf_11/OUT3 divbuf_11/OUT 0.26fF +C353 divider_1/and_0/out1 divider_1/and_0/A 0.01fF +C354 divider_1/tspc_0/Z3 divider_1/Out 0.05fF +C355 pd_1/tspc_r_0/Qbar1 pd_1/R 0.01fF +C356 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF +C357 divbuf_0/OUT divbuf_0/OUT2 0.06fF +C358 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF +C359 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C360 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF +C361 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF +C362 divider_0/tspc_0/Z3 divider_0/tspc_0/a_630_n680# 0.05fF +C363 divbuf_1/OUT5 divbuf_1/IN 0.00fF +C364 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/D 0.03fF +C365 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF +C366 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C367 divbuf_17/a_492_n240# divbuf_17/OUT5 0.01fF +C368 divider_2/tspc_1/Q divider_2/tspc_1/Z3 0.05fF +C369 divider_2/nor_1/B divider_2/tspc_0/a_630_n680# 0.35fF +C370 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF +C371 ro_complete_1/cbank_2/switch_2/vin ro_complete_1/cbank_2/v 1.30fF +C372 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z3 0.11fF +C373 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.64fF +C374 divbuf_20/a_492_n240# divbuf_20/OUT 0.00fF +C375 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C376 pd_1/DIV pd_1/tspc_r_0/Z2 0.19fF +C377 pd_0/DOWN pd_0/R 0.36fF +C378 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF +C379 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF +C380 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF +C381 divbuf_13/OUT3 divbuf_13/OUT5 0.01fF +C382 divbuf_13/OUT2 divbuf_13/OUT 0.06fF +C383 pd_1/R pd_1/and_pd_0/Z1 0.02fF +C384 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF +C385 divider_2/tspc_2/a_630_n680# divider_2/nor_0/A 0.35fF +C386 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF +C387 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF +C388 divbuf_15/IN divbuf_15/a_492_n240# 0.13fF +C389 divbuf_25/OUT2 divbuf_25/a_492_n240# 0.42fF +C390 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF +C391 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C392 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF +C393 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z4 0.12fF +C394 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z4 0.65fF +C395 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C396 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C397 divider_1/prescaler_0/tspc_1/Q divider_1/nor_0/A 0.03fF +C398 divbuf_21/OUT4 divbuf_21/OUT 1.11fF +C399 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF +C400 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.01fF +C401 divbuf_12/a_492_n240# divbuf_12/OUT5 0.01fF +C402 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF +C403 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF +C404 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF +C405 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF +C406 divider_2/tspc_1/Z3 divider_2/nor_0/B 0.38fF +C407 divider_2/tspc_0/Z1 divider_2/tspc_0/Z3 0.06fF +C408 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_2/D 0.16fF +C409 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF +C410 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF +C411 divbuf_15/OUT2 divbuf_15/OUT 0.06fF +C412 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF +C413 divbuf_3/IN divbuf_3/OUT5 0.00fF +C414 divbuf_15/OUT3 divbuf_15/OUT5 0.01fF +C415 divider_0/nor_0/A divider_0/and_0/A 0.01fF +C416 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C417 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C418 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF +C419 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF +C420 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/nor_0/B 0.03fF +C421 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF +C422 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C423 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C424 divider_2/prescaler_0/Out divider_2/clk 0.51fF +C425 divbuf_16/OUT4 divbuf_16/OUT3 5.16fF +C426 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z2 0.23fF +C427 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.29fF +C428 divbuf_23/OUT4 divbuf_23/OUT5 20.26fF +C429 divbuf_23/OUT3 divbuf_23/OUT 0.26fF +C430 pd_1/DOWN pd_1/R 0.36fF +C431 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF +C432 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF +C433 divbuf_25/OUT3 divbuf_25/OUT4 5.16fF +C434 divbuf_25/OUT2 divbuf_25/OUT5 0.02fF +C435 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_0/A 0.01fF +C436 divider_0/prescaler_0/Out divider_0/tspc_2/Z4 0.12fF +C437 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF +C438 divbuf_3/OUT4 divbuf_3/OUT 1.11fF +C439 ro_complete_1/a1 ro_complete_1/cbank_2/v 0.05fF +C440 divider_1/mc2 divider_1/and_0/A 0.16fF +C441 divider_1/prescaler_0/Out divider_1/tspc_2/a_630_n680# 0.01fF +C442 divbuf_10/OUT5 divbuf_10/OUT 43.38fF +C443 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_1/B 0.47fF +C444 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C445 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C446 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C447 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C448 divbuf_22/a_492_n240# divbuf_22/OUT 0.00fF +C449 divbuf_18/OUT3 divbuf_18/OUT 0.26fF +C450 divider_2/nor_0/B divider_2/and_0/B 0.31fF +C451 divider_2/tspc_0/Z3 divider_2/Out 0.05fF +C452 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF +C453 divider_0/tspc_0/Z3 divider_0/tspc_1/Q 0.45fF +C454 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF +C455 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF +C456 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C457 divbuf_14/OUT2 divbuf_14/OUT3 1.37fF +C458 divider_0/tspc_1/Z4 divider_0/nor_0/A 0.02fF +C459 divider_0/nor_0/B divider_0/tspc_0/Z2 0.20fF +C460 divbuf_21/a_492_n240# divbuf_21/IN 0.13fF +C461 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z1 0.01fF +C462 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C463 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_0/A 1.21fF +C464 pd_0/R pd_0/tspc_r_1/Z3 0.29fF +C465 divbuf_8/OUT4 divbuf_8/OUT 1.11fF +C466 divbuf_24/a_492_n240# divbuf_24/OUT5 0.01fF +C467 cp_0/a_10_n50# cp_0/vbias 0.19fF +C468 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF +C469 divider_0/tspc_1/Z2 divider_0/nor_0/B 0.30fF +C470 divbuf_2/OUT2 divbuf_2/a_492_n240# 0.42fF +C471 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF +C472 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF +C473 divbuf_15/OUT divbuf_15/OUT5 43.38fF +C474 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF +C475 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF +C476 divider_0/nor_0/A divider_0/tspc_2/Z3 0.38fF +C477 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF +C478 divider_1/tspc_2/Q divider_1/nor_0/B 0.22fF +C479 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF +C480 divider_1/nor_0/A divider_1/tspc_2/Z1 0.03fF +C481 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF +C482 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF +C483 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.29fF +C484 pd_1/tspc_r_0/Qbar pd_1/tspc_r_0/Qbar1 0.01fF +C485 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF +C486 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.14fF +C487 filter_0/a_4216_n5230# filter_0/v 0.19fF +C488 divbuf_15/OUT2 divbuf_15/OUT5 0.02fF +C489 divbuf_14/OUT divbuf_14/OUT4 1.11fF +C490 divider_0/nor_0/Z1 divider_0/and_0/B 0.18fF +C491 divider_0/tspc_2/Q divider_0/tspc_2/a_630_n680# 0.04fF +C492 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF +C493 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF +C494 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF +C495 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/v 1.43fF +C496 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF +C497 divbuf_10/a_492_n240# divbuf_10/OUT2 0.42fF +C498 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF +C499 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF +C500 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_1/B 0.22fF +C501 divider_1/tspc_1/Z3 divider_1/tspc_1/Q 0.05fF +C502 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF +C503 divider_2/nor_0/Z1 divider_2/and_0/B 0.18fF +C504 divbuf_11/OUT5 divbuf_11/OUT 43.38fF +C505 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/B 0.08fF +C506 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z3 0.09fF +C507 pd_1/tspc_r_1/Z2 pd_1/REF 0.19fF +C508 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/z5 0.11fF +C509 divbuf_9/a_492_n240# divbuf_9/OUT 0.00fF +C510 divbuf_0/OUT divbuf_0/OUT3 0.26fF +C511 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF +C512 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF +C513 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF +C514 divbuf_14/OUT5 divbuf_14/a_492_n240# 0.01fF +C515 divider_0/tspc_1/Q divider_0/tspc_0/Z2 0.14fF +C516 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF +C517 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF +C518 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/switch_5/vin 0.20fF +C519 divider_2/tspc_1/Q divider_2/tspc_0/a_630_n680# 0.01fF +C520 divbuf_20/IN divbuf_20/OUT5 0.00fF +C521 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF +C522 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z4 0.28fF +C523 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/D 0.03fF +C524 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF +C525 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF +C526 divider_2/tspc_2/Q divider_2/tspc_1/a_630_n680# 0.01fF +C527 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF +C528 divbuf_8/a_492_n240# divbuf_8/IN 0.13fF +C529 cp_0/a_1710_n2840# cp_0/out 0.61fF +C530 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF +C531 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF +C532 divider_2/prescaler_0/tspc_2/Q divider_2/clk 0.05fF +C533 divbuf_13/OUT4 divbuf_13/OUT 1.11fF +C534 divbuf_25/OUT2 divbuf_25/OUT 0.06fF +C535 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a5 0.09fF +C536 divbuf_17/a_492_n240# divbuf_17/OUT2 0.42fF +C537 divider_0/and_0/OUT divider_0/clk 0.04fF +C538 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF +C539 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C540 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C541 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF +C542 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C543 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z3 0.16fF +C544 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF +C545 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C546 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Q 0.91fF +C547 pd_1/DIV pd_1/tspc_r_0/z5 0.04fF +C548 pd_1/tspc_r_0/Qbar pd_1/DOWN 0.21fF +C549 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF +C550 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF +C551 divider_2/tspc_0/Z2 divider_2/tspc_0/Z4 0.36fF +C552 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF +C553 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF +C554 divbuf_12/OUT2 divbuf_12/OUT3 1.37fF +C555 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF +C556 divider_2/and_0/out1 divider_2/and_0/B 0.18fF +C557 divbuf_16/OUT5 divbuf_16/IN 0.00fF +C558 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF +C559 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF +C560 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF +C561 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF +C562 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF +C563 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.04fF +C564 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/nor_0/B 0.38fF +C565 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C566 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C567 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF +C568 divbuf_19/OUT4 divbuf_19/OUT 1.11fF +C569 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z1 0.06fF +C570 divider_1/nor_1/B divider_1/tspc_1/Q 0.22fF +C571 divbuf_11/a_492_n240# divbuf_11/OUT2 0.42fF +C572 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF +C573 divider_1/nor_0/A divider_1/and_0/A 0.01fF +C574 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Q 0.05fF +C575 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF +C576 divbuf_23/OUT5 divbuf_23/OUT 43.38fF +C577 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF +C578 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF +C579 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF +C580 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.15fF +C581 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C582 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z4 0.65fF +C583 ro_complete_1/cbank_1/switch_5/vin ro_complete_1/cbank_1/v 1.30fF +C584 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C585 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C586 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C587 divider_1/prescaler_0/Out divider_1/nor_0/A 0.15fF +C588 divbuf_22/IN divbuf_22/OUT5 0.00fF +C589 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF +C590 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z4 0.01fF +C591 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Out1 0.05fF +C592 divbuf_13/a_492_n240# divbuf_13/IN 0.13fF +C593 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF +C594 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C595 divider_0/tspc_2/Q divider_0/tspc_1/Z1 0.01fF +C596 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF +C597 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF +C598 divider_0/nor_0/B divider_0/and_0/A 0.26fF +C599 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF +C600 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF +C601 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF +C602 divbuf_16/OUT2 divbuf_16/OUT3 1.37fF +C603 divider_1/tspc_1/Z4 divider_1/nor_0/A 0.02fF +C604 pd_0/R pd_0/UP 0.45fF +C605 divider_2/tspc_2/Q divider_2/nor_0/B 0.22fF +C606 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF +C607 divider_2/nor_1/Z1 divider_2/and_0/B 0.78fF +C608 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF +C609 divbuf_24/OUT2 divbuf_24/OUT3 1.37fF +C610 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF +C611 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF +C612 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF +C613 divider_0/nor_0/A divider_0/tspc_2/Z4 0.21fF +C614 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C615 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF +C616 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF +C617 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF +C618 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF +C619 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF +C620 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF +C621 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF +C622 divider_1/nor_0/A divider_1/tspc_2/Z3 0.38fF +C623 divbuf_23/a_492_n240# divbuf_23/OUT2 0.42fF +C624 pd_0/UP pd_0/and_pd_0/Out1 0.33fF +C625 divbuf_2/OUT2 divbuf_2/OUT 0.06fF +C626 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/a_492_n240# 0.42fF +C627 divbuf_14/IN divbuf_14/OUT5 0.00fF +C628 divider_0/tspc_2/Q divider_0/nor_0/A 0.55fF +C629 divider_0/nor_0/B divider_0/tspc_1/Z4 0.21fF +C630 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF +C631 ro_complete_1/a0 ro_complete_1/cbank_1/switch_5/vin 0.09fF +C632 divider_0/and_0/A divider_0/and_0/B 0.18fF +C633 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C634 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_0/a_740_n680# 0.21fF +C635 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z4 0.12fF +C636 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF +C637 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF +C638 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/D 0.03fF +C639 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/B 0.22fF +C640 divbuf_18/OUT2 divbuf_18/OUT5 0.02fF +C641 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF +C642 divbuf_9/IN divbuf_9/OUT5 0.00fF +C643 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF +C644 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/Q 0.19fF +C645 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.01fF +C646 divbuf_0/OUT divbuf_0/OUT4 1.11fF +C647 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF +C648 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF +C649 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF +C650 ro_complete_1/a2 ro_complete_1/cbank_2/switch_2/vin 0.14fF +C651 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C652 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF +C653 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_0/z1 0.24fF +C654 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF +C655 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/v 1.30fF +C656 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divbuf_0/IN 0.05fF +C657 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF +C658 divbuf_20/OUT3 divbuf_20/OUT5 0.01fF +C659 divbuf_20/OUT2 divbuf_20/OUT 0.06fF +C660 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF +C661 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C662 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF +C663 divider_2/mc2 divider_2/and_0/A 0.16fF +C664 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF +C665 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF +C666 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF +C667 divider_2/nor_0/A divider_2/tspc_2/Z2 0.23fF +C668 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.29fF +C669 divbuf_2/IN divbuf_2/OUT5 0.00fF +C670 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C671 divbuf_14/OUT divbuf_14/OUT2 0.06fF +C672 divider_0/tspc_2/Q divider_0/tspc_1/a_630_n680# 0.01fF +C673 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z2 0.19fF +C674 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_0/vin 0.19fF +C675 io_clamp_low[2] io_analog[6] 0.53fF +C676 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.26fF C677 divider_1/mc2 divider_1/prescaler_0/tspc_2/a_630_n680# 0.33fF -C678 divbuf_25/a_492_n240# divbuf_25/OUT 0.00fF -C679 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/tspc_0/D 0.04fF -C680 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF -C681 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_0/B 0.18fF -C682 divider_1/tspc_0/Z2 divider_1/tspc_1/Q 0.14fF -C683 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z3 0.16fF -C684 divider_2/prescaler_0/Out divider_2/nor_0/A 0.15fF -C685 divider_1/tspc_1/Z2 divider_1/nor_0/A 0.15fF -C686 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/D 0.32fF -C687 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF -C688 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C689 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF -C690 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF -C691 ro_complete_1/a5 ro_complete_1/cbank_1/v 0.10fF -C692 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/a5 0.09fF -C693 io_clamp_low[0] io_clamp_high[0] 0.53fF -C694 divbuf_24/IN divbuf_24/OUT5 0.00fF -C695 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF -C696 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z4 0.08fF -C697 divider_0/tspc_1/Q divider_0/tspc_1/a_630_n680# 0.04fF -C698 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF -C699 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C700 divider_0/nor_0/A divider_0/tspc_2/Z2 0.23fF -C701 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF -C702 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF -C703 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF -C704 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF -C705 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF -C706 divbuf_7/OUT2 divbuf_7/OUT 0.06fF -C707 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF -C708 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF -C709 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.26fF -C710 divider_2/nor_0/Z1 divider_2/and_0/B 0.18fF -C711 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF -C712 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF -C713 divider_0/tspc_2/Q divider_0/tspc_1/Z4 0.15fF -C714 divider_0/tspc_0/Z4 divider_0/nor_1/B 0.22fF -C715 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF -C716 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF -C717 divbuf_2/OUT5 divbuf_2/a_492_n240# 0.01fF -C718 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C719 divider_2/Out divider_2/tspc_0/a_630_n680# 0.04fF -C720 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF -C721 divbuf_10/a_492_n240# divbuf_10/OUT5 0.01fF -C722 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z2 0.71fF -C723 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_1/Z3 0.05fF -C724 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF -C725 pll_full_0/divbuf_0/IN pll_full_0/divider_0/nor_1/B 0.27fF -C726 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z2 0.01fF -C727 divider_1/tspc_2/Q divider_1/tspc_1/Z3 0.45fF -C728 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF -C729 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF -C730 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF -C731 divider_2/tspc_2/Q divider_2/nor_0/B 0.22fF -C732 divbuf_9/OUT2 divbuf_9/OUT5 0.02fF -C733 divbuf_9/OUT3 divbuf_9/OUT4 5.16fF -C734 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C735 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C736 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF -C737 divbuf_25/a_492_n240# divbuf_25/OUT2 0.42fF -C738 divider_0/tspc_2/Q divider_0/tspc_2/Z3 0.05fF -C739 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF -C740 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF -C741 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF -C742 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF -C743 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF -C744 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF -C745 divbuf_20/OUT3 divbuf_20/OUT 0.26fF -C746 divbuf_20/OUT4 divbuf_20/OUT5 20.26fF -C747 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF -C748 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C749 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.64fF -C750 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF -C751 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF -C752 pd_1/R pd_1/REF 0.61fF -C753 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF -C754 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF -C755 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C756 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z3 0.11fF -C757 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF -C758 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF -C759 ro_complete_1/a4 ro_complete_1/cbank_2/switch_0/vin 0.12fF -C760 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/switch_5/vin 0.20fF -C761 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF -C762 pd_1/R pd_1/tspc_r_1/Z2 0.21fF -C763 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C764 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C765 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.46fF -C766 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z2 0.16fF -C767 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z1 0.08fF -C768 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/Qbar 0.01fF -C769 pll_full_0/divider_0/tspc_1/Z4 pll_full_0/divider_0/nor_0/A 0.02fF -C770 divider_2/tspc_2/Q divider_2/tspc_1/a_630_n680# 0.01fF -C771 cp_0/a_1710_n2840# cp_0/a_1710_0# 0.83fF -C772 pd_0/tspc_r_1/z5 pd_0/tspc_r_1/Qbar1 0.20fF -C773 divider_2/mc2 divider_2/nor_0/A 0.04fF -C774 divider_2/nor_0/B divider_2/tspc_1/Z2 0.30fF -C775 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF -C776 divbuf_12/OUT2 divbuf_12/OUT 0.06fF -C777 divbuf_12/OUT3 divbuf_12/OUT5 0.01fF -C778 io_clamp_low[2] io_analog[6] 0.53fF -C779 divider_2/and_0/out1 divider_2/and_0/B 0.18fF -C780 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C781 divider_0/mc2 divider_0/nor_0/A 0.04fF -C782 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C783 pd_0/R pd_0/tspc_r_0/Z2 0.21fF -C784 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/v 1.30fF -C785 divbuf_6/OUT4 divbuf_6/OUT 1.11fF -C786 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_0/Z4 0.02fF -C787 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C788 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF -C789 divbuf_17/OUT2 divbuf_17/OUT3 1.37fF -C790 divider_1/nor_0/B divider_1/tspc_1/Z4 0.21fF -C791 divider_1/tspc_0/Z3 divider_1/nor_1/B 0.38fF -C792 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF -C793 divbuf_11/a_492_n240# divbuf_11/OUT5 0.01fF -C794 divbuf_0/a_492_n240# divbuf_0/OUT2 0.42fF -C795 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF -C796 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF -C797 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z3 0.38fF -C798 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF -C799 divider_1/nor_0/A divider_1/and_0/B 0.08fF -C800 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z1 0.09fF -C801 divbuf_19/OUT divbuf_19/OUT4 1.11fF -C802 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF -C803 divider_2/nor_0/B divider_2/nor_0/A 1.21fF -C804 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF -C805 divbuf_15/OUT5 divbuf_15/IN 0.00fF -C806 divbuf_25/OUT3 divbuf_25/OUT4 5.16fF -C807 divbuf_0/OUT2 divbuf_0/OUT3 1.37fF -C808 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF -C809 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF -C810 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Q 0.04fF -C811 divider_0/prescaler_0/Out divider_0/clk 0.51fF -C812 ro_complete_1/cbank_2/switch_0/vin ro_complete_1/cbank_2/v 1.45fF -C813 ro_complete_1/a0 ro_complete_1/cbank_2/switch_5/vin 0.09fF -C814 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C815 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF -C816 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C817 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Q 0.20fF -C818 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF -C819 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF -C820 divbuf_22/OUT3 divbuf_22/OUT 0.26fF -C821 divbuf_22/OUT4 divbuf_22/OUT5 20.26fF -C822 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z2 0.01fF -C823 divider_2/tspc_2/Q divider_2/tspc_1/Z3 0.45fF -C824 divider_2/tspc_0/Z2 divider_2/tspc_0/a_630_n680# 0.01fF -C825 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF -C826 divider_2/and_0/OUT divider_2/clk 0.04fF -C827 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF -C828 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF -C829 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF -C830 divbuf_14/OUT divbuf_14/OUT5 43.38fF -C831 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/nand_1/z1 0.01fF -C832 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF -C833 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C834 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C835 divider_1/tspc_0/Z2 divider_1/tspc_0/Z3 0.16fF -C836 divider_1/tspc_0/a_630_n680# divider_1/tspc_1/Q 0.01fF -C837 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z4 0.36fF -C838 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/Out 0.05fF -C839 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF -C840 divbuf_21/a_492_n240# divbuf_21/OUT 0.00fF -C841 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C842 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF -C843 divider_2/prescaler_0/Out divider_2/tspc_2/Z2 0.11fF -C844 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/tspc_0/D 0.04fF -C845 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF -C846 divider_2/nor_0/B divider_2/tspc_1/Z1 0.03fF -C847 divbuf_24/OUT2 divbuf_24/OUT 0.06fF -C848 divbuf_24/OUT3 divbuf_24/OUT5 0.01fF -C849 divider_2/nor_0/A divider_2/and_0/A 0.01fF -C850 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF -C851 ro_complete_1/a4 ro_complete_1/cbank_1/v 0.05fF -C852 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF -C853 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C854 divider_1/tspc_1/Q divider_1/tspc_1/a_630_n680# 0.04fF -C855 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF -C856 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF -C857 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/B 0.03fF -C858 divbuf_7/OUT4 divbuf_7/OUT 1.11fF -C859 divider_1/nor_0/A divider_1/tspc_2/Z2 0.23fF -C860 divbuf_23/a_492_n240# divbuf_23/OUT5 0.01fF -C861 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z2 0.19fF -C862 divbuf_19/OUT divbuf_19/a_492_n240# 0.00fF -C863 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_0/A 0.01fF -C864 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF -C865 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.15fF -C866 divider_2/mc2 divider_2/and_0/B 0.20fF -C867 divbuf_15/OUT5 divbuf_15/OUT2 0.02fF -C868 divbuf_15/OUT4 divbuf_15/OUT3 5.16fF -C869 divbuf_0/OUT4 divbuf_0/OUT 1.11fF -C870 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_3/vin 0.20fF -C871 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF -C872 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C873 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C874 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF -C875 divider_0/mc2 divider_0/and_0/B 0.20fF -C876 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF -C877 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF -C878 divider_1/tspc_2/Q divider_1/tspc_1/Z4 0.15fF -C879 divider_1/tspc_0/Z4 divider_1/nor_1/B 0.22fF -C880 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF -C881 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF -C882 divbuf_10/OUT2 divbuf_10/OUT3 1.37fF -C883 pd_0/UP pd_0/R 0.45fF -C884 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C885 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF -C886 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF -C887 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF -C888 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF -C889 divbuf_9/OUT3 divbuf_9/OUT 0.26fF -C890 divbuf_9/OUT4 divbuf_9/OUT5 20.26fF -C891 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C892 divider_2/nor_0/B divider_2/and_0/B 0.31fF -C893 divider_0/nor_1/Z1 divider_0/nor_0/B 0.18fF -C894 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF -C895 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF -C896 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF -C897 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C898 divbuf_4/IN divbuf_4/OUT5 0.00fF -C899 ro_complete_1/cbank_1/v ro_complete_1/cbank_2/v 1.36fF -C900 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF -C901 divider_1/tspc_2/Q divider_1/tspc_2/Z3 0.05fF -C902 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF -C903 divbuf_20/OUT5 divbuf_20/OUT 43.38fF -C904 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C905 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF -C906 divbuf_8/a_492_n240# divbuf_8/OUT 0.00fF -C907 divider_2/tspc_0/Z2 divider_2/tspc_1/Q 0.14fF -C908 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF -C909 pd_1/DOWN pd_1/tspc_r_0/z5 0.03fF -C910 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF -C911 divider_2/nor_0/A divider_2/tspc_2/Z1 0.03fF -C912 pd_1/R pd_1/tspc_r_1/Qbar1 0.30fF -C913 divider_0/tspc_1/Q divider_0/tspc_0/Z3 0.45fF -C914 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF -C915 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z4 0.28fF -C916 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF -C917 pd_1/tspc_r_1/Qbar1 pd_1/UP 0.11fF -C918 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/v 1.30fF -C919 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/v 1.30fF -C920 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C921 divider_0/and_0/OUT divider_0/and_0/B 0.01fF -C922 divbuf_5/IN divbuf_5/OUT5 0.00fF -C923 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z2 0.36fF -C924 divider_1/tspc_0/Z2 divider_1/tspc_0/Z4 0.36fF -C925 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/a_630_n680# 0.19fF -C926 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z3 0.11fF -C927 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF -C928 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF -C929 pd_1/REF pd_1/tspc_r_1/z5 0.04fF -C930 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF -C931 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.45fF -C932 pd_1/tspc_r_0/Z2 pd_1/DIV 0.19fF -C933 divbuf_12/OUT4 divbuf_12/OUT 1.11fF -C934 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF -C935 divider_2/and_0/A divider_2/and_0/B 0.18fF -C936 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Q 0.91fF -C937 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C938 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/Z2 0.14fF -C939 ro_complete_1/cbank_1/switch_2/vin ro_complete_1/cbank_1/v 1.30fF -C940 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF -C941 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C942 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF -C943 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C944 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF -C945 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF -C946 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF -C947 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF -C948 divbuf_11/OUT2 divbuf_11/OUT3 1.37fF -C949 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF -C950 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z4 0.21fF -C951 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_0/z1 0.24fF -C952 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF -C953 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF -C954 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF -C955 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF -C956 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C957 ro_complete_1/a0 ro_complete_1/cbank_2/v 0.05fF -C958 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF -C959 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C960 divbuf_20/a_492_n240# divbuf_20/OUT2 0.42fF -C961 divider_1/tspc_1/Z3 divider_1/tspc_1/Z4 0.65fF -C962 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Q 0.04fF -C963 divider_1/prescaler_0/Out divider_1/clk 0.51fF -C964 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C965 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C966 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C967 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a3 0.13fF -C968 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/Z3 0.20fF -C969 pd_0/tspc_r_1/z5 pd_0/REF 0.04fF -C970 divider_2/tspc_2/Q divider_2/tspc_1/Z4 0.15fF -C971 divbuf_22/OUT5 divbuf_22/OUT 43.38fF -C972 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF -C973 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF -C974 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF -C975 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF -C976 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.26fF -C977 divbuf_13/a_492_n240# divbuf_13/OUT 0.00fF -C978 pd_1/DOWN pd_1/tspc_r_0/Z3 0.03fF -C979 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF -C980 divbuf_14/a_492_n240# divbuf_14/OUT5 0.01fF -C981 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_1/z1 0.21fF -C982 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_0/B 0.20fF -C983 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z3 0.05fF -C984 divbuf_21/IN divbuf_21/OUT5 0.00fF -C985 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF -C986 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/nand_1/z1 0.01fF -C987 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF -C988 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF -C989 divbuf_1/OUT5 divbuf_1/IN 0.00fF -C990 divider_2/tspc_2/Q divider_2/tspc_2/Z3 0.05fF -C991 divider_2/nor_0/B divider_2/tspc_1/Q 0.51fF -C992 divbuf_12/a_492_n240# divbuf_12/IN 0.13fF -C993 divbuf_24/OUT4 divbuf_24/OUT 1.11fF -C994 cp_0/a_1710_n2840# cp_0/out 0.61fF -C995 divider_0/tspc_1/Q divider_0/tspc_0/Z4 0.15fF -C996 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF -C997 divbuf_3/OUT2 divbuf_3/a_492_n240# 0.42fF -C998 ro_complete_1/a2 ro_complete_1/cbank_2/v 0.05fF -C999 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_0/vin 0.19fF -C1000 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF -C1001 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF -C1002 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF -C1003 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF -C1004 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF -C1005 divbuf_23/OUT2 divbuf_23/OUT3 1.37fF -C1006 pd_1/R pd_1/DIV 0.51fF -C1007 divbuf_15/OUT divbuf_15/OUT3 0.26fF -C1008 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF -C1009 ro_complete_1/a2 ro_complete_1/cbank_1/switch_3/vin 0.09fF -C1010 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF -C1011 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF -C1012 ro_complete_1/a3 ro_complete_1/cbank_2/v 0.05fF -C1013 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF -C1014 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF -C1015 divbuf_10/OUT2 divbuf_10/OUT5 0.02fF -C1016 divbuf_10/OUT3 divbuf_10/OUT4 5.16fF -C1017 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C1018 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF -C1019 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C1020 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF -C1021 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF -C1022 divbuf_22/a_492_n240# divbuf_22/OUT2 0.42fF -C1023 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1024 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Q 0.04fF -C1025 divider_2/tspc_1/Z4 divider_2/nor_0/A 0.02fF -C1026 divbuf_9/OUT5 divbuf_9/OUT 43.38fF -C1027 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF -C1028 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF -C1029 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/Out 0.21fF -C1030 ro_complete_1/a4 ro_complete_1/cbank_1/switch_1/vin 0.09fF -C1031 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF -C1032 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF -C1033 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF -C1034 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1035 divider_1/nor_1/Z1 divider_1/nor_0/B 0.18fF -C1036 divbuf_4/OUT2 divbuf_4/OUT 0.06fF -C1037 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF -C1038 divbuf_8/IN divbuf_8/OUT5 0.00fF -C1039 divider_2/mc2 divider_2/and_0/OUT 0.05fF -C1040 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF -C1041 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.03fF -C1042 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF -C1043 divider_2/nor_0/A divider_2/tspc_2/Z3 0.38fF -C1044 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF -C1045 divbuf_24/a_492_n240# divbuf_24/IN 0.13fF -C1046 divider_0/mc2 divider_0/and_0/OUT 0.05fF -C1047 divider_0/tspc_0/Z1 divider_0/nor_1/B 0.03fF -C1048 ro_complete_1/a3 ro_complete_1/cbank_1/switch_2/vin 0.09fF -C1049 divider_1/tspc_1/Q divider_1/tspc_0/Z3 0.45fF -C1050 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z4 0.12fF -C1051 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z4 0.28fF -C1052 divbuf_5/OUT2 divbuf_5/OUT 0.06fF -C1053 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF -C1054 pd_0/tspc_r_1/Z3 pd_0/R 0.29fF -C1055 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF -C1056 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF -C1057 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z2 1.07fF -C1058 divider_1/and_0/OUT divider_1/and_0/B 0.01fF -C1059 cp_0/a_10_n50# cp_0/a_1710_0# 0.04fF -C1060 io_clamp_high[1] io_analog[5] 0.53fF -C1061 divider_2/tspc_1/Q divider_2/tspc_1/Z3 0.05fF -C1062 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF -C1063 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF -C1064 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF -C1065 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF -C1066 divbuf_15/OUT divbuf_15/a_492_n240# 0.00fF -C1067 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF -C1068 divbuf_25/OUT2 divbuf_25/OUT 0.06fF -C1069 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/switch_5/vin 0.20fF -C1070 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z1 0.08fF -C1071 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Q 0.91fF -C1072 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF -C1073 divbuf_11/OUT2 divbuf_11/OUT5 0.02fF -C1074 divbuf_11/OUT3 divbuf_11/OUT4 5.16fF -C1075 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF -C1076 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF -C1077 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF -C1078 divbuf_19/OUT2 divbuf_19/OUT3 1.37fF -C1079 divbuf_9/a_492_n240# divbuf_9/OUT2 0.42fF -C1080 divbuf_18/OUT4 divbuf_18/OUT 1.11fF -C1081 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/Q 0.04fF -C1082 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF -C1083 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF -C1084 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF -C1085 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF -C1086 divbuf_14/IN divbuf_14/OUT5 0.00fF -C1087 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.45fF -C1088 divbuf_2/OUT2 divbuf_2/OUT 0.06fF -C1089 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/nor_0/A 0.15fF -C1090 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C1091 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF -C1092 divbuf_13/IN divbuf_13/OUT5 0.00fF -C1093 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C1094 divider_0/prescaler_0/Out divider_0/prescaler_0/m1_2700_2190# 0.11fF -C1095 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF -C1096 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF -C1097 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C1098 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1099 divider_1/mc2 divider_1/nor_1/B 0.15fF -C1100 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF -C1101 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF -C1102 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_1/Q 0.01fF -C1103 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF -C1104 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF -C1105 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_1/z1 0.21fF -C1106 divbuf_21/OUT2 divbuf_21/OUT 0.06fF -C1107 divbuf_21/OUT3 divbuf_21/OUT5 0.01fF -C1108 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF -C1109 pd_0/UP pd_0/and_pd_0/Out1 0.33fF -C1110 divider_0/nor_0/B divider_0/nor_1/B 0.47fF -C1111 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF -C1112 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/v 1.43fF -C1113 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/cbank_0/v 1.30fF -C1114 divbuf_14/OUT5 divbuf_14/OUT4 20.26fF -C1115 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF -C1116 divider_1/tspc_1/Q divider_1/tspc_0/Z4 0.15fF -C1117 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF -C1118 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.43fF -C1119 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divbuf_0/IN 0.05fF -C1120 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C1121 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/A 0.80fF -C1122 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF -C1123 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1124 divbuf_19/IN divbuf_19/a_492_n240# 0.13fF -C1125 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF -C1126 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF -C1127 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/clk 0.05fF -C1128 divbuf_23/OUT2 divbuf_23/OUT5 0.02fF -C1129 divbuf_23/OUT3 divbuf_23/OUT4 5.16fF -C1130 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF -C1131 pd_1/tspc_r_0/Z4 pd_1/DIV 0.02fF -C1132 divbuf_14/OUT2 divbuf_14/OUT5 0.02fF -C1133 divider_0/nor_0/B divider_0/tspc_2/a_630_n680# 0.01fF -C1134 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF -C1135 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF -C1136 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF -C1137 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF -C1138 divbuf_10/OUT3 divbuf_10/OUT 0.26fF -C1139 divbuf_10/OUT4 divbuf_10/OUT5 20.26fF -C1140 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C1141 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C1142 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF -C1143 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z3 0.25fF -C1144 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.45fF -C1145 divider_0/tspc_0/Z2 divider_0/nor_0/B 0.20fF -C1146 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.04fF -C1147 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF -C1148 divbuf_1/OUT3 divbuf_1/OUT2 1.37fF -C1149 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF -C1150 divbuf_4/OUT4 divbuf_4/OUT 1.11fF -C1151 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1152 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z2 0.01fF -C1153 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/Out 0.21fF -C1154 divider_2/nor_1/Z1 divider_2/nor_1/B 0.06fF -C1155 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF -C1156 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF -C1157 divbuf_18/OUT3 divbuf_18/OUT4 5.16fF -C1158 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF -C1159 divbuf_8/OUT2 divbuf_8/OUT 0.06fF -C1160 divbuf_8/OUT3 divbuf_8/OUT5 0.01fF -C1161 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF -C1162 divider_2/nor_0/A divider_2/tspc_2/Z4 0.21fF -C1163 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1164 ro_complete_1/a3 ro_complete_1/cbank_2/switch_1/vin 0.13fF -C1165 divbuf_5/OUT4 divbuf_5/OUT 1.11fF -C1166 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF -C1167 divider_1/tspc_0/Z1 divider_1/nor_1/B 0.03fF -C1168 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF -C1169 pd_0/tspc_r_0/Qbar1 pd_0/DIV 0.12fF -C1170 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF -C1171 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF -C1172 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF -C1173 io_clamp_low[0] io_analog[4] 0.53fF -C1174 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF -C1175 ro_complete_0/a5 ro_complete_0/cbank_0/switch_0/vin 0.09fF -C1176 divbuf_19/OUT3 divbuf_19/OUT4 5.16fF -C1177 divider_2/and_0/B divider_2/and_0/Z1 0.07fF -C1178 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/v 1.30fF -C1179 divbuf_2/OUT2 divbuf_2/a_492_n240# 0.42fF -C1180 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C1181 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z3 0.11fF -C1182 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/D 0.09fF -C1183 divbuf_11/OUT3 divbuf_11/OUT 0.26fF -C1184 divbuf_11/OUT4 divbuf_11/OUT5 20.26fF -C1185 divbuf_0/OUT divbuf_0/OUT2 0.06fF -C1186 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF -C1187 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF -C1188 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF -C1189 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C1190 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF -C1191 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF -C1192 divider_0/tspc_2/Q divider_0/tspc_2/a_630_n680# 0.04fF -C1193 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/D 0.03fF -C1194 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF -C1195 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C1196 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF -C1197 ro_complete_1/cbank_2/switch_2/vin ro_complete_1/cbank_2/v 1.30fF -C1198 divider_1/tspc_0/Z1 divider_1/tspc_0/Z2 1.07fF -C1199 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF -C1200 divbuf_20/a_492_n240# divbuf_20/OUT 0.00fF -C1201 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z2 0.11fF -C1202 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C1203 divbuf_16/OUT2 divbuf_16/OUT 0.06fF -C1204 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.06fF -C1205 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF -C1206 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF -C1207 divbuf_13/OUT2 divbuf_13/OUT 0.06fF -C1208 divbuf_13/OUT3 divbuf_13/OUT5 0.01fF -C1209 pd_1/R pd_1/tspc_r_0/Z3 0.27fF -C1210 divider_0/nor_0/B divider_0/tspc_1/Z1 0.03fF -C1211 divider_0/prescaler_0/tspc_1/Q divider_0/nor_0/A 0.03fF -C1212 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C1213 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF -C1214 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C1215 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C1216 divider_1/prescaler_0/Out divider_1/prescaler_0/m1_2700_2190# 0.11fF -C1217 divbuf_21/OUT4 divbuf_21/OUT 1.11fF -C1218 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF -C1219 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.01fF -C1220 divider_2/prescaler_0/Out divider_2/clk 0.51fF -C1221 divbuf_12/a_492_n240# divbuf_12/OUT5 0.01fF -C1222 divider_2/nor_1/B divider_2/tspc_0/Z1 0.03fF -C1223 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_2/D 0.16fF -C1224 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF -C1225 divider_0/nor_0/B divider_0/tspc_1/Z2 0.30fF -C1226 divider_1/mc2 divider_1/nor_0/A 0.04fF -C1227 divbuf_14/OUT5 divbuf_14/OUT3 0.01fF -C1228 divbuf_3/IN divbuf_3/OUT5 0.00fF -C1229 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1230 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C1231 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF -C1232 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Q 0.22fF -C1233 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF -C1234 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C1235 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C1236 divider_1/nor_0/B divider_1/nor_1/B 0.47fF -C1237 divider_1/tspc_0/Z3 divider_1/tspc_0/Z4 0.65fF -C1238 divider_1/nor_0/Z1 divider_1/and_0/A 0.80fF -C1239 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/A 0.35fF -C1240 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.29fF -C1241 divbuf_16/OUT divbuf_16/OUT5 43.38fF -C1242 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF -C1243 divbuf_23/OUT3 divbuf_23/OUT 0.26fF -C1244 divbuf_23/OUT4 divbuf_23/OUT5 20.26fF -C1245 divbuf_18/OUT5 divbuf_18/OUT4 20.26fF -C1246 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF -C1247 divbuf_25/OUT3 divbuf_25/OUT 0.26fF -C1248 divbuf_25/OUT4 divbuf_25/OUT5 20.26fF -C1249 divider_0/prescaler_0/Out divider_0/tspc_2/Z3 0.45fF -C1250 divider_0/nor_0/B divider_0/nor_0/A 1.21fF -C1251 divider_2/tspc_0/Z4 divider_2/nor_1/B 0.22fF -C1252 divbuf_3/OUT4 divbuf_3/OUT 1.11fF -C1253 ro_complete_1/a1 ro_complete_1/cbank_2/v 0.05fF -C1254 divbuf_10/OUT5 divbuf_10/OUT 43.38fF -C1255 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.00fF -C1256 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C1257 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C1258 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C1259 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C1260 divbuf_16/OUT3 divbuf_16/OUT 0.26fF -C1261 divider_1/nor_0/B divider_1/tspc_2/a_630_n680# 0.01fF -C1262 divbuf_22/a_492_n240# divbuf_22/OUT 0.00fF -C1263 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF -C1264 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF -C1265 pd_1/tspc_r_0/Qbar pd_1/tspc_r_0/Qbar1 0.01fF -C1266 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF -C1267 divider_0/tspc_0/Z1 divider_0/tspc_1/Q 0.01fF -C1268 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF -C1269 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_0/vin 0.19fF -C1270 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/v 1.30fF -C1271 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF -C1272 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C1273 divider_1/tspc_0/Z2 divider_1/nor_0/B 0.20fF -C1274 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.04fF -C1275 divbuf_21/a_492_n240# divbuf_21/IN 0.13fF -C1276 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C1277 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/A 0.26fF -C1278 divbuf_8/OUT4 divbuf_8/OUT 1.11fF -C1279 divbuf_24/a_492_n240# divbuf_24/OUT5 0.01fF -C1280 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF -C1281 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF -C1282 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF -C1283 divider_0/tspc_1/Z1 divider_0/tspc_2/Q 0.01fF -C1284 divider_0/nor_0/B divider_0/tspc_1/a_630_n680# 0.35fF -C1285 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF -C1286 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.14fF -C1287 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF -C1288 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF -C1289 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z4 0.00fF -C1290 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF -C1291 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF -C1292 filter_0/a_4216_n5230# filter_0/v 0.19fF -C1293 pd_0/tspc_r_1/Z2 pd_0/R 0.21fF -C1294 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.29fF -C1295 pd_0/and_pd_0/Z1 pd_0/R 0.02fF -C1296 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF -C1297 divbuf_15/OUT4 divbuf_15/OUT5 20.26fF -C1298 pd_1/DIV pd_1/tspc_r_0/Qbar1 0.12fF -C1299 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF -C1300 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF -C1301 divbuf_25/OUT3 divbuf_25/OUT2 1.37fF -C1302 divider_0/nor_0/Z1 divider_0/and_0/B 0.18fF -C1303 divider_0/tspc_2/Q divider_0/tspc_1/Z2 0.14fF -C1304 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF -C1305 divider_1/mc2 divider_1/and_0/B 0.20fF -C1306 divider_0/and_0/out1 divider_0/and_0/B 0.18fF -C1307 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z4 0.28fF -C1308 divbuf_10/a_492_n240# divbuf_10/OUT2 0.42fF -C1309 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF -C1310 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z3 0.38fF -C1311 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_1/B 0.22fF -C1312 divbuf_11/OUT5 divbuf_11/OUT 43.38fF -C1313 divbuf_9/a_492_n240# divbuf_9/OUT 0.00fF -C1314 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF -C1315 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF -C1316 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF -C1317 divbuf_2/OUT4 divbuf_2/OUT 1.11fF -C1318 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF -C1319 divbuf_0/a_492_n240# divbuf_0/OUT5 0.01fF -C1320 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT2 1.37fF -C1321 divbuf_14/OUT divbuf_14/a_492_n240# 0.00fF -C1322 divider_0/nor_0/B divider_0/and_0/B 0.31fF -C1323 divider_0/tspc_2/Q divider_0/nor_0/A 0.55fF -C1324 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF -C1325 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/switch_5/vin 0.20fF -C1326 divider_2/tspc_0/Z4 divider_2/tspc_0/Z1 0.00fF -C1327 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Q 0.91fF -C1328 divider_1/tspc_2/Q divider_1/tspc_2/a_630_n680# 0.04fF -C1329 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/D 0.03fF -C1330 divbuf_20/IN divbuf_20/OUT5 0.00fF -C1331 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF -C1332 divider_2/tspc_0/Z3 divider_2/nor_1/B 0.38fF -C1333 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF -C1334 divbuf_8/a_492_n240# divbuf_8/IN 0.13fF -C1335 divbuf_1/a_492_n240# divbuf_1/OUT2 0.42fF -C1336 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF -C1337 divbuf_13/OUT4 divbuf_13/OUT 1.11fF -C1338 divbuf_18/OUT divbuf_18/a_492_n240# 0.00fF -C1339 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF -C1340 divider_2/prescaler_0/tspc_2/Q divider_2/clk 0.05fF -C1341 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/Z3 0.20fF -C1342 divider_0/nor_0/B divider_0/tspc_1/Q 0.51fF -C1343 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF -C1344 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF -C1345 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C1346 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1347 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z4 0.65fF -C1348 divider_0/and_0/OUT divider_0/clk 0.04fF -C1349 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF -C1350 pd_1/DOWN pd_1/tspc_r_1/Qbar 0.02fF -C1351 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_0/a_630_n680# 0.04fF -C1352 divider_1/nor_0/B divider_1/tspc_1/Z1 0.03fF -C1353 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C1354 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z1 0.09fF -C1355 pd_1/REF pd_1/tspc_r_1/Z2 0.19fF -C1356 divider_1/prescaler_0/tspc_1/Q divider_1/nor_0/A 0.03fF -C1357 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_0/A 0.15fF -C1358 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF -C1359 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C1360 pd_0/tspc_r_1/Qbar pd_0/UP 0.21fF -C1361 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF -C1362 divbuf_12/OUT2 divbuf_12/OUT3 1.37fF -C1363 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF -C1364 divider_0/tspc_2/Q divider_0/tspc_1/a_630_n680# 0.01fF -C1365 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF -C1366 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF -C1367 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF -C1368 divider_0/nor_0/A divider_0/and_0/A 0.01fF -C1369 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF -C1370 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF -C1371 divider_1/nor_0/B divider_1/tspc_1/Z2 0.30fF -C1372 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C1373 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C1374 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF -C1375 ro_complete_1/a5 ro_complete_1/cbank_0/switch_0/vin 0.09fF -C1376 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1377 cp_0/upbar cp_0/down 0.02fF -C1378 divbuf_17/a_492_n240# divbuf_17/OUT5 0.01fF -C1379 divbuf_16/OUT divbuf_16/OUT4 1.11fF -C1380 divbuf_11/a_492_n240# divbuf_11/OUT2 0.42fF -C1381 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF -C1382 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Q 0.05fF -C1383 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF -C1384 divbuf_23/OUT5 divbuf_23/OUT 43.38fF -C1385 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF -C1386 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF -C1387 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_0/A 0.01fF -C1388 divider_0/prescaler_0/Out divider_0/tspc_2/Z4 0.12fF -C1389 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF -C1390 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.15fF -C1391 ro_complete_1/a2 ro_complete_1/cbank_0/switch_3/vin 0.09fF -C1392 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF -C1393 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C1394 divbuf_1/OUT2 divbuf_1/OUT 0.06fF -C1395 ro_complete_1/cbank_1/switch_5/vin ro_complete_1/cbank_1/v 1.30fF -C1396 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z4 0.01fF -C1397 divbuf_19/OUT2 divbuf_19/OUT5 0.02fF -C1398 divider_1/prescaler_0/Out divider_1/tspc_2/Z3 0.45fF -C1399 divider_1/nor_0/B divider_1/nor_0/A 1.21fF -C1400 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF -C1401 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF -C1402 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C1403 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C1404 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C1405 pd_0/tspc_r_1/Z2 pd_0/REF 0.19fF -C1406 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF -C1407 divbuf_22/IN divbuf_22/OUT5 0.00fF -C1408 divbuf_13/a_492_n240# divbuf_13/IN 0.13fF -C1409 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF -C1410 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF -C1411 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C1412 divbuf_25/a_492_n240# divbuf_25/OUT5 0.01fF -C1413 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF -C1414 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF -C1415 divider_1/tspc_0/Z1 divider_1/tspc_1/Q 0.01fF -C1416 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z3 0.06fF -C1417 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF -C1418 divbuf_17/a_492_n240# divbuf_17/OUT 0.00fF -C1419 divider_2/tspc_2/Q divider_2/tspc_2/a_630_n680# 0.04fF -C1420 divider_2/tspc_0/Z3 divider_2/tspc_0/Z1 0.06fF -C1421 divbuf_24/OUT2 divbuf_24/OUT3 1.37fF -C1422 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/Out 0.21fF -C1423 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF -C1424 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/a_630_n680# 0.19fF -C1425 divbuf_25/IN divbuf_25/OUT5 0.00fF -C1426 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF -C1427 divider_0/nor_0/A divider_0/tspc_2/Z1 0.03fF -C1428 divbuf_1/OUT3 divbuf_1/OUT 0.26fF -C1429 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C1430 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF -C1431 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF -C1432 divider_1/tspc_1/Z1 divider_1/tspc_2/Q 0.01fF -C1433 divider_1/nor_0/B divider_1/tspc_1/a_630_n680# 0.35fF -C1434 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF -C1435 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF -C1436 divider_2/mc2 divider_2/and_0/out1 0.06fF -C1437 divider_2/nor_0/Z1 divider_2/and_0/A 0.80fF -C1438 divbuf_23/a_492_n240# divbuf_23/OUT2 0.42fF -C1439 divbuf_15/OUT5 divbuf_15/OUT 43.38fF -C1440 divider_0/mc2 divider_0/and_0/out1 0.06fF -C1441 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF -C1442 divider_2/tspc_0/Z4 divider_2/tspc_0/Z3 0.65fF -C1443 divider_0/and_0/A divider_0/and_0/B 0.18fF -C1444 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF -C1445 ro_complete_1/a0 ro_complete_1/cbank_1/switch_5/vin 0.09fF -C1446 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1447 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF -C1448 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z4 0.21fF -C1449 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/nor_1/B 0.38fF -C1450 divider_1/tspc_2/Q divider_1/tspc_1/Z2 0.14fF -C1451 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF -C1452 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF -C1453 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF -C1454 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/B 0.08fF -C1455 divider_2/nor_1/Z1 divider_2/and_0/B 0.78fF -C1456 divider_1/and_0/out1 divider_1/and_0/B 0.18fF -C1457 pll_full_0/pd_0/DIV pll_full_0/pd_0/R 0.51fF -C1458 divbuf_17/OUT5 divbuf_17/OUT 43.38fF -C1459 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/Q 0.19fF -C1460 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.01fF -C1461 divider_2/nor_1/B divider_2/and_0/B 0.29fF -C1462 divbuf_9/IN divbuf_9/OUT5 0.00fF -C1463 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF -C1464 divider_0/mc2 divider_0/nor_0/B 0.06fF -C1465 divbuf_0/a_492_n240# divbuf_0/OUT 0.00fF -C1466 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_0/z1 0.24fF -C1467 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C1468 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF -C1469 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/v 1.30fF -C1470 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF -C1471 divbuf_20/OUT2 divbuf_20/OUT 0.06fF -C1472 divbuf_20/OUT3 divbuf_20/OUT5 0.01fF -C1473 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF -C1474 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C1475 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF -C1476 divider_1/nor_0/B divider_1/and_0/B 0.31fF -C1477 divider_1/tspc_2/Q divider_1/nor_0/A 0.55fF -C1478 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF -C1479 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/v 1.30fF -C1480 divbuf_0/OUT divbuf_0/OUT3 0.26fF -C1481 divider_2/tspc_0/Z2 divider_2/nor_0/B 0.20fF -C1482 divider_2/tspc_0/a_630_n680# divider_2/nor_1/B 0.35fF -C1483 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF -C1484 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF -C1485 pd_1/DOWN pd_1/R 0.36fF -C1486 divider_2/tspc_2/a_630_n680# divider_2/nor_0/A 0.35fF -C1487 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.29fF -C1488 pd_1/DOWN pd_1/UP 0.46fF -C1489 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Qbar1 0.20fF -C1490 pd_0/DOWN pd_0/R 0.36fF -C1491 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF -C1492 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF -C1493 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF -C1494 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z2 0.19fF -C1495 pd_1/REF pd_1/tspc_r_1/Qbar1 0.12fF -C1496 divbuf_17/IN divbuf_17/a_492_n240# 0.13fF -C1497 divider_1/mc2 divider_1/and_0/OUT 0.05fF -C1498 divbuf_14/OUT divbuf_14/OUT4 1.11fF -C1499 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF -C1500 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.26fF -C1501 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF -C1502 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z1 0.06fF -C1503 divider_1/nor_0/B divider_1/tspc_1/Q 0.51fF -C1504 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF -C1505 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.01fF -C1506 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C1507 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF -C1508 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF -C1509 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF -C1510 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C1511 divider_1/and_0/OUT divider_1/clk 0.04fF -C1512 divbuf_12/OUT2 divbuf_12/OUT5 0.02fF -C1513 divbuf_12/OUT3 divbuf_12/OUT4 5.16fF -C1514 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF -C1515 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF -C1516 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF -C1517 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF -C1518 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF -C1519 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF -C1520 divider_2/and_0/out1 divider_2/and_0/A 0.01fF -C1521 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF -C1522 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF -C1523 divbuf_14/OUT2 divbuf_14/OUT 0.06fF -C1524 divider_0/tspc_1/Q divider_0/tspc_1/Z3 0.05fF -C1525 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF -C1526 divider_0/Out divider_0/nor_1/B 0.22fF -C1527 divbuf_16/a_492_n240# divbuf_16/OUT 0.00fF -C1528 divider_2/prescaler_0/Out divider_2/prescaler_0/m1_2700_2190# 0.11fF -C1529 divider_1/tspc_2/Q divider_1/tspc_1/a_630_n680# 0.01fF -C1530 divider_1/tspc_1/Z1 divider_1/tspc_1/Z3 0.06fF -C1531 divbuf_6/OUT3 divbuf_6/OUT 0.26fF -C1532 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF -C1533 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.04fF -C1534 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C1535 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.58fF -C1536 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_0/vin 0.19fF -C1537 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z2 0.23fF -C1538 divider_1/nor_0/A divider_1/and_0/A 0.01fF -C1539 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF -C1540 divbuf_19/OUT divbuf_19/OUT3 0.26fF -C1541 divbuf_19/OUT5 divbuf_19/OUT4 20.26fF -C1542 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF -C1543 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a4 0.12fF -C1544 ro_complete_1/a2 ro_complete_1/cbank_2/switch_3/vin 0.09fF -C1545 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF -C1546 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF -C1547 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C1548 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF -C1549 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF -C1550 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.64fF -C1551 divbuf_17/IN divbuf_17/OUT5 0.00fF -C1552 ro_complete_1/cbank_0/v ro_complete_1/cbank_2/v 0.04fF -C1553 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_0/A 0.01fF -C1554 divider_1/prescaler_0/Out divider_1/tspc_2/Z4 0.12fF -C1555 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF -C1556 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.15fF -C1557 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF -C1558 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/B 0.22fF -C1559 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C1560 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C1561 divbuf_22/OUT2 divbuf_22/OUT 0.06fF -C1562 divbuf_22/OUT3 divbuf_22/OUT5 0.01fF -C1563 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF -C1564 divider_2/mc2 divider_2/nor_0/B 0.06fF -C1565 divider_2/tspc_2/Q divider_2/tspc_1/Z2 0.14fF -C1566 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF -C1567 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/R 0.01fF -C1568 divbuf_18/OUT5 divbuf_18/a_492_n240# 0.01fF -C1569 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF -C1570 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Qbar1 0.38fF -C1571 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF -C1572 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1573 divider_0/tspc_1/Z4 divider_0/nor_0/A 0.02fF -C1574 divider_1/tspc_0/Z1 divider_1/tspc_0/Z3 0.06fF -C1575 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z4 0.00fF -C1576 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF -C1577 divbuf_21/a_492_n240# divbuf_21/OUT5 0.01fF -C1578 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/Z3 0.05fF -C1579 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF -C1580 divbuf_18/OUT3 divbuf_18/OUT 0.26fF -C1581 divider_2/tspc_2/Q divider_2/nor_0/A 0.55fF -C1582 divider_2/nor_1/B divider_2/tspc_1/Q 0.22fF -C1583 divbuf_24/OUT2 divbuf_24/OUT5 0.02fF -C1584 divbuf_24/OUT3 divbuf_24/OUT4 5.16fF -C1585 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF -C1586 divider_0/nor_0/B divider_0/tspc_0/Z4 0.02fF -C1587 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF -C1588 divbuf_1/OUT4 divbuf_1/OUT 1.11fF -C1589 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF -C1590 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF -C1591 divider_0/nor_0/A divider_0/tspc_2/Z3 0.38fF -C1592 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF -C1593 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF -C1594 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C1595 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF -C1596 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF -C1597 divider_1/nor_0/A divider_1/tspc_2/Z1 0.03fF -C1598 divbuf_7/OUT3 divbuf_7/OUT 0.26fF -C1599 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF -C1600 filter_0/v filter_0/a_4216_n2998# 0.31fF -C1601 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z1 0.17fF -C1602 divbuf_19/OUT5 divbuf_19/a_492_n240# 0.01fF -C1603 divider_2/mc2 divider_2/and_0/A 0.16fF -C1604 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.05fF -C1605 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF -C1606 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF -C1607 divbuf_14/IN divbuf_14/a_492_n240# 0.13fF -C1608 divider_0/mc2 divider_0/and_0/A 0.16fF -C1609 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF -C1610 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF -C1611 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF -C1612 ro_complete_1/a0 ro_complete_1/cbank_1/v 0.05fF -C1613 divider_2/tspc_0/Z4 divider_2/tspc_0/a_630_n680# 0.12fF -C1614 divbuf_10/a_492_n240# divbuf_10/OUT 0.00fF -C1615 pd_0/tspc_r_1/Qbar1 pd_0/R 0.30fF -C1616 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z3 0.05fF -C1617 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1618 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF -C1619 divider_2/tspc_2/Q divider_2/tspc_1/Z1 0.01fF -C1620 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.35fF -C1621 divider_1/and_0/A divider_1/and_0/B 0.18fF -C1622 divbuf_9/OUT2 divbuf_9/OUT 0.06fF -C1623 divbuf_9/OUT3 divbuf_9/OUT5 0.01fF -C1624 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C1625 divider_2/tspc_1/Z2 divider_2/nor_0/A 0.15fF -C1626 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/D 0.32fF -C1627 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF -C1628 divider_2/nor_0/B divider_2/and_0/A 0.26fF -C1629 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF -C1630 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF -C1631 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C1632 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_4/vin 0.20fF -C1633 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF -C1634 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF -C1635 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/Q 0.04fF -C1636 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF -C1637 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF -C1638 divbuf_20/OUT4 divbuf_20/OUT 1.11fF -C1639 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_0/z1 0.24fF -C1640 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF -C1641 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C1642 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF -C1643 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF -C1644 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF -C1645 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF -C1646 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF -C1647 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF -C1648 divbuf_8/a_492_n240# divbuf_8/OUT5 0.01fF -C1649 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF -C1650 pd_1/R pd_1/tspc_r_1/Z3 0.29fF -C1651 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF -C1652 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF -C1653 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF -C1654 pd_1/tspc_r_1/Z3 pd_1/UP 0.03fF +C678 divider_1/nor_1/Z1 divider_1/nor_0/B 0.18fF +C679 divider_1/tspc_2/Q divider_1/tspc_1/Z2 0.14fF +C680 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/Out 0.05fF +C681 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z4 0.36fF +C682 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF +C683 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.01fF +C684 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF +C685 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C686 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF +C687 divider_1/and_0/OUT divider_1/clk 0.04fF +C688 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.31fF +C689 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF +C690 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C691 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF +C692 divbuf_12/OUT3 divbuf_12/OUT4 5.16fF +C693 divbuf_12/OUT2 divbuf_12/OUT5 0.02fF +C694 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF +C695 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF +C696 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF +C697 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/a_630_n680# 0.19fF +C698 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF +C699 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF +C700 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF +C701 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF +C702 divbuf_6/OUT3 divbuf_6/OUT 0.26fF +C703 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z1 0.00fF +C704 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.51fF +C705 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C706 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.58fF +C707 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF +C708 divbuf_18/OUT4 divbuf_18/OUT5 20.26fF +C709 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF +C710 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF +C711 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF +C712 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.64fF +C713 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF +C714 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF +C715 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C716 ro_complete_1/cbank_0/v ro_complete_1/cbank_2/v 0.04fF +C717 divbuf_19/a_492_n240# divbuf_19/IN 0.13fF +C718 divider_2/prescaler_0/Out divider_2/prescaler_0/m1_2700_2190# 0.11fF +C719 divider_1/prescaler_0/Out divider_1/tspc_2/Z2 0.11fF +C720 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.15fF +C721 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.14fF +C722 divider_1/nor_1/Z1 divider_1/and_0/B 0.78fF +C723 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C724 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C725 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF +C726 divbuf_22/OUT3 divbuf_22/OUT5 0.01fF +C727 divbuf_22/OUT2 divbuf_22/OUT 0.06fF +C728 pd_1/REF pd_1/tspc_r_1/Z3 0.65fF +C729 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF +C730 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF +C731 divider_0/tspc_2/Q divider_0/tspc_1/Z3 0.45fF +C732 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF +C733 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF +C734 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF +C735 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF +C736 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C737 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF +C738 divbuf_21/a_492_n240# divbuf_21/OUT5 0.01fF +C739 divider_1/tspc_0/a_630_n680# divider_1/Out 0.04fF +C740 divider_1/nor_0/B divider_1/and_0/A 0.26fF +C741 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF +C742 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF +C743 divbuf_24/OUT3 divbuf_24/OUT4 5.16fF +C744 divbuf_24/OUT2 divbuf_24/OUT5 0.02fF +C745 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF +C746 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF +C747 divider_2/nor_0/A divider_2/and_0/B 0.08fF +C748 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF +C749 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF +C750 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF +C751 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF +C752 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF +C753 divbuf_16/OUT5 divbuf_16/OUT4 20.26fF +C754 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF +C755 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF +C756 ro_complete_1/a4 ro_complete_1/cbank_2/switch_0/vin 0.12fF +C757 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF +C758 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C759 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF +C760 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF +C761 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF +C762 divbuf_7/OUT3 divbuf_7/OUT 0.26fF +C763 divider_2/prescaler_0/Out divider_2/tspc_2/Z3 0.45fF +C764 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF +C765 divider_1/nor_0/A divider_1/tspc_2/Z4 0.21fF +C766 divider_2/tspc_2/Q divider_2/tspc_2/a_630_n680# 0.04fF +C767 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.05fF +C768 divbuf_14/IN divbuf_14/a_492_n240# 0.13fF +C769 divider_0/mc2 divider_0/and_0/A 0.16fF +C770 divider_0/prescaler_0/Out divider_0/tspc_2/a_630_n680# 0.01fF +C771 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF +C772 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF +C773 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF +C774 divider_1/nor_0/Z1 divider_1/and_0/A 0.80fF +C775 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF +C776 ro_complete_1/a0 ro_complete_1/cbank_1/v 0.05fF +C777 divbuf_10/a_492_n240# divbuf_10/OUT 0.00fF +C778 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C779 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF +C780 divider_1/tspc_0/Z1 divider_1/tspc_1/Q 0.01fF +C781 divider_1/nor_0/B divider_1/tspc_1/Z4 0.21fF +C782 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/D 0.05fF +C783 divider_1/and_0/A divider_1/and_0/B 0.18fF +C784 pd_1/tspc_r_1/Qbar pd_1/UP 0.21fF +C785 divider_2/tspc_0/a_630_n680# divider_2/Out 0.04fF +C786 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/D 0.32fF +C787 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF +C788 divbuf_9/OUT3 divbuf_9/OUT5 0.01fF +C789 divbuf_9/OUT2 divbuf_9/OUT 0.06fF +C790 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF +C791 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF +C792 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C793 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF +C794 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF +C795 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/Q 0.04fF +C796 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF +C797 divbuf_1/OUT divbuf_1/OUT4 1.11fF +C798 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_4/vin 0.20fF +C799 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF +C800 divider_1/mc2 divider_1/nor_1/B 0.15fF +C801 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF +C802 ro_complete_1/cbank_2/switch_0/vin ro_complete_1/cbank_2/v 1.45fF +C803 divbuf_20/OUT4 divbuf_20/OUT 1.11fF +C804 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C805 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF +C806 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_0/z1 0.24fF +C807 divbuf_8/a_492_n240# divbuf_8/OUT5 0.01fF +C808 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF +C809 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF +C810 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/DOWN 0.21fF +C811 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF +C812 ro_complete_1/a2 ro_complete_1/cbank_1/switch_3/vin 0.09fF +C813 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF +C814 divider_0/tspc_2/Q divider_0/nor_0/B 0.22fF +C815 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF +C816 divbuf_14/OUT5 divbuf_14/OUT3 0.01fF +C817 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF +C818 divider_1/nor_1/B divider_1/tspc_0/Z1 0.03fF +C819 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z4 0.01fF +C820 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF +C821 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_0/B 0.18fF +C822 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z4 0.12fF +C823 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C824 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF +C825 divider_1/tspc_1/Q divider_1/tspc_0/Z3 0.45fF +C826 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.26fF +C827 divbuf_12/OUT4 divbuf_12/OUT5 20.26fF +C828 divbuf_12/OUT3 divbuf_12/OUT 0.26fF +C829 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF +C830 pd_0/REF pd_0/tspc_r_1/z5 0.04fF +C831 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF +C832 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF +C833 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z3 0.05fF +C834 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF +C835 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF +C836 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF +C837 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF +C838 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF +C839 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF +C840 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF +C841 divbuf_3/OUT2 divbuf_3/OUT 0.06fF +C842 ro_complete_1/a3 ro_complete_1/cbank_1/v 0.05fF +C843 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C844 divbuf_16/OUT divbuf_16/a_492_n240# 0.00fF +C845 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF +C846 divider_1/prescaler_0/tspc_0/Z2 divider_1/and_0/OUT 0.06fF +C847 divbuf_6/OUT5 divbuf_6/OUT 43.38fF +C848 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_0/B 0.02fF +C849 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF +C850 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C851 divbuf_11/a_492_n240# divbuf_11/OUT 0.00fF +C852 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF +C853 pd_1/tspc_r_1/Z2 pd_1/R 0.21fF +C854 divbuf_19/OUT divbuf_19/OUT2 0.06fF +C855 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF +C856 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF +C857 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_4/vin 0.20fF +C858 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C859 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF +C860 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF +C861 divbuf_19/a_492_n240# divbuf_19/OUT 0.00fF +C862 divider_1/tspc_0/Z2 divider_1/tspc_1/Q 0.14fF +C863 divider_1/nor_1/B divider_1/tspc_0/Z3 0.38fF +C864 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF +C865 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF +C866 divbuf_20/a_492_n240# divbuf_20/IN 0.13fF +C867 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/Z3 0.05fF +C868 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z2 0.16fF +C869 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C870 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C871 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.14fF +C872 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.78fF +C873 divbuf_22/OUT4 divbuf_22/OUT 1.11fF +C874 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF +C875 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF +C876 divbuf_18/OUT2 divbuf_18/OUT 0.06fF +C877 divbuf_13/a_492_n240# divbuf_13/OUT5 0.01fF +C878 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF +C879 divbuf_18/OUT5 divbuf_18/OUT 43.38fF +C880 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF +C881 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a1 0.14fF +C882 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/a3 0.09fF +C883 divider_2/nor_1/B divider_2/mc2 0.15fF +C884 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.45fF +C885 ro_complete_1/cbank_2/switch_5/vin ro_complete_1/cbank_2/v 1.30fF +C886 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C887 divbuf_21/OUT2 divbuf_21/OUT3 1.37fF +C888 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF +C889 divbuf_24/OUT4 divbuf_24/OUT5 20.26fF +C890 divbuf_24/OUT3 divbuf_24/OUT 0.26fF +C891 pd_1/and_pd_0/Out1 pd_1/and_pd_0/Z1 0.18fF +C892 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF +C893 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF +C894 divbuf_3/IN divbuf_3/a_492_n240# 0.13fF +C895 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF +C896 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/v 1.30fF +C897 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C898 divider_2/nor_1/B divider_2/tspc_0/Z2 0.40fF +C899 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_0/A 0.01fF +C900 divider_2/nor_1/B divider_2/tspc_0/Z4 0.22fF +C901 divider_1/tspc_1/Z3 divider_1/tspc_1/a_630_n680# 0.05fF +C902 divider_1/tspc_1/Z1 divider_1/nor_0/B 0.03fF +C903 divider_1/nor_1/B divider_1/tspc_0/Z2 0.40fF +C904 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF +C905 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF +C906 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z4 0.15fF +C907 pll_full_0/divbuf_0/IN pll_full_0/divider_0/nor_1/B 0.27fF +C908 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF +C909 divider_2/mc2 divider_2/prescaler_0/tspc_2/a_630_n680# 0.33fF +C910 divider_2/prescaler_0/Out divider_2/tspc_2/Z4 0.12fF +C911 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF +C912 divbuf_7/OUT5 divbuf_7/OUT 43.38fF +C913 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF +C914 divbuf_23/a_492_n240# divbuf_23/OUT 0.00fF +C915 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF +C916 divider_2/tspc_2/Q divider_2/nor_0/A 0.55fF +C917 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Q 0.20fF +C918 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF +C919 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C920 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z3 0.05fF +C921 divider_0/prescaler_0/Out divider_0/nor_0/A 0.15fF +C922 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF +C923 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF +C924 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF +C925 divbuf_25/OUT4 divbuf_25/OUT5 20.26fF +C926 divider_0/and_0/B divider_0/and_0/Z1 0.07fF +C927 divider_1/mc2 divider_1/and_0/out1 0.06fF +C928 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Q 0.04fF +C929 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF +C930 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/D 0.11fF +C931 divbuf_10/IN divbuf_10/OUT5 0.00fF +C932 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF +C933 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C934 divbuf_22/a_492_n240# divbuf_22/IN 0.13fF +C935 divbuf_9/OUT4 divbuf_9/OUT 1.11fF +C936 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF +C937 divbuf_18/OUT4 divbuf_18/OUT 1.11fF +C938 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/tspc_0/D 0.04fF +C939 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF +C940 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF +C941 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF +C942 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF +C943 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF +C944 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF +C945 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C946 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF +C947 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF +C948 divbuf_16/OUT5 divbuf_16/OUT2 0.02fF +C949 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF +C950 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF +C951 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF +C952 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/Q 0.04fF +C953 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF +C954 divider_2/tspc_2/Q divider_2/tspc_1/Z1 0.01fF +C955 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF +C956 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF +C957 divbuf_8/OUT2 divbuf_8/OUT3 1.37fF +C958 io_clamp_low[2] io_clamp_high[2] 0.53fF +C959 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF +C960 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF +C961 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF +C962 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF +C963 io_clamp_high[1] io_analog[5] 0.53fF +C964 divider_0/tspc_2/a_630_n680# divider_0/nor_0/A 0.35fF +C965 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF +C966 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF +C967 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF +C968 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF +C969 divider_1/nor_1/B divider_1/tspc_1/a_630_n680# 0.00fF +C970 divbuf_19/OUT5 divbuf_19/OUT3 0.01fF +C971 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF +C972 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C973 pd_0/R pd_0/and_pd_0/Z1 0.02fF +C974 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF +C975 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF +C976 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF +C977 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF +C978 divbuf_12/OUT5 divbuf_12/OUT 43.38fF +C979 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF +C980 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_2/D 0.16fF +C981 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.03fF +C982 ro_complete_1/a4 ro_complete_1/cbank_2/v 0.05fF +C983 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_0/vin 0.19fF +C984 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C985 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.11fF +C986 divider_1/tspc_1/Z2 divider_1/tspc_1/Z4 0.36fF +C987 divbuf_11/IN divbuf_11/OUT5 0.00fF +C988 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Qbar1 0.38fF +C989 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF +C990 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF +C991 divbuf_9/a_492_n240# divbuf_9/IN 0.13fF +C992 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF +C993 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF +C994 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF +C995 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C996 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF +C997 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF +C998 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C999 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF +C1000 pd_0/DIV pd_0/R 0.51fF +C1001 divbuf_18/IN divbuf_18/OUT5 0.00fF +C1002 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1003 pd_1/R pd_1/and_pd_0/Out1 0.33fF +C1004 pd_1/REF pd_1/tspc_r_1/Z4 0.02fF +C1005 pd_1/tspc_r_1/Qbar1 pd_1/UP 0.11fF +C1006 divbuf_13/OUT2 divbuf_13/OUT3 1.37fF +C1007 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF +C1008 divider_0/mc2 divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF +C1009 divider_0/nor_1/Z1 divider_0/nor_0/B 0.18fF +C1010 divbuf_25/OUT divbuf_25/OUT4 1.11fF +C1011 divider_0/nor_1/B divider_0/tspc_0/Z1 0.03fF +C1012 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF +C1013 divbuf_2/OUT4 divbuf_2/OUT 1.11fF +C1014 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a1 0.14fF +C1015 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF +C1016 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF +C1017 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z2 0.01fF +C1018 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/Out 0.21fF +C1019 divbuf_21/OUT3 divbuf_21/OUT4 5.16fF +C1020 divbuf_21/OUT2 divbuf_21/OUT5 0.02fF +C1021 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.45fF +C1022 pd_1/DIV pd_1/tspc_r_0/Qbar1 0.12fF +C1023 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF +C1024 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z1 0.09fF +C1025 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z2 0.19fF +C1026 divbuf_12/a_492_n240# divbuf_12/OUT2 0.42fF +C1027 divbuf_24/OUT5 divbuf_24/OUT 43.38fF +C1028 divbuf_14/OUT divbuf_14/OUT5 43.38fF +C1029 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF +C1030 divider_2/tspc_1/Q divider_2/tspc_0/Z2 0.14fF +C1031 ro_complete_1/a5 ro_complete_1/cbank_2/switch_0/vin 0.09fF +C1032 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF +C1033 divider_2/tspc_1/Q divider_2/tspc_0/Z4 0.15fF +C1034 divider_1/tspc_1/Z3 divider_1/nor_0/B 0.38fF +C1035 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF +C1036 divider_2/mc2 divider_2/nor_0/B 0.06fF +C1037 pd_1/DOWN pd_1/tspc_r_0/Z3 0.03fF +C1038 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/R 0.27fF +C1039 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Q 0.04fF +C1040 divbuf_23/IN divbuf_23/OUT5 0.00fF +C1041 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C1042 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF +C1043 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z4 0.12fF +C1044 divider_0/prescaler_0/Out divider_0/tspc_2/Z2 0.11fF +C1045 divider_0/tspc_0/Z3 divider_0/tspc_0/Z2 0.16fF +C1046 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF +C1047 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.14fF +C1048 divider_0/nor_1/Z1 divider_0/and_0/B 0.78fF +C1049 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF +C1050 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C1051 divbuf_10/OUT3 divbuf_10/OUT5 0.01fF +C1052 divbuf_10/OUT2 divbuf_10/OUT 0.06fF +C1053 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C1054 divider_1/nor_0/B divider_1/tspc_1/Q 0.51fF +C1055 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF +C1056 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF +C1057 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF +C1058 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF +C1059 divider_2/tspc_0/Z2 divider_2/nor_0/B 0.20fF +C1060 divider_1/and_0/B divider_1/and_0/Z1 0.07fF +C1061 pd_1/R pd_1/tspc_r_1/Z3 0.29fF +C1062 divbuf_17/OUT5 divbuf_17/OUT 43.38fF +C1063 divider_2/nor_0/B divider_2/tspc_0/Z4 0.02fF +C1064 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/nand_1/z1 0.01fF +C1065 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF +C1066 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF +C1067 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF +C1068 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF +C1069 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1070 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF +C1071 divbuf_4/OUT3 divbuf_4/OUT 0.26fF +C1072 pll_full_0/divbuf_0/IN pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF +C1073 divider_1/tspc_0/Z1 divider_1/tspc_0/Z3 0.06fF +C1074 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF +C1075 divbuf_8/OUT3 divbuf_8/OUT4 5.16fF +C1076 divbuf_8/OUT2 divbuf_8/OUT5 0.02fF +C1077 pd_0/DOWN pd_0/UP 0.46fF +C1078 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF +C1079 divbuf_17/OUT4 divbuf_17/OUT 1.11fF +C1080 divider_2/tspc_2/Q divider_2/tspc_1/Z3 0.45fF +C1081 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z2 0.01fF +C1082 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF +C1083 divbuf_24/a_492_n240# divbuf_24/OUT2 0.42fF +C1084 pd_1/UP pd_1/and_pd_0/Z1 0.06fF +C1085 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF +C1086 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF +C1087 divider_0/Out divider_0/nor_1/B 0.22fF +C1088 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF +C1089 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/a0 0.13fF +C1090 io_clamp_low[0] io_analog[4] 0.53fF +C1091 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF +C1092 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF +C1093 divider_0/prescaler_0/tspc_2/Q divider_0/clk 0.05fF +C1094 divider_1/nor_1/B divider_1/nor_0/B 0.47fF +C1095 divider_1/tspc_1/Z1 divider_1/tspc_1/Z2 1.07fF +C1096 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z1 0.08fF +C1097 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF +C1098 divbuf_5/OUT3 divbuf_5/OUT 0.26fF +C1099 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF +C1100 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF +C1101 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/nor_0/A 0.03fF +C1102 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/Z2 0.40fF +C1103 divider_1/tspc_2/a_630_n680# divider_1/nor_0/A 0.35fF +C1104 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF +C1105 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z3 0.09fF +C1106 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF +C1107 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF +C1108 divbuf_1/OUT5 divbuf_1/OUT 43.38fF +C1109 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF +C1110 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF +C1111 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF +C1112 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.00fF +C1113 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF +C1114 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF +C1115 ro_complete_1/a1 ro_complete_1/cbank_1/v 0.05fF +C1116 divider_0/and_0/out1 divider_0/and_0/B 0.18fF +C1117 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF +C1118 divider_1/mc2 divider_1/nor_0/A 0.04fF +C1119 divider_1/tspc_0/Z1 divider_1/tspc_0/Z2 1.07fF +C1120 divbuf_11/OUT3 divbuf_11/OUT5 0.01fF +C1121 divbuf_11/OUT2 divbuf_11/OUT 0.06fF +C1122 divbuf_19/a_492_n240# divbuf_19/OUT2 0.42fF +C1123 divbuf_17/OUT3 divbuf_17/OUT 0.26fF +C1124 pd_1/DOWN pd_1/UP 0.46fF +C1125 pd_1/tspc_r_0/Z3 pd_1/R 0.27fF +C1126 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF +C1127 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF +C1128 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF +C1129 divider_0/nor_0/B divider_0/tspc_2/a_630_n680# 0.01fF +C1130 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Q 0.05fF +C1131 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF +C1132 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF +C1133 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z2 0.19fF +C1134 divbuf_16/OUT divbuf_16/OUT3 0.26fF +C1135 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF +C1136 divider_1/nor_1/B divider_1/and_0/B 0.29fF +C1137 divbuf_20/a_492_n240# divbuf_20/OUT5 0.01fF +C1138 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_0/A 0.15fF +C1139 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z3 0.45fF +C1140 pd_1/DIV pd_1/tspc_r_0/Z1 0.17fF +C1141 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF +C1142 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF +C1143 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF +C1144 divider_2/mc2 divider_2/and_0/out1 0.06fF +C1145 divbuf_13/OUT3 divbuf_13/OUT4 5.16fF +C1146 divbuf_13/OUT2 divbuf_13/OUT5 0.02fF +C1147 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF +C1148 divider_2/and_0/OUT divider_2/and_0/B 0.01fF +C1149 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF +C1150 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z4 0.01fF +C1151 ro_complete_1/a4 ro_complete_1/cbank_2/switch_1/vin 0.09fF +C1152 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/v 1.30fF +C1153 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C1154 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.04fF +C1155 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF +C1156 divider_1/tspc_0/Z2 divider_1/tspc_0/Z3 0.16fF +C1157 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF +C1158 divbuf_21/OUT4 divbuf_21/OUT5 20.26fF +C1159 divbuf_21/OUT3 divbuf_21/OUT 0.26fF +C1160 pd_1/DIV pd_1/R 0.51fF +C1161 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF +C1162 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF +C1163 divider_2/tspc_1/Z2 divider_2/nor_0/B 0.30fF +C1164 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF +C1165 divbuf_14/OUT divbuf_14/a_492_n240# 0.00fF +C1166 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF +C1167 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.06fF +C1168 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF +C1169 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C1170 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF +C1171 ro_complete_1/a3 ro_complete_1/cbank_2/switch_2/vin 0.09fF +C1172 divbuf_15/OUT3 divbuf_15/OUT4 5.16fF +C1173 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF +C1174 divider_1/tspc_0/Z4 divider_1/tspc_1/Q 0.15fF +C1175 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.18fF +C1176 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C1177 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1178 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.64fF +C1179 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF +C1180 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z1 0.03fF +C1181 divbuf_23/OUT3 divbuf_23/OUT5 0.01fF +C1182 divbuf_23/OUT2 divbuf_23/OUT 0.06fF +C1183 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF +C1184 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C1185 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF +C1186 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF +C1187 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a3 0.13fF +C1188 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF +C1189 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF +C1190 divbuf_3/OUT3 divbuf_3/OUT 0.26fF +C1191 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/v 1.30fF +C1192 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1193 divbuf_10/OUT4 divbuf_10/OUT 1.11fF +C1194 divider_1/tspc_0/a_630_n680# divider_1/tspc_1/Q 0.01fF +C1195 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF +C1196 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF +C1197 divbuf_22/a_492_n240# divbuf_22/OUT5 0.01fF +C1198 pd_1/R pd_1/UP 0.45fF +C1199 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_1/z1 0.21fF +C1200 divider_2/nor_0/B divider_2/and_0/A 0.26fF +C1201 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF +C1202 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF +C1203 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/Q 0.19fF +C1204 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.01fF +C1205 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/v 1.30fF +C1206 divbuf_4/OUT5 divbuf_4/OUT 43.38fF +C1207 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C1208 divider_1/tspc_0/Z4 divider_1/nor_1/B 0.22fF +C1209 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C1210 pd_0/R pd_0/REF 0.61fF +C1211 divbuf_17/OUT2 divbuf_17/OUT 0.06fF +C1212 divbuf_17/IN divbuf_17/OUT5 0.00fF +C1213 divbuf_8/OUT4 divbuf_8/OUT5 20.26fF +C1214 divbuf_8/OUT3 divbuf_8/OUT 0.26fF +C1215 io_clamp_low[1] io_clamp_high[1] 0.53fF +C1216 divider_0/tspc_1/Z3 divider_0/tspc_1/a_630_n680# 0.05fF +C1217 divider_0/tspc_1/Z1 divider_0/nor_0/B 0.03fF +C1218 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.35fF +C1219 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF +C1220 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF +C1221 divbuf_2/IN divbuf_2/a_492_n240# 0.13fF +C1222 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF +C1223 divbuf_15/OUT divbuf_15/OUT4 1.11fF +C1224 divider_0/nor_0/A divider_0/tspc_2/Z2 0.23fF +C1225 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.29fF +C1226 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_4/vin 0.20fF +C1227 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C1228 divbuf_5/OUT5 divbuf_5/OUT 43.38fF +C1229 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF +C1230 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.01fF +C1231 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF +C1232 divider_1/nor_1/B divider_1/tspc_0/a_630_n680# 0.35fF +C1233 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z3 0.11fF +C1234 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF +C1235 divider_2/prescaler_0/Out divider_2/tspc_2/a_630_n680# 0.01fF +C1236 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF +C1237 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF +C1238 divider_1/prescaler_0/tspc_2/Q divider_1/clk 0.05fF +C1239 divider_2/nor_0/B divider_2/tspc_1/Z4 0.21fF +C1240 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF +C1241 divbuf_15/IN divbuf_15/OUT5 0.00fF +C1242 divider_0/mc2 divider_0/and_0/out1 0.06fF +C1243 divider_0/nor_0/B divider_0/nor_1/B 0.47fF +C1244 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF +C1245 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF +C1246 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF +C1247 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF +C1248 divider_0/nor_0/Z1 divider_0/and_0/A 0.80fF +C1249 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF +C1250 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF +C1251 ro_complete_1/a5 ro_complete_1/cbank_2/v 0.08fF +C1252 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1253 divbuf_10/a_492_n240# divbuf_10/IN 0.13fF +C1254 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF +C1255 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF +C1256 divbuf_11/OUT4 divbuf_11/OUT 1.11fF +C1257 divider_2/tspc_0/Z2 divider_2/tspc_0/Z1 1.07fF +C1258 divider_2/nor_0/Z1 divider_2/and_0/A 0.80fF +C1259 divider_1/and_0/out1 divider_1/and_0/B 0.18fF +C1260 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/A 0.01fF +C1261 pd_1/tspc_r_1/Z1 pd_1/REF 0.17fF +C1262 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Z4 0.20fF +C1263 divider_2/tspc_0/Z1 divider_2/tspc_0/Z4 0.00fF +C1264 divbuf_9/a_492_n240# divbuf_9/OUT5 0.01fF +C1265 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF +C1266 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF +C1267 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF +C1268 divider_0/Out divider_0/tspc_0/a_630_n680# 0.04fF +C1269 divbuf_15/a_492_n240# divbuf_15/OUT 0.00fF +C1270 divider_0/tspc_1/Q divider_0/tspc_0/Z1 0.01fF +C1271 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF +C1272 divider_0/nor_0/B divider_0/nor_0/A 1.21fF +C1273 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF +C1274 divbuf_20/OUT2 divbuf_20/OUT3 1.37fF +C1275 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_0/A 0.01fF +C1276 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z4 0.12fF +C1277 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF +C1278 divider_1/nor_0/B divider_1/tspc_2/a_630_n680# 0.01fF +C1279 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Q 0.05fF +C1280 divider_1/prescaler_0/Out divider_1/clk 0.51fF +C1281 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF +C1282 pd_1/UP pd_1/tspc_r_1/z5 0.03fF +C1283 divbuf_13/OUT4 divbuf_13/OUT5 20.26fF +C1284 divbuf_13/OUT3 divbuf_13/OUT 0.26fF +C1285 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF +C1286 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF +C1287 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF +C1288 divbuf_15/OUT2 divbuf_15/a_492_n240# 0.42fF +C1289 divider_1/prescaler_0/m1_2700_2190# divider_1/and_0/OUT 0.14fF +C1290 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF +C1291 divider_0/nor_1/B divider_0/and_0/B 0.29fF +C1292 ro_complete_1/a2 ro_complete_1/cbank_2/v 0.05fF +C1293 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF +C1294 divider_1/mc2 divider_1/nor_0/B 0.06fF +C1295 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z3 0.06fF +C1296 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF +C1297 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C1298 divbuf_21/OUT5 divbuf_21/OUT 43.38fF +C1299 pll_full_0/divider_0/tspc_1/Z4 pll_full_0/divider_0/nor_0/A 0.02fF +C1300 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_0/Z2 0.20fF +C1301 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF +C1302 divbuf_12/a_492_n240# divbuf_12/OUT 0.00fF +C1303 pd_1/DIV pd_1/tspc_r_0/Z4 0.02fF +C1304 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF +C1305 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF +C1306 divider_2/and_0/out1 divider_2/and_0/A 0.01fF +C1307 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF +C1308 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF +C1309 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.35fF +C1310 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF +C1311 divider_0/tspc_1/Q divider_0/nor_1/B 0.22fF +C1312 divbuf_15/OUT4 divbuf_15/OUT5 20.26fF +C1313 divider_0/nor_0/A divider_0/and_0/B 0.08fF +C1314 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF +C1315 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/a0 0.09fF +C1316 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C1317 divbuf_19/OUT5 divbuf_19/IN 0.00fF +C1318 divider_1/tspc_2/Q divider_1/tspc_1/Z4 0.15fF +C1319 divbuf_6/IN divbuf_6/OUT5 0.00fF +C1320 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_0/B 0.30fF +C1321 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF +C1322 divbuf_11/a_492_n240# divbuf_11/IN 0.13fF +C1323 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF +C1324 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF +C1325 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z3 0.38fF +C1326 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF +C1327 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF +C1328 divbuf_23/OUT4 divbuf_23/OUT 1.11fF +C1329 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/switch_1/vin 0.19fF +C1330 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF +C1331 divbuf_1/OUT2 divbuf_1/OUT 0.06fF +C1332 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT3 0.01fF +C1333 divbuf_25/OUT3 divbuf_25/OUT5 0.01fF +C1334 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.05fF +C1335 divider_2/nor_1/B divider_2/tspc_1/a_630_n680# 0.00fF +C1336 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/Out 0.05fF +C1337 divbuf_3/OUT5 divbuf_3/OUT 43.38fF +C1338 divider_1/tspc_2/Q divider_1/tspc_2/Z3 0.05fF +C1339 divider_1/mc2 divider_1/and_0/B 0.20fF +C1340 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.04fF +C1341 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF +C1342 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C1343 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF +C1344 divbuf_22/OUT2 divbuf_22/OUT3 1.37fF +C1345 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF +C1346 divbuf_18/OUT2 divbuf_18/a_492_n240# 0.42fF +C1347 divider_2/mc2 divider_2/nor_0/A 0.04fF +C1348 divider_2/tspc_0/Z2 divider_2/tspc_0/Z3 0.16fF +C1349 divbuf_18/OUT5 divbuf_18/a_492_n240# 0.01fF +C1350 divider_2/prescaler_0/tspc_1/Q divider_2/nor_0/A 0.03fF +C1351 divider_2/tspc_0/Z3 divider_2/tspc_0/Z4 0.65fF +C1352 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF +C1353 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C1354 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1355 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF +C1356 divbuf_15/a_492_n240# divbuf_15/OUT5 0.01fF +C1357 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/D 0.32fF +C1358 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF +C1359 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/Q 0.19fF +C1360 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.01fF +C1361 divbuf_21/a_492_n240# divbuf_21/OUT2 0.42fF +C1362 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z2 0.14fF +C1363 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C1364 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z2 0.71fF +C1365 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF +C1366 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF +C1367 divbuf_8/OUT5 divbuf_8/OUT 43.38fF +C1368 divbuf_24/a_492_n240# divbuf_24/OUT 0.00fF +C1369 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF +C1370 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1371 divider_0/tspc_1/Q divider_0/tspc_1/a_630_n680# 0.04fF +C1372 divider_0/tspc_1/Z3 divider_0/nor_0/B 0.38fF +C1373 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF +C1374 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF +C1375 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1376 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF +C1377 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z4 0.28fF +C1378 divider_2/prescaler_0/Out divider_2/nor_0/A 0.15fF +C1379 divider_1/nor_0/A divider_1/tspc_2/Z2 0.23fF +C1380 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.29fF +C1381 divbuf_7/IN divbuf_7/OUT5 0.00fF +C1382 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.06fF +C1383 pd_1/tspc_r_0/Z2 pd_1/R 0.21fF +C1384 divbuf_23/a_492_n240# divbuf_23/IN 0.13fF +C1385 divider_2/nor_1/B divider_2/tspc_1/Q 0.22fF +C1386 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF +C1387 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF +C1388 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF +C1389 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF +C1390 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF +C1391 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF +C1392 ro_complete_1/a0 ro_complete_1/cbank_2/switch_4/vin 0.13fF +C1393 ro_complete_1/cbank_0/v ro_complete_1/cbank_1/v 1.27fF +C1394 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_740_n680# 0.33fF +C1395 divider_1/nor_0/B divider_1/tspc_0/Z2 0.20fF +C1396 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Q 0.91fF +C1397 divider_1/prescaler_0/tspc_1/Z2 divider_1/and_0/OUT 0.06fF +C1398 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF +C1399 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF +C1400 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z3 0.25fF +C1401 pd_1/tspc_r_0/Qbar1 pd_1/tspc_r_0/z5 0.20fF +C1402 divbuf_9/OUT2 divbuf_9/OUT3 1.37fF +C1403 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C1404 divbuf_0/OUT5 divbuf_0/OUT4 20.26fF +C1405 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF +C1406 divider_0/tspc_0/Z4 divider_0/tspc_0/Z1 0.00fF +C1407 divider_2/nor_1/B divider_2/nor_0/B 0.47fF +C1408 divider_1/nor_0/B divider_1/nor_0/A 1.21fF +C1409 divbuf_20/OUT3 divbuf_20/OUT4 5.16fF +C1410 divbuf_20/OUT2 divbuf_20/OUT5 0.02fF +C1411 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF +C1412 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF +C1413 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF +C1414 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF +C1415 divbuf_8/a_492_n240# divbuf_8/OUT2 0.42fF +C1416 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF +C1417 divbuf_13/OUT5 divbuf_13/OUT 43.38fF +C1418 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF +C1419 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF +C1420 divider_2/nor_0/A divider_2/tspc_2/Z1 0.03fF +C1421 divbuf_25/OUT3 divbuf_25/OUT 0.26fF +C1422 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF +C1423 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z1 0.08fF +C1424 divider_0/mc2 divider_0/nor_1/B 0.15fF +C1425 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF +C1426 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF +C1427 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/cbank_0/v 1.30fF +C1428 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C1429 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1430 divbuf_19/OUT4 divbuf_19/OUT5 20.26fF +C1431 divbuf_16/OUT5 divbuf_16/a_492_n240# 0.01fF +C1432 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_2/D 0.16fF +C1433 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF +C1434 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C1435 divider_1/tspc_2/Q divider_1/tspc_1/Z1 0.01fF +C1436 divider_1/tspc_0/Z4 divider_1/tspc_0/Z1 0.00fF +C1437 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF +C1438 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z4 0.00fF +C1439 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF +C1440 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF +C1441 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/A 0.26fF +C1442 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF +C1443 divbuf_12/IN divbuf_12/OUT5 0.00fF +C1444 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/R 0.01fF +C1445 divider_0/mc2 divider_0/nor_0/A 0.04fF +C1446 divider_0/tspc_0/Z4 divider_0/nor_1/B 0.22fF +C1447 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF +C1448 divbuf_1/OUT divbuf_1/OUT3 0.26fF +C1449 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1450 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF +C1451 divbuf_6/OUT2 divbuf_6/OUT 0.06fF +C1452 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C1453 divbuf_19/OUT5 divbuf_19/OUT 43.38fF +C1454 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z2 0.16fF +C1455 divider_1/tspc_1/a_630_n680# divider_1/nor_0/B 0.35fF +C1456 divbuf_17/OUT4 divbuf_17/OUT5 20.26fF +C1457 divider_1/nor_0/A divider_1/and_0/B 0.08fF +C1458 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF +C1459 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z4 0.21fF +C1460 pd_1/DOWN pd_1/tspc_r_0/z5 0.03fF +C1461 divider_2/tspc_1/Z2 divider_2/nor_0/A 0.15fF +C1462 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/D 0.03fF +C1463 divbuf_16/OUT5 divbuf_16/OUT 43.38fF +C1464 divbuf_14/OUT divbuf_14/OUT3 0.26fF +C1465 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Q 0.20fF +C1466 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF +C1467 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF +C1468 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF +C1469 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT4 20.26fF +C1470 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1471 divider_2/tspc_1/Q divider_2/tspc_1/a_630_n680# 0.04fF +C1472 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/nor_0/A 0.55fF +C1473 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z4 0.21fF +C1474 divider_1/tspc_0/Z4 divider_1/tspc_0/Z3 0.65fF +C1475 divider_1/prescaler_0/tspc_2/Z2 divider_1/and_0/OUT 0.05fF +C1476 divbuf_22/OUT3 divbuf_22/OUT4 5.16fF +C1477 divbuf_22/OUT2 divbuf_22/OUT5 0.02fF +C1478 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF +C1479 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF +C1480 cp_0/a_1710_0# cp_0/out 0.84fF +C1481 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF +C1482 divbuf_13/a_492_n240# divbuf_13/OUT2 0.42fF +C1483 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF +C1484 divider_0/tspc_2/Q divider_0/tspc_1/Z2 0.14fF +C1485 divider_0/tspc_0/a_630_n680# divider_0/tspc_1/Q 0.01fF +C1486 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.05fF +C1487 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF +C1488 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C1489 divbuf_14/OUT5 divbuf_14/OUT4 20.26fF +C1490 divider_0/nor_0/B divider_0/and_0/B 0.31fF +C1491 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/tspc_0/D 0.04fF +C1492 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF +C1493 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C1494 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF +C1495 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C1496 divbuf_17/OUT3 divbuf_17/OUT5 0.01fF +C1497 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z3 0.05fF +C1498 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/D 0.32fF +C1499 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF +C1500 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF +C1501 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.35fF +C1502 io_clamp_low[0] io_clamp_high[0] 0.53fF +C1503 divider_2/nor_0/A divider_2/and_0/A 0.01fF +C1504 divbuf_24/IN divbuf_24/OUT5 0.00fF +C1505 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF +C1506 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF +C1507 divider_0/tspc_1/Q divider_0/nor_0/B 0.51fF +C1508 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF +C1509 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF +C1510 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF +C1511 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF +C1512 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C1513 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C1514 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF +C1515 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF +C1516 divbuf_17/OUT3 divbuf_17/OUT4 5.16fF +C1517 divider_1/mc2 divider_1/and_0/OUT 0.05fF +C1518 divider_1/tspc_0/Z4 divider_1/tspc_0/Z2 0.36fF +C1519 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF +C1520 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF +C1521 divbuf_7/OUT2 divbuf_7/OUT 0.06fF +C1522 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.26fF +C1523 divider_2/prescaler_0/Out divider_2/tspc_2/Z2 0.11fF +C1524 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF +C1525 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z4 0.14fF +C1526 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF +C1527 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_0/A 0.01fF +C1528 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF +C1529 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.43fF +C1530 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF +C1531 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF +C1532 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1533 divbuf_10/a_492_n240# divbuf_10/OUT5 0.01fF +C1534 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_740_n680# 0.08fF +C1535 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z2 0.01fF +C1536 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF +C1537 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF +C1538 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/D 0.09fF +C1539 divbuf_9/OUT3 divbuf_9/OUT4 5.16fF +C1540 divbuf_9/OUT2 divbuf_9/OUT5 0.02fF +C1541 pd_1/tspc_r_1/Qbar pd_1/tspc_r_1/Qbar1 0.01fF +C1542 divider_2/tspc_1/Z4 divider_2/nor_0/A 0.02fF +C1543 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C1544 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C1545 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF +C1546 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF +C1547 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF +C1548 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF +C1549 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF +C1550 divider_2/tspc_1/Q divider_2/nor_0/B 0.51fF +C1551 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF +C1552 divbuf_20/OUT4 divbuf_20/OUT5 20.26fF +C1553 divbuf_20/OUT3 divbuf_20/OUT 0.26fF +C1554 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C1555 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.64fF +C1556 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF +C1557 divider_2/mc2 divider_2/and_0/B 0.20fF +C1558 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF +C1559 divbuf_18/a_492_n240# divbuf_18/OUT 0.00fF +C1560 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF +C1561 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF +C1562 divider_2/nor_0/A divider_2/tspc_2/Z3 0.38fF +C1563 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF +C1564 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF +C1565 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF +C1566 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1567 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z3 0.11fF +C1568 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/switch_5/vin 0.20fF +C1569 io_clamp_high[2] io_analog[6] 0.53fF +C1570 divider_2/nor_1/B divider_2/nor_1/Z1 0.06fF +C1571 divbuf_16/IN divbuf_16/a_492_n240# 0.13fF +C1572 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF +C1573 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF +C1574 divider_1/tspc_2/Q divider_1/tspc_1/Z3 0.45fF +C1575 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Z4 0.65fF +C1576 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF +C1577 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1578 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C1579 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.46fF +C1580 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z2 1.07fF +C1581 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF +C1582 divbuf_12/OUT3 divbuf_12/OUT5 0.01fF +C1583 divbuf_12/OUT2 divbuf_12/OUT 0.06fF +C1584 pd_0/R pd_0/and_pd_0/Out1 0.33fF +C1585 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF +C1586 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF +C1587 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF +C1588 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF +C1589 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF +C1590 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1591 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C1592 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/v 1.30fF +C1593 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF +C1594 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z2 0.36fF +C1595 divbuf_6/OUT4 divbuf_6/OUT 1.11fF +C1596 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C1597 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF +C1598 divbuf_17/OUT2 divbuf_17/OUT5 0.02fF +C1599 divbuf_11/a_492_n240# divbuf_11/OUT5 0.01fF +C1600 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF +C1601 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF +C1602 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF +C1603 divbuf_25/OUT2 divbuf_25/OUT3 1.37fF +C1604 divbuf_0/OUT5 divbuf_0/OUT 43.38fF +C1605 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF +C1606 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF +C1607 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Q 0.04fF +C1608 divider_0/prescaler_0/Out divider_0/clk 0.51fF +C1609 ro_complete_1/a0 ro_complete_1/cbank_2/switch_5/vin 0.09fF +C1610 divider_2/nor_1/B divider_2/tspc_0/Z1 0.03fF +C1611 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C1612 divider_1/tspc_1/Z2 divider_1/nor_0/A 0.15fF +C1613 divider_1/prescaler_0/Out divider_1/tspc_2/Z3 0.45fF +C1614 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Q 0.20fF +C1615 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF +C1616 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C1617 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z1 0.06fF +C1618 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C1619 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF +C1620 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF +C1621 divbuf_22/OUT4 divbuf_22/OUT5 20.26fF +C1622 divbuf_22/OUT3 divbuf_22/OUT 0.26fF +C1623 cp_0/a_1710_0# cp_0/down 0.32fF +C1624 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF +C1625 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Z1 0.02fF +C1626 pd_1/REF pd_1/tspc_r_1/Qbar1 0.12fF +C1627 divider_2/and_0/OUT divider_2/clk 0.04fF +C1628 divider_0/mc2 divider_0/nor_0/B 0.06fF +C1629 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF +C1630 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF +C1631 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF +C1632 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF +C1633 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C1634 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1635 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF +C1636 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/nand_1/z1 0.01fF +C1637 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF +C1638 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF +C1639 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF +C1640 divider_1/nor_0/B divider_1/and_0/B 0.31fF +C1641 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/tspc_0/D 0.04fF +C1642 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF +C1643 divbuf_21/a_492_n240# divbuf_21/OUT 0.00fF +C1644 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1645 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF +C1646 pd_0/R pd_0/tspc_r_1/Z2 0.21fF +C1647 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF +C1648 divbuf_24/OUT3 divbuf_24/OUT5 0.01fF +C1649 divbuf_24/OUT2 divbuf_24/OUT 0.06fF +C1650 divider_0/tspc_0/Z4 divider_0/nor_0/B 0.02fF +C1651 divider_0/tspc_2/Q divider_0/tspc_1/Z4 0.15fF +C1652 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF +C1653 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/v 1.30fF +C1654 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF Xpd_0 vssa1 vssa1 pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd Xpd_1 VDD vssa1 pd_1/REF pd_1/DIV pd_1/UP pd_1/DOWN pd_1/R pd -Xcp_0 cp_0/vbias vdda1 gnd cp_0/out cp_0/down cp_0/upbar cp +Xcp_0 cp_0/vbias vssa1 gnd cp_0/out cp_0/down cp_0/upbar cp Xfilter_0 vssa1 filter_0/v filter Xro_complete_0 ro_complete_0/a0 ro_complete_0/a1 ro_complete_0/a5 ro_complete_0/a4 + ro_complete_0/a3 ro_complete_0/a2 ro_complete -Xdivbuf_0 vdda1 divbuf_0/IN divbuf_0/OUT divbuf_0/OUT2 divbuf_0/OUT3 divbuf_0/OUT4 +Xdivbuf_0 vssa1 divbuf_0/IN divbuf_0/OUT divbuf_0/OUT2 divbuf_0/OUT3 divbuf_0/OUT4 + divbuf_0/OUT5 gnd divbuf Xro_complete_1 ro_complete_1/a0 ro_complete_1/a1 ro_complete_1/a5 ro_complete_1/a4 + ro_complete_1/a3 ro_complete_1/a2 ro_complete -Xdivbuf_1 vdda1 divbuf_1/IN divbuf_1/OUT divbuf_1/OUT2 divbuf_1/OUT3 divbuf_1/OUT4 +Xdivbuf_1 vssa1 divbuf_1/IN divbuf_1/OUT divbuf_1/OUT2 divbuf_1/OUT3 divbuf_1/OUT4 + divbuf_1/OUT5 gnd divbuf -Xdivbuf_2 vdda1 divbuf_2/IN divbuf_2/OUT divbuf_2/OUT2 divbuf_2/OUT3 divbuf_2/OUT4 +Xdivbuf_2 vssa1 divbuf_2/IN divbuf_2/OUT divbuf_2/OUT2 divbuf_2/OUT3 divbuf_2/OUT4 + divbuf_2/OUT5 gnd divbuf -Xdivbuf_3 vdda1 divbuf_3/IN divbuf_3/OUT divbuf_3/OUT2 divbuf_3/OUT3 divbuf_3/OUT4 +Xdivbuf_3 vssa1 divbuf_3/IN divbuf_3/OUT divbuf_3/OUT2 divbuf_3/OUT3 divbuf_3/OUT4 + divbuf_3/OUT5 gnd divbuf -Xdivbuf_4 vdda1 divbuf_4/IN divbuf_4/OUT divbuf_4/OUT2 divbuf_4/OUT3 divbuf_4/OUT4 +Xdivbuf_4 vssa1 divbuf_4/IN divbuf_4/OUT divbuf_4/OUT2 divbuf_4/OUT3 divbuf_4/OUT4 + divbuf_4/OUT5 gnd divbuf -Xdivbuf_5 vdda1 divbuf_5/IN divbuf_5/OUT divbuf_5/OUT2 divbuf_5/OUT3 divbuf_5/OUT4 +Xdivbuf_5 vssa1 divbuf_5/IN divbuf_5/OUT divbuf_5/OUT2 divbuf_5/OUT3 divbuf_5/OUT4 + divbuf_5/OUT5 gnd divbuf -Xdivbuf_6 vdda1 divbuf_6/IN divbuf_6/OUT divbuf_6/OUT2 divbuf_6/OUT3 divbuf_6/OUT4 +Xdivbuf_6 vssa1 divbuf_6/IN divbuf_6/OUT divbuf_6/OUT2 divbuf_6/OUT3 divbuf_6/OUT4 + divbuf_6/OUT5 gnd divbuf -Xdivbuf_10 vdda1 divbuf_10/IN divbuf_10/OUT divbuf_10/OUT2 divbuf_10/OUT3 divbuf_10/OUT4 +Xdivbuf_10 vssa1 divbuf_10/IN divbuf_10/OUT divbuf_10/OUT2 divbuf_10/OUT3 divbuf_10/OUT4 + divbuf_10/OUT5 gnd divbuf -Xdivbuf_20 vssa1 divbuf_20/IN divbuf_20/OUT divbuf_20/OUT2 divbuf_20/OUT3 divbuf_20/OUT4 +Xdivbuf_20 vdd divbuf_20/IN divbuf_20/OUT divbuf_20/OUT2 divbuf_20/OUT3 divbuf_20/OUT4 + divbuf_20/OUT5 vssa1 divbuf -Xdivbuf_21 vssa1 divbuf_21/IN divbuf_21/OUT divbuf_21/OUT2 divbuf_21/OUT3 divbuf_21/OUT4 +Xdivbuf_21 vdd divbuf_21/IN divbuf_21/OUT divbuf_21/OUT2 divbuf_21/OUT3 divbuf_21/OUT4 + divbuf_21/OUT5 vssa1 divbuf -Xdivbuf_7 vdda1 divbuf_7/IN divbuf_7/OUT divbuf_7/OUT2 divbuf_7/OUT3 divbuf_7/OUT4 +Xdivbuf_7 vssa1 divbuf_7/IN divbuf_7/OUT divbuf_7/OUT2 divbuf_7/OUT3 divbuf_7/OUT4 + divbuf_7/OUT5 gnd divbuf -Xdivbuf_11 vdda1 divbuf_11/IN divbuf_11/OUT divbuf_11/OUT2 divbuf_11/OUT3 divbuf_11/OUT4 +Xdivbuf_11 vssa1 divbuf_11/IN divbuf_11/OUT divbuf_11/OUT2 divbuf_11/OUT3 divbuf_11/OUT4 + divbuf_11/OUT5 gnd divbuf -Xdivbuf_22 vssa1 divbuf_22/IN divbuf_22/OUT divbuf_22/OUT2 divbuf_22/OUT3 divbuf_22/OUT4 +Xdivbuf_22 vdd divbuf_22/IN divbuf_22/OUT divbuf_22/OUT2 divbuf_22/OUT3 divbuf_22/OUT4 + divbuf_22/OUT5 vssa1 divbuf -Xdivbuf_8 vdda1 divbuf_8/IN divbuf_8/OUT divbuf_8/OUT2 divbuf_8/OUT3 divbuf_8/OUT4 +Xdivbuf_8 vssa1 divbuf_8/IN divbuf_8/OUT divbuf_8/OUT2 divbuf_8/OUT3 divbuf_8/OUT4 + divbuf_8/OUT5 gnd divbuf -Xdivbuf_12 vdda1 divbuf_12/IN divbuf_12/OUT divbuf_12/OUT2 divbuf_12/OUT3 divbuf_12/OUT4 +Xdivbuf_12 vssa1 divbuf_12/IN divbuf_12/OUT divbuf_12/OUT2 divbuf_12/OUT3 divbuf_12/OUT4 + divbuf_12/OUT5 gnd divbuf -Xdivbuf_23 vssa1 divbuf_23/IN divbuf_23/OUT divbuf_23/OUT2 divbuf_23/OUT3 divbuf_23/OUT4 +Xdivbuf_23 vdd divbuf_23/IN divbuf_23/OUT divbuf_23/OUT2 divbuf_23/OUT3 divbuf_23/OUT4 + divbuf_23/OUT5 vssa1 divbuf -Xdivbuf_9 vdda1 divbuf_9/IN divbuf_9/OUT divbuf_9/OUT2 divbuf_9/OUT3 divbuf_9/OUT4 +Xdivbuf_9 vssa1 divbuf_9/IN divbuf_9/OUT divbuf_9/OUT2 divbuf_9/OUT3 divbuf_9/OUT4 + divbuf_9/OUT5 gnd divbuf -Xdivbuf_13 vdda1 divbuf_13/IN divbuf_13/OUT divbuf_13/OUT2 divbuf_13/OUT3 divbuf_13/OUT4 +Xdivbuf_13 vssa1 divbuf_13/IN divbuf_13/OUT divbuf_13/OUT2 divbuf_13/OUT3 divbuf_13/OUT4 + divbuf_13/OUT5 gnd divbuf -Xdivbuf_24 vssa1 divbuf_24/IN divbuf_24/OUT divbuf_24/OUT2 divbuf_24/OUT3 divbuf_24/OUT4 +Xdivbuf_24 vdd divbuf_24/IN divbuf_24/OUT divbuf_24/OUT2 divbuf_24/OUT3 divbuf_24/OUT4 + divbuf_24/OUT5 vssa1 divbuf Xdivider_0 gnd vdd divider_0/Out divider_0/clk divider_0/mc2 divider Xdivbuf_14 vssa1 divbuf_14/IN divbuf_14/OUT divbuf_14/OUT2 divbuf_14/OUT3 divbuf_14/OUT4 + divbuf_14/OUT5 gnd divbuf -Xdivbuf_25 vssa1 divbuf_25/IN divbuf_25/OUT divbuf_25/OUT2 divbuf_25/OUT3 divbuf_25/OUT4 +Xdivbuf_25 vdd divbuf_25/IN divbuf_25/OUT divbuf_25/OUT2 divbuf_25/OUT3 divbuf_25/OUT4 + divbuf_25/OUT5 vssa1 divbuf Xdivbuf_15 vssa1 divbuf_15/IN divbuf_15/OUT divbuf_15/OUT2 divbuf_15/OUT3 divbuf_15/OUT4 + divbuf_15/OUT5 gnd divbuf -Xdivider_1 vssa1 vssa1 divider_1/Out divider_1/clk divider_1/mc2 divider +Xdivider_1 vssa1 vdd divider_1/Out divider_1/clk divider_1/mc2 divider Xdivbuf_16 vssa1 divbuf_16/IN divbuf_16/OUT divbuf_16/OUT2 divbuf_16/OUT3 divbuf_16/OUT4 + divbuf_16/OUT5 vssa1 divbuf -Xdivider_2 vssa1 vssa1 divider_2/Out divider_2/clk divider_2/mc2 divider +Xdivider_2 vssa1 vdd divider_2/Out divider_2/clk divider_2/mc2 divider Xdivbuf_17 vssa1 divbuf_17/IN divbuf_17/OUT divbuf_17/OUT2 divbuf_17/OUT3 divbuf_17/OUT4 + divbuf_17/OUT5 vssa1 divbuf -Xdivbuf_18 vssa1 divbuf_18/IN divbuf_18/OUT divbuf_18/OUT2 divbuf_18/OUT3 divbuf_18/OUT4 +Xdivbuf_18 vdd divbuf_18/IN divbuf_18/OUT divbuf_18/OUT2 divbuf_18/OUT3 divbuf_18/OUT4 + divbuf_18/OUT5 vssa1 divbuf -Xdivbuf_19 vssa1 divbuf_19/IN divbuf_19/OUT divbuf_19/OUT2 divbuf_19/OUT3 divbuf_19/OUT4 +Xdivbuf_19 vdd divbuf_19/IN divbuf_19/OUT divbuf_19/OUT2 divbuf_19/OUT3 divbuf_19/OUT4 + divbuf_19/OUT5 vssa1 divbuf -Xpll_full_0 vdda1 pll_full +Xpll_full_0 vssa1 pll_full C1655 io_analog[4] gnd 43.96fF C1656 io_analog[5] gnd 44.13fF C1657 io_analog[6] gnd 43.46fF