| v {xschem version=3.0.0 file_version=1.2 } |
| G {} |
| K {} |
| V {} |
| S {} |
| E {} |
| N 2840 -630 2920 -630 { lab=out} |
| N 2580 -650 2680 -650 { lab=vctrl} |
| N 2500 -820 2760 -820 { lab=vdd} |
| N 2500 -440 2760 -440 { lab=vss} |
| N 2420 -820 2500 -820 { lab=vdd} |
| N 2420 -440 2500 -440 { lab=vss} |
| N 2760 -720 2760 -680 { lab=vdd} |
| N 2760 -820 2760 -780 { lab=vdd} |
| N 2760 -480 2760 -440 { lab=vss} |
| N 2760 -580 2760 -540 { lab=vss} |
| N 3000 -630 3050 -630 { lab=out} |
| N 3350 -590 3400 -590 { lab=vss_2} |
| N 3350 -630 3400 -630 { lab=vdd_2} |
| N 3160 270 3190 270 { lab=out_div128} |
| N 3960 270 4010 270 { lab=out_div128_buf} |
| N 3910 270 3960 270 { lab=out_div128_buf} |
| N 3390 270 3430 270 { lab=buf2a_out} |
| N 3510 270 3550 270 { lab=buf4a_out} |
| N 2480 -640 2680 -640 { lab=vsel0} |
| N 2510 -630 2680 -630 { lab=vsel1} |
| N 2540 -620 2680 -620 { lab=vsel2} |
| N 2570 -610 2680 -610 { lab=vsel3} |
| N 3350 -610 3460 -610 { lab=out_div2} |
| N 3760 -590 3810 -590 { lab=vss_2} |
| N 3760 -630 3810 -630 { lab=vdd_2} |
| N 3760 -610 3870 -610 { lab=out_div4} |
| N 3460 -630 3460 -610 { lab=out_div2} |
| N 3350 -440 3400 -440 { lab=vss_2} |
| N 3350 -480 3400 -480 { lab=vdd_2} |
| N 3350 -460 3460 -460 { lab=out_div8} |
| N 3050 -530 3050 -480 { lab=out_div4} |
| N 3050 -530 3870 -530 { lab=out_div4} |
| N 3870 -610 3870 -530 { lab=out_div4} |
| N 3760 -440 3810 -440 { lab=vss_2} |
| N 3760 -480 3810 -480 { lab=vdd_2} |
| N 3760 -460 3870 -460 { lab=out_div16} |
| N 3460 -480 3460 -460 { lab=out_div8} |
| N 3350 -290 3400 -290 { lab=vss_2} |
| N 3350 -330 3400 -330 { lab=vdd_2} |
| N 3350 -310 3460 -310 { lab=out_div32} |
| N 3050 -380 3050 -330 { lab=out_div16} |
| N 3050 -380 3870 -380 { lab=out_div16} |
| N 3870 -460 3870 -380 { lab=out_div16} |
| N 3760 -290 3810 -290 { lab=vss_2} |
| N 3760 -330 3810 -330 { lab=vdd_2} |
| N 3760 -310 3870 -310 { lab=out_div64} |
| N 3460 -330 3460 -310 { lab=out_div32} |
| N 3350 -140 3400 -140 { lab=vss_2} |
| N 3350 -180 3400 -180 { lab=vdd_2} |
| N 3350 -160 3460 -160 { lab=out_div128} |
| N 3050 -230 3050 -180 { lab=out_div64} |
| N 3050 -230 3870 -230 { lab=out_div64} |
| N 3870 -310 3870 -230 { lab=out_div64} |
| N 3760 -140 3810 -140 { lab=vss_2} |
| N 3760 -180 3810 -180 { lab=vdd_2} |
| N 3760 -160 3870 -160 { lab=out_div256} |
| N 3460 -180 3460 -160 { lab=out_div128} |
| N 2920 -630 3000 -630 { lab=out} |
| N 2760 -540 2760 -480 { lab=vss} |
| N 2760 -780 2760 -720 { lab=vdd} |
| N 2380 -650 2580 -650 { lab=vctrl} |
| N 2380 -640 2480 -640 { lab=vsel0} |
| N 2380 -630 2510 -630 { lab=vsel1} |
| N 2380 -620 2540 -620 { lab=vsel2} |
| N 2380 -610 2570 -610 { lab=vsel3} |
| N 3040 270 3160 270 { lab=out_div128} |
| N 3160 360 3190 360 { lab=out_div256} |
| N 3860 360 3910 360 { lab=out_div256_buf} |
| N 3810 360 3860 360 { lab=out_div256_buf} |
| N 3390 360 3430 360 { lab=buf2b_out} |
| N 3510 360 3550 360 { lab=buf4b_out} |
| N 3040 360 3160 360 { lab=out_div256} |
| N 3350 10 3400 10 { lab=vss_2} |
| N 3350 -30 3400 -30 { lab=vdd_2} |
| N 3350 -10 3460 -10 { lab=out_div512} |
| N 3050 -80 3050 -30 { lab=out_div256} |
| N 3050 -80 3870 -80 { lab=out_div256} |
| N 3870 -160 3870 -80 { lab=out_div256} |
| N 3760 10 3810 10 { lab=vss_2} |
| N 3760 -30 3810 -30 { lab=vdd_2} |
| N 3760 -10 3870 -10 { lab=out_div1024} |
| N 3460 -30 3460 -10 { lab=out_div512} |
| N 3190 270 3310 270 { lab=out_div128} |
| N 3190 360 3310 360 { lab=out_div256} |
| N 3630 270 3670 270 { lab=buf8a_out} |
| N 3630 360 3670 360 { lab=buf8b_out} |
| N 3750 360 3810 360 { lab=out_div256_buf} |
| N 3800 220 3800 300 { lab=buf16a_out} |
| N 3880 220 3880 300 { lab=out_div128_buf} |
| N 3880 270 3910 270 { lab=out_div128_buf} |
| N 3750 270 3800 270 { lab=buf16a_out} |
| N 3120 -820 3200 -820 { |
| lab=vdd_2} |
| N 3120 -740 3200 -740 { |
| lab=vss_2} |
| C {3-stage_cs-vco_dp9.sym} 2760 -630 0 0 {name=xvco} |
| C {lab_wire.sym} 2640 -820 0 0 {name=l1 sig_type=std_logic lab=vdd} |
| C {lab_wire.sym} 2650 -440 0 0 {name=l2 sig_type=std_logic lab=vss} |
| C {lab_wire.sym} 2650 -650 0 0 {name=l4 sig_type=std_logic lab=vctrl} |
| C {lab_wire.sym} 2960 -630 0 0 {name=l5 sig_type=std_logic lab=out} |
| C {ipin.sym} 2380 -650 0 0 {name=p1 lab=vctrl} |
| C {FD_v5.sym} 3200 -610 0 0 {name=xFD_0} |
| C {lab_wire.sym} 3390 -630 0 0 {name=l6 sig_type=std_logic lab=vdd_2} |
| C {lab_wire.sym} 3390 -590 0 0 {name=l7 sig_type=std_logic lab=vss_2} |
| C {lab_wire.sym} 3180 270 0 0 {name=l8 sig_type=std_logic lab=out_div128} |
| C {sky130_stdcells/clkbuf_2.sym} 3350 270 0 0 {name=xbuf2a VGND=vss_2 VNB=vss_2 VPB=vdd_2 VPWR=vdd_2 prefix=sky130_fd_sc_hd__ } |
| C {sky130_stdcells/clkbuf_4.sym} 3470 270 0 0 {name=xbuf4a VGND=vss_2 VNB=vss_2 VPB=vdd_2 VPWR=vdd_2 prefix=sky130_fd_sc_hd__ } |
| C {sky130_stdcells/clkbuf_8.sym} 3590 270 0 0 {name=xbuf8a VGND=vss_2 VNB=vss_2 VPB=vdd_2 VPWR=vdd_2 prefix=sky130_fd_sc_hd__ } |
| C {opin.sym} 4010 270 0 0 {name=p4 lab=out_div128_buf} |
| C {lab_wire.sym} 2550 -640 0 0 {name=l11 sig_type=std_logic lab=vsel0} |
| C {lab_wire.sym} 2580 -630 0 0 {name=l12 sig_type=std_logic lab=vsel1} |
| C {lab_wire.sym} 2600 -620 0 0 {name=l13 sig_type=std_logic lab=vsel2} |
| C {lab_wire.sym} 2630 -610 0 0 {name=l14 sig_type=std_logic lab=vsel3} |
| C {lab_wire.sym} 3400 -610 0 0 {name=l17 sig_type=std_logic lab=out_div2} |
| C {FD.sym} 3610 -610 0 0 {name=xFD_1} |
| C {lab_wire.sym} 3800 -630 0 0 {name=l18 sig_type=std_logic lab=vdd_2} |
| C {lab_wire.sym} 3800 -590 0 0 {name=l19 sig_type=std_logic lab=vss_2} |
| C {lab_wire.sym} 3810 -610 0 0 {name=l20 sig_type=std_logic lab=out_div4} |
| C {FD.sym} 3200 -460 0 0 {name=xFD_2} |
| C {lab_wire.sym} 3390 -480 0 0 {name=l21 sig_type=std_logic lab=vdd_2} |
| C {lab_wire.sym} 3390 -440 0 0 {name=l22 sig_type=std_logic lab=vss_2} |
| C {lab_wire.sym} 3400 -460 0 0 {name=l23 sig_type=std_logic lab=out_div8} |
| C {FD.sym} 3610 -460 0 0 {name=xFD_3} |
| C {lab_wire.sym} 3800 -480 0 0 {name=l24 sig_type=std_logic lab=vdd_2} |
| C {lab_wire.sym} 3800 -440 0 0 {name=l25 sig_type=std_logic lab=vss_2} |
| C {lab_wire.sym} 3810 -460 0 0 {name=l26 sig_type=std_logic lab=out_div16} |
| C {FD.sym} 3200 -310 0 0 {name=xFD_4} |
| C {lab_wire.sym} 3390 -330 0 0 {name=l27 sig_type=std_logic lab=vdd_2} |
| C {lab_wire.sym} 3390 -290 0 0 {name=l28 sig_type=std_logic lab=vss_2} |
| C {lab_wire.sym} 3400 -310 0 0 {name=l29 sig_type=std_logic lab=out_div32} |
| C {FD.sym} 3610 -310 0 0 {name=xFD_5} |
| C {lab_wire.sym} 3800 -330 0 0 {name=l30 sig_type=std_logic lab=vdd_2} |
| C {lab_wire.sym} 3800 -290 0 0 {name=l31 sig_type=std_logic lab=vss_2} |
| C {lab_wire.sym} 3810 -310 0 0 {name=l32 sig_type=std_logic lab=out_div64} |
| C {FD.sym} 3200 -160 0 0 {name=xFD_6} |
| C {lab_wire.sym} 3390 -180 0 0 {name=l33 sig_type=std_logic lab=vdd_2} |
| C {lab_wire.sym} 3390 -140 0 0 {name=l34 sig_type=std_logic lab=vss_2} |
| C {lab_wire.sym} 3420 -160 0 0 {name=l35 sig_type=std_logic lab=out_div128} |
| C {FD.sym} 3610 -160 0 0 {name=xFD_7} |
| C {lab_wire.sym} 3800 -180 0 0 {name=l36 sig_type=std_logic lab=vdd_2} |
| C {lab_wire.sym} 3800 -140 0 0 {name=l37 sig_type=std_logic lab=vss_2} |
| C {lab_wire.sym} 3840 -160 0 0 {name=l38 sig_type=std_logic lab=out_div256} |
| C {iopin.sym} 2420 -820 0 1 {name=p2 lab=vdd} |
| C {iopin.sym} 2420 -440 0 1 {name=p3 lab=vss} |
| C {ipin.sym} 2380 -640 0 0 {name=p5 lab=vsel0} |
| C {ipin.sym} 2380 -630 0 0 {name=p6 lab=vsel1} |
| C {ipin.sym} 2380 -620 0 0 {name=p7 lab=vsel2} |
| C {ipin.sym} 2380 -610 0 0 {name=p8 lab=vsel3} |
| C {lab_wire.sym} 3420 270 0 0 {name=l3 sig_type=std_logic lab=buf2a_out} |
| C {lab_wire.sym} 3540 270 0 0 {name=l9 sig_type=std_logic lab=buf4a_out} |
| C {lab_wire.sym} 3180 360 0 0 {name=l15 sig_type=std_logic lab=out_div256} |
| C {sky130_stdcells/clkbuf_2.sym} 3350 360 0 0 {name=xbuf2b VGND=vss_2 VNB=vss_2 VPB=vdd_2 VPWR=vdd_2 prefix=sky130_fd_sc_hd__ } |
| C {sky130_stdcells/clkbuf_4.sym} 3470 360 0 0 {name=xbuf4b VGND=vss_2 VNB=vss_2 VPB=vdd_2 VPWR=vdd_2 prefix=sky130_fd_sc_hd__ } |
| C {sky130_stdcells/clkbuf_8.sym} 3590 360 0 0 {name=xbuf8b VGND=vss_2 VNB=vss_2 VPB=vdd_2 VPWR=vdd prefix=sky130_fd_sc_hd__ } |
| C {opin.sym} 3910 360 0 0 {name=p9 lab=out_div256_buf} |
| C {lab_wire.sym} 3420 360 0 0 {name=l39 sig_type=std_logic lab=buf2b_out} |
| C {lab_wire.sym} 3540 360 0 0 {name=l40 sig_type=std_logic lab=buf4b_out} |
| C {FD.sym} 3200 -10 0 0 {name=xFD_8} |
| C {lab_wire.sym} 3390 -30 0 0 {name=l41 sig_type=std_logic lab=vdd_2} |
| C {lab_wire.sym} 3390 10 0 0 {name=l42 sig_type=std_logic lab=vss_2} |
| C {lab_wire.sym} 3420 -10 0 0 {name=l43 sig_type=std_logic lab=out_div512} |
| C {FD.sym} 3610 -10 0 0 {name=xFD_9} |
| C {lab_wire.sym} 3800 -30 0 0 {name=l44 sig_type=std_logic lab=vdd_2} |
| C {lab_wire.sym} 3800 10 0 0 {name=l45 sig_type=std_logic lab=vss_2} |
| C {lab_wire.sym} 3840 -10 0 0 {name=l46 sig_type=std_logic lab=out_div1024} |
| C {sky130_stdcells/clkbuf_16.sym} 3710 270 0 0 {name=xbuf16a VGND=vss_2 VNB=vss_2 VPB=vdd_2 VPWR=vdd_2 prefix=sky130_fd_sc_hd__ } |
| C {lab_wire.sym} 3660 270 0 0 {name=l10 sig_type=std_logic lab=buf8a_out} |
| C {sky130_stdcells/clkbuf_16.sym} 3710 360 0 0 {name=xbuf16b VGND=vss_2 VNB=vss_2 VPB=vdd_2 VPWR=vdd_2 prefix=sky130_fd_sc_hd__ } |
| C {lab_wire.sym} 3660 360 0 0 {name=l16 sig_type=std_logic lab=buf8b_out} |
| C {sky130_stdcells/clkbuf_16.sym} 3840 220 0 0 {name=xbuf32a_1 VGND=vss_2 VNB=vss_2 VPB=vdd_2 VPWR=vdd_2 prefix=sky130_fd_sc_hd__ } |
| C {sky130_stdcells/clkbuf_16.sym} 3840 300 0 0 {name=xbuf32a_2 VGND=vss_2 VNB=vss_2 VPB=vdd_2 VPWR=vdd_2 prefix=sky130_fd_sc_hd__ } |
| C {lab_wire.sym} 3790 270 0 0 {name=l47 sig_type=std_logic lab=buf16a_out} |
| C {iopin.sym} 3120 -820 0 1 {name=p10 lab=vdd_2} |
| C {iopin.sym} 3120 -740 0 1 {name=p11 lab=vss_2} |
