| dineshannayya | 83124b4 | 2022-04-10 12:43:31 +0530 | [diff] [blame^] | 1 | # Caravel user project includes |
| 2 | +define+UNIT_DELAY=#0.1 |
| 3 | +incdir+$(USER_PROJECT_VERILOG)/rtl/ |
| 4 | +incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes |
| 5 | +incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes |
| 6 | +incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/includes |
| 7 | +incdir+$(USER_PROJECT_VERILOG)/dv/bfm |
| 8 | +incdir+$(USER_PROJECT_VERILOG)/dv/model |
| 9 | +incdir+$(USER_PROJECT_VERILOG)/dv/agents |
| 10 | $(USER_PROJECT_VERILOG)/rtl/user_reg_map.v |
| 11 | $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v |
| 12 | $(USER_PROJECT_VERILOG)/gl/ycr_intf.v |
| 13 | $(USER_PROJECT_VERILOG)/gl/qspim_top.v |
| 14 | $(USER_PROJECT_VERILOG)/gl/wb_host.v |
| 15 | $(USER_PROJECT_VERILOG)/gl/ycr2_iconnect.v |
| 16 | $(USER_PROJECT_VERILOG)/gl/ycr_core_top.v |
| 17 | $(USER_PROJECT_VERILOG)/gl/pinmux.v |
| 18 | $(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v |
| 19 | $(USER_PROJECT_VERILOG)/gl/wb_interconnect.v |
| 20 | ########################################################### |
| 21 | # STD CELLS - they need to be below the defines.v files |
| 22 | ########################################################### |
| 23 | -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v |
| 24 | -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v |
| 25 | -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v |
| 26 | -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v |
| 27 | -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v |
| 28 | -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v |
| 29 | |
