commit c30f4561b71b321ebd64e23b8a2d4ae57b824fc3
author Jeff DiCorpo <jeffdi@efabless.com> Sat Apr 30 20:36:59 2022 -0700
committer Jeff DiCorpo <jeffdi@efabless.com> Sat Apr 30 20:36:59 2022 -0700
tree 13564b797e48501f0aebd711db7e0b9a5619968b
parent 47a54b93bcbdacc848f8947f559db1aa20c3f32d

final gds oasis

mpw_precheck/logs/gds.info

diff --git a/mpw_precheck/logs/gds.info b/mpw_precheck/logs/gds.info
new file mode 100644
index 0000000..3b19a5e
--- /dev/null
+++ b/mpw_precheck/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: 197a1b97303ea5f767d1555c44fe5e5a677fa98e
\ No newline at end of file

mpw_precheck/logs/git.info

diff --git a/mpw_precheck/logs/git.info b/mpw_precheck/logs/git.info
new file mode 100644
index 0000000..3979398
--- /dev/null
+++ b/mpw_precheck/logs/git.info
@@ -0,0 +1,3 @@
+Repository: https://github.com/dineshannayya/riscduino_dcore.git
+Branch: main
+Commit: 795890a177e9180478b895f4163340f69d9edc39

mpw_precheck/logs/klayout_beol_check.log

diff --git a/mpw_precheck/logs/klayout_beol_check.log b/mpw_precheck/logs/klayout_beol_check.log
new file mode 100644
index 0000000..5bdece6
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/opt/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/outputs/reports/klayout_beol_check.xml ..
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mpw_precheck/logs/klayout_beol_check.total

diff --git a/mpw_precheck/logs/klayout_beol_check.total b/mpw_precheck/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file

mpw_precheck/logs/klayout_feol_check.log

diff --git a/mpw_precheck/logs/klayout_feol_check.log b/mpw_precheck/logs/klayout_feol_check.log
new file mode 100644
index 0000000..6204573
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.log
@@ -0,0 +1,789 @@
+/opt/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 164.890s  Memory: 1700.00M

mpw_precheck/logs/klayout_feol_check.total

diff --git a/mpw_precheck/logs/klayout_feol_check.total b/mpw_precheck/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file

mpw_precheck/logs/klayout_met_min_ca_density_check.log

diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.log b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..bf269b0
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
@@ -0,0 +1,79 @@
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+m5_ca_density is 0.9233860865504359
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 85.900s  Memory: 1382.00M

mpw_precheck/logs/klayout_met_min_ca_density_check.total

diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.total b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file

mpw_precheck/logs/klayout_offgrid_check.log

diff --git a/mpw_precheck/logs/klayout_offgrid_check.log b/mpw_precheck/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..a354fce
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.log
@@ -0,0 +1,755 @@
+/opt/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+"output" in: sky130A_mr.drc:738
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:739
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.090s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:739
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:740
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 1.670s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:740
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:741
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:741
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:742
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.880s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:742
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:743
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.070s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:743
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:744
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.260s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:744
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:745
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:745
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:746
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.530s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:746
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:747
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:747
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:748
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.360s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:748
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:749
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:749
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:750
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.280s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:750
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:751
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:751
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.270s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.260s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.270s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.270s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.280s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.270s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.260s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"with_angle" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+"ongrid" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.260s  Memory: 2338.00M
+"output" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2338.00M
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 200.550s  Memory: 1695.00M

mpw_precheck/logs/klayout_offgrid_check.total

diff --git a/mpw_precheck/logs/klayout_offgrid_check.total b/mpw_precheck/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file

mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log

diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..bb4b84f
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/root/riscduino-dual_core__rd0_/gds/user_project_wrapper.gds, topcell=user_project_wrapper, output to /mnt/uffs/user/u5295_dinesha/design/riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+  deep:true tiled:false threads:8
+--- #err|description, table for cell: user_project_wrapper
+NO-Check ----        pwell:64/44/EMP   122/16/dat    64/59/EMP    44/16/EMP     44/5/EMP
+         ----        nwell:64/20/dat    64/16/dat     64/5/EMP
+         ----         diff:65/20/dat    65/16/EMP     65/6/EMP
+         ----          tap:65/44/dat    65/48/EMP     65/5/EMP
+         ----         poly:66/20/dat    66/16/EMP     66/5/EMP
+         ----       licon1:66/44/dat    66/58/EMP
+         ----          li1:67/20/dat    67/16/dat     67/5/EMP
+         ----         mcon:67/44/dat    67/48/EMP
+         ----         met1:68/20/dat    68/16/dat     68/5/dat
+         ----          via:68/44/dat    68/58/EMP
+         ----         met2:69/20/dat    69/16/dat     69/5/dat
+         ----         via2:69/44/dat    69/58/EMP
+         ----         met3:70/20/dat    70/16/dat     70/5/dat
+         ----         via3:70/44/dat    70/48/EMP
+         ----         met4:71/20/dat    71/16/dat     71/5/dat
+         ----         via4:71/44/dat    71/48/EMP
+         ----         met5:72/20/dat    72/16/dat     72/5/EMP
+         ----          pad:76/20/EMP     76/5/EMP    76/16/EMP
+         ----          pnp:82/44/EMP    82/59/EMP
+         ----          npn:82/20/EMP     82/5/EMP
+         ----          rdl:74/20/EMP    74/16/EMP     74/5/EMP
+         ----     inductor:82/24/EMP    82/25/EMP
+       0 total error(s) among 0 error type(s), 33 checks, cell: user_project_wrapper
+Writing report...
+VmPeak:	 2392104 kB
+VmHWM:	 1189016 kB

mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total

diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file

mpw_precheck/logs/klayout_zeroarea_check.log

diff --git a/mpw_precheck/logs/klayout_zeroarea_check.log b/mpw_precheck/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..b693433
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /mnt/uffs/user/u5295_dinesha/design/riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/outputs/user_project_wrapper_no_zero_areas.gds
+VmPeak:	 1585484 kB
+VmHWM:	 1255012 kB

mpw_precheck/logs/klayout_zeroarea_check.total

diff --git a/mpw_precheck/logs/klayout_zeroarea_check.total b/mpw_precheck/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file

mpw_precheck/logs/magic_drc_check.log

diff --git a/mpw_precheck/logs/magic_drc_check.log b/mpw_precheck/logs/magic_drc_check.log
new file mode 100644
index 0000000..442ba7c
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.log
@@ -0,0 +1,547 @@
+
+Magic 8.3 revision 274 - Compiled on Fri Mar  4 22:53:06 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    mvobsactive ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Detected an SRAM module
+Pre-loading a maglef of the SRAM block: sky130_sram_2kbyte_1rw1r_32x512_8
+Scaled magic input cell sky130_sram_2kbyte_1rw1r_32x512_8 geometry by factor of 2
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620068): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620772): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2621732): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3113978): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3117754): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3121946): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3126746): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3128794): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3308236): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3312012): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3316204): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3322668): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3324844): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3565294): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3569070): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3573262): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3579726): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3581902): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+Warning:  cell sky130_sram_2kbyte_1rw1r_32x512_8 already existed before reading GDS!
+Using pre-existing cell definition
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__o41ai_2".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__o21ba_4".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__a2111o_1".
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "ycr_core_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_2".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s15_2".
+Reading "ycr2_mintf".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "wb_host".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "uart_i2c_usb_spi_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__o2111a_4".
+Reading "wb_interconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+Reading "pinmux".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "qspim_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "user_project_wrapper".
+[INFO]: Loading user_project_wrapper
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/mnt/uffs/user/u5295_dinesha/design/riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/mnt/uffs/user/u5295_dinesha/design/riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/outputs/user_project_wrapper.magic.drc.mag)
+[INFO]: Saved

mpw_precheck/logs/magic_drc_check.total

diff --git a/mpw_precheck/logs/magic_drc_check.total b/mpw_precheck/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file

mpw_precheck/logs/pdks.info

diff --git a/mpw_precheck/logs/pdks.info b/mpw_precheck/logs/pdks.info
new file mode 100644
index 0000000..19f87e1
--- /dev/null
+++ b/mpw_precheck/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs 27ecf1c16911f7dd4428ffab96f62c1fb876ea70
+Skywater PDK c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
\ No newline at end of file

mpw_precheck/logs/precheck.log

diff --git a/mpw_precheck/logs/precheck.log b/mpw_precheck/logs/precheck.log
new file mode 100644
index 0000000..5d300f3
--- /dev/null
+++ b/mpw_precheck/logs/precheck.log
@@ -0,0 +1,71 @@
+2022-03-20 08:27:19 - [INFO] - {{Project Git Info}} Repository: https://github.com/dineshannayya/riscduino_dcore.git | Branch: main | Commit: 795890a177e9180478b895f4163340f69d9edc39
+2022-03-20 08:27:19 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: riscduino-dual_core__rd0_
+2022-03-20 08:27:24 - [INFO] - {{Project Type Info}} digital
+2022-03-20 08:27:25 - [INFO] - {{Project GDS Info}} user_project_wrapper: 197a1b97303ea5f767d1555c44fe5e5a677fa98e
+2022-03-20 08:27:25 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-03-20 08:27:25 - [INFO] - {{PDKs Info}} Open PDKs: 27ecf1c16911f7dd4428ffab96f62c1fb876ea70 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+2022-03-20 08:27:25 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/logs'
+2022-03-20 08:27:25 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-03-20 08:27:25 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-03-20 08:27:26 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-dual_core__rd0_.
+2022-03-20 08:27:26 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-03-20 08:27:27 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-dual_core__rd0_.
+2022-03-20 08:27:27 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/bfm/usb_device/core/usb1d_ctrl.v): 'utf-8' codec can't decode byte 0x96 in position 5130: invalid start byte
+2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/model/mt48lc8m8a2.v): 'utf-8' codec can't decode byte 0xa9 in position 1830: invalid start byte
+2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/user_sspi/.flash1.hex.swp): 'utf-8' codec can't decode byte 0xa0 in position 16: invalid start byte
+2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/user_sspi/.sspi_task.v.swp): 'utf-8' codec can't decode byte 0xae in position 16: invalid start byte
+2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/user_sspi/.user_sspi_tb.v.swp): 'utf-8' codec can't decode byte 0xe4 in position 20: invalid continuation byte
+2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/user_uart/.user_uart.c.un~): 'utf-8' codec can't decode byte 0x9f in position 3: invalid start byte
+2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/user_uart/simx.fst): 'utf-8' codec can't decode byte 0xde in position 22: invalid continuation byte
+2022-03-20 08:27:29 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 447 non-compliant file(s) with the SPDX Standard.
+2022-03-20 08:27:29 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['riscduino-dual_core__rd0_/Makefile', 'riscduino-dual_core__rd0_/run_regress', 'riscduino-dual_core__rd0_/gds/.magicrc', 'riscduino-dual_core__rd0_/hacks/patch/pdngen.patch', 'riscduino-dual_core__rd0_/hacks/patch/resizer.patch', 'riscduino-dual_core__rd0_/hacks/src/OpenROAD/PdnGen.tcl', 'riscduino-dual_core__rd0_/hacks/src/OpenROAD/Resizer.cc', 'riscduino-dual_core__rd0_/hacks/src/OpenSTA/network/ConcreteNetwork.cc', 'riscduino-dual_core__rd0_/hacks/src/OpenSTA/tcl/NetworkEdit.tcl', 'riscduino-dual_core__rd0_/hacks/src/OpenSTA/tcl/Sta.tcl', 'riscduino-dual_core__rd0_/hacks/src/openlane/io_place.py', 'riscduino-dual_core__rd0_/hacks/src/openlane/synth.tcl', 'riscduino-dual_core__rd0_/hacks/src/openlane/synth_top.tcl', 'riscduino-dual_core__rd0_/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib', 'riscduino-dual_core__rd0_/openlane/Makefile']
+2022-03-20 08:27:29 - [INFO] - For the full SPDX compliance report check: riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/logs/spdx_compliance_report.log
+2022-03-20 08:27:29 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-03-20 08:27:29 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-03-20 08:27:29 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-03-20 08:27:29 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-03-20 08:27:32 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-03-20 08:27:32 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-03-20 08:27:32 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-03-20 08:27:32 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-03-20 08:27:39 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. 
+2022-03-20 08:27:39 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances). 
+2022-03-20 08:27:39 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
+2022-03-20 08:27:39 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
+2022-03-20 08:27:39 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
+2022-03-20 08:27:39 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
+2022-03-20 08:27:39 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
+2022-03-20 08:27:39 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (11 instances). 
+2022-03-20 08:27:39 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
+2022-03-20 08:27:39 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
+2022-03-20 08:27:39 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
+2022-03-20 08:27:39 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
+2022-03-20 08:27:39 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
+2022-03-20 08:27:39 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2022-03-20 08:27:39 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-03-20 08:30:14 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/outputs/user_project_wrapper.xor.gds
+2022-03-20 08:30:14 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
+2022-03-20 08:30:14 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-03-20 08:55:13 - [INFO] - 0 DRC violations
+2022-03-20 08:55:13 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-03-20 08:55:13 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-03-20 08:57:33 - [INFO] - No DRC Violations found
+2022-03-20 08:57:33 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-03-20 08:57:33 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-03-20 09:14:28 - [INFO] - No DRC Violations found
+2022-03-20 09:14:28 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-03-20 09:14:28 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-03-20 09:17:50 - [INFO] - No DRC Violations found
+2022-03-20 09:17:50 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-03-20 09:17:50 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-03-20 09:19:17 - [INFO] - No DRC Violations found
+2022-03-20 09:19:17 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-03-20 09:19:17 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-03-20 09:19:51 - [INFO] - No DRC Violations found
+2022-03-20 09:19:51 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-03-20 09:19:51 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-03-20 09:20:05 - [INFO] - No DRC Violations found
+2022-03-20 09:20:05 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-03-20 09:20:05 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/logs'
+2022-03-20 09:20:05 - [INFO] - {{SUCCESS}} All Checks Passed !!!

mpw_precheck/logs/spdx_compliance_report.log

diff --git a/mpw_precheck/logs/spdx_compliance_report.log b/mpw_precheck/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..0d2de6b
--- /dev/null
+++ b/mpw_precheck/logs/spdx_compliance_report.log
@@ -0,0 +1,447 @@
+/root/riscduino-dual_core__rd0_/Makefile
+/root/riscduino-dual_core__rd0_/run_regress
+/root/riscduino-dual_core__rd0_/gds/.magicrc
+/root/riscduino-dual_core__rd0_/hacks/patch/pdngen.patch
+/root/riscduino-dual_core__rd0_/hacks/patch/resizer.patch
+/root/riscduino-dual_core__rd0_/hacks/src/OpenROAD/PdnGen.tcl
+/root/riscduino-dual_core__rd0_/hacks/src/OpenROAD/Resizer.cc
+/root/riscduino-dual_core__rd0_/hacks/src/OpenSTA/network/ConcreteNetwork.cc
+/root/riscduino-dual_core__rd0_/hacks/src/OpenSTA/tcl/NetworkEdit.tcl
+/root/riscduino-dual_core__rd0_/hacks/src/OpenSTA/tcl/Sta.tcl
+/root/riscduino-dual_core__rd0_/hacks/src/openlane/io_place.py
+/root/riscduino-dual_core__rd0_/hacks/src/openlane/synth.tcl
+/root/riscduino-dual_core__rd0_/hacks/src/openlane/synth_top.tcl
+/root/riscduino-dual_core__rd0_/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+/root/riscduino-dual_core__rd0_/openlane/Makefile
+/root/riscduino-dual_core__rd0_/openlane/Read.me
+/root/riscduino-dual_core__rd0_/openlane/clk_skew_adjust/config.tcl
+/root/riscduino-dual_core__rd0_/openlane/pinmux/base.sdc
+/root/riscduino-dual_core__rd0_/openlane/pinmux/config.tcl
+/root/riscduino-dual_core__rd0_/openlane/qspim_top/base.sdc
+/root/riscduino-dual_core__rd0_/openlane/qspim_top/config.tcl
+/root/riscduino-dual_core__rd0_/openlane/qspim_top/pdn.tcl
+/root/riscduino-dual_core__rd0_/openlane/qspim_top/sta.tcl
+/root/riscduino-dual_core__rd0_/openlane/sar_adc/config.tcl
+/root/riscduino-dual_core__rd0_/openlane/sar_adc/interactive.tcl
+/root/riscduino-dual_core__rd0_/openlane/sar_adc/pdn.tcl
+/root/riscduino-dual_core__rd0_/openlane/uart_i2cm_usb_spi_top/base.sdc
+/root/riscduino-dual_core__rd0_/openlane/uart_i2cm_usb_spi_top/config.tcl
+/root/riscduino-dual_core__rd0_/openlane/uart_i2cm_usb_spi_top/pdn.tcl
+/root/riscduino-dual_core__rd0_/openlane/uart_i2cm_usb_spi_top/sta.tcl
+/root/riscduino-dual_core__rd0_/openlane/user_project_wrapper/base.sdc
+/root/riscduino-dual_core__rd0_/openlane/user_project_wrapper/config.tcl
+/root/riscduino-dual_core__rd0_/openlane/user_project_wrapper/gen_pdn.tcl
+/root/riscduino-dual_core__rd0_/openlane/user_project_wrapper/interactive.mpw4.tcl
+/root/riscduino-dual_core__rd0_/openlane/user_project_wrapper/interactive.tcl
+/root/riscduino-dual_core__rd0_/openlane/user_project_wrapper/mod.tcl
+/root/riscduino-dual_core__rd0_/openlane/user_project_wrapper/pdn_cfg.tcl
+/root/riscduino-dual_core__rd0_/openlane/user_project_wrapper/sta.tcl
+/root/riscduino-dual_core__rd0_/openlane/wb_host/base.sdc
+/root/riscduino-dual_core__rd0_/openlane/wb_host/config.tcl
+/root/riscduino-dual_core__rd0_/openlane/wb_interconnect/base.sdc
+/root/riscduino-dual_core__rd0_/openlane/wb_interconnect/config.tcl
+/root/riscduino-dual_core__rd0_/openlane/wb_interconnect/pdn.tcl
+/root/riscduino-dual_core__rd0_/openlane/wb_interconnect/sta.tcl
+/root/riscduino-dual_core__rd0_/openlane/ycr2_mintf/base.sdc
+/root/riscduino-dual_core__rd0_/openlane/ycr2_mintf/config.tcl
+/root/riscduino-dual_core__rd0_/openlane/ycr_core/base.sdc
+/root/riscduino-dual_core__rd0_/openlane/ycr_core/config.tcl
+/root/riscduino-dual_core__rd0_/spef/pinmux.spef
+/root/riscduino-dual_core__rd0_/spef/qspim_top.spef
+/root/riscduino-dual_core__rd0_/spef/uart_i2c_usb_spi_top.spef
+/root/riscduino-dual_core__rd0_/spef/user_project_wrapper.spef
+/root/riscduino-dual_core__rd0_/spef/wb_host.spef
+/root/riscduino-dual_core__rd0_/spef/wb_interconnect.spef
+/root/riscduino-dual_core__rd0_/spef/ycr2_mintf.spef
+/root/riscduino-dual_core__rd0_/spef/ycr_core_top.spef
+/root/riscduino-dual_core__rd0_/sta/Makefile
+/root/riscduino-dual_core__rd0_/sta/base.sdc
+/root/riscduino-dual_core__rd0_/sta/run_sta
+/root/riscduino-dual_core__rd0_/sta/scripts/caravel_timing.tcl
+/root/riscduino-dual_core__rd0_/sta/scripts/or_write_verilog.tcl
+/root/riscduino-dual_core__rd0_/sta/scripts/sta.tcl
+/root/riscduino-dual_core__rd0_/sta/sdc/caravel.sdc
+/root/riscduino-dual_core__rd0_/verilog/dv/Makefile
+/root/riscduino-dual_core__rd0_/verilog/dv/agents/test_control.v
+/root/riscduino-dual_core__rd0_/verilog/dv/agents/uart_agent.v
+/root/riscduino-dual_core__rd0_/verilog/dv/agents/uart_master_tasks.sv
+/root/riscduino-dual_core__rd0_/verilog/dv/agents/usb_agents.v
+/root/riscduino-dual_core__rd0_/verilog/dv/bfm/usb1d_defines.v
+/root/riscduino-dual_core__rd0_/verilog/dv/bfm/usbd_files.v
+/root/riscduino-dual_core__rd0_/verilog/dv/bfm/usb_device/core/usb1d_core.v
+/root/riscduino-dual_core__rd0_/verilog/dv/bfm/usb_device/core/usb1d_crc16.v
+/root/riscduino-dual_core__rd0_/verilog/dv/bfm/usb_device/core/usb1d_crc5.v
+/root/riscduino-dual_core__rd0_/verilog/dv/bfm/usb_device/core/usb1d_fifo2.v
+/root/riscduino-dual_core__rd0_/verilog/dv/bfm/usb_device/core/usb1d_generic_dpram.v
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+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/openlane/ycr2_core/config.tcl
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+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/openlane/ycr2c/interactive.tcl
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/openlane/ycr2c/pdn.tcl
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+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/iverilog_vpi/system.c
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+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/coremark/core_portme.c
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/coremark/core_portme.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/dhrystone21/Makefile
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/dhrystone21/dhry.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/dhrystone21/dhry_1.c
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/dhrystone21/dhry_2.c
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+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/common/crt.S
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/common/crt_tcm.S
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/common/csr.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/common/link.ld
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/common/link_tcm.ld
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/common/reloc.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/common/riscv_csr_encoding.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/common/riscv_macros.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/common/sc_print.c
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/common/sc_print.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/common/sc_test.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/common/ycr1_specific.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/hello/Makefile
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/hello/hello.c
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/isr_sample/Makefile
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/isr_sample/isr_sample.S
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/isr_sample/timer.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/Makefile
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/aw_test_macros.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/compliance_io.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/compliance_test.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/riscv_test.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/riscv_test_macros.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/test_macros.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_isa/Makefile
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_isa/riscv_test.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_isa/rv32_tests.inc
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_isa/test_macros.h
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/verilator_wrap/ycr1_ahb_wrapper.c
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/verilator_wrap/ycr1_axi_wrapper.c
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/sim/verilator_wrap/ycr1_wb_wrapper.c
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core.files
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/run_modemsim
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/wb_top.files
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/cache/Makefile
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/cache/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/cache/src/core/dcache_tag_fifo.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/cache/src/core/dcache_top.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_app_fsm.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_tag_fifo.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_top.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/cache/src/core/ycr_cache_defs.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/cache/src/model/sky130_sram_2kbyte_1rw1r_32x512_8.v
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/ycr_clk_ctrl.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/ycr_core_top.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/ycr_dm.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/ycr_dmi.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/ycr_scu.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/ycr_tapc.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/ycr_tapc_shift_reg.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/ycr_tapc_synchronizer.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_ipic.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_csr.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_div.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_exu.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_hdu.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ialu.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_idu.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ifu.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_lsu.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mprf.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mul.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_tdu.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_top.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_tracelog.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/primitives/ycr_cg.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_ahb.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_arch_description.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_arch_types.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_cache_defs.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_csr.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_dm.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_hdu.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_ipic.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_memif.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_riscv_isa_decoding.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_scu.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_search_ms1.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_tapc.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_tdu.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/includes/ycr_wb.svh
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/lib/async_fifo.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/lib/clk_skew_adjust.gv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/lib/ctech_cells.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/lib/sync_fifo.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/lib/ycr_arb.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/lib/ycr_async_wbb.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr2_intf.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr2_mcore_router.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr2_mintf.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr2_top_ahb.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr2_top_axi.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr2_top_wb.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr_dcache_router.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr_dmem_ahb.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr_dmem_router.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr_dmem_wb.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr_dp_memory.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr_icache_router.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr_imem_ahb.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr_imem_router.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr_imem_wb.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr_mem_axi.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr_tcm.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/src/top/ycr_timer.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/synth/Makefile
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/synth/base.sdc
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/synth/run_synth
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/synth/sta.tcl
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/synth/synth.tcl
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/tb/ahb_tb.files
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/tb/axi_tb.files
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/tb/sky130_sram_2kbyte_1rw1r_32x512_8.v
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/tb/uprj_netlists.v
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/tb/wb_tb.files
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+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/tb/ycr_dmem_tb_wb.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/tb/ycr_memory_tb_ahb.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/tb/ycr_memory_tb_axi.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/tb/ycr_memory_tb_wb.sv
+/root/riscduino-dual_core__rd0_/verilog/rtl/yifive/ycr2c/tb/ycr_top_tb_runtests.sv

mpw_precheck/logs/tools.info

diff --git a/mpw_precheck/logs/tools.info b/mpw_precheck/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/mpw_precheck/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file

mpw_precheck/logs/xor_check.log

diff --git a/mpw_precheck/logs/xor_check.log b/mpw_precheck/logs/xor_check.log
new file mode 100644
index 0000000..c19695a
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.log
@@ -0,0 +1,699 @@
+Reading file /root/riscduino-dual_core__rd0_/gds/user_project_wrapper.gds for cell user_project_wrapper
+dbu=0.001
+cell user_project_wrapper dbu-bbox(ll;ur)=(-43630,-38270;2963250,3557950)
+cell user_project_wrapper dbu-bbox(left,bottom,right,top)=(-43630,-38270,2963250,3557950)
+cell user_project_wrapper dbu-size(width,height)=(3006880,3596220)
+cell user_project_wrapper micron-bbox(left,bottom,right,top)=(-43.63,-38.27,2963.25,3557.9500000000003)
+cell user_project_wrapper micron-size(width,height)=(3006.88,3596.2200000000003)
+Done.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar  4 22:53:06 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    mvobsactive ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620068): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620772): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2621732): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3113978): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3117754): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3121946): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3126746): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3128794): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3308236): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3312012): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3316204): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3322668): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3324844): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3565294): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3569070): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3573262): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3579726): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3581902): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+    5000 uses
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__o41ai_2".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__o21ba_4".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__a2111o_1".
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "ycr_core_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_2".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s15_2".
+Reading "ycr2_mintf".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "wb_host".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "uart_i2c_usb_spi_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__o2111a_4".
+Reading "wb_interconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+Reading "pinmux".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "qspim_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+
+Magic 8.3 revision 274 - Compiled on Fri Mar  4 22:53:06 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    mvobsactive ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+Reading /mnt/uffs/user/u5295_dinesha/design/riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/outputs/user_project_wrapper_erased.gds ..
+Reading /mnt/uffs/user/u5295_dinesha/design/riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/outputs/user_project_wrapper_empty_erased.gds ..
+--- Running XOR for 69/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+--- Running XOR for 70/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+--- Running XOR for 71/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+--- Running XOR for 71/44 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+--- Running XOR for 72/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+--- Running XOR for 81/14 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+Writing layout file: /mnt/uffs/user/u5295_dinesha/design/riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/outputs/user_project_wrapper.xor.gds ..
+Total elapsed: 0.120s  Memory: 523.00M

mpw_precheck/logs/xor_check.total

diff --git a/mpw_precheck/logs/xor_check.total b/mpw_precheck/logs/xor_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file

mpw_precheck/outputs/reports/klayout_beol_check.xml

diff --git a/mpw_precheck/outputs/reports/klayout_beol_check.xml b/mpw_precheck/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..5ffd971
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1: non-ring mcon should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_a</name>
+   <description>ct.1_a : minimum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_b</name>
+   <description>ct.1_b : maximum length of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>791_m1.4</name>
+   <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : mcon periphery must be enclosed by m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a_a</name>
+   <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : via outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_a</name>
+   <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_b</name>
+   <description>via.1a_b : maximum length of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a_a</name>
+   <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.5a</name>
+   <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4_a</name>
+   <description>m2.4_a : via in periphery must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_a</name>
+   <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_b</name>
+   <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4_a</name>
+   <description>via2.4_a : via must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3cd</name>
+   <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4_a</name>
+   <description>m3.4_a : via2 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1</name>
+   <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_a</name>
+   <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_b</name>
+   <description>via3.1_b : maximum length of via3 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4_a</name>
+   <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4a</name>
+   <description>m4.4a : min. m4 area : 0.240um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3_a</name>
+   <description>m4.3_a : via3 must be enclosed by met4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1</name>
+   <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_a</name>
+   <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_b</name>
+   <description>via4.1_b : maximum length of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4_a</name>
+   <description>via4.4_a : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3_a</name>
+   <description>m5.3_a : via must be enclosed by m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.4</name>
+   <description>m5.4 : min. m5 area : 4.0um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

mpw_precheck/outputs/reports/klayout_feol_check.xml

diff --git a/mpw_precheck/outputs/reports/klayout_feol_check.xml b/mpw_precheck/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..987027f
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell.2</name>
+   <description>dnwell.2 : min. dnwell width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.1</name>
+   <description>nwell.1 : min. nwell width : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.2a</name>
+   <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.6</name>
+   <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.1</name>
+   <description>hvtp.1 : min. hvtp width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.2</name>
+   <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.1</name>
+   <description>hvtr.1 : min. hvtr width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2</name>
+   <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2_a</name>
+   <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.1a</name>
+   <description>lvtn.1a : min. lvtn width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.2</name>
+   <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.1</name>
+   <description>ncm.1 : min. ncm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.2a</name>
+   <description>ncm.2a : min. ncm spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1</name>
+   <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_a</name>
+   <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_b</name>
+   <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_c</name>
+   <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.3</name>
+   <description>difftap.3 : min. difftap spacing : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.1</name>
+   <description>tunm.1 : min. tunm width : 0.41um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.2</name>
+   <description>tunm.2 : min. tunm spacing : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.1a</name>
+   <description>poly.1a : min. poly width : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.2</name>
+   <description>poly.2 : min. poly spacing : 0.21um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.1a</name>
+   <description>rpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.2</name>
+   <description>rpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.1a</name>
+   <description>urpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.2</name>
+   <description>urpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.1</name>
+   <description>npc.1 : min. npc width : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.2</name>
+   <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.1</name>
+   <description>nsd.1 : min. nsdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.2</name>
+   <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.1</name>
+   <description>psd.1 : min. psdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.2</name>
+   <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1</name>
+   <description>licon.1 : licon should be rectangle</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1_a/b</name>
+   <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13</name>
+   <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13_a</name>
+   <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.17</name>
+   <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.1</name>
+   <description>capm.1 : min. capm width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2a</name>
+   <description>capm.2a : min. capm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b</name>
+   <description>capm.2b : min. capm spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b_a</name>
+   <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3</name>
+   <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3_a</name>
+   <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.4</name>
+   <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.5</name>
+   <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.1</name>
+   <description>cap2m.1 : min. cap2m width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2a</name>
+   <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b</name>
+   <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b_a</name>
+   <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3</name>
+   <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3_a</name>
+   <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.4</name>
+   <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.5</name>
+   <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.1</name>
+   <description>hvi.1 : min. hvi width : 0.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.2a</name>
+   <description>hvi.2a : min. hvi spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.1</name>
+   <description>hvntm.1 : min. hvntm width : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.2</name>
+   <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml

diff --git a/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..698a39a
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

mpw_precheck/outputs/reports/klayout_offgrid_check.xml

diff --git a/mpw_precheck/outputs/reports/klayout_offgrid_check.xml b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..95ebbc9
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>x.3a : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>x.3a : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_angle</name>
+   <description>x.3a : non 45 degree angle pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_angle</name>
+   <description>x.3a : non 45 degree angle pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_angle</name>
+   <description>x.3a : non 45 degree angle hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_angle</name>
+   <description>x.3a : non 45 degree angle hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_angle</name>
+   <description>x.3a : non 45 degree angle lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_angle</name>
+   <description>x.3a : non 45 degree angle ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2 : non 90 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2c : non 45 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2 : non 90 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2c : non 45 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_angle</name>
+   <description>x.3a : non 45 degree angle tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_angle</name>
+   <description>x.2 : non 90 degree angle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_angle</name>
+   <description>x.3a : non 45 degree angle rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_angle</name>
+   <description>x.3a : non 45 degree angle npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_angle</name>
+   <description>x.3a : non 45 degree angle nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_angle</name>
+   <description>x.3a : non 45 degree angle psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_angle</name>
+   <description>x.2 : non 90 degree angle licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_angle</name>
+   <description>x.3a : non 45 degree angle li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_angle</name>
+   <description>x.2 : non 90 degree angle mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_angle</name>
+   <description>x.3a : non 45 degree angle vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_angle</name>
+   <description>x.3a : non 45 degree angle m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_angle</name>
+   <description>x.2 : non 90 degree angle via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_angle</name>
+   <description>x.3a : non 45 degree angle m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>x.2 : non 90 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_angle</name>
+   <description>x.3a : non 45 degree angle m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
+   <description>x.2 : non 90 degree angle via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_angle</name>
+   <description>x.3a : non 45 degree angle nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_angle</name>
+   <description>x.3a : non 45 degree angle m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_angle</name>
+   <description>x.2 : non 90 degree angle via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_angle</name>
+   <description>x.3a : non 45 degree angle m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_angle</name>
+   <description>x.3a : non 45 degree angle pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_angle</name>
+   <description>x.2 : non 90 degree angle mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_angle</name>
+   <description>x.3a : non 45 degree angle hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_angle</name>
+   <description>x.3a : non 45 degree angle hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_angle</name>
+   <description>x.3a : non 45 degree angle vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_angle</name>
+   <description>x.3a : non 45 degree angle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_angle</name>
+   <description>x.3a : non 45 degree angle pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>areaid_re_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on areaid.re</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml

diff --git a/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..1803835
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/root/riscduino-dual_core__rd0_/gds/user_project_wrapper.gds, topcell=user_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

mpw_precheck/outputs/reports/klayout_zeroarea_check.xml

diff --git a/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..7f95f69
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

mpw_precheck/outputs/reports/magic_drc_check.drc.report

diff --git a/mpw_precheck/outputs/reports/magic_drc_check.drc.report b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..46ca7f3
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+

mpw_precheck/outputs/reports/magic_drc_check.rdb

diff --git a/mpw_precheck/outputs/reports/magic_drc_check.rdb b/mpw_precheck/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..ac5b3c4
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_project_wrapper
+ 100

mpw_precheck/outputs/reports/magic_drc_check.tcl

diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tcl b/mpw_precheck/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tcl

mpw_precheck/outputs/reports/magic_drc_check.tr

diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tr b/mpw_precheck/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tr

mpw_precheck/outputs/reports/magic_drc_check.xml

diff --git a/mpw_precheck/outputs/reports/magic_drc_check.xml b/mpw_precheck/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..0eff265
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+    <categories/>
+    <cells>
+        <cell>
+            <name>user_project_wrapper</name>
+        </cell>
+    </cells>
+    <items/>
+</report-database>

mpw_precheck/outputs/user_project_wrapper.filtered.v

diff --git a/mpw_precheck/outputs/user_project_wrapper.filtered.v b/mpw_precheck/outputs/user_project_wrapper.filtered.v
new file mode 100644
index 0000000..47fd59f
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.filtered.v
@@ -0,0 +1,5733 @@
+module user_project_wrapper (user_clock2,
+    vccd1,
+    vccd2,
+    vdda1,
+    vdda2,
+    vssa1,
+    vssa2,
+    vssd1,
+    vssd2,
+    wb_clk_i,
+    wb_rst_i,
+    wbs_ack_o,
+    wbs_cyc_i,
+    wbs_stb_i,
+    wbs_we_i,
+    analog_io,
+    io_in,
+    io_oeb,
+    io_out,
+    la_data_in,
+    la_data_out,
+    la_oenb,
+    user_irq,
+    wbs_adr_i,
+    wbs_dat_i,
+    wbs_dat_o,
+    wbs_sel_i);
+ input user_clock2;
+ input vccd1;
+ input vccd2;
+ input vdda1;
+ input vdda2;
+ input vssa1;
+ input vssa2;
+ input vssd1;
+ input vssd2;
+ input wb_clk_i;
+ input wb_rst_i;
+ output wbs_ack_o;
+ input wbs_cyc_i;
+ input wbs_stb_i;
+ input wbs_we_i;
+ inout [28:0] analog_io;
+ input [37:0] io_in;
+ output [37:0] io_oeb;
+ output [37:0] io_out;
+ input [127:0] la_data_in;
+ output [127:0] la_data_out;
+ input [127:0] la_oenb;
+ output [2:0] user_irq;
+ input [31:0] wbs_adr_i;
+ input [31:0] wbs_dat_i;
+ output [31:0] wbs_dat_o;
+ input [3:0] wbs_sel_i;
+
+ wire \cfg_clk_ctrl1[0] ;
+ wire \cfg_clk_ctrl1[10] ;
+ wire \cfg_clk_ctrl1[11] ;
+ wire \cfg_clk_ctrl1[12] ;
+ wire \cfg_clk_ctrl1[13] ;
+ wire \cfg_clk_ctrl1[14] ;
+ wire \cfg_clk_ctrl1[15] ;
+ wire \cfg_clk_ctrl1[16] ;
+ wire \cfg_clk_ctrl1[17] ;
+ wire \cfg_clk_ctrl1[18] ;
+ wire \cfg_clk_ctrl1[19] ;
+ wire \cfg_clk_ctrl1[1] ;
+ wire \cfg_clk_ctrl1[20] ;
+ wire \cfg_clk_ctrl1[21] ;
+ wire \cfg_clk_ctrl1[22] ;
+ wire \cfg_clk_ctrl1[23] ;
+ wire \cfg_clk_ctrl1[24] ;
+ wire \cfg_clk_ctrl1[25] ;
+ wire \cfg_clk_ctrl1[26] ;
+ wire \cfg_clk_ctrl1[27] ;
+ wire \cfg_clk_ctrl1[28] ;
+ wire \cfg_clk_ctrl1[29] ;
+ wire \cfg_clk_ctrl1[2] ;
+ wire \cfg_clk_ctrl1[30] ;
+ wire \cfg_clk_ctrl1[31] ;
+ wire \cfg_clk_ctrl1[3] ;
+ wire \cfg_clk_ctrl1[4] ;
+ wire \cfg_clk_ctrl1[5] ;
+ wire \cfg_clk_ctrl1[6] ;
+ wire \cfg_clk_ctrl1[7] ;
+ wire \cfg_clk_ctrl1[8] ;
+ wire \cfg_clk_ctrl1[9] ;
+ wire \cfg_clk_ctrl2[0] ;
+ wire \cfg_clk_ctrl2[10] ;
+ wire \cfg_clk_ctrl2[11] ;
+ wire \cfg_clk_ctrl2[12] ;
+ wire \cfg_clk_ctrl2[13] ;
+ wire \cfg_clk_ctrl2[14] ;
+ wire \cfg_clk_ctrl2[15] ;
+ wire \cfg_clk_ctrl2[16] ;
+ wire \cfg_clk_ctrl2[17] ;
+ wire \cfg_clk_ctrl2[18] ;
+ wire \cfg_clk_ctrl2[19] ;
+ wire \cfg_clk_ctrl2[1] ;
+ wire \cfg_clk_ctrl2[20] ;
+ wire \cfg_clk_ctrl2[21] ;
+ wire \cfg_clk_ctrl2[22] ;
+ wire \cfg_clk_ctrl2[23] ;
+ wire \cfg_clk_ctrl2[24] ;
+ wire \cfg_clk_ctrl2[25] ;
+ wire \cfg_clk_ctrl2[26] ;
+ wire \cfg_clk_ctrl2[27] ;
+ wire \cfg_clk_ctrl2[28] ;
+ wire \cfg_clk_ctrl2[29] ;
+ wire \cfg_clk_ctrl2[2] ;
+ wire \cfg_clk_ctrl2[30] ;
+ wire \cfg_clk_ctrl2[31] ;
+ wire \cfg_clk_ctrl2[3] ;
+ wire \cfg_clk_ctrl2[4] ;
+ wire \cfg_clk_ctrl2[5] ;
+ wire \cfg_clk_ctrl2[6] ;
+ wire \cfg_clk_ctrl2[7] ;
+ wire \cfg_clk_ctrl2[8] ;
+ wire \cfg_clk_ctrl2[9] ;
+ wire \cfg_cska_pinmux_rp[0] ;
+ wire \cfg_cska_pinmux_rp[1] ;
+ wire \cfg_cska_pinmux_rp[2] ;
+ wire \cfg_cska_pinmux_rp[3] ;
+ wire \cfg_cska_qspi_co_rp[0] ;
+ wire \cfg_cska_qspi_co_rp[1] ;
+ wire \cfg_cska_qspi_co_rp[2] ;
+ wire \cfg_cska_qspi_co_rp[3] ;
+ wire \cfg_cska_qspi_rp[0] ;
+ wire \cfg_cska_qspi_rp[1] ;
+ wire \cfg_cska_qspi_rp[2] ;
+ wire \cfg_cska_qspi_rp[3] ;
+ wire \cfg_cska_uart_rp[0] ;
+ wire \cfg_cska_uart_rp[1] ;
+ wire \cfg_cska_uart_rp[2] ;
+ wire \cfg_cska_uart_rp[3] ;
+ wire i2c_rst_n;
+ wire i2cm_clk_i;
+ wire i2cm_clk_o;
+ wire i2cm_clk_oen;
+ wire i2cm_data_i;
+ wire i2cm_data_o;
+ wire i2cm_data_oen;
+ wire i2cm_intr_o;
+ wire \irq_lines[0] ;
+ wire \irq_lines[10] ;
+ wire \irq_lines[11] ;
+ wire \irq_lines[12] ;
+ wire \irq_lines[13] ;
+ wire \irq_lines[14] ;
+ wire \irq_lines[15] ;
+ wire \irq_lines[1] ;
+ wire \irq_lines[2] ;
+ wire \irq_lines[3] ;
+ wire \irq_lines[4] ;
+ wire \irq_lines[5] ;
+ wire \irq_lines[6] ;
+ wire \irq_lines[7] ;
+ wire \irq_lines[8] ;
+ wire \irq_lines[9] ;
+ wire pulse1m_mclk;
+ wire qspim_rst_n;
+ wire \sflash_di[0] ;
+ wire \sflash_di[1] ;
+ wire \sflash_di[2] ;
+ wire \sflash_di[3] ;
+ wire \sflash_do[0] ;
+ wire \sflash_do[1] ;
+ wire \sflash_do[2] ;
+ wire \sflash_do[3] ;
+ wire \sflash_oen[0] ;
+ wire \sflash_oen[1] ;
+ wire \sflash_oen[2] ;
+ wire \sflash_oen[3] ;
+ wire sflash_sck;
+ wire soft_irq;
+ wire \spi_csn[0] ;
+ wire \spi_csn[1] ;
+ wire \spi_csn[2] ;
+ wire \spi_csn[3] ;
+ wire sspim_rst_n;
+ wire sspim_sck;
+ wire sspim_si;
+ wire sspim_so;
+ wire sspim_ssn;
+ wire \u_riscv_top.cfg_cska_riscv[0] ;
+ wire \u_riscv_top.cfg_cska_riscv[1] ;
+ wire \u_riscv_top.cfg_cska_riscv[2] ;
+ wire \u_riscv_top.cfg_cska_riscv[3] ;
+ wire \u_riscv_top.core0_debug[0] ;
+ wire \u_riscv_top.core0_debug[10] ;
+ wire \u_riscv_top.core0_debug[11] ;
+ wire \u_riscv_top.core0_debug[12] ;
+ wire \u_riscv_top.core0_debug[13] ;
+ wire \u_riscv_top.core0_debug[14] ;
+ wire \u_riscv_top.core0_debug[15] ;
+ wire \u_riscv_top.core0_debug[16] ;
+ wire \u_riscv_top.core0_debug[17] ;
+ wire \u_riscv_top.core0_debug[18] ;
+ wire \u_riscv_top.core0_debug[19] ;
+ wire \u_riscv_top.core0_debug[1] ;
+ wire \u_riscv_top.core0_debug[20] ;
+ wire \u_riscv_top.core0_debug[21] ;
+ wire \u_riscv_top.core0_debug[22] ;
+ wire \u_riscv_top.core0_debug[23] ;
+ wire \u_riscv_top.core0_debug[24] ;
+ wire \u_riscv_top.core0_debug[25] ;
+ wire \u_riscv_top.core0_debug[26] ;
+ wire \u_riscv_top.core0_debug[27] ;
+ wire \u_riscv_top.core0_debug[28] ;
+ wire \u_riscv_top.core0_debug[29] ;
+ wire \u_riscv_top.core0_debug[2] ;
+ wire \u_riscv_top.core0_debug[30] ;
+ wire \u_riscv_top.core0_debug[31] ;
+ wire \u_riscv_top.core0_debug[32] ;
+ wire \u_riscv_top.core0_debug[33] ;
+ wire \u_riscv_top.core0_debug[34] ;
+ wire \u_riscv_top.core0_debug[35] ;
+ wire \u_riscv_top.core0_debug[36] ;
+ wire \u_riscv_top.core0_debug[37] ;
+ wire \u_riscv_top.core0_debug[38] ;
+ wire \u_riscv_top.core0_debug[39] ;
+ wire \u_riscv_top.core0_debug[3] ;
+ wire \u_riscv_top.core0_debug[40] ;
+ wire \u_riscv_top.core0_debug[41] ;
+ wire \u_riscv_top.core0_debug[42] ;
+ wire \u_riscv_top.core0_debug[43] ;
+ wire \u_riscv_top.core0_debug[44] ;
+ wire \u_riscv_top.core0_debug[45] ;
+ wire \u_riscv_top.core0_debug[46] ;
+ wire \u_riscv_top.core0_debug[47] ;
+ wire \u_riscv_top.core0_debug[48] ;
+ wire \u_riscv_top.core0_debug[4] ;
+ wire \u_riscv_top.core0_debug[5] ;
+ wire \u_riscv_top.core0_debug[6] ;
+ wire \u_riscv_top.core0_debug[7] ;
+ wire \u_riscv_top.core0_debug[8] ;
+ wire \u_riscv_top.core0_debug[9] ;
+ wire \u_riscv_top.core0_dmem_addr[0] ;
+ wire \u_riscv_top.core0_dmem_addr[10] ;
+ wire \u_riscv_top.core0_dmem_addr[11] ;
+ wire \u_riscv_top.core0_dmem_addr[12] ;
+ wire \u_riscv_top.core0_dmem_addr[13] ;
+ wire \u_riscv_top.core0_dmem_addr[14] ;
+ wire \u_riscv_top.core0_dmem_addr[15] ;
+ wire \u_riscv_top.core0_dmem_addr[16] ;
+ wire \u_riscv_top.core0_dmem_addr[17] ;
+ wire \u_riscv_top.core0_dmem_addr[18] ;
+ wire \u_riscv_top.core0_dmem_addr[19] ;
+ wire \u_riscv_top.core0_dmem_addr[1] ;
+ wire \u_riscv_top.core0_dmem_addr[20] ;
+ wire \u_riscv_top.core0_dmem_addr[21] ;
+ wire \u_riscv_top.core0_dmem_addr[22] ;
+ wire \u_riscv_top.core0_dmem_addr[23] ;
+ wire \u_riscv_top.core0_dmem_addr[24] ;
+ wire \u_riscv_top.core0_dmem_addr[25] ;
+ wire \u_riscv_top.core0_dmem_addr[26] ;
+ wire \u_riscv_top.core0_dmem_addr[27] ;
+ wire \u_riscv_top.core0_dmem_addr[28] ;
+ wire \u_riscv_top.core0_dmem_addr[29] ;
+ wire \u_riscv_top.core0_dmem_addr[2] ;
+ wire \u_riscv_top.core0_dmem_addr[30] ;
+ wire \u_riscv_top.core0_dmem_addr[31] ;
+ wire \u_riscv_top.core0_dmem_addr[3] ;
+ wire \u_riscv_top.core0_dmem_addr[4] ;
+ wire \u_riscv_top.core0_dmem_addr[5] ;
+ wire \u_riscv_top.core0_dmem_addr[6] ;
+ wire \u_riscv_top.core0_dmem_addr[7] ;
+ wire \u_riscv_top.core0_dmem_addr[8] ;
+ wire \u_riscv_top.core0_dmem_addr[9] ;
+ wire \u_riscv_top.core0_dmem_cmd ;
+ wire \u_riscv_top.core0_dmem_rdata[0] ;
+ wire \u_riscv_top.core0_dmem_rdata[10] ;
+ wire \u_riscv_top.core0_dmem_rdata[11] ;
+ wire \u_riscv_top.core0_dmem_rdata[12] ;
+ wire \u_riscv_top.core0_dmem_rdata[13] ;
+ wire \u_riscv_top.core0_dmem_rdata[14] ;
+ wire \u_riscv_top.core0_dmem_rdata[15] ;
+ wire \u_riscv_top.core0_dmem_rdata[16] ;
+ wire \u_riscv_top.core0_dmem_rdata[17] ;
+ wire \u_riscv_top.core0_dmem_rdata[18] ;
+ wire \u_riscv_top.core0_dmem_rdata[19] ;
+ wire \u_riscv_top.core0_dmem_rdata[1] ;
+ wire \u_riscv_top.core0_dmem_rdata[20] ;
+ wire \u_riscv_top.core0_dmem_rdata[21] ;
+ wire \u_riscv_top.core0_dmem_rdata[22] ;
+ wire \u_riscv_top.core0_dmem_rdata[23] ;
+ wire \u_riscv_top.core0_dmem_rdata[24] ;
+ wire \u_riscv_top.core0_dmem_rdata[25] ;
+ wire \u_riscv_top.core0_dmem_rdata[26] ;
+ wire \u_riscv_top.core0_dmem_rdata[27] ;
+ wire \u_riscv_top.core0_dmem_rdata[28] ;
+ wire \u_riscv_top.core0_dmem_rdata[29] ;
+ wire \u_riscv_top.core0_dmem_rdata[2] ;
+ wire \u_riscv_top.core0_dmem_rdata[30] ;
+ wire \u_riscv_top.core0_dmem_rdata[31] ;
+ wire \u_riscv_top.core0_dmem_rdata[3] ;
+ wire \u_riscv_top.core0_dmem_rdata[4] ;
+ wire \u_riscv_top.core0_dmem_rdata[5] ;
+ wire \u_riscv_top.core0_dmem_rdata[6] ;
+ wire \u_riscv_top.core0_dmem_rdata[7] ;
+ wire \u_riscv_top.core0_dmem_rdata[8] ;
+ wire \u_riscv_top.core0_dmem_rdata[9] ;
+ wire \u_riscv_top.core0_dmem_req ;
+ wire \u_riscv_top.core0_dmem_req_ack ;
+ wire \u_riscv_top.core0_dmem_resp[0] ;
+ wire \u_riscv_top.core0_dmem_resp[1] ;
+ wire \u_riscv_top.core0_dmem_wdata[0] ;
+ wire \u_riscv_top.core0_dmem_wdata[10] ;
+ wire \u_riscv_top.core0_dmem_wdata[11] ;
+ wire \u_riscv_top.core0_dmem_wdata[12] ;
+ wire \u_riscv_top.core0_dmem_wdata[13] ;
+ wire \u_riscv_top.core0_dmem_wdata[14] ;
+ wire \u_riscv_top.core0_dmem_wdata[15] ;
+ wire \u_riscv_top.core0_dmem_wdata[16] ;
+ wire \u_riscv_top.core0_dmem_wdata[17] ;
+ wire \u_riscv_top.core0_dmem_wdata[18] ;
+ wire \u_riscv_top.core0_dmem_wdata[19] ;
+ wire \u_riscv_top.core0_dmem_wdata[1] ;
+ wire \u_riscv_top.core0_dmem_wdata[20] ;
+ wire \u_riscv_top.core0_dmem_wdata[21] ;
+ wire \u_riscv_top.core0_dmem_wdata[22] ;
+ wire \u_riscv_top.core0_dmem_wdata[23] ;
+ wire \u_riscv_top.core0_dmem_wdata[24] ;
+ wire \u_riscv_top.core0_dmem_wdata[25] ;
+ wire \u_riscv_top.core0_dmem_wdata[26] ;
+ wire \u_riscv_top.core0_dmem_wdata[27] ;
+ wire \u_riscv_top.core0_dmem_wdata[28] ;
+ wire \u_riscv_top.core0_dmem_wdata[29] ;
+ wire \u_riscv_top.core0_dmem_wdata[2] ;
+ wire \u_riscv_top.core0_dmem_wdata[30] ;
+ wire \u_riscv_top.core0_dmem_wdata[31] ;
+ wire \u_riscv_top.core0_dmem_wdata[3] ;
+ wire \u_riscv_top.core0_dmem_wdata[4] ;
+ wire \u_riscv_top.core0_dmem_wdata[5] ;
+ wire \u_riscv_top.core0_dmem_wdata[6] ;
+ wire \u_riscv_top.core0_dmem_wdata[7] ;
+ wire \u_riscv_top.core0_dmem_wdata[8] ;
+ wire \u_riscv_top.core0_dmem_wdata[9] ;
+ wire \u_riscv_top.core0_dmem_width[0] ;
+ wire \u_riscv_top.core0_dmem_width[1] ;
+ wire \u_riscv_top.core0_imem_addr[0] ;
+ wire \u_riscv_top.core0_imem_addr[10] ;
+ wire \u_riscv_top.core0_imem_addr[11] ;
+ wire \u_riscv_top.core0_imem_addr[12] ;
+ wire \u_riscv_top.core0_imem_addr[13] ;
+ wire \u_riscv_top.core0_imem_addr[14] ;
+ wire \u_riscv_top.core0_imem_addr[15] ;
+ wire \u_riscv_top.core0_imem_addr[16] ;
+ wire \u_riscv_top.core0_imem_addr[17] ;
+ wire \u_riscv_top.core0_imem_addr[18] ;
+ wire \u_riscv_top.core0_imem_addr[19] ;
+ wire \u_riscv_top.core0_imem_addr[1] ;
+ wire \u_riscv_top.core0_imem_addr[20] ;
+ wire \u_riscv_top.core0_imem_addr[21] ;
+ wire \u_riscv_top.core0_imem_addr[22] ;
+ wire \u_riscv_top.core0_imem_addr[23] ;
+ wire \u_riscv_top.core0_imem_addr[24] ;
+ wire \u_riscv_top.core0_imem_addr[25] ;
+ wire \u_riscv_top.core0_imem_addr[26] ;
+ wire \u_riscv_top.core0_imem_addr[27] ;
+ wire \u_riscv_top.core0_imem_addr[28] ;
+ wire \u_riscv_top.core0_imem_addr[29] ;
+ wire \u_riscv_top.core0_imem_addr[2] ;
+ wire \u_riscv_top.core0_imem_addr[30] ;
+ wire \u_riscv_top.core0_imem_addr[31] ;
+ wire \u_riscv_top.core0_imem_addr[3] ;
+ wire \u_riscv_top.core0_imem_addr[4] ;
+ wire \u_riscv_top.core0_imem_addr[5] ;
+ wire \u_riscv_top.core0_imem_addr[6] ;
+ wire \u_riscv_top.core0_imem_addr[7] ;
+ wire \u_riscv_top.core0_imem_addr[8] ;
+ wire \u_riscv_top.core0_imem_addr[9] ;
+ wire \u_riscv_top.core0_imem_bl[0] ;
+ wire \u_riscv_top.core0_imem_bl[1] ;
+ wire \u_riscv_top.core0_imem_bl[2] ;
+ wire \u_riscv_top.core0_imem_cmd ;
+ wire \u_riscv_top.core0_imem_rdata[0] ;
+ wire \u_riscv_top.core0_imem_rdata[10] ;
+ wire \u_riscv_top.core0_imem_rdata[11] ;
+ wire \u_riscv_top.core0_imem_rdata[12] ;
+ wire \u_riscv_top.core0_imem_rdata[13] ;
+ wire \u_riscv_top.core0_imem_rdata[14] ;
+ wire \u_riscv_top.core0_imem_rdata[15] ;
+ wire \u_riscv_top.core0_imem_rdata[16] ;
+ wire \u_riscv_top.core0_imem_rdata[17] ;
+ wire \u_riscv_top.core0_imem_rdata[18] ;
+ wire \u_riscv_top.core0_imem_rdata[19] ;
+ wire \u_riscv_top.core0_imem_rdata[1] ;
+ wire \u_riscv_top.core0_imem_rdata[20] ;
+ wire \u_riscv_top.core0_imem_rdata[21] ;
+ wire \u_riscv_top.core0_imem_rdata[22] ;
+ wire \u_riscv_top.core0_imem_rdata[23] ;
+ wire \u_riscv_top.core0_imem_rdata[24] ;
+ wire \u_riscv_top.core0_imem_rdata[25] ;
+ wire \u_riscv_top.core0_imem_rdata[26] ;
+ wire \u_riscv_top.core0_imem_rdata[27] ;
+ wire \u_riscv_top.core0_imem_rdata[28] ;
+ wire \u_riscv_top.core0_imem_rdata[29] ;
+ wire \u_riscv_top.core0_imem_rdata[2] ;
+ wire \u_riscv_top.core0_imem_rdata[30] ;
+ wire \u_riscv_top.core0_imem_rdata[31] ;
+ wire \u_riscv_top.core0_imem_rdata[3] ;
+ wire \u_riscv_top.core0_imem_rdata[4] ;
+ wire \u_riscv_top.core0_imem_rdata[5] ;
+ wire \u_riscv_top.core0_imem_rdata[6] ;
+ wire \u_riscv_top.core0_imem_rdata[7] ;
+ wire \u_riscv_top.core0_imem_rdata[8] ;
+ wire \u_riscv_top.core0_imem_rdata[9] ;
+ wire \u_riscv_top.core0_imem_req ;
+ wire \u_riscv_top.core0_imem_req_ack ;
+ wire \u_riscv_top.core0_imem_resp[0] ;
+ wire \u_riscv_top.core0_imem_resp[1] ;
+ wire \u_riscv_top.core0_uid[0] ;
+ wire \u_riscv_top.core0_uid[1] ;
+ wire \u_riscv_top.core1_debug[0] ;
+ wire \u_riscv_top.core1_debug[10] ;
+ wire \u_riscv_top.core1_debug[11] ;
+ wire \u_riscv_top.core1_debug[12] ;
+ wire \u_riscv_top.core1_debug[13] ;
+ wire \u_riscv_top.core1_debug[14] ;
+ wire \u_riscv_top.core1_debug[15] ;
+ wire \u_riscv_top.core1_debug[16] ;
+ wire \u_riscv_top.core1_debug[17] ;
+ wire \u_riscv_top.core1_debug[18] ;
+ wire \u_riscv_top.core1_debug[19] ;
+ wire \u_riscv_top.core1_debug[1] ;
+ wire \u_riscv_top.core1_debug[20] ;
+ wire \u_riscv_top.core1_debug[21] ;
+ wire \u_riscv_top.core1_debug[22] ;
+ wire \u_riscv_top.core1_debug[23] ;
+ wire \u_riscv_top.core1_debug[24] ;
+ wire \u_riscv_top.core1_debug[25] ;
+ wire \u_riscv_top.core1_debug[26] ;
+ wire \u_riscv_top.core1_debug[27] ;
+ wire \u_riscv_top.core1_debug[28] ;
+ wire \u_riscv_top.core1_debug[29] ;
+ wire \u_riscv_top.core1_debug[2] ;
+ wire \u_riscv_top.core1_debug[30] ;
+ wire \u_riscv_top.core1_debug[31] ;
+ wire \u_riscv_top.core1_debug[32] ;
+ wire \u_riscv_top.core1_debug[33] ;
+ wire \u_riscv_top.core1_debug[34] ;
+ wire \u_riscv_top.core1_debug[35] ;
+ wire \u_riscv_top.core1_debug[36] ;
+ wire \u_riscv_top.core1_debug[37] ;
+ wire \u_riscv_top.core1_debug[38] ;
+ wire \u_riscv_top.core1_debug[39] ;
+ wire \u_riscv_top.core1_debug[3] ;
+ wire \u_riscv_top.core1_debug[40] ;
+ wire \u_riscv_top.core1_debug[41] ;
+ wire \u_riscv_top.core1_debug[42] ;
+ wire \u_riscv_top.core1_debug[43] ;
+ wire \u_riscv_top.core1_debug[44] ;
+ wire \u_riscv_top.core1_debug[45] ;
+ wire \u_riscv_top.core1_debug[46] ;
+ wire \u_riscv_top.core1_debug[47] ;
+ wire \u_riscv_top.core1_debug[48] ;
+ wire \u_riscv_top.core1_debug[4] ;
+ wire \u_riscv_top.core1_debug[5] ;
+ wire \u_riscv_top.core1_debug[6] ;
+ wire \u_riscv_top.core1_debug[7] ;
+ wire \u_riscv_top.core1_debug[8] ;
+ wire \u_riscv_top.core1_debug[9] ;
+ wire \u_riscv_top.core1_dmem_addr[0] ;
+ wire \u_riscv_top.core1_dmem_addr[10] ;
+ wire \u_riscv_top.core1_dmem_addr[11] ;
+ wire \u_riscv_top.core1_dmem_addr[12] ;
+ wire \u_riscv_top.core1_dmem_addr[13] ;
+ wire \u_riscv_top.core1_dmem_addr[14] ;
+ wire \u_riscv_top.core1_dmem_addr[15] ;
+ wire \u_riscv_top.core1_dmem_addr[16] ;
+ wire \u_riscv_top.core1_dmem_addr[17] ;
+ wire \u_riscv_top.core1_dmem_addr[18] ;
+ wire \u_riscv_top.core1_dmem_addr[19] ;
+ wire \u_riscv_top.core1_dmem_addr[1] ;
+ wire \u_riscv_top.core1_dmem_addr[20] ;
+ wire \u_riscv_top.core1_dmem_addr[21] ;
+ wire \u_riscv_top.core1_dmem_addr[22] ;
+ wire \u_riscv_top.core1_dmem_addr[23] ;
+ wire \u_riscv_top.core1_dmem_addr[24] ;
+ wire \u_riscv_top.core1_dmem_addr[25] ;
+ wire \u_riscv_top.core1_dmem_addr[26] ;
+ wire \u_riscv_top.core1_dmem_addr[27] ;
+ wire \u_riscv_top.core1_dmem_addr[28] ;
+ wire \u_riscv_top.core1_dmem_addr[29] ;
+ wire \u_riscv_top.core1_dmem_addr[2] ;
+ wire \u_riscv_top.core1_dmem_addr[30] ;
+ wire \u_riscv_top.core1_dmem_addr[31] ;
+ wire \u_riscv_top.core1_dmem_addr[3] ;
+ wire \u_riscv_top.core1_dmem_addr[4] ;
+ wire \u_riscv_top.core1_dmem_addr[5] ;
+ wire \u_riscv_top.core1_dmem_addr[6] ;
+ wire \u_riscv_top.core1_dmem_addr[7] ;
+ wire \u_riscv_top.core1_dmem_addr[8] ;
+ wire \u_riscv_top.core1_dmem_addr[9] ;
+ wire \u_riscv_top.core1_dmem_cmd ;
+ wire \u_riscv_top.core1_dmem_rdata[0] ;
+ wire \u_riscv_top.core1_dmem_rdata[10] ;
+ wire \u_riscv_top.core1_dmem_rdata[11] ;
+ wire \u_riscv_top.core1_dmem_rdata[12] ;
+ wire \u_riscv_top.core1_dmem_rdata[13] ;
+ wire \u_riscv_top.core1_dmem_rdata[14] ;
+ wire \u_riscv_top.core1_dmem_rdata[15] ;
+ wire \u_riscv_top.core1_dmem_rdata[16] ;
+ wire \u_riscv_top.core1_dmem_rdata[17] ;
+ wire \u_riscv_top.core1_dmem_rdata[18] ;
+ wire \u_riscv_top.core1_dmem_rdata[19] ;
+ wire \u_riscv_top.core1_dmem_rdata[1] ;
+ wire \u_riscv_top.core1_dmem_rdata[20] ;
+ wire \u_riscv_top.core1_dmem_rdata[21] ;
+ wire \u_riscv_top.core1_dmem_rdata[22] ;
+ wire \u_riscv_top.core1_dmem_rdata[23] ;
+ wire \u_riscv_top.core1_dmem_rdata[24] ;
+ wire \u_riscv_top.core1_dmem_rdata[25] ;
+ wire \u_riscv_top.core1_dmem_rdata[26] ;
+ wire \u_riscv_top.core1_dmem_rdata[27] ;
+ wire \u_riscv_top.core1_dmem_rdata[28] ;
+ wire \u_riscv_top.core1_dmem_rdata[29] ;
+ wire \u_riscv_top.core1_dmem_rdata[2] ;
+ wire \u_riscv_top.core1_dmem_rdata[30] ;
+ wire \u_riscv_top.core1_dmem_rdata[31] ;
+ wire \u_riscv_top.core1_dmem_rdata[3] ;
+ wire \u_riscv_top.core1_dmem_rdata[4] ;
+ wire \u_riscv_top.core1_dmem_rdata[5] ;
+ wire \u_riscv_top.core1_dmem_rdata[6] ;
+ wire \u_riscv_top.core1_dmem_rdata[7] ;
+ wire \u_riscv_top.core1_dmem_rdata[8] ;
+ wire \u_riscv_top.core1_dmem_rdata[9] ;
+ wire \u_riscv_top.core1_dmem_req ;
+ wire \u_riscv_top.core1_dmem_req_ack ;
+ wire \u_riscv_top.core1_dmem_resp[0] ;
+ wire \u_riscv_top.core1_dmem_resp[1] ;
+ wire \u_riscv_top.core1_dmem_wdata[0] ;
+ wire \u_riscv_top.core1_dmem_wdata[10] ;
+ wire \u_riscv_top.core1_dmem_wdata[11] ;
+ wire \u_riscv_top.core1_dmem_wdata[12] ;
+ wire \u_riscv_top.core1_dmem_wdata[13] ;
+ wire \u_riscv_top.core1_dmem_wdata[14] ;
+ wire \u_riscv_top.core1_dmem_wdata[15] ;
+ wire \u_riscv_top.core1_dmem_wdata[16] ;
+ wire \u_riscv_top.core1_dmem_wdata[17] ;
+ wire \u_riscv_top.core1_dmem_wdata[18] ;
+ wire \u_riscv_top.core1_dmem_wdata[19] ;
+ wire \u_riscv_top.core1_dmem_wdata[1] ;
+ wire \u_riscv_top.core1_dmem_wdata[20] ;
+ wire \u_riscv_top.core1_dmem_wdata[21] ;
+ wire \u_riscv_top.core1_dmem_wdata[22] ;
+ wire \u_riscv_top.core1_dmem_wdata[23] ;
+ wire \u_riscv_top.core1_dmem_wdata[24] ;
+ wire \u_riscv_top.core1_dmem_wdata[25] ;
+ wire \u_riscv_top.core1_dmem_wdata[26] ;
+ wire \u_riscv_top.core1_dmem_wdata[27] ;
+ wire \u_riscv_top.core1_dmem_wdata[28] ;
+ wire \u_riscv_top.core1_dmem_wdata[29] ;
+ wire \u_riscv_top.core1_dmem_wdata[2] ;
+ wire \u_riscv_top.core1_dmem_wdata[30] ;
+ wire \u_riscv_top.core1_dmem_wdata[31] ;
+ wire \u_riscv_top.core1_dmem_wdata[3] ;
+ wire \u_riscv_top.core1_dmem_wdata[4] ;
+ wire \u_riscv_top.core1_dmem_wdata[5] ;
+ wire \u_riscv_top.core1_dmem_wdata[6] ;
+ wire \u_riscv_top.core1_dmem_wdata[7] ;
+ wire \u_riscv_top.core1_dmem_wdata[8] ;
+ wire \u_riscv_top.core1_dmem_wdata[9] ;
+ wire \u_riscv_top.core1_dmem_width[0] ;
+ wire \u_riscv_top.core1_dmem_width[1] ;
+ wire \u_riscv_top.core1_imem_addr[0] ;
+ wire \u_riscv_top.core1_imem_addr[10] ;
+ wire \u_riscv_top.core1_imem_addr[11] ;
+ wire \u_riscv_top.core1_imem_addr[12] ;
+ wire \u_riscv_top.core1_imem_addr[13] ;
+ wire \u_riscv_top.core1_imem_addr[14] ;
+ wire \u_riscv_top.core1_imem_addr[15] ;
+ wire \u_riscv_top.core1_imem_addr[16] ;
+ wire \u_riscv_top.core1_imem_addr[17] ;
+ wire \u_riscv_top.core1_imem_addr[18] ;
+ wire \u_riscv_top.core1_imem_addr[19] ;
+ wire \u_riscv_top.core1_imem_addr[1] ;
+ wire \u_riscv_top.core1_imem_addr[20] ;
+ wire \u_riscv_top.core1_imem_addr[21] ;
+ wire \u_riscv_top.core1_imem_addr[22] ;
+ wire \u_riscv_top.core1_imem_addr[23] ;
+ wire \u_riscv_top.core1_imem_addr[24] ;
+ wire \u_riscv_top.core1_imem_addr[25] ;
+ wire \u_riscv_top.core1_imem_addr[26] ;
+ wire \u_riscv_top.core1_imem_addr[27] ;
+ wire \u_riscv_top.core1_imem_addr[28] ;
+ wire \u_riscv_top.core1_imem_addr[29] ;
+ wire \u_riscv_top.core1_imem_addr[2] ;
+ wire \u_riscv_top.core1_imem_addr[30] ;
+ wire \u_riscv_top.core1_imem_addr[31] ;
+ wire \u_riscv_top.core1_imem_addr[3] ;
+ wire \u_riscv_top.core1_imem_addr[4] ;
+ wire \u_riscv_top.core1_imem_addr[5] ;
+ wire \u_riscv_top.core1_imem_addr[6] ;
+ wire \u_riscv_top.core1_imem_addr[7] ;
+ wire \u_riscv_top.core1_imem_addr[8] ;
+ wire \u_riscv_top.core1_imem_addr[9] ;
+ wire \u_riscv_top.core1_imem_bl[0] ;
+ wire \u_riscv_top.core1_imem_bl[1] ;
+ wire \u_riscv_top.core1_imem_bl[2] ;
+ wire \u_riscv_top.core1_imem_cmd ;
+ wire \u_riscv_top.core1_imem_rdata[0] ;
+ wire \u_riscv_top.core1_imem_rdata[10] ;
+ wire \u_riscv_top.core1_imem_rdata[11] ;
+ wire \u_riscv_top.core1_imem_rdata[12] ;
+ wire \u_riscv_top.core1_imem_rdata[13] ;
+ wire \u_riscv_top.core1_imem_rdata[14] ;
+ wire \u_riscv_top.core1_imem_rdata[15] ;
+ wire \u_riscv_top.core1_imem_rdata[16] ;
+ wire \u_riscv_top.core1_imem_rdata[17] ;
+ wire \u_riscv_top.core1_imem_rdata[18] ;
+ wire \u_riscv_top.core1_imem_rdata[19] ;
+ wire \u_riscv_top.core1_imem_rdata[1] ;
+ wire \u_riscv_top.core1_imem_rdata[20] ;
+ wire \u_riscv_top.core1_imem_rdata[21] ;
+ wire \u_riscv_top.core1_imem_rdata[22] ;
+ wire \u_riscv_top.core1_imem_rdata[23] ;
+ wire \u_riscv_top.core1_imem_rdata[24] ;
+ wire \u_riscv_top.core1_imem_rdata[25] ;
+ wire \u_riscv_top.core1_imem_rdata[26] ;
+ wire \u_riscv_top.core1_imem_rdata[27] ;
+ wire \u_riscv_top.core1_imem_rdata[28] ;
+ wire \u_riscv_top.core1_imem_rdata[29] ;
+ wire \u_riscv_top.core1_imem_rdata[2] ;
+ wire \u_riscv_top.core1_imem_rdata[30] ;
+ wire \u_riscv_top.core1_imem_rdata[31] ;
+ wire \u_riscv_top.core1_imem_rdata[3] ;
+ wire \u_riscv_top.core1_imem_rdata[4] ;
+ wire \u_riscv_top.core1_imem_rdata[5] ;
+ wire \u_riscv_top.core1_imem_rdata[6] ;
+ wire \u_riscv_top.core1_imem_rdata[7] ;
+ wire \u_riscv_top.core1_imem_rdata[8] ;
+ wire \u_riscv_top.core1_imem_rdata[9] ;
+ wire \u_riscv_top.core1_imem_req ;
+ wire \u_riscv_top.core1_imem_req_ack ;
+ wire \u_riscv_top.core1_imem_resp[0] ;
+ wire \u_riscv_top.core1_imem_resp[1] ;
+ wire \u_riscv_top.core1_uid[0] ;
+ wire \u_riscv_top.core1_uid[1] ;
+ wire \u_riscv_top.core2_uid[0] ;
+ wire \u_riscv_top.core2_uid[1] ;
+ wire \u_riscv_top.core3_uid[0] ;
+ wire \u_riscv_top.core3_uid[1] ;
+ wire \u_riscv_top.core_clk ;
+ wire \u_riscv_top.core_debug_sel[0] ;
+ wire \u_riscv_top.core_debug_sel[1] ;
+ wire \u_riscv_top.cpu_core_rst_n[0] ;
+ wire \u_riscv_top.cpu_core_rst_n[1] ;
+ wire \u_riscv_top.cpu_core_rst_n_sync[0] ;
+ wire \u_riscv_top.cpu_core_rst_n_sync[1] ;
+ wire \u_riscv_top.cpu_intf_rst_n ;
+ wire \u_riscv_top.dcache_mem_addr0[0] ;
+ wire \u_riscv_top.dcache_mem_addr0[1] ;
+ wire \u_riscv_top.dcache_mem_addr0[2] ;
+ wire \u_riscv_top.dcache_mem_addr0[3] ;
+ wire \u_riscv_top.dcache_mem_addr0[4] ;
+ wire \u_riscv_top.dcache_mem_addr0[5] ;
+ wire \u_riscv_top.dcache_mem_addr0[6] ;
+ wire \u_riscv_top.dcache_mem_addr0[7] ;
+ wire \u_riscv_top.dcache_mem_addr0[8] ;
+ wire \u_riscv_top.dcache_mem_addr1[0] ;
+ wire \u_riscv_top.dcache_mem_addr1[1] ;
+ wire \u_riscv_top.dcache_mem_addr1[2] ;
+ wire \u_riscv_top.dcache_mem_addr1[3] ;
+ wire \u_riscv_top.dcache_mem_addr1[4] ;
+ wire \u_riscv_top.dcache_mem_addr1[5] ;
+ wire \u_riscv_top.dcache_mem_addr1[6] ;
+ wire \u_riscv_top.dcache_mem_addr1[7] ;
+ wire \u_riscv_top.dcache_mem_addr1[8] ;
+ wire \u_riscv_top.dcache_mem_clk0 ;
+ wire \u_riscv_top.dcache_mem_clk1 ;
+ wire \u_riscv_top.dcache_mem_csb0 ;
+ wire \u_riscv_top.dcache_mem_csb1 ;
+ wire \u_riscv_top.dcache_mem_din0[0] ;
+ wire \u_riscv_top.dcache_mem_din0[10] ;
+ wire \u_riscv_top.dcache_mem_din0[11] ;
+ wire \u_riscv_top.dcache_mem_din0[12] ;
+ wire \u_riscv_top.dcache_mem_din0[13] ;
+ wire \u_riscv_top.dcache_mem_din0[14] ;
+ wire \u_riscv_top.dcache_mem_din0[15] ;
+ wire \u_riscv_top.dcache_mem_din0[16] ;
+ wire \u_riscv_top.dcache_mem_din0[17] ;
+ wire \u_riscv_top.dcache_mem_din0[18] ;
+ wire \u_riscv_top.dcache_mem_din0[19] ;
+ wire \u_riscv_top.dcache_mem_din0[1] ;
+ wire \u_riscv_top.dcache_mem_din0[20] ;
+ wire \u_riscv_top.dcache_mem_din0[21] ;
+ wire \u_riscv_top.dcache_mem_din0[22] ;
+ wire \u_riscv_top.dcache_mem_din0[23] ;
+ wire \u_riscv_top.dcache_mem_din0[24] ;
+ wire \u_riscv_top.dcache_mem_din0[25] ;
+ wire \u_riscv_top.dcache_mem_din0[26] ;
+ wire \u_riscv_top.dcache_mem_din0[27] ;
+ wire \u_riscv_top.dcache_mem_din0[28] ;
+ wire \u_riscv_top.dcache_mem_din0[29] ;
+ wire \u_riscv_top.dcache_mem_din0[2] ;
+ wire \u_riscv_top.dcache_mem_din0[30] ;
+ wire \u_riscv_top.dcache_mem_din0[31] ;
+ wire \u_riscv_top.dcache_mem_din0[3] ;
+ wire \u_riscv_top.dcache_mem_din0[4] ;
+ wire \u_riscv_top.dcache_mem_din0[5] ;
+ wire \u_riscv_top.dcache_mem_din0[6] ;
+ wire \u_riscv_top.dcache_mem_din0[7] ;
+ wire \u_riscv_top.dcache_mem_din0[8] ;
+ wire \u_riscv_top.dcache_mem_din0[9] ;
+ wire \u_riscv_top.dcache_mem_dout0[0] ;
+ wire \u_riscv_top.dcache_mem_dout0[10] ;
+ wire \u_riscv_top.dcache_mem_dout0[11] ;
+ wire \u_riscv_top.dcache_mem_dout0[12] ;
+ wire \u_riscv_top.dcache_mem_dout0[13] ;
+ wire \u_riscv_top.dcache_mem_dout0[14] ;
+ wire \u_riscv_top.dcache_mem_dout0[15] ;
+ wire \u_riscv_top.dcache_mem_dout0[16] ;
+ wire \u_riscv_top.dcache_mem_dout0[17] ;
+ wire \u_riscv_top.dcache_mem_dout0[18] ;
+ wire \u_riscv_top.dcache_mem_dout0[19] ;
+ wire \u_riscv_top.dcache_mem_dout0[1] ;
+ wire \u_riscv_top.dcache_mem_dout0[20] ;
+ wire \u_riscv_top.dcache_mem_dout0[21] ;
+ wire \u_riscv_top.dcache_mem_dout0[22] ;
+ wire \u_riscv_top.dcache_mem_dout0[23] ;
+ wire \u_riscv_top.dcache_mem_dout0[24] ;
+ wire \u_riscv_top.dcache_mem_dout0[25] ;
+ wire \u_riscv_top.dcache_mem_dout0[26] ;
+ wire \u_riscv_top.dcache_mem_dout0[27] ;
+ wire \u_riscv_top.dcache_mem_dout0[28] ;
+ wire \u_riscv_top.dcache_mem_dout0[29] ;
+ wire \u_riscv_top.dcache_mem_dout0[2] ;
+ wire \u_riscv_top.dcache_mem_dout0[30] ;
+ wire \u_riscv_top.dcache_mem_dout0[31] ;
+ wire \u_riscv_top.dcache_mem_dout0[3] ;
+ wire \u_riscv_top.dcache_mem_dout0[4] ;
+ wire \u_riscv_top.dcache_mem_dout0[5] ;
+ wire \u_riscv_top.dcache_mem_dout0[6] ;
+ wire \u_riscv_top.dcache_mem_dout0[7] ;
+ wire \u_riscv_top.dcache_mem_dout0[8] ;
+ wire \u_riscv_top.dcache_mem_dout0[9] ;
+ wire \u_riscv_top.dcache_mem_dout1[0] ;
+ wire \u_riscv_top.dcache_mem_dout1[10] ;
+ wire \u_riscv_top.dcache_mem_dout1[11] ;
+ wire \u_riscv_top.dcache_mem_dout1[12] ;
+ wire \u_riscv_top.dcache_mem_dout1[13] ;
+ wire \u_riscv_top.dcache_mem_dout1[14] ;
+ wire \u_riscv_top.dcache_mem_dout1[15] ;
+ wire \u_riscv_top.dcache_mem_dout1[16] ;
+ wire \u_riscv_top.dcache_mem_dout1[17] ;
+ wire \u_riscv_top.dcache_mem_dout1[18] ;
+ wire \u_riscv_top.dcache_mem_dout1[19] ;
+ wire \u_riscv_top.dcache_mem_dout1[1] ;
+ wire \u_riscv_top.dcache_mem_dout1[20] ;
+ wire \u_riscv_top.dcache_mem_dout1[21] ;
+ wire \u_riscv_top.dcache_mem_dout1[22] ;
+ wire \u_riscv_top.dcache_mem_dout1[23] ;
+ wire \u_riscv_top.dcache_mem_dout1[24] ;
+ wire \u_riscv_top.dcache_mem_dout1[25] ;
+ wire \u_riscv_top.dcache_mem_dout1[26] ;
+ wire \u_riscv_top.dcache_mem_dout1[27] ;
+ wire \u_riscv_top.dcache_mem_dout1[28] ;
+ wire \u_riscv_top.dcache_mem_dout1[29] ;
+ wire \u_riscv_top.dcache_mem_dout1[2] ;
+ wire \u_riscv_top.dcache_mem_dout1[30] ;
+ wire \u_riscv_top.dcache_mem_dout1[31] ;
+ wire \u_riscv_top.dcache_mem_dout1[3] ;
+ wire \u_riscv_top.dcache_mem_dout1[4] ;
+ wire \u_riscv_top.dcache_mem_dout1[5] ;
+ wire \u_riscv_top.dcache_mem_dout1[6] ;
+ wire \u_riscv_top.dcache_mem_dout1[7] ;
+ wire \u_riscv_top.dcache_mem_dout1[8] ;
+ wire \u_riscv_top.dcache_mem_dout1[9] ;
+ wire \u_riscv_top.dcache_mem_web0 ;
+ wire \u_riscv_top.dcache_mem_wmask0[0] ;
+ wire \u_riscv_top.dcache_mem_wmask0[1] ;
+ wire \u_riscv_top.dcache_mem_wmask0[2] ;
+ wire \u_riscv_top.dcache_mem_wmask0[3] ;
+ wire \u_riscv_top.icache_mem_addr0[0] ;
+ wire \u_riscv_top.icache_mem_addr0[1] ;
+ wire \u_riscv_top.icache_mem_addr0[2] ;
+ wire \u_riscv_top.icache_mem_addr0[3] ;
+ wire \u_riscv_top.icache_mem_addr0[4] ;
+ wire \u_riscv_top.icache_mem_addr0[5] ;
+ wire \u_riscv_top.icache_mem_addr0[6] ;
+ wire \u_riscv_top.icache_mem_addr0[7] ;
+ wire \u_riscv_top.icache_mem_addr0[8] ;
+ wire \u_riscv_top.icache_mem_addr1[0] ;
+ wire \u_riscv_top.icache_mem_addr1[1] ;
+ wire \u_riscv_top.icache_mem_addr1[2] ;
+ wire \u_riscv_top.icache_mem_addr1[3] ;
+ wire \u_riscv_top.icache_mem_addr1[4] ;
+ wire \u_riscv_top.icache_mem_addr1[5] ;
+ wire \u_riscv_top.icache_mem_addr1[6] ;
+ wire \u_riscv_top.icache_mem_addr1[7] ;
+ wire \u_riscv_top.icache_mem_addr1[8] ;
+ wire \u_riscv_top.icache_mem_clk0 ;
+ wire \u_riscv_top.icache_mem_clk1 ;
+ wire \u_riscv_top.icache_mem_csb0 ;
+ wire \u_riscv_top.icache_mem_csb1 ;
+ wire \u_riscv_top.icache_mem_din0[0] ;
+ wire \u_riscv_top.icache_mem_din0[10] ;
+ wire \u_riscv_top.icache_mem_din0[11] ;
+ wire \u_riscv_top.icache_mem_din0[12] ;
+ wire \u_riscv_top.icache_mem_din0[13] ;
+ wire \u_riscv_top.icache_mem_din0[14] ;
+ wire \u_riscv_top.icache_mem_din0[15] ;
+ wire \u_riscv_top.icache_mem_din0[16] ;
+ wire \u_riscv_top.icache_mem_din0[17] ;
+ wire \u_riscv_top.icache_mem_din0[18] ;
+ wire \u_riscv_top.icache_mem_din0[19] ;
+ wire \u_riscv_top.icache_mem_din0[1] ;
+ wire \u_riscv_top.icache_mem_din0[20] ;
+ wire \u_riscv_top.icache_mem_din0[21] ;
+ wire \u_riscv_top.icache_mem_din0[22] ;
+ wire \u_riscv_top.icache_mem_din0[23] ;
+ wire \u_riscv_top.icache_mem_din0[24] ;
+ wire \u_riscv_top.icache_mem_din0[25] ;
+ wire \u_riscv_top.icache_mem_din0[26] ;
+ wire \u_riscv_top.icache_mem_din0[27] ;
+ wire \u_riscv_top.icache_mem_din0[28] ;
+ wire \u_riscv_top.icache_mem_din0[29] ;
+ wire \u_riscv_top.icache_mem_din0[2] ;
+ wire \u_riscv_top.icache_mem_din0[30] ;
+ wire \u_riscv_top.icache_mem_din0[31] ;
+ wire \u_riscv_top.icache_mem_din0[3] ;
+ wire \u_riscv_top.icache_mem_din0[4] ;
+ wire \u_riscv_top.icache_mem_din0[5] ;
+ wire \u_riscv_top.icache_mem_din0[6] ;
+ wire \u_riscv_top.icache_mem_din0[7] ;
+ wire \u_riscv_top.icache_mem_din0[8] ;
+ wire \u_riscv_top.icache_mem_din0[9] ;
+ wire \u_riscv_top.icache_mem_dout1[0] ;
+ wire \u_riscv_top.icache_mem_dout1[10] ;
+ wire \u_riscv_top.icache_mem_dout1[11] ;
+ wire \u_riscv_top.icache_mem_dout1[12] ;
+ wire \u_riscv_top.icache_mem_dout1[13] ;
+ wire \u_riscv_top.icache_mem_dout1[14] ;
+ wire \u_riscv_top.icache_mem_dout1[15] ;
+ wire \u_riscv_top.icache_mem_dout1[16] ;
+ wire \u_riscv_top.icache_mem_dout1[17] ;
+ wire \u_riscv_top.icache_mem_dout1[18] ;
+ wire \u_riscv_top.icache_mem_dout1[19] ;
+ wire \u_riscv_top.icache_mem_dout1[1] ;
+ wire \u_riscv_top.icache_mem_dout1[20] ;
+ wire \u_riscv_top.icache_mem_dout1[21] ;
+ wire \u_riscv_top.icache_mem_dout1[22] ;
+ wire \u_riscv_top.icache_mem_dout1[23] ;
+ wire \u_riscv_top.icache_mem_dout1[24] ;
+ wire \u_riscv_top.icache_mem_dout1[25] ;
+ wire \u_riscv_top.icache_mem_dout1[26] ;
+ wire \u_riscv_top.icache_mem_dout1[27] ;
+ wire \u_riscv_top.icache_mem_dout1[28] ;
+ wire \u_riscv_top.icache_mem_dout1[29] ;
+ wire \u_riscv_top.icache_mem_dout1[2] ;
+ wire \u_riscv_top.icache_mem_dout1[30] ;
+ wire \u_riscv_top.icache_mem_dout1[31] ;
+ wire \u_riscv_top.icache_mem_dout1[3] ;
+ wire \u_riscv_top.icache_mem_dout1[4] ;
+ wire \u_riscv_top.icache_mem_dout1[5] ;
+ wire \u_riscv_top.icache_mem_dout1[6] ;
+ wire \u_riscv_top.icache_mem_dout1[7] ;
+ wire \u_riscv_top.icache_mem_dout1[8] ;
+ wire \u_riscv_top.icache_mem_dout1[9] ;
+ wire \u_riscv_top.icache_mem_web0 ;
+ wire \u_riscv_top.icache_mem_wmask0[0] ;
+ wire \u_riscv_top.icache_mem_wmask0[1] ;
+ wire \u_riscv_top.icache_mem_wmask0[2] ;
+ wire \u_riscv_top.icache_mem_wmask0[3] ;
+ wire \u_riscv_top.irq_lines[0] ;
+ wire \u_riscv_top.irq_lines[10] ;
+ wire \u_riscv_top.irq_lines[11] ;
+ wire \u_riscv_top.irq_lines[12] ;
+ wire \u_riscv_top.irq_lines[13] ;
+ wire \u_riscv_top.irq_lines[14] ;
+ wire \u_riscv_top.irq_lines[15] ;
+ wire \u_riscv_top.irq_lines[1] ;
+ wire \u_riscv_top.irq_lines[2] ;
+ wire \u_riscv_top.irq_lines[3] ;
+ wire \u_riscv_top.irq_lines[4] ;
+ wire \u_riscv_top.irq_lines[5] ;
+ wire \u_riscv_top.irq_lines[6] ;
+ wire \u_riscv_top.irq_lines[7] ;
+ wire \u_riscv_top.irq_lines[8] ;
+ wire \u_riscv_top.irq_lines[9] ;
+ wire \u_riscv_top.pwrup_rst_n ;
+ wire \u_riscv_top.pwrup_rst_n_sync ;
+ wire \u_riscv_top.rst_n_sync ;
+ wire \u_riscv_top.rtc_clk ;
+ wire \u_riscv_top.soft_irq ;
+ wire \u_riscv_top.sram0_addr0[0] ;
+ wire \u_riscv_top.sram0_addr0[1] ;
+ wire \u_riscv_top.sram0_addr0[2] ;
+ wire \u_riscv_top.sram0_addr0[3] ;
+ wire \u_riscv_top.sram0_addr0[4] ;
+ wire \u_riscv_top.sram0_addr0[5] ;
+ wire \u_riscv_top.sram0_addr0[6] ;
+ wire \u_riscv_top.sram0_addr0[7] ;
+ wire \u_riscv_top.sram0_addr0[8] ;
+ wire \u_riscv_top.sram0_addr1[0] ;
+ wire \u_riscv_top.sram0_addr1[1] ;
+ wire \u_riscv_top.sram0_addr1[2] ;
+ wire \u_riscv_top.sram0_addr1[3] ;
+ wire \u_riscv_top.sram0_addr1[4] ;
+ wire \u_riscv_top.sram0_addr1[5] ;
+ wire \u_riscv_top.sram0_addr1[6] ;
+ wire \u_riscv_top.sram0_addr1[7] ;
+ wire \u_riscv_top.sram0_addr1[8] ;
+ wire \u_riscv_top.sram0_clk0 ;
+ wire \u_riscv_top.sram0_clk1 ;
+ wire \u_riscv_top.sram0_csb0 ;
+ wire \u_riscv_top.sram0_csb1 ;
+ wire \u_riscv_top.sram0_din0[0] ;
+ wire \u_riscv_top.sram0_din0[10] ;
+ wire \u_riscv_top.sram0_din0[11] ;
+ wire \u_riscv_top.sram0_din0[12] ;
+ wire \u_riscv_top.sram0_din0[13] ;
+ wire \u_riscv_top.sram0_din0[14] ;
+ wire \u_riscv_top.sram0_din0[15] ;
+ wire \u_riscv_top.sram0_din0[16] ;
+ wire \u_riscv_top.sram0_din0[17] ;
+ wire \u_riscv_top.sram0_din0[18] ;
+ wire \u_riscv_top.sram0_din0[19] ;
+ wire \u_riscv_top.sram0_din0[1] ;
+ wire \u_riscv_top.sram0_din0[20] ;
+ wire \u_riscv_top.sram0_din0[21] ;
+ wire \u_riscv_top.sram0_din0[22] ;
+ wire \u_riscv_top.sram0_din0[23] ;
+ wire \u_riscv_top.sram0_din0[24] ;
+ wire \u_riscv_top.sram0_din0[25] ;
+ wire \u_riscv_top.sram0_din0[26] ;
+ wire \u_riscv_top.sram0_din0[27] ;
+ wire \u_riscv_top.sram0_din0[28] ;
+ wire \u_riscv_top.sram0_din0[29] ;
+ wire \u_riscv_top.sram0_din0[2] ;
+ wire \u_riscv_top.sram0_din0[30] ;
+ wire \u_riscv_top.sram0_din0[31] ;
+ wire \u_riscv_top.sram0_din0[3] ;
+ wire \u_riscv_top.sram0_din0[4] ;
+ wire \u_riscv_top.sram0_din0[5] ;
+ wire \u_riscv_top.sram0_din0[6] ;
+ wire \u_riscv_top.sram0_din0[7] ;
+ wire \u_riscv_top.sram0_din0[8] ;
+ wire \u_riscv_top.sram0_din0[9] ;
+ wire \u_riscv_top.sram0_dout0[0] ;
+ wire \u_riscv_top.sram0_dout0[10] ;
+ wire \u_riscv_top.sram0_dout0[11] ;
+ wire \u_riscv_top.sram0_dout0[12] ;
+ wire \u_riscv_top.sram0_dout0[13] ;
+ wire \u_riscv_top.sram0_dout0[14] ;
+ wire \u_riscv_top.sram0_dout0[15] ;
+ wire \u_riscv_top.sram0_dout0[16] ;
+ wire \u_riscv_top.sram0_dout0[17] ;
+ wire \u_riscv_top.sram0_dout0[18] ;
+ wire \u_riscv_top.sram0_dout0[19] ;
+ wire \u_riscv_top.sram0_dout0[1] ;
+ wire \u_riscv_top.sram0_dout0[20] ;
+ wire \u_riscv_top.sram0_dout0[21] ;
+ wire \u_riscv_top.sram0_dout0[22] ;
+ wire \u_riscv_top.sram0_dout0[23] ;
+ wire \u_riscv_top.sram0_dout0[24] ;
+ wire \u_riscv_top.sram0_dout0[25] ;
+ wire \u_riscv_top.sram0_dout0[26] ;
+ wire \u_riscv_top.sram0_dout0[27] ;
+ wire \u_riscv_top.sram0_dout0[28] ;
+ wire \u_riscv_top.sram0_dout0[29] ;
+ wire \u_riscv_top.sram0_dout0[2] ;
+ wire \u_riscv_top.sram0_dout0[30] ;
+ wire \u_riscv_top.sram0_dout0[31] ;
+ wire \u_riscv_top.sram0_dout0[3] ;
+ wire \u_riscv_top.sram0_dout0[4] ;
+ wire \u_riscv_top.sram0_dout0[5] ;
+ wire \u_riscv_top.sram0_dout0[6] ;
+ wire \u_riscv_top.sram0_dout0[7] ;
+ wire \u_riscv_top.sram0_dout0[8] ;
+ wire \u_riscv_top.sram0_dout0[9] ;
+ wire \u_riscv_top.sram0_dout1[0] ;
+ wire \u_riscv_top.sram0_dout1[10] ;
+ wire \u_riscv_top.sram0_dout1[11] ;
+ wire \u_riscv_top.sram0_dout1[12] ;
+ wire \u_riscv_top.sram0_dout1[13] ;
+ wire \u_riscv_top.sram0_dout1[14] ;
+ wire \u_riscv_top.sram0_dout1[15] ;
+ wire \u_riscv_top.sram0_dout1[16] ;
+ wire \u_riscv_top.sram0_dout1[17] ;
+ wire \u_riscv_top.sram0_dout1[18] ;
+ wire \u_riscv_top.sram0_dout1[19] ;
+ wire \u_riscv_top.sram0_dout1[1] ;
+ wire \u_riscv_top.sram0_dout1[20] ;
+ wire \u_riscv_top.sram0_dout1[21] ;
+ wire \u_riscv_top.sram0_dout1[22] ;
+ wire \u_riscv_top.sram0_dout1[23] ;
+ wire \u_riscv_top.sram0_dout1[24] ;
+ wire \u_riscv_top.sram0_dout1[25] ;
+ wire \u_riscv_top.sram0_dout1[26] ;
+ wire \u_riscv_top.sram0_dout1[27] ;
+ wire \u_riscv_top.sram0_dout1[28] ;
+ wire \u_riscv_top.sram0_dout1[29] ;
+ wire \u_riscv_top.sram0_dout1[2] ;
+ wire \u_riscv_top.sram0_dout1[30] ;
+ wire \u_riscv_top.sram0_dout1[31] ;
+ wire \u_riscv_top.sram0_dout1[3] ;
+ wire \u_riscv_top.sram0_dout1[4] ;
+ wire \u_riscv_top.sram0_dout1[5] ;
+ wire \u_riscv_top.sram0_dout1[6] ;
+ wire \u_riscv_top.sram0_dout1[7] ;
+ wire \u_riscv_top.sram0_dout1[8] ;
+ wire \u_riscv_top.sram0_dout1[9] ;
+ wire \u_riscv_top.sram0_web0 ;
+ wire \u_riscv_top.sram0_wmask0[0] ;
+ wire \u_riscv_top.sram0_wmask0[1] ;
+ wire \u_riscv_top.sram0_wmask0[2] ;
+ wire \u_riscv_top.sram0_wmask0[3] ;
+ wire \u_riscv_top.test_mode ;
+ wire \u_riscv_top.test_rst_n ;
+ wire \u_riscv_top.timer_irq ;
+ wire \u_riscv_top.timer_val[0] ;
+ wire \u_riscv_top.timer_val[10] ;
+ wire \u_riscv_top.timer_val[11] ;
+ wire \u_riscv_top.timer_val[12] ;
+ wire \u_riscv_top.timer_val[13] ;
+ wire \u_riscv_top.timer_val[14] ;
+ wire \u_riscv_top.timer_val[15] ;
+ wire \u_riscv_top.timer_val[16] ;
+ wire \u_riscv_top.timer_val[17] ;
+ wire \u_riscv_top.timer_val[18] ;
+ wire \u_riscv_top.timer_val[19] ;
+ wire \u_riscv_top.timer_val[1] ;
+ wire \u_riscv_top.timer_val[20] ;
+ wire \u_riscv_top.timer_val[21] ;
+ wire \u_riscv_top.timer_val[22] ;
+ wire \u_riscv_top.timer_val[23] ;
+ wire \u_riscv_top.timer_val[24] ;
+ wire \u_riscv_top.timer_val[25] ;
+ wire \u_riscv_top.timer_val[26] ;
+ wire \u_riscv_top.timer_val[27] ;
+ wire \u_riscv_top.timer_val[28] ;
+ wire \u_riscv_top.timer_val[29] ;
+ wire \u_riscv_top.timer_val[2] ;
+ wire \u_riscv_top.timer_val[30] ;
+ wire \u_riscv_top.timer_val[31] ;
+ wire \u_riscv_top.timer_val[32] ;
+ wire \u_riscv_top.timer_val[33] ;
+ wire \u_riscv_top.timer_val[34] ;
+ wire \u_riscv_top.timer_val[35] ;
+ wire \u_riscv_top.timer_val[36] ;
+ wire \u_riscv_top.timer_val[37] ;
+ wire \u_riscv_top.timer_val[38] ;
+ wire \u_riscv_top.timer_val[39] ;
+ wire \u_riscv_top.timer_val[3] ;
+ wire \u_riscv_top.timer_val[40] ;
+ wire \u_riscv_top.timer_val[41] ;
+ wire \u_riscv_top.timer_val[42] ;
+ wire \u_riscv_top.timer_val[43] ;
+ wire \u_riscv_top.timer_val[44] ;
+ wire \u_riscv_top.timer_val[45] ;
+ wire \u_riscv_top.timer_val[46] ;
+ wire \u_riscv_top.timer_val[47] ;
+ wire \u_riscv_top.timer_val[48] ;
+ wire \u_riscv_top.timer_val[49] ;
+ wire \u_riscv_top.timer_val[4] ;
+ wire \u_riscv_top.timer_val[50] ;
+ wire \u_riscv_top.timer_val[51] ;
+ wire \u_riscv_top.timer_val[52] ;
+ wire \u_riscv_top.timer_val[53] ;
+ wire \u_riscv_top.timer_val[54] ;
+ wire \u_riscv_top.timer_val[55] ;
+ wire \u_riscv_top.timer_val[56] ;
+ wire \u_riscv_top.timer_val[57] ;
+ wire \u_riscv_top.timer_val[58] ;
+ wire \u_riscv_top.timer_val[59] ;
+ wire \u_riscv_top.timer_val[5] ;
+ wire \u_riscv_top.timer_val[60] ;
+ wire \u_riscv_top.timer_val[61] ;
+ wire \u_riscv_top.timer_val[62] ;
+ wire \u_riscv_top.timer_val[63] ;
+ wire \u_riscv_top.timer_val[6] ;
+ wire \u_riscv_top.timer_val[7] ;
+ wire \u_riscv_top.timer_val[8] ;
+ wire \u_riscv_top.timer_val[9] ;
+ wire \u_riscv_top.wb_clk ;
+ wire \u_riscv_top.wb_dcache_ack_i ;
+ wire \u_riscv_top.wb_dcache_adr_o[0] ;
+ wire \u_riscv_top.wb_dcache_adr_o[10] ;
+ wire \u_riscv_top.wb_dcache_adr_o[11] ;
+ wire \u_riscv_top.wb_dcache_adr_o[12] ;
+ wire \u_riscv_top.wb_dcache_adr_o[13] ;
+ wire \u_riscv_top.wb_dcache_adr_o[14] ;
+ wire \u_riscv_top.wb_dcache_adr_o[15] ;
+ wire \u_riscv_top.wb_dcache_adr_o[16] ;
+ wire \u_riscv_top.wb_dcache_adr_o[17] ;
+ wire \u_riscv_top.wb_dcache_adr_o[18] ;
+ wire \u_riscv_top.wb_dcache_adr_o[19] ;
+ wire \u_riscv_top.wb_dcache_adr_o[1] ;
+ wire \u_riscv_top.wb_dcache_adr_o[20] ;
+ wire \u_riscv_top.wb_dcache_adr_o[21] ;
+ wire \u_riscv_top.wb_dcache_adr_o[22] ;
+ wire \u_riscv_top.wb_dcache_adr_o[23] ;
+ wire \u_riscv_top.wb_dcache_adr_o[24] ;
+ wire \u_riscv_top.wb_dcache_adr_o[25] ;
+ wire \u_riscv_top.wb_dcache_adr_o[26] ;
+ wire \u_riscv_top.wb_dcache_adr_o[27] ;
+ wire \u_riscv_top.wb_dcache_adr_o[28] ;
+ wire \u_riscv_top.wb_dcache_adr_o[29] ;
+ wire \u_riscv_top.wb_dcache_adr_o[2] ;
+ wire \u_riscv_top.wb_dcache_adr_o[30] ;
+ wire \u_riscv_top.wb_dcache_adr_o[31] ;
+ wire \u_riscv_top.wb_dcache_adr_o[3] ;
+ wire \u_riscv_top.wb_dcache_adr_o[4] ;
+ wire \u_riscv_top.wb_dcache_adr_o[5] ;
+ wire \u_riscv_top.wb_dcache_adr_o[6] ;
+ wire \u_riscv_top.wb_dcache_adr_o[7] ;
+ wire \u_riscv_top.wb_dcache_adr_o[8] ;
+ wire \u_riscv_top.wb_dcache_adr_o[9] ;
+ wire \u_riscv_top.wb_dcache_bl_o[0] ;
+ wire \u_riscv_top.wb_dcache_bl_o[1] ;
+ wire \u_riscv_top.wb_dcache_bl_o[2] ;
+ wire \u_riscv_top.wb_dcache_bl_o[3] ;
+ wire \u_riscv_top.wb_dcache_bl_o[4] ;
+ wire \u_riscv_top.wb_dcache_bl_o[5] ;
+ wire \u_riscv_top.wb_dcache_bl_o[6] ;
+ wire \u_riscv_top.wb_dcache_bl_o[7] ;
+ wire \u_riscv_top.wb_dcache_bl_o[8] ;
+ wire \u_riscv_top.wb_dcache_bl_o[9] ;
+ wire \u_riscv_top.wb_dcache_bry_o ;
+ wire \u_riscv_top.wb_dcache_dat_i[0] ;
+ wire \u_riscv_top.wb_dcache_dat_i[10] ;
+ wire \u_riscv_top.wb_dcache_dat_i[11] ;
+ wire \u_riscv_top.wb_dcache_dat_i[12] ;
+ wire \u_riscv_top.wb_dcache_dat_i[13] ;
+ wire \u_riscv_top.wb_dcache_dat_i[14] ;
+ wire \u_riscv_top.wb_dcache_dat_i[15] ;
+ wire \u_riscv_top.wb_dcache_dat_i[16] ;
+ wire \u_riscv_top.wb_dcache_dat_i[17] ;
+ wire \u_riscv_top.wb_dcache_dat_i[18] ;
+ wire \u_riscv_top.wb_dcache_dat_i[19] ;
+ wire \u_riscv_top.wb_dcache_dat_i[1] ;
+ wire \u_riscv_top.wb_dcache_dat_i[20] ;
+ wire \u_riscv_top.wb_dcache_dat_i[21] ;
+ wire \u_riscv_top.wb_dcache_dat_i[22] ;
+ wire \u_riscv_top.wb_dcache_dat_i[23] ;
+ wire \u_riscv_top.wb_dcache_dat_i[24] ;
+ wire \u_riscv_top.wb_dcache_dat_i[25] ;
+ wire \u_riscv_top.wb_dcache_dat_i[26] ;
+ wire \u_riscv_top.wb_dcache_dat_i[27] ;
+ wire \u_riscv_top.wb_dcache_dat_i[28] ;
+ wire \u_riscv_top.wb_dcache_dat_i[29] ;
+ wire \u_riscv_top.wb_dcache_dat_i[2] ;
+ wire \u_riscv_top.wb_dcache_dat_i[30] ;
+ wire \u_riscv_top.wb_dcache_dat_i[31] ;
+ wire \u_riscv_top.wb_dcache_dat_i[3] ;
+ wire \u_riscv_top.wb_dcache_dat_i[4] ;
+ wire \u_riscv_top.wb_dcache_dat_i[5] ;
+ wire \u_riscv_top.wb_dcache_dat_i[6] ;
+ wire \u_riscv_top.wb_dcache_dat_i[7] ;
+ wire \u_riscv_top.wb_dcache_dat_i[8] ;
+ wire \u_riscv_top.wb_dcache_dat_i[9] ;
+ wire \u_riscv_top.wb_dcache_dat_o[0] ;
+ wire \u_riscv_top.wb_dcache_dat_o[10] ;
+ wire \u_riscv_top.wb_dcache_dat_o[11] ;
+ wire \u_riscv_top.wb_dcache_dat_o[12] ;
+ wire \u_riscv_top.wb_dcache_dat_o[13] ;
+ wire \u_riscv_top.wb_dcache_dat_o[14] ;
+ wire \u_riscv_top.wb_dcache_dat_o[15] ;
+ wire \u_riscv_top.wb_dcache_dat_o[16] ;
+ wire \u_riscv_top.wb_dcache_dat_o[17] ;
+ wire \u_riscv_top.wb_dcache_dat_o[18] ;
+ wire \u_riscv_top.wb_dcache_dat_o[19] ;
+ wire \u_riscv_top.wb_dcache_dat_o[1] ;
+ wire \u_riscv_top.wb_dcache_dat_o[20] ;
+ wire \u_riscv_top.wb_dcache_dat_o[21] ;
+ wire \u_riscv_top.wb_dcache_dat_o[22] ;
+ wire \u_riscv_top.wb_dcache_dat_o[23] ;
+ wire \u_riscv_top.wb_dcache_dat_o[24] ;
+ wire \u_riscv_top.wb_dcache_dat_o[25] ;
+ wire \u_riscv_top.wb_dcache_dat_o[26] ;
+ wire \u_riscv_top.wb_dcache_dat_o[27] ;
+ wire \u_riscv_top.wb_dcache_dat_o[28] ;
+ wire \u_riscv_top.wb_dcache_dat_o[29] ;
+ wire \u_riscv_top.wb_dcache_dat_o[2] ;
+ wire \u_riscv_top.wb_dcache_dat_o[30] ;
+ wire \u_riscv_top.wb_dcache_dat_o[31] ;
+ wire \u_riscv_top.wb_dcache_dat_o[3] ;
+ wire \u_riscv_top.wb_dcache_dat_o[4] ;
+ wire \u_riscv_top.wb_dcache_dat_o[5] ;
+ wire \u_riscv_top.wb_dcache_dat_o[6] ;
+ wire \u_riscv_top.wb_dcache_dat_o[7] ;
+ wire \u_riscv_top.wb_dcache_dat_o[8] ;
+ wire \u_riscv_top.wb_dcache_dat_o[9] ;
+ wire \u_riscv_top.wb_dcache_err_i ;
+ wire \u_riscv_top.wb_dcache_lack_i ;
+ wire \u_riscv_top.wb_dcache_sel_o[0] ;
+ wire \u_riscv_top.wb_dcache_sel_o[1] ;
+ wire \u_riscv_top.wb_dcache_sel_o[2] ;
+ wire \u_riscv_top.wb_dcache_sel_o[3] ;
+ wire \u_riscv_top.wb_dcache_stb_o ;
+ wire \u_riscv_top.wb_dcache_we_o ;
+ wire \u_riscv_top.wb_icache_ack_i ;
+ wire \u_riscv_top.wb_icache_adr_o[0] ;
+ wire \u_riscv_top.wb_icache_adr_o[10] ;
+ wire \u_riscv_top.wb_icache_adr_o[11] ;
+ wire \u_riscv_top.wb_icache_adr_o[12] ;
+ wire \u_riscv_top.wb_icache_adr_o[13] ;
+ wire \u_riscv_top.wb_icache_adr_o[14] ;
+ wire \u_riscv_top.wb_icache_adr_o[15] ;
+ wire \u_riscv_top.wb_icache_adr_o[16] ;
+ wire \u_riscv_top.wb_icache_adr_o[17] ;
+ wire \u_riscv_top.wb_icache_adr_o[18] ;
+ wire \u_riscv_top.wb_icache_adr_o[19] ;
+ wire \u_riscv_top.wb_icache_adr_o[1] ;
+ wire \u_riscv_top.wb_icache_adr_o[20] ;
+ wire \u_riscv_top.wb_icache_adr_o[21] ;
+ wire \u_riscv_top.wb_icache_adr_o[22] ;
+ wire \u_riscv_top.wb_icache_adr_o[23] ;
+ wire \u_riscv_top.wb_icache_adr_o[24] ;
+ wire \u_riscv_top.wb_icache_adr_o[25] ;
+ wire \u_riscv_top.wb_icache_adr_o[26] ;
+ wire \u_riscv_top.wb_icache_adr_o[27] ;
+ wire \u_riscv_top.wb_icache_adr_o[28] ;
+ wire \u_riscv_top.wb_icache_adr_o[29] ;
+ wire \u_riscv_top.wb_icache_adr_o[2] ;
+ wire \u_riscv_top.wb_icache_adr_o[30] ;
+ wire \u_riscv_top.wb_icache_adr_o[31] ;
+ wire \u_riscv_top.wb_icache_adr_o[3] ;
+ wire \u_riscv_top.wb_icache_adr_o[4] ;
+ wire \u_riscv_top.wb_icache_adr_o[5] ;
+ wire \u_riscv_top.wb_icache_adr_o[6] ;
+ wire \u_riscv_top.wb_icache_adr_o[7] ;
+ wire \u_riscv_top.wb_icache_adr_o[8] ;
+ wire \u_riscv_top.wb_icache_adr_o[9] ;
+ wire \u_riscv_top.wb_icache_bl_o[0] ;
+ wire \u_riscv_top.wb_icache_bl_o[1] ;
+ wire \u_riscv_top.wb_icache_bl_o[2] ;
+ wire \u_riscv_top.wb_icache_bl_o[3] ;
+ wire \u_riscv_top.wb_icache_bl_o[4] ;
+ wire \u_riscv_top.wb_icache_bl_o[5] ;
+ wire \u_riscv_top.wb_icache_bl_o[6] ;
+ wire \u_riscv_top.wb_icache_bl_o[7] ;
+ wire \u_riscv_top.wb_icache_bl_o[8] ;
+ wire \u_riscv_top.wb_icache_bl_o[9] ;
+ wire \u_riscv_top.wb_icache_bry_o ;
+ wire \u_riscv_top.wb_icache_dat_i[0] ;
+ wire \u_riscv_top.wb_icache_dat_i[10] ;
+ wire \u_riscv_top.wb_icache_dat_i[11] ;
+ wire \u_riscv_top.wb_icache_dat_i[12] ;
+ wire \u_riscv_top.wb_icache_dat_i[13] ;
+ wire \u_riscv_top.wb_icache_dat_i[14] ;
+ wire \u_riscv_top.wb_icache_dat_i[15] ;
+ wire \u_riscv_top.wb_icache_dat_i[16] ;
+ wire \u_riscv_top.wb_icache_dat_i[17] ;
+ wire \u_riscv_top.wb_icache_dat_i[18] ;
+ wire \u_riscv_top.wb_icache_dat_i[19] ;
+ wire \u_riscv_top.wb_icache_dat_i[1] ;
+ wire \u_riscv_top.wb_icache_dat_i[20] ;
+ wire \u_riscv_top.wb_icache_dat_i[21] ;
+ wire \u_riscv_top.wb_icache_dat_i[22] ;
+ wire \u_riscv_top.wb_icache_dat_i[23] ;
+ wire \u_riscv_top.wb_icache_dat_i[24] ;
+ wire \u_riscv_top.wb_icache_dat_i[25] ;
+ wire \u_riscv_top.wb_icache_dat_i[26] ;
+ wire \u_riscv_top.wb_icache_dat_i[27] ;
+ wire \u_riscv_top.wb_icache_dat_i[28] ;
+ wire \u_riscv_top.wb_icache_dat_i[29] ;
+ wire \u_riscv_top.wb_icache_dat_i[2] ;
+ wire \u_riscv_top.wb_icache_dat_i[30] ;
+ wire \u_riscv_top.wb_icache_dat_i[31] ;
+ wire \u_riscv_top.wb_icache_dat_i[3] ;
+ wire \u_riscv_top.wb_icache_dat_i[4] ;
+ wire \u_riscv_top.wb_icache_dat_i[5] ;
+ wire \u_riscv_top.wb_icache_dat_i[6] ;
+ wire \u_riscv_top.wb_icache_dat_i[7] ;
+ wire \u_riscv_top.wb_icache_dat_i[8] ;
+ wire \u_riscv_top.wb_icache_dat_i[9] ;
+ wire \u_riscv_top.wb_icache_err_i ;
+ wire \u_riscv_top.wb_icache_lack_i ;
+ wire \u_riscv_top.wb_icache_sel_o[0] ;
+ wire \u_riscv_top.wb_icache_sel_o[1] ;
+ wire \u_riscv_top.wb_icache_sel_o[2] ;
+ wire \u_riscv_top.wb_icache_sel_o[3] ;
+ wire \u_riscv_top.wb_icache_stb_o ;
+ wire \u_riscv_top.wb_icache_we_o ;
+ wire \u_riscv_top.wbd_clk_int ;
+ wire \u_riscv_top.wbd_dmem_ack_i ;
+ wire \u_riscv_top.wbd_dmem_adr_o[0] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[10] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[11] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[12] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[13] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[14] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[15] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[16] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[17] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[18] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[19] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[1] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[20] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[21] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[22] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[23] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[24] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[25] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[26] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[27] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[28] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[29] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[2] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[30] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[31] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[3] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[4] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[5] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[6] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[7] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[8] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[9] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[0] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[10] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[11] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[12] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[13] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[14] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[15] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[16] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[17] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[18] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[19] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[1] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[20] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[21] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[22] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[23] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[24] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[25] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[26] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[27] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[28] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[29] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[2] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[30] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[31] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[3] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[4] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[5] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[6] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[7] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[8] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[9] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[0] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[10] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[11] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[12] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[13] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[14] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[15] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[16] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[17] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[18] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[19] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[1] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[20] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[21] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[22] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[23] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[24] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[25] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[26] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[27] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[28] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[29] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[2] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[30] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[31] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[3] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[4] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[5] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[6] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[7] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[8] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[9] ;
+ wire \u_riscv_top.wbd_dmem_err_i ;
+ wire \u_riscv_top.wbd_dmem_sel_o[0] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[1] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[2] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[3] ;
+ wire \u_riscv_top.wbd_dmem_stb_o ;
+ wire \u_riscv_top.wbd_dmem_we_o ;
+ wire uart_rst_n;
+ wire uart_rxd;
+ wire uart_txd;
+ wire uartm_rxd;
+ wire uartm_txd;
+ wire usb_clk;
+ wire usb_dn_i;
+ wire usb_dn_o;
+ wire usb_dp_i;
+ wire usb_dp_o;
+ wire usb_intr_o;
+ wire usb_oen;
+ wire usb_rst_n;
+ wire wbd_clk_int;
+ wire wbd_clk_pinmux_rp;
+ wire wbd_clk_pinmux_skew;
+ wire wbd_clk_qspi_rp;
+ wire wbd_clk_spi;
+ wire wbd_clk_uart_rp;
+ wire wbd_clk_uart_skew;
+ wire wbd_clk_wh;
+ wire wbd_clk_wi_skew;
+ wire wbd_glbl_ack_i;
+ wire \wbd_glbl_adr_o[0] ;
+ wire \wbd_glbl_adr_o[1] ;
+ wire \wbd_glbl_adr_o[2] ;
+ wire \wbd_glbl_adr_o[3] ;
+ wire \wbd_glbl_adr_o[4] ;
+ wire \wbd_glbl_adr_o[5] ;
+ wire \wbd_glbl_adr_o[6] ;
+ wire \wbd_glbl_adr_o[7] ;
+ wire wbd_glbl_cyc_o;
+ wire \wbd_glbl_dat_i[0] ;
+ wire \wbd_glbl_dat_i[10] ;
+ wire \wbd_glbl_dat_i[11] ;
+ wire \wbd_glbl_dat_i[12] ;
+ wire \wbd_glbl_dat_i[13] ;
+ wire \wbd_glbl_dat_i[14] ;
+ wire \wbd_glbl_dat_i[15] ;
+ wire \wbd_glbl_dat_i[16] ;
+ wire \wbd_glbl_dat_i[17] ;
+ wire \wbd_glbl_dat_i[18] ;
+ wire \wbd_glbl_dat_i[19] ;
+ wire \wbd_glbl_dat_i[1] ;
+ wire \wbd_glbl_dat_i[20] ;
+ wire \wbd_glbl_dat_i[21] ;
+ wire \wbd_glbl_dat_i[22] ;
+ wire \wbd_glbl_dat_i[23] ;
+ wire \wbd_glbl_dat_i[24] ;
+ wire \wbd_glbl_dat_i[25] ;
+ wire \wbd_glbl_dat_i[26] ;
+ wire \wbd_glbl_dat_i[27] ;
+ wire \wbd_glbl_dat_i[28] ;
+ wire \wbd_glbl_dat_i[29] ;
+ wire \wbd_glbl_dat_i[2] ;
+ wire \wbd_glbl_dat_i[30] ;
+ wire \wbd_glbl_dat_i[31] ;
+ wire \wbd_glbl_dat_i[3] ;
+ wire \wbd_glbl_dat_i[4] ;
+ wire \wbd_glbl_dat_i[5] ;
+ wire \wbd_glbl_dat_i[6] ;
+ wire \wbd_glbl_dat_i[7] ;
+ wire \wbd_glbl_dat_i[8] ;
+ wire \wbd_glbl_dat_i[9] ;
+ wire \wbd_glbl_dat_o[0] ;
+ wire \wbd_glbl_dat_o[10] ;
+ wire \wbd_glbl_dat_o[11] ;
+ wire \wbd_glbl_dat_o[12] ;
+ wire \wbd_glbl_dat_o[13] ;
+ wire \wbd_glbl_dat_o[14] ;
+ wire \wbd_glbl_dat_o[15] ;
+ wire \wbd_glbl_dat_o[16] ;
+ wire \wbd_glbl_dat_o[17] ;
+ wire \wbd_glbl_dat_o[18] ;
+ wire \wbd_glbl_dat_o[19] ;
+ wire \wbd_glbl_dat_o[1] ;
+ wire \wbd_glbl_dat_o[20] ;
+ wire \wbd_glbl_dat_o[21] ;
+ wire \wbd_glbl_dat_o[22] ;
+ wire \wbd_glbl_dat_o[23] ;
+ wire \wbd_glbl_dat_o[24] ;
+ wire \wbd_glbl_dat_o[25] ;
+ wire \wbd_glbl_dat_o[26] ;
+ wire \wbd_glbl_dat_o[27] ;
+ wire \wbd_glbl_dat_o[28] ;
+ wire \wbd_glbl_dat_o[29] ;
+ wire \wbd_glbl_dat_o[2] ;
+ wire \wbd_glbl_dat_o[30] ;
+ wire \wbd_glbl_dat_o[31] ;
+ wire \wbd_glbl_dat_o[3] ;
+ wire \wbd_glbl_dat_o[4] ;
+ wire \wbd_glbl_dat_o[5] ;
+ wire \wbd_glbl_dat_o[6] ;
+ wire \wbd_glbl_dat_o[7] ;
+ wire \wbd_glbl_dat_o[8] ;
+ wire \wbd_glbl_dat_o[9] ;
+ wire \wbd_glbl_sel_o[0] ;
+ wire \wbd_glbl_sel_o[1] ;
+ wire \wbd_glbl_sel_o[2] ;
+ wire \wbd_glbl_sel_o[3] ;
+ wire wbd_glbl_stb_o;
+ wire wbd_glbl_we_o;
+ wire wbd_int_ack_o;
+ wire \wbd_int_adr_i[0] ;
+ wire \wbd_int_adr_i[10] ;
+ wire \wbd_int_adr_i[11] ;
+ wire \wbd_int_adr_i[12] ;
+ wire \wbd_int_adr_i[13] ;
+ wire \wbd_int_adr_i[14] ;
+ wire \wbd_int_adr_i[15] ;
+ wire \wbd_int_adr_i[16] ;
+ wire \wbd_int_adr_i[17] ;
+ wire \wbd_int_adr_i[18] ;
+ wire \wbd_int_adr_i[19] ;
+ wire \wbd_int_adr_i[1] ;
+ wire \wbd_int_adr_i[20] ;
+ wire \wbd_int_adr_i[21] ;
+ wire \wbd_int_adr_i[22] ;
+ wire \wbd_int_adr_i[23] ;
+ wire \wbd_int_adr_i[24] ;
+ wire \wbd_int_adr_i[25] ;
+ wire \wbd_int_adr_i[26] ;
+ wire \wbd_int_adr_i[27] ;
+ wire \wbd_int_adr_i[28] ;
+ wire \wbd_int_adr_i[29] ;
+ wire \wbd_int_adr_i[2] ;
+ wire \wbd_int_adr_i[30] ;
+ wire \wbd_int_adr_i[31] ;
+ wire \wbd_int_adr_i[3] ;
+ wire \wbd_int_adr_i[4] ;
+ wire \wbd_int_adr_i[5] ;
+ wire \wbd_int_adr_i[6] ;
+ wire \wbd_int_adr_i[7] ;
+ wire \wbd_int_adr_i[8] ;
+ wire \wbd_int_adr_i[9] ;
+ wire wbd_int_cyc_i;
+ wire \wbd_int_dat_i[0] ;
+ wire \wbd_int_dat_i[10] ;
+ wire \wbd_int_dat_i[11] ;
+ wire \wbd_int_dat_i[12] ;
+ wire \wbd_int_dat_i[13] ;
+ wire \wbd_int_dat_i[14] ;
+ wire \wbd_int_dat_i[15] ;
+ wire \wbd_int_dat_i[16] ;
+ wire \wbd_int_dat_i[17] ;
+ wire \wbd_int_dat_i[18] ;
+ wire \wbd_int_dat_i[19] ;
+ wire \wbd_int_dat_i[1] ;
+ wire \wbd_int_dat_i[20] ;
+ wire \wbd_int_dat_i[21] ;
+ wire \wbd_int_dat_i[22] ;
+ wire \wbd_int_dat_i[23] ;
+ wire \wbd_int_dat_i[24] ;
+ wire \wbd_int_dat_i[25] ;
+ wire \wbd_int_dat_i[26] ;
+ wire \wbd_int_dat_i[27] ;
+ wire \wbd_int_dat_i[28] ;
+ wire \wbd_int_dat_i[29] ;
+ wire \wbd_int_dat_i[2] ;
+ wire \wbd_int_dat_i[30] ;
+ wire \wbd_int_dat_i[31] ;
+ wire \wbd_int_dat_i[3] ;
+ wire \wbd_int_dat_i[4] ;
+ wire \wbd_int_dat_i[5] ;
+ wire \wbd_int_dat_i[6] ;
+ wire \wbd_int_dat_i[7] ;
+ wire \wbd_int_dat_i[8] ;
+ wire \wbd_int_dat_i[9] ;
+ wire \wbd_int_dat_o[0] ;
+ wire \wbd_int_dat_o[10] ;
+ wire \wbd_int_dat_o[11] ;
+ wire \wbd_int_dat_o[12] ;
+ wire \wbd_int_dat_o[13] ;
+ wire \wbd_int_dat_o[14] ;
+ wire \wbd_int_dat_o[15] ;
+ wire \wbd_int_dat_o[16] ;
+ wire \wbd_int_dat_o[17] ;
+ wire \wbd_int_dat_o[18] ;
+ wire \wbd_int_dat_o[19] ;
+ wire \wbd_int_dat_o[1] ;
+ wire \wbd_int_dat_o[20] ;
+ wire \wbd_int_dat_o[21] ;
+ wire \wbd_int_dat_o[22] ;
+ wire \wbd_int_dat_o[23] ;
+ wire \wbd_int_dat_o[24] ;
+ wire \wbd_int_dat_o[25] ;
+ wire \wbd_int_dat_o[26] ;
+ wire \wbd_int_dat_o[27] ;
+ wire \wbd_int_dat_o[28] ;
+ wire \wbd_int_dat_o[29] ;
+ wire \wbd_int_dat_o[2] ;
+ wire \wbd_int_dat_o[30] ;
+ wire \wbd_int_dat_o[31] ;
+ wire \wbd_int_dat_o[3] ;
+ wire \wbd_int_dat_o[4] ;
+ wire \wbd_int_dat_o[5] ;
+ wire \wbd_int_dat_o[6] ;
+ wire \wbd_int_dat_o[7] ;
+ wire \wbd_int_dat_o[8] ;
+ wire \wbd_int_dat_o[9] ;
+ wire wbd_int_err_o;
+ wire \wbd_int_sel_i[0] ;
+ wire \wbd_int_sel_i[1] ;
+ wire \wbd_int_sel_i[2] ;
+ wire \wbd_int_sel_i[3] ;
+ wire wbd_int_stb_i;
+ wire wbd_int_we_i;
+ wire wbd_spim_ack_i;
+ wire \wbd_spim_adr_o[0] ;
+ wire \wbd_spim_adr_o[10] ;
+ wire \wbd_spim_adr_o[11] ;
+ wire \wbd_spim_adr_o[12] ;
+ wire \wbd_spim_adr_o[13] ;
+ wire \wbd_spim_adr_o[14] ;
+ wire \wbd_spim_adr_o[15] ;
+ wire \wbd_spim_adr_o[16] ;
+ wire \wbd_spim_adr_o[17] ;
+ wire \wbd_spim_adr_o[18] ;
+ wire \wbd_spim_adr_o[19] ;
+ wire \wbd_spim_adr_o[1] ;
+ wire \wbd_spim_adr_o[20] ;
+ wire \wbd_spim_adr_o[21] ;
+ wire \wbd_spim_adr_o[22] ;
+ wire \wbd_spim_adr_o[23] ;
+ wire \wbd_spim_adr_o[24] ;
+ wire \wbd_spim_adr_o[25] ;
+ wire \wbd_spim_adr_o[26] ;
+ wire \wbd_spim_adr_o[27] ;
+ wire \wbd_spim_adr_o[28] ;
+ wire \wbd_spim_adr_o[29] ;
+ wire \wbd_spim_adr_o[2] ;
+ wire \wbd_spim_adr_o[30] ;
+ wire \wbd_spim_adr_o[31] ;
+ wire \wbd_spim_adr_o[3] ;
+ wire \wbd_spim_adr_o[4] ;
+ wire \wbd_spim_adr_o[5] ;
+ wire \wbd_spim_adr_o[6] ;
+ wire \wbd_spim_adr_o[7] ;
+ wire \wbd_spim_adr_o[8] ;
+ wire \wbd_spim_adr_o[9] ;
+ wire \wbd_spim_bl_o[0] ;
+ wire \wbd_spim_bl_o[1] ;
+ wire \wbd_spim_bl_o[2] ;
+ wire \wbd_spim_bl_o[3] ;
+ wire \wbd_spim_bl_o[4] ;
+ wire \wbd_spim_bl_o[5] ;
+ wire \wbd_spim_bl_o[6] ;
+ wire \wbd_spim_bl_o[7] ;
+ wire \wbd_spim_bl_o[8] ;
+ wire \wbd_spim_bl_o[9] ;
+ wire wbd_spim_bry_o;
+ wire wbd_spim_cyc_o;
+ wire \wbd_spim_dat_i[0] ;
+ wire \wbd_spim_dat_i[10] ;
+ wire \wbd_spim_dat_i[11] ;
+ wire \wbd_spim_dat_i[12] ;
+ wire \wbd_spim_dat_i[13] ;
+ wire \wbd_spim_dat_i[14] ;
+ wire \wbd_spim_dat_i[15] ;
+ wire \wbd_spim_dat_i[16] ;
+ wire \wbd_spim_dat_i[17] ;
+ wire \wbd_spim_dat_i[18] ;
+ wire \wbd_spim_dat_i[19] ;
+ wire \wbd_spim_dat_i[1] ;
+ wire \wbd_spim_dat_i[20] ;
+ wire \wbd_spim_dat_i[21] ;
+ wire \wbd_spim_dat_i[22] ;
+ wire \wbd_spim_dat_i[23] ;
+ wire \wbd_spim_dat_i[24] ;
+ wire \wbd_spim_dat_i[25] ;
+ wire \wbd_spim_dat_i[26] ;
+ wire \wbd_spim_dat_i[27] ;
+ wire \wbd_spim_dat_i[28] ;
+ wire \wbd_spim_dat_i[29] ;
+ wire \wbd_spim_dat_i[2] ;
+ wire \wbd_spim_dat_i[30] ;
+ wire \wbd_spim_dat_i[31] ;
+ wire \wbd_spim_dat_i[3] ;
+ wire \wbd_spim_dat_i[4] ;
+ wire \wbd_spim_dat_i[5] ;
+ wire \wbd_spim_dat_i[6] ;
+ wire \wbd_spim_dat_i[7] ;
+ wire \wbd_spim_dat_i[8] ;
+ wire \wbd_spim_dat_i[9] ;
+ wire \wbd_spim_dat_o[0] ;
+ wire \wbd_spim_dat_o[10] ;
+ wire \wbd_spim_dat_o[11] ;
+ wire \wbd_spim_dat_o[12] ;
+ wire \wbd_spim_dat_o[13] ;
+ wire \wbd_spim_dat_o[14] ;
+ wire \wbd_spim_dat_o[15] ;
+ wire \wbd_spim_dat_o[16] ;
+ wire \wbd_spim_dat_o[17] ;
+ wire \wbd_spim_dat_o[18] ;
+ wire \wbd_spim_dat_o[19] ;
+ wire \wbd_spim_dat_o[1] ;
+ wire \wbd_spim_dat_o[20] ;
+ wire \wbd_spim_dat_o[21] ;
+ wire \wbd_spim_dat_o[22] ;
+ wire \wbd_spim_dat_o[23] ;
+ wire \wbd_spim_dat_o[24] ;
+ wire \wbd_spim_dat_o[25] ;
+ wire \wbd_spim_dat_o[26] ;
+ wire \wbd_spim_dat_o[27] ;
+ wire \wbd_spim_dat_o[28] ;
+ wire \wbd_spim_dat_o[29] ;
+ wire \wbd_spim_dat_o[2] ;
+ wire \wbd_spim_dat_o[30] ;
+ wire \wbd_spim_dat_o[31] ;
+ wire \wbd_spim_dat_o[3] ;
+ wire \wbd_spim_dat_o[4] ;
+ wire \wbd_spim_dat_o[5] ;
+ wire \wbd_spim_dat_o[6] ;
+ wire \wbd_spim_dat_o[7] ;
+ wire \wbd_spim_dat_o[8] ;
+ wire \wbd_spim_dat_o[9] ;
+ wire wbd_spim_err_i;
+ wire wbd_spim_lack_i;
+ wire \wbd_spim_sel_o[0] ;
+ wire \wbd_spim_sel_o[1] ;
+ wire \wbd_spim_sel_o[2] ;
+ wire \wbd_spim_sel_o[3] ;
+ wire wbd_spim_stb_o;
+ wire wbd_spim_we_o;
+ wire wbd_uart_ack_i;
+ wire \wbd_uart_adr_o[0] ;
+ wire \wbd_uart_adr_o[1] ;
+ wire \wbd_uart_adr_o[2] ;
+ wire \wbd_uart_adr_o[3] ;
+ wire \wbd_uart_adr_o[4] ;
+ wire \wbd_uart_adr_o[5] ;
+ wire \wbd_uart_adr_o[6] ;
+ wire \wbd_uart_adr_o[7] ;
+ wire wbd_uart_cyc_o;
+ wire \wbd_uart_dat_i[0] ;
+ wire \wbd_uart_dat_i[10] ;
+ wire \wbd_uart_dat_i[11] ;
+ wire \wbd_uart_dat_i[12] ;
+ wire \wbd_uart_dat_i[13] ;
+ wire \wbd_uart_dat_i[14] ;
+ wire \wbd_uart_dat_i[15] ;
+ wire \wbd_uart_dat_i[16] ;
+ wire \wbd_uart_dat_i[17] ;
+ wire \wbd_uart_dat_i[18] ;
+ wire \wbd_uart_dat_i[19] ;
+ wire \wbd_uart_dat_i[1] ;
+ wire \wbd_uart_dat_i[20] ;
+ wire \wbd_uart_dat_i[21] ;
+ wire \wbd_uart_dat_i[22] ;
+ wire \wbd_uart_dat_i[23] ;
+ wire \wbd_uart_dat_i[24] ;
+ wire \wbd_uart_dat_i[25] ;
+ wire \wbd_uart_dat_i[26] ;
+ wire \wbd_uart_dat_i[27] ;
+ wire \wbd_uart_dat_i[28] ;
+ wire \wbd_uart_dat_i[29] ;
+ wire \wbd_uart_dat_i[2] ;
+ wire \wbd_uart_dat_i[30] ;
+ wire \wbd_uart_dat_i[31] ;
+ wire \wbd_uart_dat_i[3] ;
+ wire \wbd_uart_dat_i[4] ;
+ wire \wbd_uart_dat_i[5] ;
+ wire \wbd_uart_dat_i[6] ;
+ wire \wbd_uart_dat_i[7] ;
+ wire \wbd_uart_dat_i[8] ;
+ wire \wbd_uart_dat_i[9] ;
+ wire \wbd_uart_dat_o[0] ;
+ wire \wbd_uart_dat_o[10] ;
+ wire \wbd_uart_dat_o[11] ;
+ wire \wbd_uart_dat_o[12] ;
+ wire \wbd_uart_dat_o[13] ;
+ wire \wbd_uart_dat_o[14] ;
+ wire \wbd_uart_dat_o[15] ;
+ wire \wbd_uart_dat_o[16] ;
+ wire \wbd_uart_dat_o[17] ;
+ wire \wbd_uart_dat_o[18] ;
+ wire \wbd_uart_dat_o[19] ;
+ wire \wbd_uart_dat_o[1] ;
+ wire \wbd_uart_dat_o[20] ;
+ wire \wbd_uart_dat_o[21] ;
+ wire \wbd_uart_dat_o[22] ;
+ wire \wbd_uart_dat_o[23] ;
+ wire \wbd_uart_dat_o[24] ;
+ wire \wbd_uart_dat_o[25] ;
+ wire \wbd_uart_dat_o[26] ;
+ wire \wbd_uart_dat_o[27] ;
+ wire \wbd_uart_dat_o[28] ;
+ wire \wbd_uart_dat_o[29] ;
+ wire \wbd_uart_dat_o[2] ;
+ wire \wbd_uart_dat_o[30] ;
+ wire \wbd_uart_dat_o[31] ;
+ wire \wbd_uart_dat_o[3] ;
+ wire \wbd_uart_dat_o[4] ;
+ wire \wbd_uart_dat_o[5] ;
+ wire \wbd_uart_dat_o[6] ;
+ wire \wbd_uart_dat_o[7] ;
+ wire \wbd_uart_dat_o[8] ;
+ wire \wbd_uart_dat_o[9] ;
+ wire \wbd_uart_sel_o[0] ;
+ wire \wbd_uart_sel_o[1] ;
+ wire \wbd_uart_sel_o[2] ;
+ wire \wbd_uart_sel_o[3] ;
+ wire wbd_uart_stb_o;
+ wire wbd_uart_we_o;
+
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_dcache_2kb (.csb0(\u_riscv_top.dcache_mem_csb0 ),
+    .csb1(\u_riscv_top.dcache_mem_csb1 ),
+    .web0(\u_riscv_top.dcache_mem_web0 ),
+    .clk0(\u_riscv_top.dcache_mem_clk0 ),
+    .clk1(\u_riscv_top.dcache_mem_clk1 ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\u_riscv_top.dcache_mem_addr0[8] ,
+    \u_riscv_top.dcache_mem_addr0[7] ,
+    \u_riscv_top.dcache_mem_addr0[6] ,
+    \u_riscv_top.dcache_mem_addr0[5] ,
+    \u_riscv_top.dcache_mem_addr0[4] ,
+    \u_riscv_top.dcache_mem_addr0[3] ,
+    \u_riscv_top.dcache_mem_addr0[2] ,
+    \u_riscv_top.dcache_mem_addr0[1] ,
+    \u_riscv_top.dcache_mem_addr0[0] }),
+    .addr1({\u_riscv_top.dcache_mem_addr1[8] ,
+    \u_riscv_top.dcache_mem_addr1[7] ,
+    \u_riscv_top.dcache_mem_addr1[6] ,
+    \u_riscv_top.dcache_mem_addr1[5] ,
+    \u_riscv_top.dcache_mem_addr1[4] ,
+    \u_riscv_top.dcache_mem_addr1[3] ,
+    \u_riscv_top.dcache_mem_addr1[2] ,
+    \u_riscv_top.dcache_mem_addr1[1] ,
+    \u_riscv_top.dcache_mem_addr1[0] }),
+    .din0({\u_riscv_top.dcache_mem_din0[31] ,
+    \u_riscv_top.dcache_mem_din0[30] ,
+    \u_riscv_top.dcache_mem_din0[29] ,
+    \u_riscv_top.dcache_mem_din0[28] ,
+    \u_riscv_top.dcache_mem_din0[27] ,
+    \u_riscv_top.dcache_mem_din0[26] ,
+    \u_riscv_top.dcache_mem_din0[25] ,
+    \u_riscv_top.dcache_mem_din0[24] ,
+    \u_riscv_top.dcache_mem_din0[23] ,
+    \u_riscv_top.dcache_mem_din0[22] ,
+    \u_riscv_top.dcache_mem_din0[21] ,
+    \u_riscv_top.dcache_mem_din0[20] ,
+    \u_riscv_top.dcache_mem_din0[19] ,
+    \u_riscv_top.dcache_mem_din0[18] ,
+    \u_riscv_top.dcache_mem_din0[17] ,
+    \u_riscv_top.dcache_mem_din0[16] ,
+    \u_riscv_top.dcache_mem_din0[15] ,
+    \u_riscv_top.dcache_mem_din0[14] ,
+    \u_riscv_top.dcache_mem_din0[13] ,
+    \u_riscv_top.dcache_mem_din0[12] ,
+    \u_riscv_top.dcache_mem_din0[11] ,
+    \u_riscv_top.dcache_mem_din0[10] ,
+    \u_riscv_top.dcache_mem_din0[9] ,
+    \u_riscv_top.dcache_mem_din0[8] ,
+    \u_riscv_top.dcache_mem_din0[7] ,
+    \u_riscv_top.dcache_mem_din0[6] ,
+    \u_riscv_top.dcache_mem_din0[5] ,
+    \u_riscv_top.dcache_mem_din0[4] ,
+    \u_riscv_top.dcache_mem_din0[3] ,
+    \u_riscv_top.dcache_mem_din0[2] ,
+    \u_riscv_top.dcache_mem_din0[1] ,
+    \u_riscv_top.dcache_mem_din0[0] }),
+    .dout0({\u_riscv_top.dcache_mem_dout0[31] ,
+    \u_riscv_top.dcache_mem_dout0[30] ,
+    \u_riscv_top.dcache_mem_dout0[29] ,
+    \u_riscv_top.dcache_mem_dout0[28] ,
+    \u_riscv_top.dcache_mem_dout0[27] ,
+    \u_riscv_top.dcache_mem_dout0[26] ,
+    \u_riscv_top.dcache_mem_dout0[25] ,
+    \u_riscv_top.dcache_mem_dout0[24] ,
+    \u_riscv_top.dcache_mem_dout0[23] ,
+    \u_riscv_top.dcache_mem_dout0[22] ,
+    \u_riscv_top.dcache_mem_dout0[21] ,
+    \u_riscv_top.dcache_mem_dout0[20] ,
+    \u_riscv_top.dcache_mem_dout0[19] ,
+    \u_riscv_top.dcache_mem_dout0[18] ,
+    \u_riscv_top.dcache_mem_dout0[17] ,
+    \u_riscv_top.dcache_mem_dout0[16] ,
+    \u_riscv_top.dcache_mem_dout0[15] ,
+    \u_riscv_top.dcache_mem_dout0[14] ,
+    \u_riscv_top.dcache_mem_dout0[13] ,
+    \u_riscv_top.dcache_mem_dout0[12] ,
+    \u_riscv_top.dcache_mem_dout0[11] ,
+    \u_riscv_top.dcache_mem_dout0[10] ,
+    \u_riscv_top.dcache_mem_dout0[9] ,
+    \u_riscv_top.dcache_mem_dout0[8] ,
+    \u_riscv_top.dcache_mem_dout0[7] ,
+    \u_riscv_top.dcache_mem_dout0[6] ,
+    \u_riscv_top.dcache_mem_dout0[5] ,
+    \u_riscv_top.dcache_mem_dout0[4] ,
+    \u_riscv_top.dcache_mem_dout0[3] ,
+    \u_riscv_top.dcache_mem_dout0[2] ,
+    \u_riscv_top.dcache_mem_dout0[1] ,
+    \u_riscv_top.dcache_mem_dout0[0] }),
+    .dout1({\u_riscv_top.dcache_mem_dout1[31] ,
+    \u_riscv_top.dcache_mem_dout1[30] ,
+    \u_riscv_top.dcache_mem_dout1[29] ,
+    \u_riscv_top.dcache_mem_dout1[28] ,
+    \u_riscv_top.dcache_mem_dout1[27] ,
+    \u_riscv_top.dcache_mem_dout1[26] ,
+    \u_riscv_top.dcache_mem_dout1[25] ,
+    \u_riscv_top.dcache_mem_dout1[24] ,
+    \u_riscv_top.dcache_mem_dout1[23] ,
+    \u_riscv_top.dcache_mem_dout1[22] ,
+    \u_riscv_top.dcache_mem_dout1[21] ,
+    \u_riscv_top.dcache_mem_dout1[20] ,
+    \u_riscv_top.dcache_mem_dout1[19] ,
+    \u_riscv_top.dcache_mem_dout1[18] ,
+    \u_riscv_top.dcache_mem_dout1[17] ,
+    \u_riscv_top.dcache_mem_dout1[16] ,
+    \u_riscv_top.dcache_mem_dout1[15] ,
+    \u_riscv_top.dcache_mem_dout1[14] ,
+    \u_riscv_top.dcache_mem_dout1[13] ,
+    \u_riscv_top.dcache_mem_dout1[12] ,
+    \u_riscv_top.dcache_mem_dout1[11] ,
+    \u_riscv_top.dcache_mem_dout1[10] ,
+    \u_riscv_top.dcache_mem_dout1[9] ,
+    \u_riscv_top.dcache_mem_dout1[8] ,
+    \u_riscv_top.dcache_mem_dout1[7] ,
+    \u_riscv_top.dcache_mem_dout1[6] ,
+    \u_riscv_top.dcache_mem_dout1[5] ,
+    \u_riscv_top.dcache_mem_dout1[4] ,
+    \u_riscv_top.dcache_mem_dout1[3] ,
+    \u_riscv_top.dcache_mem_dout1[2] ,
+    \u_riscv_top.dcache_mem_dout1[1] ,
+    \u_riscv_top.dcache_mem_dout1[0] }),
+    .wmask0({\u_riscv_top.dcache_mem_wmask0[3] ,
+    \u_riscv_top.dcache_mem_wmask0[2] ,
+    \u_riscv_top.dcache_mem_wmask0[1] ,
+    \u_riscv_top.dcache_mem_wmask0[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_icache_2kb (.csb0(\u_riscv_top.icache_mem_csb0 ),
+    .csb1(\u_riscv_top.icache_mem_csb1 ),
+    .web0(\u_riscv_top.icache_mem_web0 ),
+    .clk0(\u_riscv_top.icache_mem_clk0 ),
+    .clk1(\u_riscv_top.icache_mem_clk1 ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\u_riscv_top.icache_mem_addr0[8] ,
+    \u_riscv_top.icache_mem_addr0[7] ,
+    \u_riscv_top.icache_mem_addr0[6] ,
+    \u_riscv_top.icache_mem_addr0[5] ,
+    \u_riscv_top.icache_mem_addr0[4] ,
+    \u_riscv_top.icache_mem_addr0[3] ,
+    \u_riscv_top.icache_mem_addr0[2] ,
+    \u_riscv_top.icache_mem_addr0[1] ,
+    \u_riscv_top.icache_mem_addr0[0] }),
+    .addr1({\u_riscv_top.icache_mem_addr1[8] ,
+    \u_riscv_top.icache_mem_addr1[7] ,
+    \u_riscv_top.icache_mem_addr1[6] ,
+    \u_riscv_top.icache_mem_addr1[5] ,
+    \u_riscv_top.icache_mem_addr1[4] ,
+    \u_riscv_top.icache_mem_addr1[3] ,
+    \u_riscv_top.icache_mem_addr1[2] ,
+    \u_riscv_top.icache_mem_addr1[1] ,
+    \u_riscv_top.icache_mem_addr1[0] }),
+    .din0({\u_riscv_top.icache_mem_din0[31] ,
+    \u_riscv_top.icache_mem_din0[30] ,
+    \u_riscv_top.icache_mem_din0[29] ,
+    \u_riscv_top.icache_mem_din0[28] ,
+    \u_riscv_top.icache_mem_din0[27] ,
+    \u_riscv_top.icache_mem_din0[26] ,
+    \u_riscv_top.icache_mem_din0[25] ,
+    \u_riscv_top.icache_mem_din0[24] ,
+    \u_riscv_top.icache_mem_din0[23] ,
+    \u_riscv_top.icache_mem_din0[22] ,
+    \u_riscv_top.icache_mem_din0[21] ,
+    \u_riscv_top.icache_mem_din0[20] ,
+    \u_riscv_top.icache_mem_din0[19] ,
+    \u_riscv_top.icache_mem_din0[18] ,
+    \u_riscv_top.icache_mem_din0[17] ,
+    \u_riscv_top.icache_mem_din0[16] ,
+    \u_riscv_top.icache_mem_din0[15] ,
+    \u_riscv_top.icache_mem_din0[14] ,
+    \u_riscv_top.icache_mem_din0[13] ,
+    \u_riscv_top.icache_mem_din0[12] ,
+    \u_riscv_top.icache_mem_din0[11] ,
+    \u_riscv_top.icache_mem_din0[10] ,
+    \u_riscv_top.icache_mem_din0[9] ,
+    \u_riscv_top.icache_mem_din0[8] ,
+    \u_riscv_top.icache_mem_din0[7] ,
+    \u_riscv_top.icache_mem_din0[6] ,
+    \u_riscv_top.icache_mem_din0[5] ,
+    \u_riscv_top.icache_mem_din0[4] ,
+    \u_riscv_top.icache_mem_din0[3] ,
+    \u_riscv_top.icache_mem_din0[2] ,
+    \u_riscv_top.icache_mem_din0[1] ,
+    \u_riscv_top.icache_mem_din0[0] }),
+    .dout0({_NC1,
+    _NC2,
+    _NC3,
+    _NC4,
+    _NC5,
+    _NC6,
+    _NC7,
+    _NC8,
+    _NC9,
+    _NC10,
+    _NC11,
+    _NC12,
+    _NC13,
+    _NC14,
+    _NC15,
+    _NC16,
+    _NC17,
+    _NC18,
+    _NC19,
+    _NC20,
+    _NC21,
+    _NC22,
+    _NC23,
+    _NC24,
+    _NC25,
+    _NC26,
+    _NC27,
+    _NC28,
+    _NC29,
+    _NC30,
+    _NC31,
+    _NC32}),
+    .dout1({\u_riscv_top.icache_mem_dout1[31] ,
+    \u_riscv_top.icache_mem_dout1[30] ,
+    \u_riscv_top.icache_mem_dout1[29] ,
+    \u_riscv_top.icache_mem_dout1[28] ,
+    \u_riscv_top.icache_mem_dout1[27] ,
+    \u_riscv_top.icache_mem_dout1[26] ,
+    \u_riscv_top.icache_mem_dout1[25] ,
+    \u_riscv_top.icache_mem_dout1[24] ,
+    \u_riscv_top.icache_mem_dout1[23] ,
+    \u_riscv_top.icache_mem_dout1[22] ,
+    \u_riscv_top.icache_mem_dout1[21] ,
+    \u_riscv_top.icache_mem_dout1[20] ,
+    \u_riscv_top.icache_mem_dout1[19] ,
+    \u_riscv_top.icache_mem_dout1[18] ,
+    \u_riscv_top.icache_mem_dout1[17] ,
+    \u_riscv_top.icache_mem_dout1[16] ,
+    \u_riscv_top.icache_mem_dout1[15] ,
+    \u_riscv_top.icache_mem_dout1[14] ,
+    \u_riscv_top.icache_mem_dout1[13] ,
+    \u_riscv_top.icache_mem_dout1[12] ,
+    \u_riscv_top.icache_mem_dout1[11] ,
+    \u_riscv_top.icache_mem_dout1[10] ,
+    \u_riscv_top.icache_mem_dout1[9] ,
+    \u_riscv_top.icache_mem_dout1[8] ,
+    \u_riscv_top.icache_mem_dout1[7] ,
+    \u_riscv_top.icache_mem_dout1[6] ,
+    \u_riscv_top.icache_mem_dout1[5] ,
+    \u_riscv_top.icache_mem_dout1[4] ,
+    \u_riscv_top.icache_mem_dout1[3] ,
+    \u_riscv_top.icache_mem_dout1[2] ,
+    \u_riscv_top.icache_mem_dout1[1] ,
+    \u_riscv_top.icache_mem_dout1[0] }),
+    .wmask0({\u_riscv_top.icache_mem_wmask0[3] ,
+    \u_riscv_top.icache_mem_wmask0[2] ,
+    \u_riscv_top.icache_mem_wmask0[1] ,
+    \u_riscv_top.icache_mem_wmask0[0] }));
+ wb_interconnect u_intercon (.clk_i(wbd_clk_wi_skew),
+    .m0_wbd_ack_o(wbd_int_ack_o),
+    .m0_wbd_cyc_i(wbd_int_cyc_i),
+    .m0_wbd_err_o(wbd_int_err_o),
+    .m0_wbd_stb_i(wbd_int_stb_i),
+    .m0_wbd_we_i(wbd_int_we_i),
+    .m1_wbd_ack_o(\u_riscv_top.wbd_dmem_ack_i ),
+    .m1_wbd_cyc_i(\u_riscv_top.wbd_dmem_stb_o ),
+    .m1_wbd_err_o(\u_riscv_top.wbd_dmem_err_i ),
+    .m1_wbd_stb_i(\u_riscv_top.wbd_dmem_stb_o ),
+    .m1_wbd_we_i(\u_riscv_top.wbd_dmem_we_o ),
+    .m2_wbd_ack_o(\u_riscv_top.wb_dcache_ack_i ),
+    .m2_wbd_bry_i(\u_riscv_top.wb_dcache_bry_o ),
+    .m2_wbd_cyc_i(\u_riscv_top.wb_dcache_stb_o ),
+    .m2_wbd_err_o(\u_riscv_top.wb_dcache_err_i ),
+    .m2_wbd_lack_o(\u_riscv_top.wb_dcache_lack_i ),
+    .m2_wbd_stb_i(\u_riscv_top.wb_dcache_stb_o ),
+    .m2_wbd_we_i(\u_riscv_top.wb_dcache_we_o ),
+    .m3_wbd_ack_o(\u_riscv_top.wb_icache_ack_i ),
+    .m3_wbd_bry_i(\u_riscv_top.wb_icache_bry_o ),
+    .m3_wbd_cyc_i(\u_riscv_top.wb_icache_stb_o ),
+    .m3_wbd_err_o(\u_riscv_top.wb_icache_err_i ),
+    .m3_wbd_lack_o(\u_riscv_top.wb_icache_lack_i ),
+    .m3_wbd_stb_i(\u_riscv_top.wb_icache_stb_o ),
+    .m3_wbd_we_i(\u_riscv_top.wb_icache_we_o ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .s0_wbd_ack_i(wbd_spim_ack_i),
+    .s0_wbd_bry_o(wbd_spim_bry_o),
+    .s0_wbd_cyc_o(wbd_spim_cyc_o),
+    .s0_wbd_lack_i(wbd_spim_lack_i),
+    .s0_wbd_stb_o(wbd_spim_stb_o),
+    .s0_wbd_we_o(wbd_spim_we_o),
+    .s1_wbd_ack_i(wbd_uart_ack_i),
+    .s1_wbd_cyc_o(wbd_uart_cyc_o),
+    .s1_wbd_stb_o(wbd_uart_stb_o),
+    .s1_wbd_we_o(wbd_uart_we_o),
+    .s2_wbd_ack_i(wbd_glbl_ack_i),
+    .s2_wbd_cyc_o(wbd_glbl_cyc_o),
+    .s2_wbd_stb_o(wbd_glbl_stb_o),
+    .s2_wbd_we_o(wbd_glbl_we_o),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_int),
+    .wbd_clk_wi(wbd_clk_wi_skew),
+    .cfg_cska_wi({\cfg_clk_ctrl1[3] ,
+    \cfg_clk_ctrl1[2] ,
+    \cfg_clk_ctrl1[1] ,
+    \cfg_clk_ctrl1[0] }),
+    .ch_clk_in({wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int}),
+    .ch_clk_out({wbd_clk_pinmux_rp,
+    wbd_clk_uart_rp,
+    wbd_clk_qspi_rp,
+    \u_riscv_top.wbd_clk_int }),
+    .ch_data_in({soft_irq,
+    \irq_lines[15] ,
+    \irq_lines[14] ,
+    \irq_lines[13] ,
+    \irq_lines[12] ,
+    \irq_lines[11] ,
+    \irq_lines[10] ,
+    \irq_lines[9] ,
+    \irq_lines[8] ,
+    \irq_lines[7] ,
+    \irq_lines[6] ,
+    \irq_lines[5] ,
+    \irq_lines[4] ,
+    \irq_lines[3] ,
+    \irq_lines[2] ,
+    \irq_lines[1] ,
+    \irq_lines[0] ,
+    \cfg_clk_ctrl1[27] ,
+    \cfg_clk_ctrl1[26] ,
+    \cfg_clk_ctrl1[25] ,
+    \cfg_clk_ctrl1[24] ,
+    \cfg_clk_ctrl1[23] ,
+    \cfg_clk_ctrl1[22] ,
+    \cfg_clk_ctrl1[21] ,
+    \cfg_clk_ctrl1[20] ,
+    \cfg_clk_ctrl1[19] ,
+    \cfg_clk_ctrl1[18] ,
+    \cfg_clk_ctrl1[17] ,
+    \cfg_clk_ctrl1[16] ,
+    \cfg_clk_ctrl1[15] ,
+    \cfg_clk_ctrl1[14] ,
+    \cfg_clk_ctrl1[13] ,
+    \cfg_clk_ctrl1[12] ,
+    \cfg_clk_ctrl1[11] ,
+    \cfg_clk_ctrl1[10] ,
+    \cfg_clk_ctrl1[9] ,
+    \cfg_clk_ctrl1[8] }),
+    .ch_data_out({\u_riscv_top.soft_irq ,
+    \u_riscv_top.irq_lines[15] ,
+    \u_riscv_top.irq_lines[14] ,
+    \u_riscv_top.irq_lines[13] ,
+    \u_riscv_top.irq_lines[12] ,
+    \u_riscv_top.irq_lines[11] ,
+    \u_riscv_top.irq_lines[10] ,
+    \u_riscv_top.irq_lines[9] ,
+    \u_riscv_top.irq_lines[8] ,
+    \u_riscv_top.irq_lines[7] ,
+    \u_riscv_top.irq_lines[6] ,
+    \u_riscv_top.irq_lines[5] ,
+    \u_riscv_top.irq_lines[4] ,
+    \u_riscv_top.irq_lines[3] ,
+    \u_riscv_top.irq_lines[2] ,
+    \u_riscv_top.irq_lines[1] ,
+    \u_riscv_top.irq_lines[0] ,
+    \cfg_cska_qspi_co_rp[3] ,
+    \cfg_cska_qspi_co_rp[2] ,
+    \cfg_cska_qspi_co_rp[1] ,
+    \cfg_cska_qspi_co_rp[0] ,
+    \cfg_cska_pinmux_rp[3] ,
+    \cfg_cska_pinmux_rp[2] ,
+    \cfg_cska_pinmux_rp[1] ,
+    \cfg_cska_pinmux_rp[0] ,
+    \cfg_cska_uart_rp[3] ,
+    \cfg_cska_uart_rp[2] ,
+    \cfg_cska_uart_rp[1] ,
+    \cfg_cska_uart_rp[0] ,
+    \cfg_cska_qspi_rp[3] ,
+    \cfg_cska_qspi_rp[2] ,
+    \cfg_cska_qspi_rp[1] ,
+    \cfg_cska_qspi_rp[0] ,
+    \u_riscv_top.cfg_cska_riscv[3] ,
+    \u_riscv_top.cfg_cska_riscv[2] ,
+    \u_riscv_top.cfg_cska_riscv[1] ,
+    \u_riscv_top.cfg_cska_riscv[0] }),
+    .m0_wbd_adr_i({\wbd_int_adr_i[31] ,
+    \wbd_int_adr_i[30] ,
+    \wbd_int_adr_i[29] ,
+    \wbd_int_adr_i[28] ,
+    \wbd_int_adr_i[27] ,
+    \wbd_int_adr_i[26] ,
+    \wbd_int_adr_i[25] ,
+    \wbd_int_adr_i[24] ,
+    \wbd_int_adr_i[23] ,
+    \wbd_int_adr_i[22] ,
+    \wbd_int_adr_i[21] ,
+    \wbd_int_adr_i[20] ,
+    \wbd_int_adr_i[19] ,
+    \wbd_int_adr_i[18] ,
+    \wbd_int_adr_i[17] ,
+    \wbd_int_adr_i[16] ,
+    \wbd_int_adr_i[15] ,
+    \wbd_int_adr_i[14] ,
+    \wbd_int_adr_i[13] ,
+    \wbd_int_adr_i[12] ,
+    \wbd_int_adr_i[11] ,
+    \wbd_int_adr_i[10] ,
+    \wbd_int_adr_i[9] ,
+    \wbd_int_adr_i[8] ,
+    \wbd_int_adr_i[7] ,
+    \wbd_int_adr_i[6] ,
+    \wbd_int_adr_i[5] ,
+    \wbd_int_adr_i[4] ,
+    \wbd_int_adr_i[3] ,
+    \wbd_int_adr_i[2] ,
+    \wbd_int_adr_i[1] ,
+    \wbd_int_adr_i[0] }),
+    .m0_wbd_dat_i({\wbd_int_dat_i[31] ,
+    \wbd_int_dat_i[30] ,
+    \wbd_int_dat_i[29] ,
+    \wbd_int_dat_i[28] ,
+    \wbd_int_dat_i[27] ,
+    \wbd_int_dat_i[26] ,
+    \wbd_int_dat_i[25] ,
+    \wbd_int_dat_i[24] ,
+    \wbd_int_dat_i[23] ,
+    \wbd_int_dat_i[22] ,
+    \wbd_int_dat_i[21] ,
+    \wbd_int_dat_i[20] ,
+    \wbd_int_dat_i[19] ,
+    \wbd_int_dat_i[18] ,
+    \wbd_int_dat_i[17] ,
+    \wbd_int_dat_i[16] ,
+    \wbd_int_dat_i[15] ,
+    \wbd_int_dat_i[14] ,
+    \wbd_int_dat_i[13] ,
+    \wbd_int_dat_i[12] ,
+    \wbd_int_dat_i[11] ,
+    \wbd_int_dat_i[10] ,
+    \wbd_int_dat_i[9] ,
+    \wbd_int_dat_i[8] ,
+    \wbd_int_dat_i[7] ,
+    \wbd_int_dat_i[6] ,
+    \wbd_int_dat_i[5] ,
+    \wbd_int_dat_i[4] ,
+    \wbd_int_dat_i[3] ,
+    \wbd_int_dat_i[2] ,
+    \wbd_int_dat_i[1] ,
+    \wbd_int_dat_i[0] }),
+    .m0_wbd_dat_o({\wbd_int_dat_o[31] ,
+    \wbd_int_dat_o[30] ,
+    \wbd_int_dat_o[29] ,
+    \wbd_int_dat_o[28] ,
+    \wbd_int_dat_o[27] ,
+    \wbd_int_dat_o[26] ,
+    \wbd_int_dat_o[25] ,
+    \wbd_int_dat_o[24] ,
+    \wbd_int_dat_o[23] ,
+    \wbd_int_dat_o[22] ,
+    \wbd_int_dat_o[21] ,
+    \wbd_int_dat_o[20] ,
+    \wbd_int_dat_o[19] ,
+    \wbd_int_dat_o[18] ,
+    \wbd_int_dat_o[17] ,
+    \wbd_int_dat_o[16] ,
+    \wbd_int_dat_o[15] ,
+    \wbd_int_dat_o[14] ,
+    \wbd_int_dat_o[13] ,
+    \wbd_int_dat_o[12] ,
+    \wbd_int_dat_o[11] ,
+    \wbd_int_dat_o[10] ,
+    \wbd_int_dat_o[9] ,
+    \wbd_int_dat_o[8] ,
+    \wbd_int_dat_o[7] ,
+    \wbd_int_dat_o[6] ,
+    \wbd_int_dat_o[5] ,
+    \wbd_int_dat_o[4] ,
+    \wbd_int_dat_o[3] ,
+    \wbd_int_dat_o[2] ,
+    \wbd_int_dat_o[1] ,
+    \wbd_int_dat_o[0] }),
+    .m0_wbd_sel_i({\wbd_int_sel_i[3] ,
+    \wbd_int_sel_i[2] ,
+    \wbd_int_sel_i[1] ,
+    \wbd_int_sel_i[0] }),
+    .m1_wbd_adr_i({\u_riscv_top.wbd_dmem_adr_o[31] ,
+    \u_riscv_top.wbd_dmem_adr_o[30] ,
+    \u_riscv_top.wbd_dmem_adr_o[29] ,
+    \u_riscv_top.wbd_dmem_adr_o[28] ,
+    \u_riscv_top.wbd_dmem_adr_o[27] ,
+    \u_riscv_top.wbd_dmem_adr_o[26] ,
+    \u_riscv_top.wbd_dmem_adr_o[25] ,
+    \u_riscv_top.wbd_dmem_adr_o[24] ,
+    \u_riscv_top.wbd_dmem_adr_o[23] ,
+    \u_riscv_top.wbd_dmem_adr_o[22] ,
+    \u_riscv_top.wbd_dmem_adr_o[21] ,
+    \u_riscv_top.wbd_dmem_adr_o[20] ,
+    \u_riscv_top.wbd_dmem_adr_o[19] ,
+    \u_riscv_top.wbd_dmem_adr_o[18] ,
+    \u_riscv_top.wbd_dmem_adr_o[17] ,
+    \u_riscv_top.wbd_dmem_adr_o[16] ,
+    \u_riscv_top.wbd_dmem_adr_o[15] ,
+    \u_riscv_top.wbd_dmem_adr_o[14] ,
+    \u_riscv_top.wbd_dmem_adr_o[13] ,
+    \u_riscv_top.wbd_dmem_adr_o[12] ,
+    \u_riscv_top.wbd_dmem_adr_o[11] ,
+    \u_riscv_top.wbd_dmem_adr_o[10] ,
+    \u_riscv_top.wbd_dmem_adr_o[9] ,
+    \u_riscv_top.wbd_dmem_adr_o[8] ,
+    \u_riscv_top.wbd_dmem_adr_o[7] ,
+    \u_riscv_top.wbd_dmem_adr_o[6] ,
+    \u_riscv_top.wbd_dmem_adr_o[5] ,
+    \u_riscv_top.wbd_dmem_adr_o[4] ,
+    \u_riscv_top.wbd_dmem_adr_o[3] ,
+    \u_riscv_top.wbd_dmem_adr_o[2] ,
+    \u_riscv_top.wbd_dmem_adr_o[1] ,
+    \u_riscv_top.wbd_dmem_adr_o[0] }),
+    .m1_wbd_dat_i({\u_riscv_top.wbd_dmem_dat_o[31] ,
+    \u_riscv_top.wbd_dmem_dat_o[30] ,
+    \u_riscv_top.wbd_dmem_dat_o[29] ,
+    \u_riscv_top.wbd_dmem_dat_o[28] ,
+    \u_riscv_top.wbd_dmem_dat_o[27] ,
+    \u_riscv_top.wbd_dmem_dat_o[26] ,
+    \u_riscv_top.wbd_dmem_dat_o[25] ,
+    \u_riscv_top.wbd_dmem_dat_o[24] ,
+    \u_riscv_top.wbd_dmem_dat_o[23] ,
+    \u_riscv_top.wbd_dmem_dat_o[22] ,
+    \u_riscv_top.wbd_dmem_dat_o[21] ,
+    \u_riscv_top.wbd_dmem_dat_o[20] ,
+    \u_riscv_top.wbd_dmem_dat_o[19] ,
+    \u_riscv_top.wbd_dmem_dat_o[18] ,
+    \u_riscv_top.wbd_dmem_dat_o[17] ,
+    \u_riscv_top.wbd_dmem_dat_o[16] ,
+    \u_riscv_top.wbd_dmem_dat_o[15] ,
+    \u_riscv_top.wbd_dmem_dat_o[14] ,
+    \u_riscv_top.wbd_dmem_dat_o[13] ,
+    \u_riscv_top.wbd_dmem_dat_o[12] ,
+    \u_riscv_top.wbd_dmem_dat_o[11] ,
+    \u_riscv_top.wbd_dmem_dat_o[10] ,
+    \u_riscv_top.wbd_dmem_dat_o[9] ,
+    \u_riscv_top.wbd_dmem_dat_o[8] ,
+    \u_riscv_top.wbd_dmem_dat_o[7] ,
+    \u_riscv_top.wbd_dmem_dat_o[6] ,
+    \u_riscv_top.wbd_dmem_dat_o[5] ,
+    \u_riscv_top.wbd_dmem_dat_o[4] ,
+    \u_riscv_top.wbd_dmem_dat_o[3] ,
+    \u_riscv_top.wbd_dmem_dat_o[2] ,
+    \u_riscv_top.wbd_dmem_dat_o[1] ,
+    \u_riscv_top.wbd_dmem_dat_o[0] }),
+    .m1_wbd_dat_o({\u_riscv_top.wbd_dmem_dat_i[31] ,
+    \u_riscv_top.wbd_dmem_dat_i[30] ,
+    \u_riscv_top.wbd_dmem_dat_i[29] ,
+    \u_riscv_top.wbd_dmem_dat_i[28] ,
+    \u_riscv_top.wbd_dmem_dat_i[27] ,
+    \u_riscv_top.wbd_dmem_dat_i[26] ,
+    \u_riscv_top.wbd_dmem_dat_i[25] ,
+    \u_riscv_top.wbd_dmem_dat_i[24] ,
+    \u_riscv_top.wbd_dmem_dat_i[23] ,
+    \u_riscv_top.wbd_dmem_dat_i[22] ,
+    \u_riscv_top.wbd_dmem_dat_i[21] ,
+    \u_riscv_top.wbd_dmem_dat_i[20] ,
+    \u_riscv_top.wbd_dmem_dat_i[19] ,
+    \u_riscv_top.wbd_dmem_dat_i[18] ,
+    \u_riscv_top.wbd_dmem_dat_i[17] ,
+    \u_riscv_top.wbd_dmem_dat_i[16] ,
+    \u_riscv_top.wbd_dmem_dat_i[15] ,
+    \u_riscv_top.wbd_dmem_dat_i[14] ,
+    \u_riscv_top.wbd_dmem_dat_i[13] ,
+    \u_riscv_top.wbd_dmem_dat_i[12] ,
+    \u_riscv_top.wbd_dmem_dat_i[11] ,
+    \u_riscv_top.wbd_dmem_dat_i[10] ,
+    \u_riscv_top.wbd_dmem_dat_i[9] ,
+    \u_riscv_top.wbd_dmem_dat_i[8] ,
+    \u_riscv_top.wbd_dmem_dat_i[7] ,
+    \u_riscv_top.wbd_dmem_dat_i[6] ,
+    \u_riscv_top.wbd_dmem_dat_i[5] ,
+    \u_riscv_top.wbd_dmem_dat_i[4] ,
+    \u_riscv_top.wbd_dmem_dat_i[3] ,
+    \u_riscv_top.wbd_dmem_dat_i[2] ,
+    \u_riscv_top.wbd_dmem_dat_i[1] ,
+    \u_riscv_top.wbd_dmem_dat_i[0] }),
+    .m1_wbd_sel_i({\u_riscv_top.wbd_dmem_sel_o[3] ,
+    \u_riscv_top.wbd_dmem_sel_o[2] ,
+    \u_riscv_top.wbd_dmem_sel_o[1] ,
+    \u_riscv_top.wbd_dmem_sel_o[0] }),
+    .m2_wbd_adr_i({\u_riscv_top.wb_dcache_adr_o[31] ,
+    \u_riscv_top.wb_dcache_adr_o[30] ,
+    \u_riscv_top.wb_dcache_adr_o[29] ,
+    \u_riscv_top.wb_dcache_adr_o[28] ,
+    \u_riscv_top.wb_dcache_adr_o[27] ,
+    \u_riscv_top.wb_dcache_adr_o[26] ,
+    \u_riscv_top.wb_dcache_adr_o[25] ,
+    \u_riscv_top.wb_dcache_adr_o[24] ,
+    \u_riscv_top.wb_dcache_adr_o[23] ,
+    \u_riscv_top.wb_dcache_adr_o[22] ,
+    \u_riscv_top.wb_dcache_adr_o[21] ,
+    \u_riscv_top.wb_dcache_adr_o[20] ,
+    \u_riscv_top.wb_dcache_adr_o[19] ,
+    \u_riscv_top.wb_dcache_adr_o[18] ,
+    \u_riscv_top.wb_dcache_adr_o[17] ,
+    \u_riscv_top.wb_dcache_adr_o[16] ,
+    \u_riscv_top.wb_dcache_adr_o[15] ,
+    \u_riscv_top.wb_dcache_adr_o[14] ,
+    \u_riscv_top.wb_dcache_adr_o[13] ,
+    \u_riscv_top.wb_dcache_adr_o[12] ,
+    \u_riscv_top.wb_dcache_adr_o[11] ,
+    \u_riscv_top.wb_dcache_adr_o[10] ,
+    \u_riscv_top.wb_dcache_adr_o[9] ,
+    \u_riscv_top.wb_dcache_adr_o[8] ,
+    \u_riscv_top.wb_dcache_adr_o[7] ,
+    \u_riscv_top.wb_dcache_adr_o[6] ,
+    \u_riscv_top.wb_dcache_adr_o[5] ,
+    \u_riscv_top.wb_dcache_adr_o[4] ,
+    \u_riscv_top.wb_dcache_adr_o[3] ,
+    \u_riscv_top.wb_dcache_adr_o[2] ,
+    \u_riscv_top.wb_dcache_adr_o[1] ,
+    \u_riscv_top.wb_dcache_adr_o[0] }),
+    .m2_wbd_bl_i({\u_riscv_top.wb_dcache_bl_o[9] ,
+    \u_riscv_top.wb_dcache_bl_o[8] ,
+    \u_riscv_top.wb_dcache_bl_o[7] ,
+    \u_riscv_top.wb_dcache_bl_o[6] ,
+    \u_riscv_top.wb_dcache_bl_o[5] ,
+    \u_riscv_top.wb_dcache_bl_o[4] ,
+    \u_riscv_top.wb_dcache_bl_o[3] ,
+    \u_riscv_top.wb_dcache_bl_o[2] ,
+    \u_riscv_top.wb_dcache_bl_o[1] ,
+    \u_riscv_top.wb_dcache_bl_o[0] }),
+    .m2_wbd_dat_i({\u_riscv_top.wb_dcache_dat_o[31] ,
+    \u_riscv_top.wb_dcache_dat_o[30] ,
+    \u_riscv_top.wb_dcache_dat_o[29] ,
+    \u_riscv_top.wb_dcache_dat_o[28] ,
+    \u_riscv_top.wb_dcache_dat_o[27] ,
+    \u_riscv_top.wb_dcache_dat_o[26] ,
+    \u_riscv_top.wb_dcache_dat_o[25] ,
+    \u_riscv_top.wb_dcache_dat_o[24] ,
+    \u_riscv_top.wb_dcache_dat_o[23] ,
+    \u_riscv_top.wb_dcache_dat_o[22] ,
+    \u_riscv_top.wb_dcache_dat_o[21] ,
+    \u_riscv_top.wb_dcache_dat_o[20] ,
+    \u_riscv_top.wb_dcache_dat_o[19] ,
+    \u_riscv_top.wb_dcache_dat_o[18] ,
+    \u_riscv_top.wb_dcache_dat_o[17] ,
+    \u_riscv_top.wb_dcache_dat_o[16] ,
+    \u_riscv_top.wb_dcache_dat_o[15] ,
+    \u_riscv_top.wb_dcache_dat_o[14] ,
+    \u_riscv_top.wb_dcache_dat_o[13] ,
+    \u_riscv_top.wb_dcache_dat_o[12] ,
+    \u_riscv_top.wb_dcache_dat_o[11] ,
+    \u_riscv_top.wb_dcache_dat_o[10] ,
+    \u_riscv_top.wb_dcache_dat_o[9] ,
+    \u_riscv_top.wb_dcache_dat_o[8] ,
+    \u_riscv_top.wb_dcache_dat_o[7] ,
+    \u_riscv_top.wb_dcache_dat_o[6] ,
+    \u_riscv_top.wb_dcache_dat_o[5] ,
+    \u_riscv_top.wb_dcache_dat_o[4] ,
+    \u_riscv_top.wb_dcache_dat_o[3] ,
+    \u_riscv_top.wb_dcache_dat_o[2] ,
+    \u_riscv_top.wb_dcache_dat_o[1] ,
+    \u_riscv_top.wb_dcache_dat_o[0] }),
+    .m2_wbd_dat_o({\u_riscv_top.wb_dcache_dat_i[31] ,
+    \u_riscv_top.wb_dcache_dat_i[30] ,
+    \u_riscv_top.wb_dcache_dat_i[29] ,
+    \u_riscv_top.wb_dcache_dat_i[28] ,
+    \u_riscv_top.wb_dcache_dat_i[27] ,
+    \u_riscv_top.wb_dcache_dat_i[26] ,
+    \u_riscv_top.wb_dcache_dat_i[25] ,
+    \u_riscv_top.wb_dcache_dat_i[24] ,
+    \u_riscv_top.wb_dcache_dat_i[23] ,
+    \u_riscv_top.wb_dcache_dat_i[22] ,
+    \u_riscv_top.wb_dcache_dat_i[21] ,
+    \u_riscv_top.wb_dcache_dat_i[20] ,
+    \u_riscv_top.wb_dcache_dat_i[19] ,
+    \u_riscv_top.wb_dcache_dat_i[18] ,
+    \u_riscv_top.wb_dcache_dat_i[17] ,
+    \u_riscv_top.wb_dcache_dat_i[16] ,
+    \u_riscv_top.wb_dcache_dat_i[15] ,
+    \u_riscv_top.wb_dcache_dat_i[14] ,
+    \u_riscv_top.wb_dcache_dat_i[13] ,
+    \u_riscv_top.wb_dcache_dat_i[12] ,
+    \u_riscv_top.wb_dcache_dat_i[11] ,
+    \u_riscv_top.wb_dcache_dat_i[10] ,
+    \u_riscv_top.wb_dcache_dat_i[9] ,
+    \u_riscv_top.wb_dcache_dat_i[8] ,
+    \u_riscv_top.wb_dcache_dat_i[7] ,
+    \u_riscv_top.wb_dcache_dat_i[6] ,
+    \u_riscv_top.wb_dcache_dat_i[5] ,
+    \u_riscv_top.wb_dcache_dat_i[4] ,
+    \u_riscv_top.wb_dcache_dat_i[3] ,
+    \u_riscv_top.wb_dcache_dat_i[2] ,
+    \u_riscv_top.wb_dcache_dat_i[1] ,
+    \u_riscv_top.wb_dcache_dat_i[0] }),
+    .m2_wbd_sel_i({\u_riscv_top.wb_dcache_sel_o[3] ,
+    \u_riscv_top.wb_dcache_sel_o[2] ,
+    \u_riscv_top.wb_dcache_sel_o[1] ,
+    \u_riscv_top.wb_dcache_sel_o[0] }),
+    .m3_wbd_adr_i({\u_riscv_top.wb_icache_adr_o[31] ,
+    \u_riscv_top.wb_icache_adr_o[30] ,
+    \u_riscv_top.wb_icache_adr_o[29] ,
+    \u_riscv_top.wb_icache_adr_o[28] ,
+    \u_riscv_top.wb_icache_adr_o[27] ,
+    \u_riscv_top.wb_icache_adr_o[26] ,
+    \u_riscv_top.wb_icache_adr_o[25] ,
+    \u_riscv_top.wb_icache_adr_o[24] ,
+    \u_riscv_top.wb_icache_adr_o[23] ,
+    \u_riscv_top.wb_icache_adr_o[22] ,
+    \u_riscv_top.wb_icache_adr_o[21] ,
+    \u_riscv_top.wb_icache_adr_o[20] ,
+    \u_riscv_top.wb_icache_adr_o[19] ,
+    \u_riscv_top.wb_icache_adr_o[18] ,
+    \u_riscv_top.wb_icache_adr_o[17] ,
+    \u_riscv_top.wb_icache_adr_o[16] ,
+    \u_riscv_top.wb_icache_adr_o[15] ,
+    \u_riscv_top.wb_icache_adr_o[14] ,
+    \u_riscv_top.wb_icache_adr_o[13] ,
+    \u_riscv_top.wb_icache_adr_o[12] ,
+    \u_riscv_top.wb_icache_adr_o[11] ,
+    \u_riscv_top.wb_icache_adr_o[10] ,
+    \u_riscv_top.wb_icache_adr_o[9] ,
+    \u_riscv_top.wb_icache_adr_o[8] ,
+    \u_riscv_top.wb_icache_adr_o[7] ,
+    \u_riscv_top.wb_icache_adr_o[6] ,
+    \u_riscv_top.wb_icache_adr_o[5] ,
+    \u_riscv_top.wb_icache_adr_o[4] ,
+    \u_riscv_top.wb_icache_adr_o[3] ,
+    \u_riscv_top.wb_icache_adr_o[2] ,
+    \u_riscv_top.wb_icache_adr_o[1] ,
+    \u_riscv_top.wb_icache_adr_o[0] }),
+    .m3_wbd_bl_i({\u_riscv_top.wb_icache_bl_o[9] ,
+    \u_riscv_top.wb_icache_bl_o[8] ,
+    \u_riscv_top.wb_icache_bl_o[7] ,
+    \u_riscv_top.wb_icache_bl_o[6] ,
+    \u_riscv_top.wb_icache_bl_o[5] ,
+    \u_riscv_top.wb_icache_bl_o[4] ,
+    \u_riscv_top.wb_icache_bl_o[3] ,
+    \u_riscv_top.wb_icache_bl_o[2] ,
+    \u_riscv_top.wb_icache_bl_o[1] ,
+    \u_riscv_top.wb_icache_bl_o[0] }),
+    .m3_wbd_dat_o({\u_riscv_top.wb_icache_dat_i[31] ,
+    \u_riscv_top.wb_icache_dat_i[30] ,
+    \u_riscv_top.wb_icache_dat_i[29] ,
+    \u_riscv_top.wb_icache_dat_i[28] ,
+    \u_riscv_top.wb_icache_dat_i[27] ,
+    \u_riscv_top.wb_icache_dat_i[26] ,
+    \u_riscv_top.wb_icache_dat_i[25] ,
+    \u_riscv_top.wb_icache_dat_i[24] ,
+    \u_riscv_top.wb_icache_dat_i[23] ,
+    \u_riscv_top.wb_icache_dat_i[22] ,
+    \u_riscv_top.wb_icache_dat_i[21] ,
+    \u_riscv_top.wb_icache_dat_i[20] ,
+    \u_riscv_top.wb_icache_dat_i[19] ,
+    \u_riscv_top.wb_icache_dat_i[18] ,
+    \u_riscv_top.wb_icache_dat_i[17] ,
+    \u_riscv_top.wb_icache_dat_i[16] ,
+    \u_riscv_top.wb_icache_dat_i[15] ,
+    \u_riscv_top.wb_icache_dat_i[14] ,
+    \u_riscv_top.wb_icache_dat_i[13] ,
+    \u_riscv_top.wb_icache_dat_i[12] ,
+    \u_riscv_top.wb_icache_dat_i[11] ,
+    \u_riscv_top.wb_icache_dat_i[10] ,
+    \u_riscv_top.wb_icache_dat_i[9] ,
+    \u_riscv_top.wb_icache_dat_i[8] ,
+    \u_riscv_top.wb_icache_dat_i[7] ,
+    \u_riscv_top.wb_icache_dat_i[6] ,
+    \u_riscv_top.wb_icache_dat_i[5] ,
+    \u_riscv_top.wb_icache_dat_i[4] ,
+    \u_riscv_top.wb_icache_dat_i[3] ,
+    \u_riscv_top.wb_icache_dat_i[2] ,
+    \u_riscv_top.wb_icache_dat_i[1] ,
+    \u_riscv_top.wb_icache_dat_i[0] }),
+    .m3_wbd_sel_i({\u_riscv_top.wb_icache_sel_o[3] ,
+    \u_riscv_top.wb_icache_sel_o[2] ,
+    \u_riscv_top.wb_icache_sel_o[1] ,
+    \u_riscv_top.wb_icache_sel_o[0] }),
+    .s0_wbd_adr_o({\wbd_spim_adr_o[31] ,
+    \wbd_spim_adr_o[30] ,
+    \wbd_spim_adr_o[29] ,
+    \wbd_spim_adr_o[28] ,
+    \wbd_spim_adr_o[27] ,
+    \wbd_spim_adr_o[26] ,
+    \wbd_spim_adr_o[25] ,
+    \wbd_spim_adr_o[24] ,
+    \wbd_spim_adr_o[23] ,
+    \wbd_spim_adr_o[22] ,
+    \wbd_spim_adr_o[21] ,
+    \wbd_spim_adr_o[20] ,
+    \wbd_spim_adr_o[19] ,
+    \wbd_spim_adr_o[18] ,
+    \wbd_spim_adr_o[17] ,
+    \wbd_spim_adr_o[16] ,
+    \wbd_spim_adr_o[15] ,
+    \wbd_spim_adr_o[14] ,
+    \wbd_spim_adr_o[13] ,
+    \wbd_spim_adr_o[12] ,
+    \wbd_spim_adr_o[11] ,
+    \wbd_spim_adr_o[10] ,
+    \wbd_spim_adr_o[9] ,
+    \wbd_spim_adr_o[8] ,
+    \wbd_spim_adr_o[7] ,
+    \wbd_spim_adr_o[6] ,
+    \wbd_spim_adr_o[5] ,
+    \wbd_spim_adr_o[4] ,
+    \wbd_spim_adr_o[3] ,
+    \wbd_spim_adr_o[2] ,
+    \wbd_spim_adr_o[1] ,
+    \wbd_spim_adr_o[0] }),
+    .s0_wbd_bl_o({\wbd_spim_bl_o[9] ,
+    \wbd_spim_bl_o[8] ,
+    \wbd_spim_bl_o[7] ,
+    \wbd_spim_bl_o[6] ,
+    \wbd_spim_bl_o[5] ,
+    \wbd_spim_bl_o[4] ,
+    \wbd_spim_bl_o[3] ,
+    \wbd_spim_bl_o[2] ,
+    \wbd_spim_bl_o[1] ,
+    \wbd_spim_bl_o[0] }),
+    .s0_wbd_dat_i({\wbd_spim_dat_i[31] ,
+    \wbd_spim_dat_i[30] ,
+    \wbd_spim_dat_i[29] ,
+    \wbd_spim_dat_i[28] ,
+    \wbd_spim_dat_i[27] ,
+    \wbd_spim_dat_i[26] ,
+    \wbd_spim_dat_i[25] ,
+    \wbd_spim_dat_i[24] ,
+    \wbd_spim_dat_i[23] ,
+    \wbd_spim_dat_i[22] ,
+    \wbd_spim_dat_i[21] ,
+    \wbd_spim_dat_i[20] ,
+    \wbd_spim_dat_i[19] ,
+    \wbd_spim_dat_i[18] ,
+    \wbd_spim_dat_i[17] ,
+    \wbd_spim_dat_i[16] ,
+    \wbd_spim_dat_i[15] ,
+    \wbd_spim_dat_i[14] ,
+    \wbd_spim_dat_i[13] ,
+    \wbd_spim_dat_i[12] ,
+    \wbd_spim_dat_i[11] ,
+    \wbd_spim_dat_i[10] ,
+    \wbd_spim_dat_i[9] ,
+    \wbd_spim_dat_i[8] ,
+    \wbd_spim_dat_i[7] ,
+    \wbd_spim_dat_i[6] ,
+    \wbd_spim_dat_i[5] ,
+    \wbd_spim_dat_i[4] ,
+    \wbd_spim_dat_i[3] ,
+    \wbd_spim_dat_i[2] ,
+    \wbd_spim_dat_i[1] ,
+    \wbd_spim_dat_i[0] }),
+    .s0_wbd_dat_o({\wbd_spim_dat_o[31] ,
+    \wbd_spim_dat_o[30] ,
+    \wbd_spim_dat_o[29] ,
+    \wbd_spim_dat_o[28] ,
+    \wbd_spim_dat_o[27] ,
+    \wbd_spim_dat_o[26] ,
+    \wbd_spim_dat_o[25] ,
+    \wbd_spim_dat_o[24] ,
+    \wbd_spim_dat_o[23] ,
+    \wbd_spim_dat_o[22] ,
+    \wbd_spim_dat_o[21] ,
+    \wbd_spim_dat_o[20] ,
+    \wbd_spim_dat_o[19] ,
+    \wbd_spim_dat_o[18] ,
+    \wbd_spim_dat_o[17] ,
+    \wbd_spim_dat_o[16] ,
+    \wbd_spim_dat_o[15] ,
+    \wbd_spim_dat_o[14] ,
+    \wbd_spim_dat_o[13] ,
+    \wbd_spim_dat_o[12] ,
+    \wbd_spim_dat_o[11] ,
+    \wbd_spim_dat_o[10] ,
+    \wbd_spim_dat_o[9] ,
+    \wbd_spim_dat_o[8] ,
+    \wbd_spim_dat_o[7] ,
+    \wbd_spim_dat_o[6] ,
+    \wbd_spim_dat_o[5] ,
+    \wbd_spim_dat_o[4] ,
+    \wbd_spim_dat_o[3] ,
+    \wbd_spim_dat_o[2] ,
+    \wbd_spim_dat_o[1] ,
+    \wbd_spim_dat_o[0] }),
+    .s0_wbd_sel_o({\wbd_spim_sel_o[3] ,
+    \wbd_spim_sel_o[2] ,
+    \wbd_spim_sel_o[1] ,
+    \wbd_spim_sel_o[0] }),
+    .s1_wbd_adr_o({\wbd_uart_adr_o[7] ,
+    \wbd_uart_adr_o[6] ,
+    \wbd_uart_adr_o[5] ,
+    \wbd_uart_adr_o[4] ,
+    \wbd_uart_adr_o[3] ,
+    \wbd_uart_adr_o[2] ,
+    \wbd_uart_adr_o[1] ,
+    \wbd_uart_adr_o[0] }),
+    .s1_wbd_dat_i({\wbd_uart_dat_i[31] ,
+    \wbd_uart_dat_i[30] ,
+    \wbd_uart_dat_i[29] ,
+    \wbd_uart_dat_i[28] ,
+    \wbd_uart_dat_i[27] ,
+    \wbd_uart_dat_i[26] ,
+    \wbd_uart_dat_i[25] ,
+    \wbd_uart_dat_i[24] ,
+    \wbd_uart_dat_i[23] ,
+    \wbd_uart_dat_i[22] ,
+    \wbd_uart_dat_i[21] ,
+    \wbd_uart_dat_i[20] ,
+    \wbd_uart_dat_i[19] ,
+    \wbd_uart_dat_i[18] ,
+    \wbd_uart_dat_i[17] ,
+    \wbd_uart_dat_i[16] ,
+    \wbd_uart_dat_i[15] ,
+    \wbd_uart_dat_i[14] ,
+    \wbd_uart_dat_i[13] ,
+    \wbd_uart_dat_i[12] ,
+    \wbd_uart_dat_i[11] ,
+    \wbd_uart_dat_i[10] ,
+    \wbd_uart_dat_i[9] ,
+    \wbd_uart_dat_i[8] ,
+    \wbd_uart_dat_i[7] ,
+    \wbd_uart_dat_i[6] ,
+    \wbd_uart_dat_i[5] ,
+    \wbd_uart_dat_i[4] ,
+    \wbd_uart_dat_i[3] ,
+    \wbd_uart_dat_i[2] ,
+    \wbd_uart_dat_i[1] ,
+    \wbd_uart_dat_i[0] }),
+    .s1_wbd_dat_o({\wbd_uart_dat_o[31] ,
+    \wbd_uart_dat_o[30] ,
+    \wbd_uart_dat_o[29] ,
+    \wbd_uart_dat_o[28] ,
+    \wbd_uart_dat_o[27] ,
+    \wbd_uart_dat_o[26] ,
+    \wbd_uart_dat_o[25] ,
+    \wbd_uart_dat_o[24] ,
+    \wbd_uart_dat_o[23] ,
+    \wbd_uart_dat_o[22] ,
+    \wbd_uart_dat_o[21] ,
+    \wbd_uart_dat_o[20] ,
+    \wbd_uart_dat_o[19] ,
+    \wbd_uart_dat_o[18] ,
+    \wbd_uart_dat_o[17] ,
+    \wbd_uart_dat_o[16] ,
+    \wbd_uart_dat_o[15] ,
+    \wbd_uart_dat_o[14] ,
+    \wbd_uart_dat_o[13] ,
+    \wbd_uart_dat_o[12] ,
+    \wbd_uart_dat_o[11] ,
+    \wbd_uart_dat_o[10] ,
+    \wbd_uart_dat_o[9] ,
+    \wbd_uart_dat_o[8] ,
+    \wbd_uart_dat_o[7] ,
+    \wbd_uart_dat_o[6] ,
+    \wbd_uart_dat_o[5] ,
+    \wbd_uart_dat_o[4] ,
+    \wbd_uart_dat_o[3] ,
+    \wbd_uart_dat_o[2] ,
+    \wbd_uart_dat_o[1] ,
+    \wbd_uart_dat_o[0] }),
+    .s1_wbd_sel_o({\wbd_uart_sel_o[3] ,
+    \wbd_uart_sel_o[2] ,
+    \wbd_uart_sel_o[1] ,
+    \wbd_uart_sel_o[0] }),
+    .s2_wbd_adr_o({\wbd_glbl_adr_o[7] ,
+    \wbd_glbl_adr_o[6] ,
+    \wbd_glbl_adr_o[5] ,
+    \wbd_glbl_adr_o[4] ,
+    \wbd_glbl_adr_o[3] ,
+    \wbd_glbl_adr_o[2] ,
+    \wbd_glbl_adr_o[1] ,
+    \wbd_glbl_adr_o[0] }),
+    .s2_wbd_dat_i({\wbd_glbl_dat_i[31] ,
+    \wbd_glbl_dat_i[30] ,
+    \wbd_glbl_dat_i[29] ,
+    \wbd_glbl_dat_i[28] ,
+    \wbd_glbl_dat_i[27] ,
+    \wbd_glbl_dat_i[26] ,
+    \wbd_glbl_dat_i[25] ,
+    \wbd_glbl_dat_i[24] ,
+    \wbd_glbl_dat_i[23] ,
+    \wbd_glbl_dat_i[22] ,
+    \wbd_glbl_dat_i[21] ,
+    \wbd_glbl_dat_i[20] ,
+    \wbd_glbl_dat_i[19] ,
+    \wbd_glbl_dat_i[18] ,
+    \wbd_glbl_dat_i[17] ,
+    \wbd_glbl_dat_i[16] ,
+    \wbd_glbl_dat_i[15] ,
+    \wbd_glbl_dat_i[14] ,
+    \wbd_glbl_dat_i[13] ,
+    \wbd_glbl_dat_i[12] ,
+    \wbd_glbl_dat_i[11] ,
+    \wbd_glbl_dat_i[10] ,
+    \wbd_glbl_dat_i[9] ,
+    \wbd_glbl_dat_i[8] ,
+    \wbd_glbl_dat_i[7] ,
+    \wbd_glbl_dat_i[6] ,
+    \wbd_glbl_dat_i[5] ,
+    \wbd_glbl_dat_i[4] ,
+    \wbd_glbl_dat_i[3] ,
+    \wbd_glbl_dat_i[2] ,
+    \wbd_glbl_dat_i[1] ,
+    \wbd_glbl_dat_i[0] }),
+    .s2_wbd_dat_o({\wbd_glbl_dat_o[31] ,
+    \wbd_glbl_dat_o[30] ,
+    \wbd_glbl_dat_o[29] ,
+    \wbd_glbl_dat_o[28] ,
+    \wbd_glbl_dat_o[27] ,
+    \wbd_glbl_dat_o[26] ,
+    \wbd_glbl_dat_o[25] ,
+    \wbd_glbl_dat_o[24] ,
+    \wbd_glbl_dat_o[23] ,
+    \wbd_glbl_dat_o[22] ,
+    \wbd_glbl_dat_o[21] ,
+    \wbd_glbl_dat_o[20] ,
+    \wbd_glbl_dat_o[19] ,
+    \wbd_glbl_dat_o[18] ,
+    \wbd_glbl_dat_o[17] ,
+    \wbd_glbl_dat_o[16] ,
+    \wbd_glbl_dat_o[15] ,
+    \wbd_glbl_dat_o[14] ,
+    \wbd_glbl_dat_o[13] ,
+    \wbd_glbl_dat_o[12] ,
+    \wbd_glbl_dat_o[11] ,
+    \wbd_glbl_dat_o[10] ,
+    \wbd_glbl_dat_o[9] ,
+    \wbd_glbl_dat_o[8] ,
+    \wbd_glbl_dat_o[7] ,
+    \wbd_glbl_dat_o[6] ,
+    \wbd_glbl_dat_o[5] ,
+    \wbd_glbl_dat_o[4] ,
+    \wbd_glbl_dat_o[3] ,
+    \wbd_glbl_dat_o[2] ,
+    \wbd_glbl_dat_o[1] ,
+    \wbd_glbl_dat_o[0] }),
+    .s2_wbd_sel_o({\wbd_glbl_sel_o[3] ,
+    \wbd_glbl_sel_o[2] ,
+    \wbd_glbl_sel_o[1] ,
+    \wbd_glbl_sel_o[0] }));
+ pinmux u_pinmux (.cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+    .h_reset_n(\u_riscv_top.pwrup_rst_n ),
+    .i2cm_clk_i(i2cm_clk_i),
+    .i2cm_clk_o(i2cm_clk_o),
+    .i2cm_clk_oen(i2cm_clk_oen),
+    .i2cm_data_i(i2cm_data_i),
+    .i2cm_data_o(i2cm_data_o),
+    .i2cm_data_oen(i2cm_data_oen),
+    .i2cm_intr(i2cm_intr_o),
+    .i2cm_rst_n(i2c_rst_n),
+    .mclk(wbd_clk_pinmux_skew),
+    .pulse1m_mclk(pulse1m_mclk),
+    .qspim_rst_n(qspim_rst_n),
+    .reg_ack(wbd_glbl_ack_i),
+    .reg_cs(wbd_glbl_stb_o),
+    .reg_wr(wbd_glbl_we_o),
+    .sflash_sck(sflash_sck),
+    .soft_irq(soft_irq),
+    .spim_miso(sspim_so),
+    .spim_mosi(sspim_si),
+    .spim_sck(sspim_sck),
+    .spim_ss(sspim_ssn),
+    .sspim_rst_n(sspim_rst_n),
+    .uart_rst_n(uart_rst_n),
+    .uart_rxd(uart_rxd),
+    .uart_txd(uart_txd),
+    .uartm_rxd(uartm_rxd),
+    .uartm_txd(uartm_txd),
+    .usb_dn_i(usb_dn_i),
+    .usb_dn_o(usb_dn_o),
+    .usb_dp_i(usb_dp_i),
+    .usb_dp_o(usb_dp_o),
+    .usb_intr(usb_intr_o),
+    .usb_oen(usb_oen),
+    .usb_rst_n(usb_rst_n),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_pinmux_rp),
+    .wbd_clk_pinmux(wbd_clk_pinmux_skew),
+    .cfg_cska_pinmux({\cfg_cska_pinmux_rp[3] ,
+    \cfg_cska_pinmux_rp[2] ,
+    \cfg_cska_pinmux_rp[1] ,
+    \cfg_cska_pinmux_rp[0] }),
+    .cfg_riscv_debug_sel({\u_riscv_top.core_debug_sel[1] ,
+    \u_riscv_top.core_debug_sel[0] }),
+    .cpu_core_rst_n({\u_riscv_top.cpu_core_rst_n[1] ,
+    \u_riscv_top.cpu_core_rst_n[0] }),
+    .digital_io_in({io_in[37],
+    io_in[36],
+    io_in[35],
+    io_in[34],
+    io_in[33],
+    io_in[32],
+    io_in[31],
+    io_in[30],
+    io_in[29],
+    io_in[28],
+    io_in[27],
+    io_in[26],
+    io_in[25],
+    io_in[24],
+    io_in[23],
+    io_in[22],
+    io_in[21],
+    io_in[20],
+    io_in[19],
+    io_in[18],
+    io_in[17],
+    io_in[16],
+    io_in[15],
+    io_in[14],
+    io_in[13],
+    io_in[12],
+    io_in[11],
+    io_in[10],
+    io_in[9],
+    io_in[8],
+    io_in[7],
+    io_in[6],
+    io_in[5],
+    io_in[4],
+    io_in[3],
+    io_in[2],
+    io_in[1],
+    io_in[0]}),
+    .digital_io_oen({io_oeb[37],
+    io_oeb[36],
+    io_oeb[35],
+    io_oeb[34],
+    io_oeb[33],
+    io_oeb[32],
+    io_oeb[31],
+    io_oeb[30],
+    io_oeb[29],
+    io_oeb[28],
+    io_oeb[27],
+    io_oeb[26],
+    io_oeb[25],
+    io_oeb[24],
+    io_oeb[23],
+    io_oeb[22],
+    io_oeb[21],
+    io_oeb[20],
+    io_oeb[19],
+    io_oeb[18],
+    io_oeb[17],
+    io_oeb[16],
+    io_oeb[15],
+    io_oeb[14],
+    io_oeb[13],
+    io_oeb[12],
+    io_oeb[11],
+    io_oeb[10],
+    io_oeb[9],
+    io_oeb[8],
+    io_oeb[7],
+    io_oeb[6],
+    io_oeb[5],
+    io_oeb[4],
+    io_oeb[3],
+    io_oeb[2],
+    io_oeb[1],
+    io_oeb[0]}),
+    .digital_io_out({io_out[37],
+    io_out[36],
+    io_out[35],
+    io_out[34],
+    io_out[33],
+    io_out[32],
+    io_out[31],
+    io_out[30],
+    io_out[29],
+    io_out[28],
+    io_out[27],
+    io_out[26],
+    io_out[25],
+    io_out[24],
+    io_out[23],
+    io_out[22],
+    io_out[21],
+    io_out[20],
+    io_out[19],
+    io_out[18],
+    io_out[17],
+    io_out[16],
+    io_out[15],
+    io_out[14],
+    io_out[13],
+    io_out[12],
+    io_out[11],
+    io_out[10],
+    io_out[9],
+    io_out[8],
+    io_out[7],
+    io_out[6],
+    io_out[5],
+    io_out[4],
+    io_out[3],
+    io_out[2],
+    io_out[1],
+    io_out[0]}),
+    .irq_lines({\irq_lines[15] ,
+    \irq_lines[14] ,
+    \irq_lines[13] ,
+    \irq_lines[12] ,
+    \irq_lines[11] ,
+    \irq_lines[10] ,
+    \irq_lines[9] ,
+    \irq_lines[8] ,
+    \irq_lines[7] ,
+    \irq_lines[6] ,
+    \irq_lines[5] ,
+    \irq_lines[4] ,
+    \irq_lines[3] ,
+    \irq_lines[2] ,
+    \irq_lines[1] ,
+    \irq_lines[0] }),
+    .pinmux_debug({la_data_out[127],
+    la_data_out[126],
+    la_data_out[125],
+    la_data_out[124],
+    la_data_out[123],
+    la_data_out[122],
+    la_data_out[121],
+    la_data_out[120],
+    la_data_out[119],
+    la_data_out[118],
+    la_data_out[117],
+    la_data_out[116],
+    la_data_out[115],
+    la_data_out[114],
+    la_data_out[113],
+    la_data_out[112],
+    la_data_out[111],
+    la_data_out[110],
+    la_data_out[109],
+    la_data_out[108],
+    la_data_out[107],
+    la_data_out[106],
+    la_data_out[105],
+    la_data_out[104],
+    la_data_out[103],
+    la_data_out[102],
+    la_data_out[101],
+    la_data_out[100],
+    la_data_out[99],
+    la_data_out[98],
+    la_data_out[97],
+    la_data_out[96]}),
+    .reg_addr({\wbd_glbl_adr_o[7] ,
+    \wbd_glbl_adr_o[6] ,
+    \wbd_glbl_adr_o[5] ,
+    \wbd_glbl_adr_o[4] ,
+    \wbd_glbl_adr_o[3] ,
+    \wbd_glbl_adr_o[2] ,
+    \wbd_glbl_adr_o[1] ,
+    \wbd_glbl_adr_o[0] }),
+    .reg_be({\wbd_glbl_sel_o[3] ,
+    \wbd_glbl_sel_o[2] ,
+    \wbd_glbl_sel_o[1] ,
+    \wbd_glbl_sel_o[0] }),
+    .reg_rdata({\wbd_glbl_dat_i[31] ,
+    \wbd_glbl_dat_i[30] ,
+    \wbd_glbl_dat_i[29] ,
+    \wbd_glbl_dat_i[28] ,
+    \wbd_glbl_dat_i[27] ,
+    \wbd_glbl_dat_i[26] ,
+    \wbd_glbl_dat_i[25] ,
+    \wbd_glbl_dat_i[24] ,
+    \wbd_glbl_dat_i[23] ,
+    \wbd_glbl_dat_i[22] ,
+    \wbd_glbl_dat_i[21] ,
+    \wbd_glbl_dat_i[20] ,
+    \wbd_glbl_dat_i[19] ,
+    \wbd_glbl_dat_i[18] ,
+    \wbd_glbl_dat_i[17] ,
+    \wbd_glbl_dat_i[16] ,
+    \wbd_glbl_dat_i[15] ,
+    \wbd_glbl_dat_i[14] ,
+    \wbd_glbl_dat_i[13] ,
+    \wbd_glbl_dat_i[12] ,
+    \wbd_glbl_dat_i[11] ,
+    \wbd_glbl_dat_i[10] ,
+    \wbd_glbl_dat_i[9] ,
+    \wbd_glbl_dat_i[8] ,
+    \wbd_glbl_dat_i[7] ,
+    \wbd_glbl_dat_i[6] ,
+    \wbd_glbl_dat_i[5] ,
+    \wbd_glbl_dat_i[4] ,
+    \wbd_glbl_dat_i[3] ,
+    \wbd_glbl_dat_i[2] ,
+    \wbd_glbl_dat_i[1] ,
+    \wbd_glbl_dat_i[0] }),
+    .reg_wdata({\wbd_glbl_dat_o[31] ,
+    \wbd_glbl_dat_o[30] ,
+    \wbd_glbl_dat_o[29] ,
+    \wbd_glbl_dat_o[28] ,
+    \wbd_glbl_dat_o[27] ,
+    \wbd_glbl_dat_o[26] ,
+    \wbd_glbl_dat_o[25] ,
+    \wbd_glbl_dat_o[24] ,
+    \wbd_glbl_dat_o[23] ,
+    \wbd_glbl_dat_o[22] ,
+    \wbd_glbl_dat_o[21] ,
+    \wbd_glbl_dat_o[20] ,
+    \wbd_glbl_dat_o[19] ,
+    \wbd_glbl_dat_o[18] ,
+    \wbd_glbl_dat_o[17] ,
+    \wbd_glbl_dat_o[16] ,
+    \wbd_glbl_dat_o[15] ,
+    \wbd_glbl_dat_o[14] ,
+    \wbd_glbl_dat_o[13] ,
+    \wbd_glbl_dat_o[12] ,
+    \wbd_glbl_dat_o[11] ,
+    \wbd_glbl_dat_o[10] ,
+    \wbd_glbl_dat_o[9] ,
+    \wbd_glbl_dat_o[8] ,
+    \wbd_glbl_dat_o[7] ,
+    \wbd_glbl_dat_o[6] ,
+    \wbd_glbl_dat_o[5] ,
+    \wbd_glbl_dat_o[4] ,
+    \wbd_glbl_dat_o[3] ,
+    \wbd_glbl_dat_o[2] ,
+    \wbd_glbl_dat_o[1] ,
+    \wbd_glbl_dat_o[0] }),
+    .sflash_di({\sflash_di[3] ,
+    \sflash_di[2] ,
+    \sflash_di[1] ,
+    \sflash_di[0] }),
+    .sflash_do({\sflash_do[3] ,
+    \sflash_do[2] ,
+    \sflash_do[1] ,
+    \sflash_do[0] }),
+    .sflash_oen({\sflash_oen[3] ,
+    \sflash_oen[2] ,
+    \sflash_oen[1] ,
+    \sflash_oen[0] }),
+    .sflash_ss({\spi_csn[3] ,
+    \spi_csn[2] ,
+    \spi_csn[1] ,
+    \spi_csn[0] }),
+    .user_irq({user_irq[2],
+    user_irq[1],
+    user_irq[0]}));
+ qspim_top u_qspi_master (.mclk(wbd_clk_spi),
+    .rst_n(qspim_rst_n),
+    .spi_clk(sflash_sck),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_ack_o(wbd_spim_ack_i),
+    .wbd_bry_i(wbd_spim_bry_o),
+    .wbd_clk_int(wbd_clk_qspi_rp),
+    .wbd_clk_spi(wbd_clk_spi),
+    .wbd_err_o(wbd_spim_err_i),
+    .wbd_lack_o(wbd_spim_lack_i),
+    .wbd_stb_i(wbd_spim_stb_o),
+    .wbd_we_i(wbd_spim_we_o),
+    .cfg_cska_sp_co({\cfg_cska_qspi_co_rp[3] ,
+    \cfg_cska_qspi_co_rp[2] ,
+    \cfg_cska_qspi_co_rp[1] ,
+    \cfg_cska_qspi_co_rp[0] }),
+    .cfg_cska_spi({\cfg_cska_qspi_rp[3] ,
+    \cfg_cska_qspi_rp[2] ,
+    \cfg_cska_qspi_rp[1] ,
+    \cfg_cska_qspi_rp[0] }),
+    .spi_csn({\spi_csn[3] ,
+    \spi_csn[2] ,
+    \spi_csn[1] ,
+    \spi_csn[0] }),
+    .spi_debug({la_data_out[95],
+    la_data_out[94],
+    la_data_out[93],
+    la_data_out[92],
+    la_data_out[91],
+    la_data_out[90],
+    la_data_out[89],
+    la_data_out[88],
+    la_data_out[87],
+    la_data_out[86],
+    la_data_out[85],
+    la_data_out[84],
+    la_data_out[83],
+    la_data_out[82],
+    la_data_out[81],
+    la_data_out[80],
+    la_data_out[79],
+    la_data_out[78],
+    la_data_out[77],
+    la_data_out[76],
+    la_data_out[75],
+    la_data_out[74],
+    la_data_out[73],
+    la_data_out[72],
+    la_data_out[71],
+    la_data_out[70],
+    la_data_out[69],
+    la_data_out[68],
+    la_data_out[67],
+    la_data_out[66],
+    la_data_out[65],
+    la_data_out[64]}),
+    .spi_oen({\sflash_oen[3] ,
+    \sflash_oen[2] ,
+    \sflash_oen[1] ,
+    \sflash_oen[0] }),
+    .spi_sdi({\sflash_di[3] ,
+    \sflash_di[2] ,
+    \sflash_di[1] ,
+    \sflash_di[0] }),
+    .spi_sdo({\sflash_do[3] ,
+    \sflash_do[2] ,
+    \sflash_do[1] ,
+    \sflash_do[0] }),
+    .wbd_adr_i({\wbd_spim_adr_o[31] ,
+    \wbd_spim_adr_o[30] ,
+    \wbd_spim_adr_o[29] ,
+    \wbd_spim_adr_o[28] ,
+    \wbd_spim_adr_o[27] ,
+    \wbd_spim_adr_o[26] ,
+    \wbd_spim_adr_o[25] ,
+    \wbd_spim_adr_o[24] ,
+    \wbd_spim_adr_o[23] ,
+    \wbd_spim_adr_o[22] ,
+    \wbd_spim_adr_o[21] ,
+    \wbd_spim_adr_o[20] ,
+    \wbd_spim_adr_o[19] ,
+    \wbd_spim_adr_o[18] ,
+    \wbd_spim_adr_o[17] ,
+    \wbd_spim_adr_o[16] ,
+    \wbd_spim_adr_o[15] ,
+    \wbd_spim_adr_o[14] ,
+    \wbd_spim_adr_o[13] ,
+    \wbd_spim_adr_o[12] ,
+    \wbd_spim_adr_o[11] ,
+    \wbd_spim_adr_o[10] ,
+    \wbd_spim_adr_o[9] ,
+    \wbd_spim_adr_o[8] ,
+    \wbd_spim_adr_o[7] ,
+    \wbd_spim_adr_o[6] ,
+    \wbd_spim_adr_o[5] ,
+    \wbd_spim_adr_o[4] ,
+    \wbd_spim_adr_o[3] ,
+    \wbd_spim_adr_o[2] ,
+    \wbd_spim_adr_o[1] ,
+    \wbd_spim_adr_o[0] }),
+    .wbd_bl_i({\wbd_spim_bl_o[9] ,
+    \wbd_spim_bl_o[8] ,
+    \wbd_spim_bl_o[7] ,
+    \wbd_spim_bl_o[6] ,
+    \wbd_spim_bl_o[5] ,
+    \wbd_spim_bl_o[4] ,
+    \wbd_spim_bl_o[3] ,
+    \wbd_spim_bl_o[2] ,
+    \wbd_spim_bl_o[1] ,
+    \wbd_spim_bl_o[0] }),
+    .wbd_dat_i({\wbd_spim_dat_o[31] ,
+    \wbd_spim_dat_o[30] ,
+    \wbd_spim_dat_o[29] ,
+    \wbd_spim_dat_o[28] ,
+    \wbd_spim_dat_o[27] ,
+    \wbd_spim_dat_o[26] ,
+    \wbd_spim_dat_o[25] ,
+    \wbd_spim_dat_o[24] ,
+    \wbd_spim_dat_o[23] ,
+    \wbd_spim_dat_o[22] ,
+    \wbd_spim_dat_o[21] ,
+    \wbd_spim_dat_o[20] ,
+    \wbd_spim_dat_o[19] ,
+    \wbd_spim_dat_o[18] ,
+    \wbd_spim_dat_o[17] ,
+    \wbd_spim_dat_o[16] ,
+    \wbd_spim_dat_o[15] ,
+    \wbd_spim_dat_o[14] ,
+    \wbd_spim_dat_o[13] ,
+    \wbd_spim_dat_o[12] ,
+    \wbd_spim_dat_o[11] ,
+    \wbd_spim_dat_o[10] ,
+    \wbd_spim_dat_o[9] ,
+    \wbd_spim_dat_o[8] ,
+    \wbd_spim_dat_o[7] ,
+    \wbd_spim_dat_o[6] ,
+    \wbd_spim_dat_o[5] ,
+    \wbd_spim_dat_o[4] ,
+    \wbd_spim_dat_o[3] ,
+    \wbd_spim_dat_o[2] ,
+    \wbd_spim_dat_o[1] ,
+    \wbd_spim_dat_o[0] }),
+    .wbd_dat_o({\wbd_spim_dat_i[31] ,
+    \wbd_spim_dat_i[30] ,
+    \wbd_spim_dat_i[29] ,
+    \wbd_spim_dat_i[28] ,
+    \wbd_spim_dat_i[27] ,
+    \wbd_spim_dat_i[26] ,
+    \wbd_spim_dat_i[25] ,
+    \wbd_spim_dat_i[24] ,
+    \wbd_spim_dat_i[23] ,
+    \wbd_spim_dat_i[22] ,
+    \wbd_spim_dat_i[21] ,
+    \wbd_spim_dat_i[20] ,
+    \wbd_spim_dat_i[19] ,
+    \wbd_spim_dat_i[18] ,
+    \wbd_spim_dat_i[17] ,
+    \wbd_spim_dat_i[16] ,
+    \wbd_spim_dat_i[15] ,
+    \wbd_spim_dat_i[14] ,
+    \wbd_spim_dat_i[13] ,
+    \wbd_spim_dat_i[12] ,
+    \wbd_spim_dat_i[11] ,
+    \wbd_spim_dat_i[10] ,
+    \wbd_spim_dat_i[9] ,
+    \wbd_spim_dat_i[8] ,
+    \wbd_spim_dat_i[7] ,
+    \wbd_spim_dat_i[6] ,
+    \wbd_spim_dat_i[5] ,
+    \wbd_spim_dat_i[4] ,
+    \wbd_spim_dat_i[3] ,
+    \wbd_spim_dat_i[2] ,
+    \wbd_spim_dat_i[1] ,
+    \wbd_spim_dat_i[0] }),
+    .wbd_sel_i({\wbd_spim_sel_o[3] ,
+    \wbd_spim_sel_o[2] ,
+    \wbd_spim_sel_o[1] ,
+    \wbd_spim_sel_o[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_0  (.clk(\u_riscv_top.core_clk ),
+    .core2dmem_cmd_o(\u_riscv_top.core0_dmem_cmd ),
+    .core2dmem_req_o(\u_riscv_top.core0_dmem_req ),
+    .core2imem_cmd_o(\u_riscv_top.core0_imem_cmd ),
+    .core2imem_req_o(\u_riscv_top.core0_imem_req ),
+    .core_irq_mtimer_i(\u_riscv_top.timer_irq ),
+    .core_irq_soft_i(\u_riscv_top.soft_irq ),
+    .cpu_rst_n(\u_riscv_top.cpu_core_rst_n_sync[0] ),
+    .dmem2core_req_ack_i(\u_riscv_top.core0_dmem_req_ack ),
+    .imem2core_req_ack_i(\u_riscv_top.core0_imem_req_ack ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n_sync ),
+    .rst_n(\u_riscv_top.rst_n_sync ),
+    .test_mode(\u_riscv_top.test_mode ),
+    .test_rst_n(\u_riscv_top.test_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .core2dmem_addr_o({\u_riscv_top.core0_dmem_addr[31] ,
+    \u_riscv_top.core0_dmem_addr[30] ,
+    \u_riscv_top.core0_dmem_addr[29] ,
+    \u_riscv_top.core0_dmem_addr[28] ,
+    \u_riscv_top.core0_dmem_addr[27] ,
+    \u_riscv_top.core0_dmem_addr[26] ,
+    \u_riscv_top.core0_dmem_addr[25] ,
+    \u_riscv_top.core0_dmem_addr[24] ,
+    \u_riscv_top.core0_dmem_addr[23] ,
+    \u_riscv_top.core0_dmem_addr[22] ,
+    \u_riscv_top.core0_dmem_addr[21] ,
+    \u_riscv_top.core0_dmem_addr[20] ,
+    \u_riscv_top.core0_dmem_addr[19] ,
+    \u_riscv_top.core0_dmem_addr[18] ,
+    \u_riscv_top.core0_dmem_addr[17] ,
+    \u_riscv_top.core0_dmem_addr[16] ,
+    \u_riscv_top.core0_dmem_addr[15] ,
+    \u_riscv_top.core0_dmem_addr[14] ,
+    \u_riscv_top.core0_dmem_addr[13] ,
+    \u_riscv_top.core0_dmem_addr[12] ,
+    \u_riscv_top.core0_dmem_addr[11] ,
+    \u_riscv_top.core0_dmem_addr[10] ,
+    \u_riscv_top.core0_dmem_addr[9] ,
+    \u_riscv_top.core0_dmem_addr[8] ,
+    \u_riscv_top.core0_dmem_addr[7] ,
+    \u_riscv_top.core0_dmem_addr[6] ,
+    \u_riscv_top.core0_dmem_addr[5] ,
+    \u_riscv_top.core0_dmem_addr[4] ,
+    \u_riscv_top.core0_dmem_addr[3] ,
+    \u_riscv_top.core0_dmem_addr[2] ,
+    \u_riscv_top.core0_dmem_addr[1] ,
+    \u_riscv_top.core0_dmem_addr[0] }),
+    .core2dmem_wdata_o({\u_riscv_top.core0_dmem_wdata[31] ,
+    \u_riscv_top.core0_dmem_wdata[30] ,
+    \u_riscv_top.core0_dmem_wdata[29] ,
+    \u_riscv_top.core0_dmem_wdata[28] ,
+    \u_riscv_top.core0_dmem_wdata[27] ,
+    \u_riscv_top.core0_dmem_wdata[26] ,
+    \u_riscv_top.core0_dmem_wdata[25] ,
+    \u_riscv_top.core0_dmem_wdata[24] ,
+    \u_riscv_top.core0_dmem_wdata[23] ,
+    \u_riscv_top.core0_dmem_wdata[22] ,
+    \u_riscv_top.core0_dmem_wdata[21] ,
+    \u_riscv_top.core0_dmem_wdata[20] ,
+    \u_riscv_top.core0_dmem_wdata[19] ,
+    \u_riscv_top.core0_dmem_wdata[18] ,
+    \u_riscv_top.core0_dmem_wdata[17] ,
+    \u_riscv_top.core0_dmem_wdata[16] ,
+    \u_riscv_top.core0_dmem_wdata[15] ,
+    \u_riscv_top.core0_dmem_wdata[14] ,
+    \u_riscv_top.core0_dmem_wdata[13] ,
+    \u_riscv_top.core0_dmem_wdata[12] ,
+    \u_riscv_top.core0_dmem_wdata[11] ,
+    \u_riscv_top.core0_dmem_wdata[10] ,
+    \u_riscv_top.core0_dmem_wdata[9] ,
+    \u_riscv_top.core0_dmem_wdata[8] ,
+    \u_riscv_top.core0_dmem_wdata[7] ,
+    \u_riscv_top.core0_dmem_wdata[6] ,
+    \u_riscv_top.core0_dmem_wdata[5] ,
+    \u_riscv_top.core0_dmem_wdata[4] ,
+    \u_riscv_top.core0_dmem_wdata[3] ,
+    \u_riscv_top.core0_dmem_wdata[2] ,
+    \u_riscv_top.core0_dmem_wdata[1] ,
+    \u_riscv_top.core0_dmem_wdata[0] }),
+    .core2dmem_width_o({\u_riscv_top.core0_dmem_width[1] ,
+    \u_riscv_top.core0_dmem_width[0] }),
+    .core2imem_addr_o({\u_riscv_top.core0_imem_addr[31] ,
+    \u_riscv_top.core0_imem_addr[30] ,
+    \u_riscv_top.core0_imem_addr[29] ,
+    \u_riscv_top.core0_imem_addr[28] ,
+    \u_riscv_top.core0_imem_addr[27] ,
+    \u_riscv_top.core0_imem_addr[26] ,
+    \u_riscv_top.core0_imem_addr[25] ,
+    \u_riscv_top.core0_imem_addr[24] ,
+    \u_riscv_top.core0_imem_addr[23] ,
+    \u_riscv_top.core0_imem_addr[22] ,
+    \u_riscv_top.core0_imem_addr[21] ,
+    \u_riscv_top.core0_imem_addr[20] ,
+    \u_riscv_top.core0_imem_addr[19] ,
+    \u_riscv_top.core0_imem_addr[18] ,
+    \u_riscv_top.core0_imem_addr[17] ,
+    \u_riscv_top.core0_imem_addr[16] ,
+    \u_riscv_top.core0_imem_addr[15] ,
+    \u_riscv_top.core0_imem_addr[14] ,
+    \u_riscv_top.core0_imem_addr[13] ,
+    \u_riscv_top.core0_imem_addr[12] ,
+    \u_riscv_top.core0_imem_addr[11] ,
+    \u_riscv_top.core0_imem_addr[10] ,
+    \u_riscv_top.core0_imem_addr[9] ,
+    \u_riscv_top.core0_imem_addr[8] ,
+    \u_riscv_top.core0_imem_addr[7] ,
+    \u_riscv_top.core0_imem_addr[6] ,
+    \u_riscv_top.core0_imem_addr[5] ,
+    \u_riscv_top.core0_imem_addr[4] ,
+    \u_riscv_top.core0_imem_addr[3] ,
+    \u_riscv_top.core0_imem_addr[2] ,
+    \u_riscv_top.core0_imem_addr[1] ,
+    \u_riscv_top.core0_imem_addr[0] }),
+    .core2imem_bl_o({\u_riscv_top.core0_imem_bl[2] ,
+    \u_riscv_top.core0_imem_bl[1] ,
+    \u_riscv_top.core0_imem_bl[0] }),
+    .core_debug({\u_riscv_top.core0_debug[48] ,
+    \u_riscv_top.core0_debug[47] ,
+    \u_riscv_top.core0_debug[46] ,
+    \u_riscv_top.core0_debug[45] ,
+    \u_riscv_top.core0_debug[44] ,
+    \u_riscv_top.core0_debug[43] ,
+    \u_riscv_top.core0_debug[42] ,
+    \u_riscv_top.core0_debug[41] ,
+    \u_riscv_top.core0_debug[40] ,
+    \u_riscv_top.core0_debug[39] ,
+    \u_riscv_top.core0_debug[38] ,
+    \u_riscv_top.core0_debug[37] ,
+    \u_riscv_top.core0_debug[36] ,
+    \u_riscv_top.core0_debug[35] ,
+    \u_riscv_top.core0_debug[34] ,
+    \u_riscv_top.core0_debug[33] ,
+    \u_riscv_top.core0_debug[32] ,
+    \u_riscv_top.core0_debug[31] ,
+    \u_riscv_top.core0_debug[30] ,
+    \u_riscv_top.core0_debug[29] ,
+    \u_riscv_top.core0_debug[28] ,
+    \u_riscv_top.core0_debug[27] ,
+    \u_riscv_top.core0_debug[26] ,
+    \u_riscv_top.core0_debug[25] ,
+    \u_riscv_top.core0_debug[24] ,
+    \u_riscv_top.core0_debug[23] ,
+    \u_riscv_top.core0_debug[22] ,
+    \u_riscv_top.core0_debug[21] ,
+    \u_riscv_top.core0_debug[20] ,
+    \u_riscv_top.core0_debug[19] ,
+    \u_riscv_top.core0_debug[18] ,
+    \u_riscv_top.core0_debug[17] ,
+    \u_riscv_top.core0_debug[16] ,
+    \u_riscv_top.core0_debug[15] ,
+    \u_riscv_top.core0_debug[14] ,
+    \u_riscv_top.core0_debug[13] ,
+    \u_riscv_top.core0_debug[12] ,
+    \u_riscv_top.core0_debug[11] ,
+    \u_riscv_top.core0_debug[10] ,
+    \u_riscv_top.core0_debug[9] ,
+    \u_riscv_top.core0_debug[8] ,
+    \u_riscv_top.core0_debug[7] ,
+    \u_riscv_top.core0_debug[6] ,
+    \u_riscv_top.core0_debug[5] ,
+    \u_riscv_top.core0_debug[4] ,
+    \u_riscv_top.core0_debug[3] ,
+    \u_riscv_top.core0_debug[2] ,
+    \u_riscv_top.core0_debug[1] ,
+    \u_riscv_top.core0_debug[0] }),
+    .core_irq_lines_i({\u_riscv_top.irq_lines[15] ,
+    \u_riscv_top.irq_lines[14] ,
+    \u_riscv_top.irq_lines[13] ,
+    \u_riscv_top.irq_lines[12] ,
+    \u_riscv_top.irq_lines[11] ,
+    \u_riscv_top.irq_lines[10] ,
+    \u_riscv_top.irq_lines[9] ,
+    \u_riscv_top.irq_lines[8] ,
+    \u_riscv_top.irq_lines[7] ,
+    \u_riscv_top.irq_lines[6] ,
+    \u_riscv_top.irq_lines[5] ,
+    \u_riscv_top.irq_lines[4] ,
+    \u_riscv_top.irq_lines[3] ,
+    \u_riscv_top.irq_lines[2] ,
+    \u_riscv_top.irq_lines[1] ,
+    \u_riscv_top.irq_lines[0] }),
+    .core_mtimer_val_i({\u_riscv_top.timer_val[63] ,
+    \u_riscv_top.timer_val[62] ,
+    \u_riscv_top.timer_val[61] ,
+    \u_riscv_top.timer_val[60] ,
+    \u_riscv_top.timer_val[59] ,
+    \u_riscv_top.timer_val[58] ,
+    \u_riscv_top.timer_val[57] ,
+    \u_riscv_top.timer_val[56] ,
+    \u_riscv_top.timer_val[55] ,
+    \u_riscv_top.timer_val[54] ,
+    \u_riscv_top.timer_val[53] ,
+    \u_riscv_top.timer_val[52] ,
+    \u_riscv_top.timer_val[51] ,
+    \u_riscv_top.timer_val[50] ,
+    \u_riscv_top.timer_val[49] ,
+    \u_riscv_top.timer_val[48] ,
+    \u_riscv_top.timer_val[47] ,
+    \u_riscv_top.timer_val[46] ,
+    \u_riscv_top.timer_val[45] ,
+    \u_riscv_top.timer_val[44] ,
+    \u_riscv_top.timer_val[43] ,
+    \u_riscv_top.timer_val[42] ,
+    \u_riscv_top.timer_val[41] ,
+    \u_riscv_top.timer_val[40] ,
+    \u_riscv_top.timer_val[39] ,
+    \u_riscv_top.timer_val[38] ,
+    \u_riscv_top.timer_val[37] ,
+    \u_riscv_top.timer_val[36] ,
+    \u_riscv_top.timer_val[35] ,
+    \u_riscv_top.timer_val[34] ,
+    \u_riscv_top.timer_val[33] ,
+    \u_riscv_top.timer_val[32] ,
+    \u_riscv_top.timer_val[31] ,
+    \u_riscv_top.timer_val[30] ,
+    \u_riscv_top.timer_val[29] ,
+    \u_riscv_top.timer_val[28] ,
+    \u_riscv_top.timer_val[27] ,
+    \u_riscv_top.timer_val[26] ,
+    \u_riscv_top.timer_val[25] ,
+    \u_riscv_top.timer_val[24] ,
+    \u_riscv_top.timer_val[23] ,
+    \u_riscv_top.timer_val[22] ,
+    \u_riscv_top.timer_val[21] ,
+    \u_riscv_top.timer_val[20] ,
+    \u_riscv_top.timer_val[19] ,
+    \u_riscv_top.timer_val[18] ,
+    \u_riscv_top.timer_val[17] ,
+    \u_riscv_top.timer_val[16] ,
+    \u_riscv_top.timer_val[15] ,
+    \u_riscv_top.timer_val[14] ,
+    \u_riscv_top.timer_val[13] ,
+    \u_riscv_top.timer_val[12] ,
+    \u_riscv_top.timer_val[11] ,
+    \u_riscv_top.timer_val[10] ,
+    \u_riscv_top.timer_val[9] ,
+    \u_riscv_top.timer_val[8] ,
+    \u_riscv_top.timer_val[7] ,
+    \u_riscv_top.timer_val[6] ,
+    \u_riscv_top.timer_val[5] ,
+    \u_riscv_top.timer_val[4] ,
+    \u_riscv_top.timer_val[3] ,
+    \u_riscv_top.timer_val[2] ,
+    \u_riscv_top.timer_val[1] ,
+    \u_riscv_top.timer_val[0] }),
+    .core_uid({\u_riscv_top.core0_uid[1] ,
+    \u_riscv_top.core0_uid[0] }),
+    .dmem2core_rdata_i({\u_riscv_top.core0_dmem_rdata[31] ,
+    \u_riscv_top.core0_dmem_rdata[30] ,
+    \u_riscv_top.core0_dmem_rdata[29] ,
+    \u_riscv_top.core0_dmem_rdata[28] ,
+    \u_riscv_top.core0_dmem_rdata[27] ,
+    \u_riscv_top.core0_dmem_rdata[26] ,
+    \u_riscv_top.core0_dmem_rdata[25] ,
+    \u_riscv_top.core0_dmem_rdata[24] ,
+    \u_riscv_top.core0_dmem_rdata[23] ,
+    \u_riscv_top.core0_dmem_rdata[22] ,
+    \u_riscv_top.core0_dmem_rdata[21] ,
+    \u_riscv_top.core0_dmem_rdata[20] ,
+    \u_riscv_top.core0_dmem_rdata[19] ,
+    \u_riscv_top.core0_dmem_rdata[18] ,
+    \u_riscv_top.core0_dmem_rdata[17] ,
+    \u_riscv_top.core0_dmem_rdata[16] ,
+    \u_riscv_top.core0_dmem_rdata[15] ,
+    \u_riscv_top.core0_dmem_rdata[14] ,
+    \u_riscv_top.core0_dmem_rdata[13] ,
+    \u_riscv_top.core0_dmem_rdata[12] ,
+    \u_riscv_top.core0_dmem_rdata[11] ,
+    \u_riscv_top.core0_dmem_rdata[10] ,
+    \u_riscv_top.core0_dmem_rdata[9] ,
+    \u_riscv_top.core0_dmem_rdata[8] ,
+    \u_riscv_top.core0_dmem_rdata[7] ,
+    \u_riscv_top.core0_dmem_rdata[6] ,
+    \u_riscv_top.core0_dmem_rdata[5] ,
+    \u_riscv_top.core0_dmem_rdata[4] ,
+    \u_riscv_top.core0_dmem_rdata[3] ,
+    \u_riscv_top.core0_dmem_rdata[2] ,
+    \u_riscv_top.core0_dmem_rdata[1] ,
+    \u_riscv_top.core0_dmem_rdata[0] }),
+    .dmem2core_resp_i({\u_riscv_top.core0_dmem_resp[1] ,
+    \u_riscv_top.core0_dmem_resp[0] }),
+    .imem2core_rdata_i({\u_riscv_top.core0_imem_rdata[31] ,
+    \u_riscv_top.core0_imem_rdata[30] ,
+    \u_riscv_top.core0_imem_rdata[29] ,
+    \u_riscv_top.core0_imem_rdata[28] ,
+    \u_riscv_top.core0_imem_rdata[27] ,
+    \u_riscv_top.core0_imem_rdata[26] ,
+    \u_riscv_top.core0_imem_rdata[25] ,
+    \u_riscv_top.core0_imem_rdata[24] ,
+    \u_riscv_top.core0_imem_rdata[23] ,
+    \u_riscv_top.core0_imem_rdata[22] ,
+    \u_riscv_top.core0_imem_rdata[21] ,
+    \u_riscv_top.core0_imem_rdata[20] ,
+    \u_riscv_top.core0_imem_rdata[19] ,
+    \u_riscv_top.core0_imem_rdata[18] ,
+    \u_riscv_top.core0_imem_rdata[17] ,
+    \u_riscv_top.core0_imem_rdata[16] ,
+    \u_riscv_top.core0_imem_rdata[15] ,
+    \u_riscv_top.core0_imem_rdata[14] ,
+    \u_riscv_top.core0_imem_rdata[13] ,
+    \u_riscv_top.core0_imem_rdata[12] ,
+    \u_riscv_top.core0_imem_rdata[11] ,
+    \u_riscv_top.core0_imem_rdata[10] ,
+    \u_riscv_top.core0_imem_rdata[9] ,
+    \u_riscv_top.core0_imem_rdata[8] ,
+    \u_riscv_top.core0_imem_rdata[7] ,
+    \u_riscv_top.core0_imem_rdata[6] ,
+    \u_riscv_top.core0_imem_rdata[5] ,
+    \u_riscv_top.core0_imem_rdata[4] ,
+    \u_riscv_top.core0_imem_rdata[3] ,
+    \u_riscv_top.core0_imem_rdata[2] ,
+    \u_riscv_top.core0_imem_rdata[1] ,
+    \u_riscv_top.core0_imem_rdata[0] }),
+    .imem2core_resp_i({\u_riscv_top.core0_imem_resp[1] ,
+    \u_riscv_top.core0_imem_resp[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_1  (.clk(\u_riscv_top.core_clk ),
+    .core2dmem_cmd_o(\u_riscv_top.core1_dmem_cmd ),
+    .core2dmem_req_o(\u_riscv_top.core1_dmem_req ),
+    .core2imem_cmd_o(\u_riscv_top.core1_imem_cmd ),
+    .core2imem_req_o(\u_riscv_top.core1_imem_req ),
+    .core_irq_mtimer_i(\u_riscv_top.timer_irq ),
+    .core_irq_soft_i(\u_riscv_top.soft_irq ),
+    .cpu_rst_n(\u_riscv_top.cpu_core_rst_n_sync[1] ),
+    .dmem2core_req_ack_i(\u_riscv_top.core1_dmem_req_ack ),
+    .imem2core_req_ack_i(\u_riscv_top.core1_imem_req_ack ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n_sync ),
+    .rst_n(\u_riscv_top.rst_n_sync ),
+    .test_mode(\u_riscv_top.test_mode ),
+    .test_rst_n(\u_riscv_top.test_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .core2dmem_addr_o({\u_riscv_top.core1_dmem_addr[31] ,
+    \u_riscv_top.core1_dmem_addr[30] ,
+    \u_riscv_top.core1_dmem_addr[29] ,
+    \u_riscv_top.core1_dmem_addr[28] ,
+    \u_riscv_top.core1_dmem_addr[27] ,
+    \u_riscv_top.core1_dmem_addr[26] ,
+    \u_riscv_top.core1_dmem_addr[25] ,
+    \u_riscv_top.core1_dmem_addr[24] ,
+    \u_riscv_top.core1_dmem_addr[23] ,
+    \u_riscv_top.core1_dmem_addr[22] ,
+    \u_riscv_top.core1_dmem_addr[21] ,
+    \u_riscv_top.core1_dmem_addr[20] ,
+    \u_riscv_top.core1_dmem_addr[19] ,
+    \u_riscv_top.core1_dmem_addr[18] ,
+    \u_riscv_top.core1_dmem_addr[17] ,
+    \u_riscv_top.core1_dmem_addr[16] ,
+    \u_riscv_top.core1_dmem_addr[15] ,
+    \u_riscv_top.core1_dmem_addr[14] ,
+    \u_riscv_top.core1_dmem_addr[13] ,
+    \u_riscv_top.core1_dmem_addr[12] ,
+    \u_riscv_top.core1_dmem_addr[11] ,
+    \u_riscv_top.core1_dmem_addr[10] ,
+    \u_riscv_top.core1_dmem_addr[9] ,
+    \u_riscv_top.core1_dmem_addr[8] ,
+    \u_riscv_top.core1_dmem_addr[7] ,
+    \u_riscv_top.core1_dmem_addr[6] ,
+    \u_riscv_top.core1_dmem_addr[5] ,
+    \u_riscv_top.core1_dmem_addr[4] ,
+    \u_riscv_top.core1_dmem_addr[3] ,
+    \u_riscv_top.core1_dmem_addr[2] ,
+    \u_riscv_top.core1_dmem_addr[1] ,
+    \u_riscv_top.core1_dmem_addr[0] }),
+    .core2dmem_wdata_o({\u_riscv_top.core1_dmem_wdata[31] ,
+    \u_riscv_top.core1_dmem_wdata[30] ,
+    \u_riscv_top.core1_dmem_wdata[29] ,
+    \u_riscv_top.core1_dmem_wdata[28] ,
+    \u_riscv_top.core1_dmem_wdata[27] ,
+    \u_riscv_top.core1_dmem_wdata[26] ,
+    \u_riscv_top.core1_dmem_wdata[25] ,
+    \u_riscv_top.core1_dmem_wdata[24] ,
+    \u_riscv_top.core1_dmem_wdata[23] ,
+    \u_riscv_top.core1_dmem_wdata[22] ,
+    \u_riscv_top.core1_dmem_wdata[21] ,
+    \u_riscv_top.core1_dmem_wdata[20] ,
+    \u_riscv_top.core1_dmem_wdata[19] ,
+    \u_riscv_top.core1_dmem_wdata[18] ,
+    \u_riscv_top.core1_dmem_wdata[17] ,
+    \u_riscv_top.core1_dmem_wdata[16] ,
+    \u_riscv_top.core1_dmem_wdata[15] ,
+    \u_riscv_top.core1_dmem_wdata[14] ,
+    \u_riscv_top.core1_dmem_wdata[13] ,
+    \u_riscv_top.core1_dmem_wdata[12] ,
+    \u_riscv_top.core1_dmem_wdata[11] ,
+    \u_riscv_top.core1_dmem_wdata[10] ,
+    \u_riscv_top.core1_dmem_wdata[9] ,
+    \u_riscv_top.core1_dmem_wdata[8] ,
+    \u_riscv_top.core1_dmem_wdata[7] ,
+    \u_riscv_top.core1_dmem_wdata[6] ,
+    \u_riscv_top.core1_dmem_wdata[5] ,
+    \u_riscv_top.core1_dmem_wdata[4] ,
+    \u_riscv_top.core1_dmem_wdata[3] ,
+    \u_riscv_top.core1_dmem_wdata[2] ,
+    \u_riscv_top.core1_dmem_wdata[1] ,
+    \u_riscv_top.core1_dmem_wdata[0] }),
+    .core2dmem_width_o({\u_riscv_top.core1_dmem_width[1] ,
+    \u_riscv_top.core1_dmem_width[0] }),
+    .core2imem_addr_o({\u_riscv_top.core1_imem_addr[31] ,
+    \u_riscv_top.core1_imem_addr[30] ,
+    \u_riscv_top.core1_imem_addr[29] ,
+    \u_riscv_top.core1_imem_addr[28] ,
+    \u_riscv_top.core1_imem_addr[27] ,
+    \u_riscv_top.core1_imem_addr[26] ,
+    \u_riscv_top.core1_imem_addr[25] ,
+    \u_riscv_top.core1_imem_addr[24] ,
+    \u_riscv_top.core1_imem_addr[23] ,
+    \u_riscv_top.core1_imem_addr[22] ,
+    \u_riscv_top.core1_imem_addr[21] ,
+    \u_riscv_top.core1_imem_addr[20] ,
+    \u_riscv_top.core1_imem_addr[19] ,
+    \u_riscv_top.core1_imem_addr[18] ,
+    \u_riscv_top.core1_imem_addr[17] ,
+    \u_riscv_top.core1_imem_addr[16] ,
+    \u_riscv_top.core1_imem_addr[15] ,
+    \u_riscv_top.core1_imem_addr[14] ,
+    \u_riscv_top.core1_imem_addr[13] ,
+    \u_riscv_top.core1_imem_addr[12] ,
+    \u_riscv_top.core1_imem_addr[11] ,
+    \u_riscv_top.core1_imem_addr[10] ,
+    \u_riscv_top.core1_imem_addr[9] ,
+    \u_riscv_top.core1_imem_addr[8] ,
+    \u_riscv_top.core1_imem_addr[7] ,
+    \u_riscv_top.core1_imem_addr[6] ,
+    \u_riscv_top.core1_imem_addr[5] ,
+    \u_riscv_top.core1_imem_addr[4] ,
+    \u_riscv_top.core1_imem_addr[3] ,
+    \u_riscv_top.core1_imem_addr[2] ,
+    \u_riscv_top.core1_imem_addr[1] ,
+    \u_riscv_top.core1_imem_addr[0] }),
+    .core2imem_bl_o({\u_riscv_top.core1_imem_bl[2] ,
+    \u_riscv_top.core1_imem_bl[1] ,
+    \u_riscv_top.core1_imem_bl[0] }),
+    .core_debug({\u_riscv_top.core1_debug[48] ,
+    \u_riscv_top.core1_debug[47] ,
+    \u_riscv_top.core1_debug[46] ,
+    \u_riscv_top.core1_debug[45] ,
+    \u_riscv_top.core1_debug[44] ,
+    \u_riscv_top.core1_debug[43] ,
+    \u_riscv_top.core1_debug[42] ,
+    \u_riscv_top.core1_debug[41] ,
+    \u_riscv_top.core1_debug[40] ,
+    \u_riscv_top.core1_debug[39] ,
+    \u_riscv_top.core1_debug[38] ,
+    \u_riscv_top.core1_debug[37] ,
+    \u_riscv_top.core1_debug[36] ,
+    \u_riscv_top.core1_debug[35] ,
+    \u_riscv_top.core1_debug[34] ,
+    \u_riscv_top.core1_debug[33] ,
+    \u_riscv_top.core1_debug[32] ,
+    \u_riscv_top.core1_debug[31] ,
+    \u_riscv_top.core1_debug[30] ,
+    \u_riscv_top.core1_debug[29] ,
+    \u_riscv_top.core1_debug[28] ,
+    \u_riscv_top.core1_debug[27] ,
+    \u_riscv_top.core1_debug[26] ,
+    \u_riscv_top.core1_debug[25] ,
+    \u_riscv_top.core1_debug[24] ,
+    \u_riscv_top.core1_debug[23] ,
+    \u_riscv_top.core1_debug[22] ,
+    \u_riscv_top.core1_debug[21] ,
+    \u_riscv_top.core1_debug[20] ,
+    \u_riscv_top.core1_debug[19] ,
+    \u_riscv_top.core1_debug[18] ,
+    \u_riscv_top.core1_debug[17] ,
+    \u_riscv_top.core1_debug[16] ,
+    \u_riscv_top.core1_debug[15] ,
+    \u_riscv_top.core1_debug[14] ,
+    \u_riscv_top.core1_debug[13] ,
+    \u_riscv_top.core1_debug[12] ,
+    \u_riscv_top.core1_debug[11] ,
+    \u_riscv_top.core1_debug[10] ,
+    \u_riscv_top.core1_debug[9] ,
+    \u_riscv_top.core1_debug[8] ,
+    \u_riscv_top.core1_debug[7] ,
+    \u_riscv_top.core1_debug[6] ,
+    \u_riscv_top.core1_debug[5] ,
+    \u_riscv_top.core1_debug[4] ,
+    \u_riscv_top.core1_debug[3] ,
+    \u_riscv_top.core1_debug[2] ,
+    \u_riscv_top.core1_debug[1] ,
+    \u_riscv_top.core1_debug[0] }),
+    .core_irq_lines_i({\u_riscv_top.irq_lines[15] ,
+    \u_riscv_top.irq_lines[14] ,
+    \u_riscv_top.irq_lines[13] ,
+    \u_riscv_top.irq_lines[12] ,
+    \u_riscv_top.irq_lines[11] ,
+    \u_riscv_top.irq_lines[10] ,
+    \u_riscv_top.irq_lines[9] ,
+    \u_riscv_top.irq_lines[8] ,
+    \u_riscv_top.irq_lines[7] ,
+    \u_riscv_top.irq_lines[6] ,
+    \u_riscv_top.irq_lines[5] ,
+    \u_riscv_top.irq_lines[4] ,
+    \u_riscv_top.irq_lines[3] ,
+    \u_riscv_top.irq_lines[2] ,
+    \u_riscv_top.irq_lines[1] ,
+    \u_riscv_top.irq_lines[0] }),
+    .core_mtimer_val_i({\u_riscv_top.timer_val[63] ,
+    \u_riscv_top.timer_val[62] ,
+    \u_riscv_top.timer_val[61] ,
+    \u_riscv_top.timer_val[60] ,
+    \u_riscv_top.timer_val[59] ,
+    \u_riscv_top.timer_val[58] ,
+    \u_riscv_top.timer_val[57] ,
+    \u_riscv_top.timer_val[56] ,
+    \u_riscv_top.timer_val[55] ,
+    \u_riscv_top.timer_val[54] ,
+    \u_riscv_top.timer_val[53] ,
+    \u_riscv_top.timer_val[52] ,
+    \u_riscv_top.timer_val[51] ,
+    \u_riscv_top.timer_val[50] ,
+    \u_riscv_top.timer_val[49] ,
+    \u_riscv_top.timer_val[48] ,
+    \u_riscv_top.timer_val[47] ,
+    \u_riscv_top.timer_val[46] ,
+    \u_riscv_top.timer_val[45] ,
+    \u_riscv_top.timer_val[44] ,
+    \u_riscv_top.timer_val[43] ,
+    \u_riscv_top.timer_val[42] ,
+    \u_riscv_top.timer_val[41] ,
+    \u_riscv_top.timer_val[40] ,
+    \u_riscv_top.timer_val[39] ,
+    \u_riscv_top.timer_val[38] ,
+    \u_riscv_top.timer_val[37] ,
+    \u_riscv_top.timer_val[36] ,
+    \u_riscv_top.timer_val[35] ,
+    \u_riscv_top.timer_val[34] ,
+    \u_riscv_top.timer_val[33] ,
+    \u_riscv_top.timer_val[32] ,
+    \u_riscv_top.timer_val[31] ,
+    \u_riscv_top.timer_val[30] ,
+    \u_riscv_top.timer_val[29] ,
+    \u_riscv_top.timer_val[28] ,
+    \u_riscv_top.timer_val[27] ,
+    \u_riscv_top.timer_val[26] ,
+    \u_riscv_top.timer_val[25] ,
+    \u_riscv_top.timer_val[24] ,
+    \u_riscv_top.timer_val[23] ,
+    \u_riscv_top.timer_val[22] ,
+    \u_riscv_top.timer_val[21] ,
+    \u_riscv_top.timer_val[20] ,
+    \u_riscv_top.timer_val[19] ,
+    \u_riscv_top.timer_val[18] ,
+    \u_riscv_top.timer_val[17] ,
+    \u_riscv_top.timer_val[16] ,
+    \u_riscv_top.timer_val[15] ,
+    \u_riscv_top.timer_val[14] ,
+    \u_riscv_top.timer_val[13] ,
+    \u_riscv_top.timer_val[12] ,
+    \u_riscv_top.timer_val[11] ,
+    \u_riscv_top.timer_val[10] ,
+    \u_riscv_top.timer_val[9] ,
+    \u_riscv_top.timer_val[8] ,
+    \u_riscv_top.timer_val[7] ,
+    \u_riscv_top.timer_val[6] ,
+    \u_riscv_top.timer_val[5] ,
+    \u_riscv_top.timer_val[4] ,
+    \u_riscv_top.timer_val[3] ,
+    \u_riscv_top.timer_val[2] ,
+    \u_riscv_top.timer_val[1] ,
+    \u_riscv_top.timer_val[0] }),
+    .core_uid({\u_riscv_top.core1_uid[1] ,
+    \u_riscv_top.core1_uid[0] }),
+    .dmem2core_rdata_i({\u_riscv_top.core1_dmem_rdata[31] ,
+    \u_riscv_top.core1_dmem_rdata[30] ,
+    \u_riscv_top.core1_dmem_rdata[29] ,
+    \u_riscv_top.core1_dmem_rdata[28] ,
+    \u_riscv_top.core1_dmem_rdata[27] ,
+    \u_riscv_top.core1_dmem_rdata[26] ,
+    \u_riscv_top.core1_dmem_rdata[25] ,
+    \u_riscv_top.core1_dmem_rdata[24] ,
+    \u_riscv_top.core1_dmem_rdata[23] ,
+    \u_riscv_top.core1_dmem_rdata[22] ,
+    \u_riscv_top.core1_dmem_rdata[21] ,
+    \u_riscv_top.core1_dmem_rdata[20] ,
+    \u_riscv_top.core1_dmem_rdata[19] ,
+    \u_riscv_top.core1_dmem_rdata[18] ,
+    \u_riscv_top.core1_dmem_rdata[17] ,
+    \u_riscv_top.core1_dmem_rdata[16] ,
+    \u_riscv_top.core1_dmem_rdata[15] ,
+    \u_riscv_top.core1_dmem_rdata[14] ,
+    \u_riscv_top.core1_dmem_rdata[13] ,
+    \u_riscv_top.core1_dmem_rdata[12] ,
+    \u_riscv_top.core1_dmem_rdata[11] ,
+    \u_riscv_top.core1_dmem_rdata[10] ,
+    \u_riscv_top.core1_dmem_rdata[9] ,
+    \u_riscv_top.core1_dmem_rdata[8] ,
+    \u_riscv_top.core1_dmem_rdata[7] ,
+    \u_riscv_top.core1_dmem_rdata[6] ,
+    \u_riscv_top.core1_dmem_rdata[5] ,
+    \u_riscv_top.core1_dmem_rdata[4] ,
+    \u_riscv_top.core1_dmem_rdata[3] ,
+    \u_riscv_top.core1_dmem_rdata[2] ,
+    \u_riscv_top.core1_dmem_rdata[1] ,
+    \u_riscv_top.core1_dmem_rdata[0] }),
+    .dmem2core_resp_i({\u_riscv_top.core1_dmem_resp[1] ,
+    \u_riscv_top.core1_dmem_resp[0] }),
+    .imem2core_rdata_i({\u_riscv_top.core1_imem_rdata[31] ,
+    \u_riscv_top.core1_imem_rdata[30] ,
+    \u_riscv_top.core1_imem_rdata[29] ,
+    \u_riscv_top.core1_imem_rdata[28] ,
+    \u_riscv_top.core1_imem_rdata[27] ,
+    \u_riscv_top.core1_imem_rdata[26] ,
+    \u_riscv_top.core1_imem_rdata[25] ,
+    \u_riscv_top.core1_imem_rdata[24] ,
+    \u_riscv_top.core1_imem_rdata[23] ,
+    \u_riscv_top.core1_imem_rdata[22] ,
+    \u_riscv_top.core1_imem_rdata[21] ,
+    \u_riscv_top.core1_imem_rdata[20] ,
+    \u_riscv_top.core1_imem_rdata[19] ,
+    \u_riscv_top.core1_imem_rdata[18] ,
+    \u_riscv_top.core1_imem_rdata[17] ,
+    \u_riscv_top.core1_imem_rdata[16] ,
+    \u_riscv_top.core1_imem_rdata[15] ,
+    \u_riscv_top.core1_imem_rdata[14] ,
+    \u_riscv_top.core1_imem_rdata[13] ,
+    \u_riscv_top.core1_imem_rdata[12] ,
+    \u_riscv_top.core1_imem_rdata[11] ,
+    \u_riscv_top.core1_imem_rdata[10] ,
+    \u_riscv_top.core1_imem_rdata[9] ,
+    \u_riscv_top.core1_imem_rdata[8] ,
+    \u_riscv_top.core1_imem_rdata[7] ,
+    \u_riscv_top.core1_imem_rdata[6] ,
+    \u_riscv_top.core1_imem_rdata[5] ,
+    \u_riscv_top.core1_imem_rdata[4] ,
+    \u_riscv_top.core1_imem_rdata[3] ,
+    \u_riscv_top.core1_imem_rdata[2] ,
+    \u_riscv_top.core1_imem_rdata[1] ,
+    \u_riscv_top.core1_imem_rdata[0] }),
+    .imem2core_resp_i({\u_riscv_top.core1_imem_resp[1] ,
+    \u_riscv_top.core1_imem_resp[0] }));
+ ycr2_mintf \u_riscv_top.u_mintf  (.core0_dmem_cmd(\u_riscv_top.core0_dmem_cmd ),
+    .core0_dmem_req(\u_riscv_top.core0_dmem_req ),
+    .core0_dmem_req_ack(\u_riscv_top.core0_dmem_req_ack ),
+    .core0_imem_cmd(\u_riscv_top.core0_imem_cmd ),
+    .core0_imem_req(\u_riscv_top.core0_imem_req ),
+    .core0_imem_req_ack(\u_riscv_top.core0_imem_req_ack ),
+    .core1_dmem_cmd(\u_riscv_top.core1_dmem_cmd ),
+    .core1_dmem_req(\u_riscv_top.core1_dmem_req ),
+    .core1_dmem_req_ack(\u_riscv_top.core1_dmem_req_ack ),
+    .core1_imem_cmd(\u_riscv_top.core1_imem_cmd ),
+    .core1_imem_req(\u_riscv_top.core1_imem_req ),
+    .core1_imem_req_ack(\u_riscv_top.core1_imem_req_ack ),
+    .core_clk(\u_riscv_top.core_clk ),
+    .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+    .dcache_mem_clk0(\u_riscv_top.dcache_mem_clk0 ),
+    .dcache_mem_clk1(\u_riscv_top.dcache_mem_clk1 ),
+    .dcache_mem_csb0(\u_riscv_top.dcache_mem_csb0 ),
+    .dcache_mem_csb1(\u_riscv_top.dcache_mem_csb1 ),
+    .dcache_mem_web0(\u_riscv_top.dcache_mem_web0 ),
+    .icache_mem_clk0(\u_riscv_top.icache_mem_clk0 ),
+    .icache_mem_clk1(\u_riscv_top.icache_mem_clk1 ),
+    .icache_mem_csb0(\u_riscv_top.icache_mem_csb0 ),
+    .icache_mem_csb1(\u_riscv_top.icache_mem_csb1 ),
+    .icache_mem_web0(\u_riscv_top.icache_mem_web0 ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .pwrup_rst_n_sync(\u_riscv_top.pwrup_rst_n_sync ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rst_n_sync(\u_riscv_top.rst_n_sync ),
+    .rtc_clk(\u_riscv_top.rtc_clk ),
+    .sram0_clk0(\u_riscv_top.sram0_clk0 ),
+    .sram0_clk1(\u_riscv_top.sram0_clk1 ),
+    .sram0_csb0(\u_riscv_top.sram0_csb0 ),
+    .sram0_csb1(\u_riscv_top.sram0_csb1 ),
+    .sram0_web0(\u_riscv_top.sram0_web0 ),
+    .test_mode(\u_riscv_top.test_mode ),
+    .test_rst_n(\u_riscv_top.test_rst_n ),
+    .timer_irq(\u_riscv_top.timer_irq ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wb_clk(\u_riscv_top.wb_clk ),
+    .wb_dcache_ack_i(\u_riscv_top.wb_dcache_ack_i ),
+    .wb_dcache_bry_o(\u_riscv_top.wb_dcache_bry_o ),
+    .wb_dcache_err_i(\u_riscv_top.wb_dcache_err_i ),
+    .wb_dcache_lack_i(\u_riscv_top.wb_dcache_lack_i ),
+    .wb_dcache_stb_o(\u_riscv_top.wb_dcache_stb_o ),
+    .wb_dcache_we_o(\u_riscv_top.wb_dcache_we_o ),
+    .wb_icache_ack_i(\u_riscv_top.wb_icache_ack_i ),
+    .wb_icache_bry_o(\u_riscv_top.wb_icache_bry_o ),
+    .wb_icache_err_i(\u_riscv_top.wb_icache_err_i ),
+    .wb_icache_lack_i(\u_riscv_top.wb_icache_lack_i ),
+    .wb_icache_stb_o(\u_riscv_top.wb_icache_stb_o ),
+    .wb_icache_we_o(\u_riscv_top.wb_icache_we_o ),
+    .wb_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .wbd_clk_int(\u_riscv_top.wbd_clk_int ),
+    .wbd_clk_riscv(\u_riscv_top.wb_clk ),
+    .wbd_dmem_ack_i(\u_riscv_top.wbd_dmem_ack_i ),
+    .wbd_dmem_err_i(\u_riscv_top.wbd_dmem_err_i ),
+    .wbd_dmem_stb_o(\u_riscv_top.wbd_dmem_stb_o ),
+    .wbd_dmem_we_o(\u_riscv_top.wbd_dmem_we_o ),
+    .cfg_cska_riscv({\u_riscv_top.cfg_cska_riscv[3] ,
+    \u_riscv_top.cfg_cska_riscv[2] ,
+    \u_riscv_top.cfg_cska_riscv[1] ,
+    \u_riscv_top.cfg_cska_riscv[0] }),
+    .core0_debug({\u_riscv_top.core0_debug[48] ,
+    \u_riscv_top.core0_debug[47] ,
+    \u_riscv_top.core0_debug[46] ,
+    \u_riscv_top.core0_debug[45] ,
+    \u_riscv_top.core0_debug[44] ,
+    \u_riscv_top.core0_debug[43] ,
+    \u_riscv_top.core0_debug[42] ,
+    \u_riscv_top.core0_debug[41] ,
+    \u_riscv_top.core0_debug[40] ,
+    \u_riscv_top.core0_debug[39] ,
+    \u_riscv_top.core0_debug[38] ,
+    \u_riscv_top.core0_debug[37] ,
+    \u_riscv_top.core0_debug[36] ,
+    \u_riscv_top.core0_debug[35] ,
+    \u_riscv_top.core0_debug[34] ,
+    \u_riscv_top.core0_debug[33] ,
+    \u_riscv_top.core0_debug[32] ,
+    \u_riscv_top.core0_debug[31] ,
+    \u_riscv_top.core0_debug[30] ,
+    \u_riscv_top.core0_debug[29] ,
+    \u_riscv_top.core0_debug[28] ,
+    \u_riscv_top.core0_debug[27] ,
+    \u_riscv_top.core0_debug[26] ,
+    \u_riscv_top.core0_debug[25] ,
+    \u_riscv_top.core0_debug[24] ,
+    \u_riscv_top.core0_debug[23] ,
+    \u_riscv_top.core0_debug[22] ,
+    \u_riscv_top.core0_debug[21] ,
+    \u_riscv_top.core0_debug[20] ,
+    \u_riscv_top.core0_debug[19] ,
+    \u_riscv_top.core0_debug[18] ,
+    \u_riscv_top.core0_debug[17] ,
+    \u_riscv_top.core0_debug[16] ,
+    \u_riscv_top.core0_debug[15] ,
+    \u_riscv_top.core0_debug[14] ,
+    \u_riscv_top.core0_debug[13] ,
+    \u_riscv_top.core0_debug[12] ,
+    \u_riscv_top.core0_debug[11] ,
+    \u_riscv_top.core0_debug[10] ,
+    \u_riscv_top.core0_debug[9] ,
+    \u_riscv_top.core0_debug[8] ,
+    \u_riscv_top.core0_debug[7] ,
+    \u_riscv_top.core0_debug[6] ,
+    \u_riscv_top.core0_debug[5] ,
+    \u_riscv_top.core0_debug[4] ,
+    \u_riscv_top.core0_debug[3] ,
+    \u_riscv_top.core0_debug[2] ,
+    \u_riscv_top.core0_debug[1] ,
+    \u_riscv_top.core0_debug[0] }),
+    .core0_dmem_addr({\u_riscv_top.core0_dmem_addr[31] ,
+    \u_riscv_top.core0_dmem_addr[30] ,
+    \u_riscv_top.core0_dmem_addr[29] ,
+    \u_riscv_top.core0_dmem_addr[28] ,
+    \u_riscv_top.core0_dmem_addr[27] ,
+    \u_riscv_top.core0_dmem_addr[26] ,
+    \u_riscv_top.core0_dmem_addr[25] ,
+    \u_riscv_top.core0_dmem_addr[24] ,
+    \u_riscv_top.core0_dmem_addr[23] ,
+    \u_riscv_top.core0_dmem_addr[22] ,
+    \u_riscv_top.core0_dmem_addr[21] ,
+    \u_riscv_top.core0_dmem_addr[20] ,
+    \u_riscv_top.core0_dmem_addr[19] ,
+    \u_riscv_top.core0_dmem_addr[18] ,
+    \u_riscv_top.core0_dmem_addr[17] ,
+    \u_riscv_top.core0_dmem_addr[16] ,
+    \u_riscv_top.core0_dmem_addr[15] ,
+    \u_riscv_top.core0_dmem_addr[14] ,
+    \u_riscv_top.core0_dmem_addr[13] ,
+    \u_riscv_top.core0_dmem_addr[12] ,
+    \u_riscv_top.core0_dmem_addr[11] ,
+    \u_riscv_top.core0_dmem_addr[10] ,
+    \u_riscv_top.core0_dmem_addr[9] ,
+    \u_riscv_top.core0_dmem_addr[8] ,
+    \u_riscv_top.core0_dmem_addr[7] ,
+    \u_riscv_top.core0_dmem_addr[6] ,
+    \u_riscv_top.core0_dmem_addr[5] ,
+    \u_riscv_top.core0_dmem_addr[4] ,
+    \u_riscv_top.core0_dmem_addr[3] ,
+    \u_riscv_top.core0_dmem_addr[2] ,
+    \u_riscv_top.core0_dmem_addr[1] ,
+    \u_riscv_top.core0_dmem_addr[0] }),
+    .core0_dmem_rdata({\u_riscv_top.core0_dmem_rdata[31] ,
+    \u_riscv_top.core0_dmem_rdata[30] ,
+    \u_riscv_top.core0_dmem_rdata[29] ,
+    \u_riscv_top.core0_dmem_rdata[28] ,
+    \u_riscv_top.core0_dmem_rdata[27] ,
+    \u_riscv_top.core0_dmem_rdata[26] ,
+    \u_riscv_top.core0_dmem_rdata[25] ,
+    \u_riscv_top.core0_dmem_rdata[24] ,
+    \u_riscv_top.core0_dmem_rdata[23] ,
+    \u_riscv_top.core0_dmem_rdata[22] ,
+    \u_riscv_top.core0_dmem_rdata[21] ,
+    \u_riscv_top.core0_dmem_rdata[20] ,
+    \u_riscv_top.core0_dmem_rdata[19] ,
+    \u_riscv_top.core0_dmem_rdata[18] ,
+    \u_riscv_top.core0_dmem_rdata[17] ,
+    \u_riscv_top.core0_dmem_rdata[16] ,
+    \u_riscv_top.core0_dmem_rdata[15] ,
+    \u_riscv_top.core0_dmem_rdata[14] ,
+    \u_riscv_top.core0_dmem_rdata[13] ,
+    \u_riscv_top.core0_dmem_rdata[12] ,
+    \u_riscv_top.core0_dmem_rdata[11] ,
+    \u_riscv_top.core0_dmem_rdata[10] ,
+    \u_riscv_top.core0_dmem_rdata[9] ,
+    \u_riscv_top.core0_dmem_rdata[8] ,
+    \u_riscv_top.core0_dmem_rdata[7] ,
+    \u_riscv_top.core0_dmem_rdata[6] ,
+    \u_riscv_top.core0_dmem_rdata[5] ,
+    \u_riscv_top.core0_dmem_rdata[4] ,
+    \u_riscv_top.core0_dmem_rdata[3] ,
+    \u_riscv_top.core0_dmem_rdata[2] ,
+    \u_riscv_top.core0_dmem_rdata[1] ,
+    \u_riscv_top.core0_dmem_rdata[0] }),
+    .core0_dmem_resp({\u_riscv_top.core0_dmem_resp[1] ,
+    \u_riscv_top.core0_dmem_resp[0] }),
+    .core0_dmem_wdata({\u_riscv_top.core0_dmem_wdata[31] ,
+    \u_riscv_top.core0_dmem_wdata[30] ,
+    \u_riscv_top.core0_dmem_wdata[29] ,
+    \u_riscv_top.core0_dmem_wdata[28] ,
+    \u_riscv_top.core0_dmem_wdata[27] ,
+    \u_riscv_top.core0_dmem_wdata[26] ,
+    \u_riscv_top.core0_dmem_wdata[25] ,
+    \u_riscv_top.core0_dmem_wdata[24] ,
+    \u_riscv_top.core0_dmem_wdata[23] ,
+    \u_riscv_top.core0_dmem_wdata[22] ,
+    \u_riscv_top.core0_dmem_wdata[21] ,
+    \u_riscv_top.core0_dmem_wdata[20] ,
+    \u_riscv_top.core0_dmem_wdata[19] ,
+    \u_riscv_top.core0_dmem_wdata[18] ,
+    \u_riscv_top.core0_dmem_wdata[17] ,
+    \u_riscv_top.core0_dmem_wdata[16] ,
+    \u_riscv_top.core0_dmem_wdata[15] ,
+    \u_riscv_top.core0_dmem_wdata[14] ,
+    \u_riscv_top.core0_dmem_wdata[13] ,
+    \u_riscv_top.core0_dmem_wdata[12] ,
+    \u_riscv_top.core0_dmem_wdata[11] ,
+    \u_riscv_top.core0_dmem_wdata[10] ,
+    \u_riscv_top.core0_dmem_wdata[9] ,
+    \u_riscv_top.core0_dmem_wdata[8] ,
+    \u_riscv_top.core0_dmem_wdata[7] ,
+    \u_riscv_top.core0_dmem_wdata[6] ,
+    \u_riscv_top.core0_dmem_wdata[5] ,
+    \u_riscv_top.core0_dmem_wdata[4] ,
+    \u_riscv_top.core0_dmem_wdata[3] ,
+    \u_riscv_top.core0_dmem_wdata[2] ,
+    \u_riscv_top.core0_dmem_wdata[1] ,
+    \u_riscv_top.core0_dmem_wdata[0] }),
+    .core0_dmem_width({\u_riscv_top.core0_dmem_width[1] ,
+    \u_riscv_top.core0_dmem_width[0] }),
+    .core0_imem_addr({\u_riscv_top.core0_imem_addr[31] ,
+    \u_riscv_top.core0_imem_addr[30] ,
+    \u_riscv_top.core0_imem_addr[29] ,
+    \u_riscv_top.core0_imem_addr[28] ,
+    \u_riscv_top.core0_imem_addr[27] ,
+    \u_riscv_top.core0_imem_addr[26] ,
+    \u_riscv_top.core0_imem_addr[25] ,
+    \u_riscv_top.core0_imem_addr[24] ,
+    \u_riscv_top.core0_imem_addr[23] ,
+    \u_riscv_top.core0_imem_addr[22] ,
+    \u_riscv_top.core0_imem_addr[21] ,
+    \u_riscv_top.core0_imem_addr[20] ,
+    \u_riscv_top.core0_imem_addr[19] ,
+    \u_riscv_top.core0_imem_addr[18] ,
+    \u_riscv_top.core0_imem_addr[17] ,
+    \u_riscv_top.core0_imem_addr[16] ,
+    \u_riscv_top.core0_imem_addr[15] ,
+    \u_riscv_top.core0_imem_addr[14] ,
+    \u_riscv_top.core0_imem_addr[13] ,
+    \u_riscv_top.core0_imem_addr[12] ,
+    \u_riscv_top.core0_imem_addr[11] ,
+    \u_riscv_top.core0_imem_addr[10] ,
+    \u_riscv_top.core0_imem_addr[9] ,
+    \u_riscv_top.core0_imem_addr[8] ,
+    \u_riscv_top.core0_imem_addr[7] ,
+    \u_riscv_top.core0_imem_addr[6] ,
+    \u_riscv_top.core0_imem_addr[5] ,
+    \u_riscv_top.core0_imem_addr[4] ,
+    \u_riscv_top.core0_imem_addr[3] ,
+    \u_riscv_top.core0_imem_addr[2] ,
+    \u_riscv_top.core0_imem_addr[1] ,
+    \u_riscv_top.core0_imem_addr[0] }),
+    .core0_imem_bl({\u_riscv_top.core0_imem_bl[2] ,
+    \u_riscv_top.core0_imem_bl[1] ,
+    \u_riscv_top.core0_imem_bl[0] }),
+    .core0_imem_rdata({\u_riscv_top.core0_imem_rdata[31] ,
+    \u_riscv_top.core0_imem_rdata[30] ,
+    \u_riscv_top.core0_imem_rdata[29] ,
+    \u_riscv_top.core0_imem_rdata[28] ,
+    \u_riscv_top.core0_imem_rdata[27] ,
+    \u_riscv_top.core0_imem_rdata[26] ,
+    \u_riscv_top.core0_imem_rdata[25] ,
+    \u_riscv_top.core0_imem_rdata[24] ,
+    \u_riscv_top.core0_imem_rdata[23] ,
+    \u_riscv_top.core0_imem_rdata[22] ,
+    \u_riscv_top.core0_imem_rdata[21] ,
+    \u_riscv_top.core0_imem_rdata[20] ,
+    \u_riscv_top.core0_imem_rdata[19] ,
+    \u_riscv_top.core0_imem_rdata[18] ,
+    \u_riscv_top.core0_imem_rdata[17] ,
+    \u_riscv_top.core0_imem_rdata[16] ,
+    \u_riscv_top.core0_imem_rdata[15] ,
+    \u_riscv_top.core0_imem_rdata[14] ,
+    \u_riscv_top.core0_imem_rdata[13] ,
+    \u_riscv_top.core0_imem_rdata[12] ,
+    \u_riscv_top.core0_imem_rdata[11] ,
+    \u_riscv_top.core0_imem_rdata[10] ,
+    \u_riscv_top.core0_imem_rdata[9] ,
+    \u_riscv_top.core0_imem_rdata[8] ,
+    \u_riscv_top.core0_imem_rdata[7] ,
+    \u_riscv_top.core0_imem_rdata[6] ,
+    \u_riscv_top.core0_imem_rdata[5] ,
+    \u_riscv_top.core0_imem_rdata[4] ,
+    \u_riscv_top.core0_imem_rdata[3] ,
+    \u_riscv_top.core0_imem_rdata[2] ,
+    \u_riscv_top.core0_imem_rdata[1] ,
+    \u_riscv_top.core0_imem_rdata[0] }),
+    .core0_imem_resp({\u_riscv_top.core0_imem_resp[1] ,
+    \u_riscv_top.core0_imem_resp[0] }),
+    .core0_uid({\u_riscv_top.core0_uid[1] ,
+    \u_riscv_top.core0_uid[0] }),
+    .core1_debug({\u_riscv_top.core1_debug[48] ,
+    \u_riscv_top.core1_debug[47] ,
+    \u_riscv_top.core1_debug[46] ,
+    \u_riscv_top.core1_debug[45] ,
+    \u_riscv_top.core1_debug[44] ,
+    \u_riscv_top.core1_debug[43] ,
+    \u_riscv_top.core1_debug[42] ,
+    \u_riscv_top.core1_debug[41] ,
+    \u_riscv_top.core1_debug[40] ,
+    \u_riscv_top.core1_debug[39] ,
+    \u_riscv_top.core1_debug[38] ,
+    \u_riscv_top.core1_debug[37] ,
+    \u_riscv_top.core1_debug[36] ,
+    \u_riscv_top.core1_debug[35] ,
+    \u_riscv_top.core1_debug[34] ,
+    \u_riscv_top.core1_debug[33] ,
+    \u_riscv_top.core1_debug[32] ,
+    \u_riscv_top.core1_debug[31] ,
+    \u_riscv_top.core1_debug[30] ,
+    \u_riscv_top.core1_debug[29] ,
+    \u_riscv_top.core1_debug[28] ,
+    \u_riscv_top.core1_debug[27] ,
+    \u_riscv_top.core1_debug[26] ,
+    \u_riscv_top.core1_debug[25] ,
+    \u_riscv_top.core1_debug[24] ,
+    \u_riscv_top.core1_debug[23] ,
+    \u_riscv_top.core1_debug[22] ,
+    \u_riscv_top.core1_debug[21] ,
+    \u_riscv_top.core1_debug[20] ,
+    \u_riscv_top.core1_debug[19] ,
+    \u_riscv_top.core1_debug[18] ,
+    \u_riscv_top.core1_debug[17] ,
+    \u_riscv_top.core1_debug[16] ,
+    \u_riscv_top.core1_debug[15] ,
+    \u_riscv_top.core1_debug[14] ,
+    \u_riscv_top.core1_debug[13] ,
+    \u_riscv_top.core1_debug[12] ,
+    \u_riscv_top.core1_debug[11] ,
+    \u_riscv_top.core1_debug[10] ,
+    \u_riscv_top.core1_debug[9] ,
+    \u_riscv_top.core1_debug[8] ,
+    \u_riscv_top.core1_debug[7] ,
+    \u_riscv_top.core1_debug[6] ,
+    \u_riscv_top.core1_debug[5] ,
+    \u_riscv_top.core1_debug[4] ,
+    \u_riscv_top.core1_debug[3] ,
+    \u_riscv_top.core1_debug[2] ,
+    \u_riscv_top.core1_debug[1] ,
+    \u_riscv_top.core1_debug[0] }),
+    .core1_dmem_addr({\u_riscv_top.core1_dmem_addr[31] ,
+    \u_riscv_top.core1_dmem_addr[30] ,
+    \u_riscv_top.core1_dmem_addr[29] ,
+    \u_riscv_top.core1_dmem_addr[28] ,
+    \u_riscv_top.core1_dmem_addr[27] ,
+    \u_riscv_top.core1_dmem_addr[26] ,
+    \u_riscv_top.core1_dmem_addr[25] ,
+    \u_riscv_top.core1_dmem_addr[24] ,
+    \u_riscv_top.core1_dmem_addr[23] ,
+    \u_riscv_top.core1_dmem_addr[22] ,
+    \u_riscv_top.core1_dmem_addr[21] ,
+    \u_riscv_top.core1_dmem_addr[20] ,
+    \u_riscv_top.core1_dmem_addr[19] ,
+    \u_riscv_top.core1_dmem_addr[18] ,
+    \u_riscv_top.core1_dmem_addr[17] ,
+    \u_riscv_top.core1_dmem_addr[16] ,
+    \u_riscv_top.core1_dmem_addr[15] ,
+    \u_riscv_top.core1_dmem_addr[14] ,
+    \u_riscv_top.core1_dmem_addr[13] ,
+    \u_riscv_top.core1_dmem_addr[12] ,
+    \u_riscv_top.core1_dmem_addr[11] ,
+    \u_riscv_top.core1_dmem_addr[10] ,
+    \u_riscv_top.core1_dmem_addr[9] ,
+    \u_riscv_top.core1_dmem_addr[8] ,
+    \u_riscv_top.core1_dmem_addr[7] ,
+    \u_riscv_top.core1_dmem_addr[6] ,
+    \u_riscv_top.core1_dmem_addr[5] ,
+    \u_riscv_top.core1_dmem_addr[4] ,
+    \u_riscv_top.core1_dmem_addr[3] ,
+    \u_riscv_top.core1_dmem_addr[2] ,
+    \u_riscv_top.core1_dmem_addr[1] ,
+    \u_riscv_top.core1_dmem_addr[0] }),
+    .core1_dmem_rdata({\u_riscv_top.core1_dmem_rdata[31] ,
+    \u_riscv_top.core1_dmem_rdata[30] ,
+    \u_riscv_top.core1_dmem_rdata[29] ,
+    \u_riscv_top.core1_dmem_rdata[28] ,
+    \u_riscv_top.core1_dmem_rdata[27] ,
+    \u_riscv_top.core1_dmem_rdata[26] ,
+    \u_riscv_top.core1_dmem_rdata[25] ,
+    \u_riscv_top.core1_dmem_rdata[24] ,
+    \u_riscv_top.core1_dmem_rdata[23] ,
+    \u_riscv_top.core1_dmem_rdata[22] ,
+    \u_riscv_top.core1_dmem_rdata[21] ,
+    \u_riscv_top.core1_dmem_rdata[20] ,
+    \u_riscv_top.core1_dmem_rdata[19] ,
+    \u_riscv_top.core1_dmem_rdata[18] ,
+    \u_riscv_top.core1_dmem_rdata[17] ,
+    \u_riscv_top.core1_dmem_rdata[16] ,
+    \u_riscv_top.core1_dmem_rdata[15] ,
+    \u_riscv_top.core1_dmem_rdata[14] ,
+    \u_riscv_top.core1_dmem_rdata[13] ,
+    \u_riscv_top.core1_dmem_rdata[12] ,
+    \u_riscv_top.core1_dmem_rdata[11] ,
+    \u_riscv_top.core1_dmem_rdata[10] ,
+    \u_riscv_top.core1_dmem_rdata[9] ,
+    \u_riscv_top.core1_dmem_rdata[8] ,
+    \u_riscv_top.core1_dmem_rdata[7] ,
+    \u_riscv_top.core1_dmem_rdata[6] ,
+    \u_riscv_top.core1_dmem_rdata[5] ,
+    \u_riscv_top.core1_dmem_rdata[4] ,
+    \u_riscv_top.core1_dmem_rdata[3] ,
+    \u_riscv_top.core1_dmem_rdata[2] ,
+    \u_riscv_top.core1_dmem_rdata[1] ,
+    \u_riscv_top.core1_dmem_rdata[0] }),
+    .core1_dmem_resp({\u_riscv_top.core1_dmem_resp[1] ,
+    \u_riscv_top.core1_dmem_resp[0] }),
+    .core1_dmem_wdata({\u_riscv_top.core1_dmem_wdata[31] ,
+    \u_riscv_top.core1_dmem_wdata[30] ,
+    \u_riscv_top.core1_dmem_wdata[29] ,
+    \u_riscv_top.core1_dmem_wdata[28] ,
+    \u_riscv_top.core1_dmem_wdata[27] ,
+    \u_riscv_top.core1_dmem_wdata[26] ,
+    \u_riscv_top.core1_dmem_wdata[25] ,
+    \u_riscv_top.core1_dmem_wdata[24] ,
+    \u_riscv_top.core1_dmem_wdata[23] ,
+    \u_riscv_top.core1_dmem_wdata[22] ,
+    \u_riscv_top.core1_dmem_wdata[21] ,
+    \u_riscv_top.core1_dmem_wdata[20] ,
+    \u_riscv_top.core1_dmem_wdata[19] ,
+    \u_riscv_top.core1_dmem_wdata[18] ,
+    \u_riscv_top.core1_dmem_wdata[17] ,
+    \u_riscv_top.core1_dmem_wdata[16] ,
+    \u_riscv_top.core1_dmem_wdata[15] ,
+    \u_riscv_top.core1_dmem_wdata[14] ,
+    \u_riscv_top.core1_dmem_wdata[13] ,
+    \u_riscv_top.core1_dmem_wdata[12] ,
+    \u_riscv_top.core1_dmem_wdata[11] ,
+    \u_riscv_top.core1_dmem_wdata[10] ,
+    \u_riscv_top.core1_dmem_wdata[9] ,
+    \u_riscv_top.core1_dmem_wdata[8] ,
+    \u_riscv_top.core1_dmem_wdata[7] ,
+    \u_riscv_top.core1_dmem_wdata[6] ,
+    \u_riscv_top.core1_dmem_wdata[5] ,
+    \u_riscv_top.core1_dmem_wdata[4] ,
+    \u_riscv_top.core1_dmem_wdata[3] ,
+    \u_riscv_top.core1_dmem_wdata[2] ,
+    \u_riscv_top.core1_dmem_wdata[1] ,
+    \u_riscv_top.core1_dmem_wdata[0] }),
+    .core1_dmem_width({\u_riscv_top.core1_dmem_width[1] ,
+    \u_riscv_top.core1_dmem_width[0] }),
+    .core1_imem_addr({\u_riscv_top.core1_imem_addr[31] ,
+    \u_riscv_top.core1_imem_addr[30] ,
+    \u_riscv_top.core1_imem_addr[29] ,
+    \u_riscv_top.core1_imem_addr[28] ,
+    \u_riscv_top.core1_imem_addr[27] ,
+    \u_riscv_top.core1_imem_addr[26] ,
+    \u_riscv_top.core1_imem_addr[25] ,
+    \u_riscv_top.core1_imem_addr[24] ,
+    \u_riscv_top.core1_imem_addr[23] ,
+    \u_riscv_top.core1_imem_addr[22] ,
+    \u_riscv_top.core1_imem_addr[21] ,
+    \u_riscv_top.core1_imem_addr[20] ,
+    \u_riscv_top.core1_imem_addr[19] ,
+    \u_riscv_top.core1_imem_addr[18] ,
+    \u_riscv_top.core1_imem_addr[17] ,
+    \u_riscv_top.core1_imem_addr[16] ,
+    \u_riscv_top.core1_imem_addr[15] ,
+    \u_riscv_top.core1_imem_addr[14] ,
+    \u_riscv_top.core1_imem_addr[13] ,
+    \u_riscv_top.core1_imem_addr[12] ,
+    \u_riscv_top.core1_imem_addr[11] ,
+    \u_riscv_top.core1_imem_addr[10] ,
+    \u_riscv_top.core1_imem_addr[9] ,
+    \u_riscv_top.core1_imem_addr[8] ,
+    \u_riscv_top.core1_imem_addr[7] ,
+    \u_riscv_top.core1_imem_addr[6] ,
+    \u_riscv_top.core1_imem_addr[5] ,
+    \u_riscv_top.core1_imem_addr[4] ,
+    \u_riscv_top.core1_imem_addr[3] ,
+    \u_riscv_top.core1_imem_addr[2] ,
+    \u_riscv_top.core1_imem_addr[1] ,
+    \u_riscv_top.core1_imem_addr[0] }),
+    .core1_imem_bl({\u_riscv_top.core1_imem_bl[2] ,
+    \u_riscv_top.core1_imem_bl[1] ,
+    \u_riscv_top.core1_imem_bl[0] }),
+    .core1_imem_rdata({\u_riscv_top.core1_imem_rdata[31] ,
+    \u_riscv_top.core1_imem_rdata[30] ,
+    \u_riscv_top.core1_imem_rdata[29] ,
+    \u_riscv_top.core1_imem_rdata[28] ,
+    \u_riscv_top.core1_imem_rdata[27] ,
+    \u_riscv_top.core1_imem_rdata[26] ,
+    \u_riscv_top.core1_imem_rdata[25] ,
+    \u_riscv_top.core1_imem_rdata[24] ,
+    \u_riscv_top.core1_imem_rdata[23] ,
+    \u_riscv_top.core1_imem_rdata[22] ,
+    \u_riscv_top.core1_imem_rdata[21] ,
+    \u_riscv_top.core1_imem_rdata[20] ,
+    \u_riscv_top.core1_imem_rdata[19] ,
+    \u_riscv_top.core1_imem_rdata[18] ,
+    \u_riscv_top.core1_imem_rdata[17] ,
+    \u_riscv_top.core1_imem_rdata[16] ,
+    \u_riscv_top.core1_imem_rdata[15] ,
+    \u_riscv_top.core1_imem_rdata[14] ,
+    \u_riscv_top.core1_imem_rdata[13] ,
+    \u_riscv_top.core1_imem_rdata[12] ,
+    \u_riscv_top.core1_imem_rdata[11] ,
+    \u_riscv_top.core1_imem_rdata[10] ,
+    \u_riscv_top.core1_imem_rdata[9] ,
+    \u_riscv_top.core1_imem_rdata[8] ,
+    \u_riscv_top.core1_imem_rdata[7] ,
+    \u_riscv_top.core1_imem_rdata[6] ,
+    \u_riscv_top.core1_imem_rdata[5] ,
+    \u_riscv_top.core1_imem_rdata[4] ,
+    \u_riscv_top.core1_imem_rdata[3] ,
+    \u_riscv_top.core1_imem_rdata[2] ,
+    \u_riscv_top.core1_imem_rdata[1] ,
+    \u_riscv_top.core1_imem_rdata[0] }),
+    .core1_imem_resp({\u_riscv_top.core1_imem_resp[1] ,
+    \u_riscv_top.core1_imem_resp[0] }),
+    .core1_uid({\u_riscv_top.core1_uid[1] ,
+    \u_riscv_top.core1_uid[0] }),
+    .core2_uid({\u_riscv_top.core2_uid[1] ,
+    \u_riscv_top.core2_uid[0] }),
+    .core3_uid({\u_riscv_top.core3_uid[1] ,
+    \u_riscv_top.core3_uid[0] }),
+    .core_debug_sel({\u_riscv_top.core_debug_sel[1] ,
+    \u_riscv_top.core_debug_sel[0] }),
+    .cpu_core_rst_n({\u_riscv_top.cpu_core_rst_n[1] ,
+    \u_riscv_top.cpu_core_rst_n[0] }),
+    .cpu_core_rst_n_sync({\u_riscv_top.cpu_core_rst_n_sync[1] ,
+    \u_riscv_top.cpu_core_rst_n_sync[0] }),
+    .dcache_mem_addr0({\u_riscv_top.dcache_mem_addr0[8] ,
+    \u_riscv_top.dcache_mem_addr0[7] ,
+    \u_riscv_top.dcache_mem_addr0[6] ,
+    \u_riscv_top.dcache_mem_addr0[5] ,
+    \u_riscv_top.dcache_mem_addr0[4] ,
+    \u_riscv_top.dcache_mem_addr0[3] ,
+    \u_riscv_top.dcache_mem_addr0[2] ,
+    \u_riscv_top.dcache_mem_addr0[1] ,
+    \u_riscv_top.dcache_mem_addr0[0] }),
+    .dcache_mem_addr1({\u_riscv_top.dcache_mem_addr1[8] ,
+    \u_riscv_top.dcache_mem_addr1[7] ,
+    \u_riscv_top.dcache_mem_addr1[6] ,
+    \u_riscv_top.dcache_mem_addr1[5] ,
+    \u_riscv_top.dcache_mem_addr1[4] ,
+    \u_riscv_top.dcache_mem_addr1[3] ,
+    \u_riscv_top.dcache_mem_addr1[2] ,
+    \u_riscv_top.dcache_mem_addr1[1] ,
+    \u_riscv_top.dcache_mem_addr1[0] }),
+    .dcache_mem_din0({\u_riscv_top.dcache_mem_din0[31] ,
+    \u_riscv_top.dcache_mem_din0[30] ,
+    \u_riscv_top.dcache_mem_din0[29] ,
+    \u_riscv_top.dcache_mem_din0[28] ,
+    \u_riscv_top.dcache_mem_din0[27] ,
+    \u_riscv_top.dcache_mem_din0[26] ,
+    \u_riscv_top.dcache_mem_din0[25] ,
+    \u_riscv_top.dcache_mem_din0[24] ,
+    \u_riscv_top.dcache_mem_din0[23] ,
+    \u_riscv_top.dcache_mem_din0[22] ,
+    \u_riscv_top.dcache_mem_din0[21] ,
+    \u_riscv_top.dcache_mem_din0[20] ,
+    \u_riscv_top.dcache_mem_din0[19] ,
+    \u_riscv_top.dcache_mem_din0[18] ,
+    \u_riscv_top.dcache_mem_din0[17] ,
+    \u_riscv_top.dcache_mem_din0[16] ,
+    \u_riscv_top.dcache_mem_din0[15] ,
+    \u_riscv_top.dcache_mem_din0[14] ,
+    \u_riscv_top.dcache_mem_din0[13] ,
+    \u_riscv_top.dcache_mem_din0[12] ,
+    \u_riscv_top.dcache_mem_din0[11] ,
+    \u_riscv_top.dcache_mem_din0[10] ,
+    \u_riscv_top.dcache_mem_din0[9] ,
+    \u_riscv_top.dcache_mem_din0[8] ,
+    \u_riscv_top.dcache_mem_din0[7] ,
+    \u_riscv_top.dcache_mem_din0[6] ,
+    \u_riscv_top.dcache_mem_din0[5] ,
+    \u_riscv_top.dcache_mem_din0[4] ,
+    \u_riscv_top.dcache_mem_din0[3] ,
+    \u_riscv_top.dcache_mem_din0[2] ,
+    \u_riscv_top.dcache_mem_din0[1] ,
+    \u_riscv_top.dcache_mem_din0[0] }),
+    .dcache_mem_dout0({\u_riscv_top.dcache_mem_dout0[31] ,
+    \u_riscv_top.dcache_mem_dout0[30] ,
+    \u_riscv_top.dcache_mem_dout0[29] ,
+    \u_riscv_top.dcache_mem_dout0[28] ,
+    \u_riscv_top.dcache_mem_dout0[27] ,
+    \u_riscv_top.dcache_mem_dout0[26] ,
+    \u_riscv_top.dcache_mem_dout0[25] ,
+    \u_riscv_top.dcache_mem_dout0[24] ,
+    \u_riscv_top.dcache_mem_dout0[23] ,
+    \u_riscv_top.dcache_mem_dout0[22] ,
+    \u_riscv_top.dcache_mem_dout0[21] ,
+    \u_riscv_top.dcache_mem_dout0[20] ,
+    \u_riscv_top.dcache_mem_dout0[19] ,
+    \u_riscv_top.dcache_mem_dout0[18] ,
+    \u_riscv_top.dcache_mem_dout0[17] ,
+    \u_riscv_top.dcache_mem_dout0[16] ,
+    \u_riscv_top.dcache_mem_dout0[15] ,
+    \u_riscv_top.dcache_mem_dout0[14] ,
+    \u_riscv_top.dcache_mem_dout0[13] ,
+    \u_riscv_top.dcache_mem_dout0[12] ,
+    \u_riscv_top.dcache_mem_dout0[11] ,
+    \u_riscv_top.dcache_mem_dout0[10] ,
+    \u_riscv_top.dcache_mem_dout0[9] ,
+    \u_riscv_top.dcache_mem_dout0[8] ,
+    \u_riscv_top.dcache_mem_dout0[7] ,
+    \u_riscv_top.dcache_mem_dout0[6] ,
+    \u_riscv_top.dcache_mem_dout0[5] ,
+    \u_riscv_top.dcache_mem_dout0[4] ,
+    \u_riscv_top.dcache_mem_dout0[3] ,
+    \u_riscv_top.dcache_mem_dout0[2] ,
+    \u_riscv_top.dcache_mem_dout0[1] ,
+    \u_riscv_top.dcache_mem_dout0[0] }),
+    .dcache_mem_dout1({\u_riscv_top.dcache_mem_dout1[31] ,
+    \u_riscv_top.dcache_mem_dout1[30] ,
+    \u_riscv_top.dcache_mem_dout1[29] ,
+    \u_riscv_top.dcache_mem_dout1[28] ,
+    \u_riscv_top.dcache_mem_dout1[27] ,
+    \u_riscv_top.dcache_mem_dout1[26] ,
+    \u_riscv_top.dcache_mem_dout1[25] ,
+    \u_riscv_top.dcache_mem_dout1[24] ,
+    \u_riscv_top.dcache_mem_dout1[23] ,
+    \u_riscv_top.dcache_mem_dout1[22] ,
+    \u_riscv_top.dcache_mem_dout1[21] ,
+    \u_riscv_top.dcache_mem_dout1[20] ,
+    \u_riscv_top.dcache_mem_dout1[19] ,
+    \u_riscv_top.dcache_mem_dout1[18] ,
+    \u_riscv_top.dcache_mem_dout1[17] ,
+    \u_riscv_top.dcache_mem_dout1[16] ,
+    \u_riscv_top.dcache_mem_dout1[15] ,
+    \u_riscv_top.dcache_mem_dout1[14] ,
+    \u_riscv_top.dcache_mem_dout1[13] ,
+    \u_riscv_top.dcache_mem_dout1[12] ,
+    \u_riscv_top.dcache_mem_dout1[11] ,
+    \u_riscv_top.dcache_mem_dout1[10] ,
+    \u_riscv_top.dcache_mem_dout1[9] ,
+    \u_riscv_top.dcache_mem_dout1[8] ,
+    \u_riscv_top.dcache_mem_dout1[7] ,
+    \u_riscv_top.dcache_mem_dout1[6] ,
+    \u_riscv_top.dcache_mem_dout1[5] ,
+    \u_riscv_top.dcache_mem_dout1[4] ,
+    \u_riscv_top.dcache_mem_dout1[3] ,
+    \u_riscv_top.dcache_mem_dout1[2] ,
+    \u_riscv_top.dcache_mem_dout1[1] ,
+    \u_riscv_top.dcache_mem_dout1[0] }),
+    .dcache_mem_wmask0({\u_riscv_top.dcache_mem_wmask0[3] ,
+    \u_riscv_top.dcache_mem_wmask0[2] ,
+    \u_riscv_top.dcache_mem_wmask0[1] ,
+    \u_riscv_top.dcache_mem_wmask0[0] }),
+    .icache_mem_addr0({\u_riscv_top.icache_mem_addr0[8] ,
+    \u_riscv_top.icache_mem_addr0[7] ,
+    \u_riscv_top.icache_mem_addr0[6] ,
+    \u_riscv_top.icache_mem_addr0[5] ,
+    \u_riscv_top.icache_mem_addr0[4] ,
+    \u_riscv_top.icache_mem_addr0[3] ,
+    \u_riscv_top.icache_mem_addr0[2] ,
+    \u_riscv_top.icache_mem_addr0[1] ,
+    \u_riscv_top.icache_mem_addr0[0] }),
+    .icache_mem_addr1({\u_riscv_top.icache_mem_addr1[8] ,
+    \u_riscv_top.icache_mem_addr1[7] ,
+    \u_riscv_top.icache_mem_addr1[6] ,
+    \u_riscv_top.icache_mem_addr1[5] ,
+    \u_riscv_top.icache_mem_addr1[4] ,
+    \u_riscv_top.icache_mem_addr1[3] ,
+    \u_riscv_top.icache_mem_addr1[2] ,
+    \u_riscv_top.icache_mem_addr1[1] ,
+    \u_riscv_top.icache_mem_addr1[0] }),
+    .icache_mem_din0({\u_riscv_top.icache_mem_din0[31] ,
+    \u_riscv_top.icache_mem_din0[30] ,
+    \u_riscv_top.icache_mem_din0[29] ,
+    \u_riscv_top.icache_mem_din0[28] ,
+    \u_riscv_top.icache_mem_din0[27] ,
+    \u_riscv_top.icache_mem_din0[26] ,
+    \u_riscv_top.icache_mem_din0[25] ,
+    \u_riscv_top.icache_mem_din0[24] ,
+    \u_riscv_top.icache_mem_din0[23] ,
+    \u_riscv_top.icache_mem_din0[22] ,
+    \u_riscv_top.icache_mem_din0[21] ,
+    \u_riscv_top.icache_mem_din0[20] ,
+    \u_riscv_top.icache_mem_din0[19] ,
+    \u_riscv_top.icache_mem_din0[18] ,
+    \u_riscv_top.icache_mem_din0[17] ,
+    \u_riscv_top.icache_mem_din0[16] ,
+    \u_riscv_top.icache_mem_din0[15] ,
+    \u_riscv_top.icache_mem_din0[14] ,
+    \u_riscv_top.icache_mem_din0[13] ,
+    \u_riscv_top.icache_mem_din0[12] ,
+    \u_riscv_top.icache_mem_din0[11] ,
+    \u_riscv_top.icache_mem_din0[10] ,
+    \u_riscv_top.icache_mem_din0[9] ,
+    \u_riscv_top.icache_mem_din0[8] ,
+    \u_riscv_top.icache_mem_din0[7] ,
+    \u_riscv_top.icache_mem_din0[6] ,
+    \u_riscv_top.icache_mem_din0[5] ,
+    \u_riscv_top.icache_mem_din0[4] ,
+    \u_riscv_top.icache_mem_din0[3] ,
+    \u_riscv_top.icache_mem_din0[2] ,
+    \u_riscv_top.icache_mem_din0[1] ,
+    \u_riscv_top.icache_mem_din0[0] }),
+    .icache_mem_dout1({\u_riscv_top.icache_mem_dout1[31] ,
+    \u_riscv_top.icache_mem_dout1[30] ,
+    \u_riscv_top.icache_mem_dout1[29] ,
+    \u_riscv_top.icache_mem_dout1[28] ,
+    \u_riscv_top.icache_mem_dout1[27] ,
+    \u_riscv_top.icache_mem_dout1[26] ,
+    \u_riscv_top.icache_mem_dout1[25] ,
+    \u_riscv_top.icache_mem_dout1[24] ,
+    \u_riscv_top.icache_mem_dout1[23] ,
+    \u_riscv_top.icache_mem_dout1[22] ,
+    \u_riscv_top.icache_mem_dout1[21] ,
+    \u_riscv_top.icache_mem_dout1[20] ,
+    \u_riscv_top.icache_mem_dout1[19] ,
+    \u_riscv_top.icache_mem_dout1[18] ,
+    \u_riscv_top.icache_mem_dout1[17] ,
+    \u_riscv_top.icache_mem_dout1[16] ,
+    \u_riscv_top.icache_mem_dout1[15] ,
+    \u_riscv_top.icache_mem_dout1[14] ,
+    \u_riscv_top.icache_mem_dout1[13] ,
+    \u_riscv_top.icache_mem_dout1[12] ,
+    \u_riscv_top.icache_mem_dout1[11] ,
+    \u_riscv_top.icache_mem_dout1[10] ,
+    \u_riscv_top.icache_mem_dout1[9] ,
+    \u_riscv_top.icache_mem_dout1[8] ,
+    \u_riscv_top.icache_mem_dout1[7] ,
+    \u_riscv_top.icache_mem_dout1[6] ,
+    \u_riscv_top.icache_mem_dout1[5] ,
+    \u_riscv_top.icache_mem_dout1[4] ,
+    \u_riscv_top.icache_mem_dout1[3] ,
+    \u_riscv_top.icache_mem_dout1[2] ,
+    \u_riscv_top.icache_mem_dout1[1] ,
+    \u_riscv_top.icache_mem_dout1[0] }),
+    .icache_mem_wmask0({\u_riscv_top.icache_mem_wmask0[3] ,
+    \u_riscv_top.icache_mem_wmask0[2] ,
+    \u_riscv_top.icache_mem_wmask0[1] ,
+    \u_riscv_top.icache_mem_wmask0[0] }),
+    .riscv_debug({la_data_out[63],
+    la_data_out[62],
+    la_data_out[61],
+    la_data_out[60],
+    la_data_out[59],
+    la_data_out[58],
+    la_data_out[57],
+    la_data_out[56],
+    la_data_out[55],
+    la_data_out[54],
+    la_data_out[53],
+    la_data_out[52],
+    la_data_out[51],
+    la_data_out[50],
+    la_data_out[49],
+    la_data_out[48],
+    la_data_out[47],
+    la_data_out[46],
+    la_data_out[45],
+    la_data_out[44],
+    la_data_out[43],
+    la_data_out[42],
+    la_data_out[41],
+    la_data_out[40],
+    la_data_out[39],
+    la_data_out[38],
+    la_data_out[37],
+    la_data_out[36],
+    la_data_out[35],
+    la_data_out[34],
+    la_data_out[33],
+    la_data_out[32],
+    la_data_out[31],
+    la_data_out[30],
+    la_data_out[29],
+    la_data_out[28],
+    la_data_out[27],
+    la_data_out[26],
+    la_data_out[25],
+    la_data_out[24],
+    la_data_out[23],
+    la_data_out[22],
+    la_data_out[21],
+    la_data_out[20],
+    la_data_out[19],
+    la_data_out[18],
+    la_data_out[17],
+    la_data_out[16],
+    la_data_out[15],
+    la_data_out[14],
+    la_data_out[13],
+    la_data_out[12],
+    la_data_out[11],
+    la_data_out[10],
+    la_data_out[9],
+    la_data_out[8],
+    la_data_out[7],
+    la_data_out[6],
+    la_data_out[5],
+    la_data_out[4],
+    la_data_out[3],
+    la_data_out[2],
+    la_data_out[1],
+    la_data_out[0]}),
+    .sram0_addr0({\u_riscv_top.sram0_addr0[8] ,
+    \u_riscv_top.sram0_addr0[7] ,
+    \u_riscv_top.sram0_addr0[6] ,
+    \u_riscv_top.sram0_addr0[5] ,
+    \u_riscv_top.sram0_addr0[4] ,
+    \u_riscv_top.sram0_addr0[3] ,
+    \u_riscv_top.sram0_addr0[2] ,
+    \u_riscv_top.sram0_addr0[1] ,
+    \u_riscv_top.sram0_addr0[0] }),
+    .sram0_addr1({\u_riscv_top.sram0_addr1[8] ,
+    \u_riscv_top.sram0_addr1[7] ,
+    \u_riscv_top.sram0_addr1[6] ,
+    \u_riscv_top.sram0_addr1[5] ,
+    \u_riscv_top.sram0_addr1[4] ,
+    \u_riscv_top.sram0_addr1[3] ,
+    \u_riscv_top.sram0_addr1[2] ,
+    \u_riscv_top.sram0_addr1[1] ,
+    \u_riscv_top.sram0_addr1[0] }),
+    .sram0_din0({\u_riscv_top.sram0_din0[31] ,
+    \u_riscv_top.sram0_din0[30] ,
+    \u_riscv_top.sram0_din0[29] ,
+    \u_riscv_top.sram0_din0[28] ,
+    \u_riscv_top.sram0_din0[27] ,
+    \u_riscv_top.sram0_din0[26] ,
+    \u_riscv_top.sram0_din0[25] ,
+    \u_riscv_top.sram0_din0[24] ,
+    \u_riscv_top.sram0_din0[23] ,
+    \u_riscv_top.sram0_din0[22] ,
+    \u_riscv_top.sram0_din0[21] ,
+    \u_riscv_top.sram0_din0[20] ,
+    \u_riscv_top.sram0_din0[19] ,
+    \u_riscv_top.sram0_din0[18] ,
+    \u_riscv_top.sram0_din0[17] ,
+    \u_riscv_top.sram0_din0[16] ,
+    \u_riscv_top.sram0_din0[15] ,
+    \u_riscv_top.sram0_din0[14] ,
+    \u_riscv_top.sram0_din0[13] ,
+    \u_riscv_top.sram0_din0[12] ,
+    \u_riscv_top.sram0_din0[11] ,
+    \u_riscv_top.sram0_din0[10] ,
+    \u_riscv_top.sram0_din0[9] ,
+    \u_riscv_top.sram0_din0[8] ,
+    \u_riscv_top.sram0_din0[7] ,
+    \u_riscv_top.sram0_din0[6] ,
+    \u_riscv_top.sram0_din0[5] ,
+    \u_riscv_top.sram0_din0[4] ,
+    \u_riscv_top.sram0_din0[3] ,
+    \u_riscv_top.sram0_din0[2] ,
+    \u_riscv_top.sram0_din0[1] ,
+    \u_riscv_top.sram0_din0[0] }),
+    .sram0_dout0({\u_riscv_top.sram0_dout0[31] ,
+    \u_riscv_top.sram0_dout0[30] ,
+    \u_riscv_top.sram0_dout0[29] ,
+    \u_riscv_top.sram0_dout0[28] ,
+    \u_riscv_top.sram0_dout0[27] ,
+    \u_riscv_top.sram0_dout0[26] ,
+    \u_riscv_top.sram0_dout0[25] ,
+    \u_riscv_top.sram0_dout0[24] ,
+    \u_riscv_top.sram0_dout0[23] ,
+    \u_riscv_top.sram0_dout0[22] ,
+    \u_riscv_top.sram0_dout0[21] ,
+    \u_riscv_top.sram0_dout0[20] ,
+    \u_riscv_top.sram0_dout0[19] ,
+    \u_riscv_top.sram0_dout0[18] ,
+    \u_riscv_top.sram0_dout0[17] ,
+    \u_riscv_top.sram0_dout0[16] ,
+    \u_riscv_top.sram0_dout0[15] ,
+    \u_riscv_top.sram0_dout0[14] ,
+    \u_riscv_top.sram0_dout0[13] ,
+    \u_riscv_top.sram0_dout0[12] ,
+    \u_riscv_top.sram0_dout0[11] ,
+    \u_riscv_top.sram0_dout0[10] ,
+    \u_riscv_top.sram0_dout0[9] ,
+    \u_riscv_top.sram0_dout0[8] ,
+    \u_riscv_top.sram0_dout0[7] ,
+    \u_riscv_top.sram0_dout0[6] ,
+    \u_riscv_top.sram0_dout0[5] ,
+    \u_riscv_top.sram0_dout0[4] ,
+    \u_riscv_top.sram0_dout0[3] ,
+    \u_riscv_top.sram0_dout0[2] ,
+    \u_riscv_top.sram0_dout0[1] ,
+    \u_riscv_top.sram0_dout0[0] }),
+    .sram0_dout1({\u_riscv_top.sram0_dout1[31] ,
+    \u_riscv_top.sram0_dout1[30] ,
+    \u_riscv_top.sram0_dout1[29] ,
+    \u_riscv_top.sram0_dout1[28] ,
+    \u_riscv_top.sram0_dout1[27] ,
+    \u_riscv_top.sram0_dout1[26] ,
+    \u_riscv_top.sram0_dout1[25] ,
+    \u_riscv_top.sram0_dout1[24] ,
+    \u_riscv_top.sram0_dout1[23] ,
+    \u_riscv_top.sram0_dout1[22] ,
+    \u_riscv_top.sram0_dout1[21] ,
+    \u_riscv_top.sram0_dout1[20] ,
+    \u_riscv_top.sram0_dout1[19] ,
+    \u_riscv_top.sram0_dout1[18] ,
+    \u_riscv_top.sram0_dout1[17] ,
+    \u_riscv_top.sram0_dout1[16] ,
+    \u_riscv_top.sram0_dout1[15] ,
+    \u_riscv_top.sram0_dout1[14] ,
+    \u_riscv_top.sram0_dout1[13] ,
+    \u_riscv_top.sram0_dout1[12] ,
+    \u_riscv_top.sram0_dout1[11] ,
+    \u_riscv_top.sram0_dout1[10] ,
+    \u_riscv_top.sram0_dout1[9] ,
+    \u_riscv_top.sram0_dout1[8] ,
+    \u_riscv_top.sram0_dout1[7] ,
+    \u_riscv_top.sram0_dout1[6] ,
+    \u_riscv_top.sram0_dout1[5] ,
+    \u_riscv_top.sram0_dout1[4] ,
+    \u_riscv_top.sram0_dout1[3] ,
+    \u_riscv_top.sram0_dout1[2] ,
+    \u_riscv_top.sram0_dout1[1] ,
+    \u_riscv_top.sram0_dout1[0] }),
+    .sram0_wmask0({\u_riscv_top.sram0_wmask0[3] ,
+    \u_riscv_top.sram0_wmask0[2] ,
+    \u_riscv_top.sram0_wmask0[1] ,
+    \u_riscv_top.sram0_wmask0[0] }),
+    .timer_val({\u_riscv_top.timer_val[63] ,
+    \u_riscv_top.timer_val[62] ,
+    \u_riscv_top.timer_val[61] ,
+    \u_riscv_top.timer_val[60] ,
+    \u_riscv_top.timer_val[59] ,
+    \u_riscv_top.timer_val[58] ,
+    \u_riscv_top.timer_val[57] ,
+    \u_riscv_top.timer_val[56] ,
+    \u_riscv_top.timer_val[55] ,
+    \u_riscv_top.timer_val[54] ,
+    \u_riscv_top.timer_val[53] ,
+    \u_riscv_top.timer_val[52] ,
+    \u_riscv_top.timer_val[51] ,
+    \u_riscv_top.timer_val[50] ,
+    \u_riscv_top.timer_val[49] ,
+    \u_riscv_top.timer_val[48] ,
+    \u_riscv_top.timer_val[47] ,
+    \u_riscv_top.timer_val[46] ,
+    \u_riscv_top.timer_val[45] ,
+    \u_riscv_top.timer_val[44] ,
+    \u_riscv_top.timer_val[43] ,
+    \u_riscv_top.timer_val[42] ,
+    \u_riscv_top.timer_val[41] ,
+    \u_riscv_top.timer_val[40] ,
+    \u_riscv_top.timer_val[39] ,
+    \u_riscv_top.timer_val[38] ,
+    \u_riscv_top.timer_val[37] ,
+    \u_riscv_top.timer_val[36] ,
+    \u_riscv_top.timer_val[35] ,
+    \u_riscv_top.timer_val[34] ,
+    \u_riscv_top.timer_val[33] ,
+    \u_riscv_top.timer_val[32] ,
+    \u_riscv_top.timer_val[31] ,
+    \u_riscv_top.timer_val[30] ,
+    \u_riscv_top.timer_val[29] ,
+    \u_riscv_top.timer_val[28] ,
+    \u_riscv_top.timer_val[27] ,
+    \u_riscv_top.timer_val[26] ,
+    \u_riscv_top.timer_val[25] ,
+    \u_riscv_top.timer_val[24] ,
+    \u_riscv_top.timer_val[23] ,
+    \u_riscv_top.timer_val[22] ,
+    \u_riscv_top.timer_val[21] ,
+    \u_riscv_top.timer_val[20] ,
+    \u_riscv_top.timer_val[19] ,
+    \u_riscv_top.timer_val[18] ,
+    \u_riscv_top.timer_val[17] ,
+    \u_riscv_top.timer_val[16] ,
+    \u_riscv_top.timer_val[15] ,
+    \u_riscv_top.timer_val[14] ,
+    \u_riscv_top.timer_val[13] ,
+    \u_riscv_top.timer_val[12] ,
+    \u_riscv_top.timer_val[11] ,
+    \u_riscv_top.timer_val[10] ,
+    \u_riscv_top.timer_val[9] ,
+    \u_riscv_top.timer_val[8] ,
+    \u_riscv_top.timer_val[7] ,
+    \u_riscv_top.timer_val[6] ,
+    \u_riscv_top.timer_val[5] ,
+    \u_riscv_top.timer_val[4] ,
+    \u_riscv_top.timer_val[3] ,
+    \u_riscv_top.timer_val[2] ,
+    \u_riscv_top.timer_val[1] ,
+    \u_riscv_top.timer_val[0] }),
+    .wb_dcache_adr_o({\u_riscv_top.wb_dcache_adr_o[31] ,
+    \u_riscv_top.wb_dcache_adr_o[30] ,
+    \u_riscv_top.wb_dcache_adr_o[29] ,
+    \u_riscv_top.wb_dcache_adr_o[28] ,
+    \u_riscv_top.wb_dcache_adr_o[27] ,
+    \u_riscv_top.wb_dcache_adr_o[26] ,
+    \u_riscv_top.wb_dcache_adr_o[25] ,
+    \u_riscv_top.wb_dcache_adr_o[24] ,
+    \u_riscv_top.wb_dcache_adr_o[23] ,
+    \u_riscv_top.wb_dcache_adr_o[22] ,
+    \u_riscv_top.wb_dcache_adr_o[21] ,
+    \u_riscv_top.wb_dcache_adr_o[20] ,
+    \u_riscv_top.wb_dcache_adr_o[19] ,
+    \u_riscv_top.wb_dcache_adr_o[18] ,
+    \u_riscv_top.wb_dcache_adr_o[17] ,
+    \u_riscv_top.wb_dcache_adr_o[16] ,
+    \u_riscv_top.wb_dcache_adr_o[15] ,
+    \u_riscv_top.wb_dcache_adr_o[14] ,
+    \u_riscv_top.wb_dcache_adr_o[13] ,
+    \u_riscv_top.wb_dcache_adr_o[12] ,
+    \u_riscv_top.wb_dcache_adr_o[11] ,
+    \u_riscv_top.wb_dcache_adr_o[10] ,
+    \u_riscv_top.wb_dcache_adr_o[9] ,
+    \u_riscv_top.wb_dcache_adr_o[8] ,
+    \u_riscv_top.wb_dcache_adr_o[7] ,
+    \u_riscv_top.wb_dcache_adr_o[6] ,
+    \u_riscv_top.wb_dcache_adr_o[5] ,
+    \u_riscv_top.wb_dcache_adr_o[4] ,
+    \u_riscv_top.wb_dcache_adr_o[3] ,
+    \u_riscv_top.wb_dcache_adr_o[2] ,
+    \u_riscv_top.wb_dcache_adr_o[1] ,
+    \u_riscv_top.wb_dcache_adr_o[0] }),
+    .wb_dcache_bl_o({\u_riscv_top.wb_dcache_bl_o[9] ,
+    \u_riscv_top.wb_dcache_bl_o[8] ,
+    \u_riscv_top.wb_dcache_bl_o[7] ,
+    \u_riscv_top.wb_dcache_bl_o[6] ,
+    \u_riscv_top.wb_dcache_bl_o[5] ,
+    \u_riscv_top.wb_dcache_bl_o[4] ,
+    \u_riscv_top.wb_dcache_bl_o[3] ,
+    \u_riscv_top.wb_dcache_bl_o[2] ,
+    \u_riscv_top.wb_dcache_bl_o[1] ,
+    \u_riscv_top.wb_dcache_bl_o[0] }),
+    .wb_dcache_dat_i({\u_riscv_top.wb_dcache_dat_i[31] ,
+    \u_riscv_top.wb_dcache_dat_i[30] ,
+    \u_riscv_top.wb_dcache_dat_i[29] ,
+    \u_riscv_top.wb_dcache_dat_i[28] ,
+    \u_riscv_top.wb_dcache_dat_i[27] ,
+    \u_riscv_top.wb_dcache_dat_i[26] ,
+    \u_riscv_top.wb_dcache_dat_i[25] ,
+    \u_riscv_top.wb_dcache_dat_i[24] ,
+    \u_riscv_top.wb_dcache_dat_i[23] ,
+    \u_riscv_top.wb_dcache_dat_i[22] ,
+    \u_riscv_top.wb_dcache_dat_i[21] ,
+    \u_riscv_top.wb_dcache_dat_i[20] ,
+    \u_riscv_top.wb_dcache_dat_i[19] ,
+    \u_riscv_top.wb_dcache_dat_i[18] ,
+    \u_riscv_top.wb_dcache_dat_i[17] ,
+    \u_riscv_top.wb_dcache_dat_i[16] ,
+    \u_riscv_top.wb_dcache_dat_i[15] ,
+    \u_riscv_top.wb_dcache_dat_i[14] ,
+    \u_riscv_top.wb_dcache_dat_i[13] ,
+    \u_riscv_top.wb_dcache_dat_i[12] ,
+    \u_riscv_top.wb_dcache_dat_i[11] ,
+    \u_riscv_top.wb_dcache_dat_i[10] ,
+    \u_riscv_top.wb_dcache_dat_i[9] ,
+    \u_riscv_top.wb_dcache_dat_i[8] ,
+    \u_riscv_top.wb_dcache_dat_i[7] ,
+    \u_riscv_top.wb_dcache_dat_i[6] ,
+    \u_riscv_top.wb_dcache_dat_i[5] ,
+    \u_riscv_top.wb_dcache_dat_i[4] ,
+    \u_riscv_top.wb_dcache_dat_i[3] ,
+    \u_riscv_top.wb_dcache_dat_i[2] ,
+    \u_riscv_top.wb_dcache_dat_i[1] ,
+    \u_riscv_top.wb_dcache_dat_i[0] }),
+    .wb_dcache_dat_o({\u_riscv_top.wb_dcache_dat_o[31] ,
+    \u_riscv_top.wb_dcache_dat_o[30] ,
+    \u_riscv_top.wb_dcache_dat_o[29] ,
+    \u_riscv_top.wb_dcache_dat_o[28] ,
+    \u_riscv_top.wb_dcache_dat_o[27] ,
+    \u_riscv_top.wb_dcache_dat_o[26] ,
+    \u_riscv_top.wb_dcache_dat_o[25] ,
+    \u_riscv_top.wb_dcache_dat_o[24] ,
+    \u_riscv_top.wb_dcache_dat_o[23] ,
+    \u_riscv_top.wb_dcache_dat_o[22] ,
+    \u_riscv_top.wb_dcache_dat_o[21] ,
+    \u_riscv_top.wb_dcache_dat_o[20] ,
+    \u_riscv_top.wb_dcache_dat_o[19] ,
+    \u_riscv_top.wb_dcache_dat_o[18] ,
+    \u_riscv_top.wb_dcache_dat_o[17] ,
+    \u_riscv_top.wb_dcache_dat_o[16] ,
+    \u_riscv_top.wb_dcache_dat_o[15] ,
+    \u_riscv_top.wb_dcache_dat_o[14] ,
+    \u_riscv_top.wb_dcache_dat_o[13] ,
+    \u_riscv_top.wb_dcache_dat_o[12] ,
+    \u_riscv_top.wb_dcache_dat_o[11] ,
+    \u_riscv_top.wb_dcache_dat_o[10] ,
+    \u_riscv_top.wb_dcache_dat_o[9] ,
+    \u_riscv_top.wb_dcache_dat_o[8] ,
+    \u_riscv_top.wb_dcache_dat_o[7] ,
+    \u_riscv_top.wb_dcache_dat_o[6] ,
+    \u_riscv_top.wb_dcache_dat_o[5] ,
+    \u_riscv_top.wb_dcache_dat_o[4] ,
+    \u_riscv_top.wb_dcache_dat_o[3] ,
+    \u_riscv_top.wb_dcache_dat_o[2] ,
+    \u_riscv_top.wb_dcache_dat_o[1] ,
+    \u_riscv_top.wb_dcache_dat_o[0] }),
+    .wb_dcache_sel_o({\u_riscv_top.wb_dcache_sel_o[3] ,
+    \u_riscv_top.wb_dcache_sel_o[2] ,
+    \u_riscv_top.wb_dcache_sel_o[1] ,
+    \u_riscv_top.wb_dcache_sel_o[0] }),
+    .wb_icache_adr_o({\u_riscv_top.wb_icache_adr_o[31] ,
+    \u_riscv_top.wb_icache_adr_o[30] ,
+    \u_riscv_top.wb_icache_adr_o[29] ,
+    \u_riscv_top.wb_icache_adr_o[28] ,
+    \u_riscv_top.wb_icache_adr_o[27] ,
+    \u_riscv_top.wb_icache_adr_o[26] ,
+    \u_riscv_top.wb_icache_adr_o[25] ,
+    \u_riscv_top.wb_icache_adr_o[24] ,
+    \u_riscv_top.wb_icache_adr_o[23] ,
+    \u_riscv_top.wb_icache_adr_o[22] ,
+    \u_riscv_top.wb_icache_adr_o[21] ,
+    \u_riscv_top.wb_icache_adr_o[20] ,
+    \u_riscv_top.wb_icache_adr_o[19] ,
+    \u_riscv_top.wb_icache_adr_o[18] ,
+    \u_riscv_top.wb_icache_adr_o[17] ,
+    \u_riscv_top.wb_icache_adr_o[16] ,
+    \u_riscv_top.wb_icache_adr_o[15] ,
+    \u_riscv_top.wb_icache_adr_o[14] ,
+    \u_riscv_top.wb_icache_adr_o[13] ,
+    \u_riscv_top.wb_icache_adr_o[12] ,
+    \u_riscv_top.wb_icache_adr_o[11] ,
+    \u_riscv_top.wb_icache_adr_o[10] ,
+    \u_riscv_top.wb_icache_adr_o[9] ,
+    \u_riscv_top.wb_icache_adr_o[8] ,
+    \u_riscv_top.wb_icache_adr_o[7] ,
+    \u_riscv_top.wb_icache_adr_o[6] ,
+    \u_riscv_top.wb_icache_adr_o[5] ,
+    \u_riscv_top.wb_icache_adr_o[4] ,
+    \u_riscv_top.wb_icache_adr_o[3] ,
+    \u_riscv_top.wb_icache_adr_o[2] ,
+    \u_riscv_top.wb_icache_adr_o[1] ,
+    \u_riscv_top.wb_icache_adr_o[0] }),
+    .wb_icache_bl_o({\u_riscv_top.wb_icache_bl_o[9] ,
+    \u_riscv_top.wb_icache_bl_o[8] ,
+    \u_riscv_top.wb_icache_bl_o[7] ,
+    \u_riscv_top.wb_icache_bl_o[6] ,
+    \u_riscv_top.wb_icache_bl_o[5] ,
+    \u_riscv_top.wb_icache_bl_o[4] ,
+    \u_riscv_top.wb_icache_bl_o[3] ,
+    \u_riscv_top.wb_icache_bl_o[2] ,
+    \u_riscv_top.wb_icache_bl_o[1] ,
+    \u_riscv_top.wb_icache_bl_o[0] }),
+    .wb_icache_dat_i({\u_riscv_top.wb_icache_dat_i[31] ,
+    \u_riscv_top.wb_icache_dat_i[30] ,
+    \u_riscv_top.wb_icache_dat_i[29] ,
+    \u_riscv_top.wb_icache_dat_i[28] ,
+    \u_riscv_top.wb_icache_dat_i[27] ,
+    \u_riscv_top.wb_icache_dat_i[26] ,
+    \u_riscv_top.wb_icache_dat_i[25] ,
+    \u_riscv_top.wb_icache_dat_i[24] ,
+    \u_riscv_top.wb_icache_dat_i[23] ,
+    \u_riscv_top.wb_icache_dat_i[22] ,
+    \u_riscv_top.wb_icache_dat_i[21] ,
+    \u_riscv_top.wb_icache_dat_i[20] ,
+    \u_riscv_top.wb_icache_dat_i[19] ,
+    \u_riscv_top.wb_icache_dat_i[18] ,
+    \u_riscv_top.wb_icache_dat_i[17] ,
+    \u_riscv_top.wb_icache_dat_i[16] ,
+    \u_riscv_top.wb_icache_dat_i[15] ,
+    \u_riscv_top.wb_icache_dat_i[14] ,
+    \u_riscv_top.wb_icache_dat_i[13] ,
+    \u_riscv_top.wb_icache_dat_i[12] ,
+    \u_riscv_top.wb_icache_dat_i[11] ,
+    \u_riscv_top.wb_icache_dat_i[10] ,
+    \u_riscv_top.wb_icache_dat_i[9] ,
+    \u_riscv_top.wb_icache_dat_i[8] ,
+    \u_riscv_top.wb_icache_dat_i[7] ,
+    \u_riscv_top.wb_icache_dat_i[6] ,
+    \u_riscv_top.wb_icache_dat_i[5] ,
+    \u_riscv_top.wb_icache_dat_i[4] ,
+    \u_riscv_top.wb_icache_dat_i[3] ,
+    \u_riscv_top.wb_icache_dat_i[2] ,
+    \u_riscv_top.wb_icache_dat_i[1] ,
+    \u_riscv_top.wb_icache_dat_i[0] }),
+    .wb_icache_sel_o({\u_riscv_top.wb_icache_sel_o[3] ,
+    \u_riscv_top.wb_icache_sel_o[2] ,
+    \u_riscv_top.wb_icache_sel_o[1] ,
+    \u_riscv_top.wb_icache_sel_o[0] }),
+    .wbd_dmem_adr_o({\u_riscv_top.wbd_dmem_adr_o[31] ,
+    \u_riscv_top.wbd_dmem_adr_o[30] ,
+    \u_riscv_top.wbd_dmem_adr_o[29] ,
+    \u_riscv_top.wbd_dmem_adr_o[28] ,
+    \u_riscv_top.wbd_dmem_adr_o[27] ,
+    \u_riscv_top.wbd_dmem_adr_o[26] ,
+    \u_riscv_top.wbd_dmem_adr_o[25] ,
+    \u_riscv_top.wbd_dmem_adr_o[24] ,
+    \u_riscv_top.wbd_dmem_adr_o[23] ,
+    \u_riscv_top.wbd_dmem_adr_o[22] ,
+    \u_riscv_top.wbd_dmem_adr_o[21] ,
+    \u_riscv_top.wbd_dmem_adr_o[20] ,
+    \u_riscv_top.wbd_dmem_adr_o[19] ,
+    \u_riscv_top.wbd_dmem_adr_o[18] ,
+    \u_riscv_top.wbd_dmem_adr_o[17] ,
+    \u_riscv_top.wbd_dmem_adr_o[16] ,
+    \u_riscv_top.wbd_dmem_adr_o[15] ,
+    \u_riscv_top.wbd_dmem_adr_o[14] ,
+    \u_riscv_top.wbd_dmem_adr_o[13] ,
+    \u_riscv_top.wbd_dmem_adr_o[12] ,
+    \u_riscv_top.wbd_dmem_adr_o[11] ,
+    \u_riscv_top.wbd_dmem_adr_o[10] ,
+    \u_riscv_top.wbd_dmem_adr_o[9] ,
+    \u_riscv_top.wbd_dmem_adr_o[8] ,
+    \u_riscv_top.wbd_dmem_adr_o[7] ,
+    \u_riscv_top.wbd_dmem_adr_o[6] ,
+    \u_riscv_top.wbd_dmem_adr_o[5] ,
+    \u_riscv_top.wbd_dmem_adr_o[4] ,
+    \u_riscv_top.wbd_dmem_adr_o[3] ,
+    \u_riscv_top.wbd_dmem_adr_o[2] ,
+    \u_riscv_top.wbd_dmem_adr_o[1] ,
+    \u_riscv_top.wbd_dmem_adr_o[0] }),
+    .wbd_dmem_dat_i({\u_riscv_top.wbd_dmem_dat_i[31] ,
+    \u_riscv_top.wbd_dmem_dat_i[30] ,
+    \u_riscv_top.wbd_dmem_dat_i[29] ,
+    \u_riscv_top.wbd_dmem_dat_i[28] ,
+    \u_riscv_top.wbd_dmem_dat_i[27] ,
+    \u_riscv_top.wbd_dmem_dat_i[26] ,
+    \u_riscv_top.wbd_dmem_dat_i[25] ,
+    \u_riscv_top.wbd_dmem_dat_i[24] ,
+    \u_riscv_top.wbd_dmem_dat_i[23] ,
+    \u_riscv_top.wbd_dmem_dat_i[22] ,
+    \u_riscv_top.wbd_dmem_dat_i[21] ,
+    \u_riscv_top.wbd_dmem_dat_i[20] ,
+    \u_riscv_top.wbd_dmem_dat_i[19] ,
+    \u_riscv_top.wbd_dmem_dat_i[18] ,
+    \u_riscv_top.wbd_dmem_dat_i[17] ,
+    \u_riscv_top.wbd_dmem_dat_i[16] ,
+    \u_riscv_top.wbd_dmem_dat_i[15] ,
+    \u_riscv_top.wbd_dmem_dat_i[14] ,
+    \u_riscv_top.wbd_dmem_dat_i[13] ,
+    \u_riscv_top.wbd_dmem_dat_i[12] ,
+    \u_riscv_top.wbd_dmem_dat_i[11] ,
+    \u_riscv_top.wbd_dmem_dat_i[10] ,
+    \u_riscv_top.wbd_dmem_dat_i[9] ,
+    \u_riscv_top.wbd_dmem_dat_i[8] ,
+    \u_riscv_top.wbd_dmem_dat_i[7] ,
+    \u_riscv_top.wbd_dmem_dat_i[6] ,
+    \u_riscv_top.wbd_dmem_dat_i[5] ,
+    \u_riscv_top.wbd_dmem_dat_i[4] ,
+    \u_riscv_top.wbd_dmem_dat_i[3] ,
+    \u_riscv_top.wbd_dmem_dat_i[2] ,
+    \u_riscv_top.wbd_dmem_dat_i[1] ,
+    \u_riscv_top.wbd_dmem_dat_i[0] }),
+    .wbd_dmem_dat_o({\u_riscv_top.wbd_dmem_dat_o[31] ,
+    \u_riscv_top.wbd_dmem_dat_o[30] ,
+    \u_riscv_top.wbd_dmem_dat_o[29] ,
+    \u_riscv_top.wbd_dmem_dat_o[28] ,
+    \u_riscv_top.wbd_dmem_dat_o[27] ,
+    \u_riscv_top.wbd_dmem_dat_o[26] ,
+    \u_riscv_top.wbd_dmem_dat_o[25] ,
+    \u_riscv_top.wbd_dmem_dat_o[24] ,
+    \u_riscv_top.wbd_dmem_dat_o[23] ,
+    \u_riscv_top.wbd_dmem_dat_o[22] ,
+    \u_riscv_top.wbd_dmem_dat_o[21] ,
+    \u_riscv_top.wbd_dmem_dat_o[20] ,
+    \u_riscv_top.wbd_dmem_dat_o[19] ,
+    \u_riscv_top.wbd_dmem_dat_o[18] ,
+    \u_riscv_top.wbd_dmem_dat_o[17] ,
+    \u_riscv_top.wbd_dmem_dat_o[16] ,
+    \u_riscv_top.wbd_dmem_dat_o[15] ,
+    \u_riscv_top.wbd_dmem_dat_o[14] ,
+    \u_riscv_top.wbd_dmem_dat_o[13] ,
+    \u_riscv_top.wbd_dmem_dat_o[12] ,
+    \u_riscv_top.wbd_dmem_dat_o[11] ,
+    \u_riscv_top.wbd_dmem_dat_o[10] ,
+    \u_riscv_top.wbd_dmem_dat_o[9] ,
+    \u_riscv_top.wbd_dmem_dat_o[8] ,
+    \u_riscv_top.wbd_dmem_dat_o[7] ,
+    \u_riscv_top.wbd_dmem_dat_o[6] ,
+    \u_riscv_top.wbd_dmem_dat_o[5] ,
+    \u_riscv_top.wbd_dmem_dat_o[4] ,
+    \u_riscv_top.wbd_dmem_dat_o[3] ,
+    \u_riscv_top.wbd_dmem_dat_o[2] ,
+    \u_riscv_top.wbd_dmem_dat_o[1] ,
+    \u_riscv_top.wbd_dmem_dat_o[0] }),
+    .wbd_dmem_sel_o({\u_riscv_top.wbd_dmem_sel_o[3] ,
+    \u_riscv_top.wbd_dmem_sel_o[2] ,
+    \u_riscv_top.wbd_dmem_sel_o[1] ,
+    \u_riscv_top.wbd_dmem_sel_o[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb (.csb0(\u_riscv_top.sram0_csb0 ),
+    .csb1(\u_riscv_top.sram0_csb1 ),
+    .web0(\u_riscv_top.sram0_web0 ),
+    .clk0(\u_riscv_top.sram0_clk0 ),
+    .clk1(\u_riscv_top.sram0_clk1 ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\u_riscv_top.sram0_addr0[8] ,
+    \u_riscv_top.sram0_addr0[7] ,
+    \u_riscv_top.sram0_addr0[6] ,
+    \u_riscv_top.sram0_addr0[5] ,
+    \u_riscv_top.sram0_addr0[4] ,
+    \u_riscv_top.sram0_addr0[3] ,
+    \u_riscv_top.sram0_addr0[2] ,
+    \u_riscv_top.sram0_addr0[1] ,
+    \u_riscv_top.sram0_addr0[0] }),
+    .addr1({\u_riscv_top.sram0_addr1[8] ,
+    \u_riscv_top.sram0_addr1[7] ,
+    \u_riscv_top.sram0_addr1[6] ,
+    \u_riscv_top.sram0_addr1[5] ,
+    \u_riscv_top.sram0_addr1[4] ,
+    \u_riscv_top.sram0_addr1[3] ,
+    \u_riscv_top.sram0_addr1[2] ,
+    \u_riscv_top.sram0_addr1[1] ,
+    \u_riscv_top.sram0_addr1[0] }),
+    .din0({\u_riscv_top.sram0_din0[31] ,
+    \u_riscv_top.sram0_din0[30] ,
+    \u_riscv_top.sram0_din0[29] ,
+    \u_riscv_top.sram0_din0[28] ,
+    \u_riscv_top.sram0_din0[27] ,
+    \u_riscv_top.sram0_din0[26] ,
+    \u_riscv_top.sram0_din0[25] ,
+    \u_riscv_top.sram0_din0[24] ,
+    \u_riscv_top.sram0_din0[23] ,
+    \u_riscv_top.sram0_din0[22] ,
+    \u_riscv_top.sram0_din0[21] ,
+    \u_riscv_top.sram0_din0[20] ,
+    \u_riscv_top.sram0_din0[19] ,
+    \u_riscv_top.sram0_din0[18] ,
+    \u_riscv_top.sram0_din0[17] ,
+    \u_riscv_top.sram0_din0[16] ,
+    \u_riscv_top.sram0_din0[15] ,
+    \u_riscv_top.sram0_din0[14] ,
+    \u_riscv_top.sram0_din0[13] ,
+    \u_riscv_top.sram0_din0[12] ,
+    \u_riscv_top.sram0_din0[11] ,
+    \u_riscv_top.sram0_din0[10] ,
+    \u_riscv_top.sram0_din0[9] ,
+    \u_riscv_top.sram0_din0[8] ,
+    \u_riscv_top.sram0_din0[7] ,
+    \u_riscv_top.sram0_din0[6] ,
+    \u_riscv_top.sram0_din0[5] ,
+    \u_riscv_top.sram0_din0[4] ,
+    \u_riscv_top.sram0_din0[3] ,
+    \u_riscv_top.sram0_din0[2] ,
+    \u_riscv_top.sram0_din0[1] ,
+    \u_riscv_top.sram0_din0[0] }),
+    .dout0({\u_riscv_top.sram0_dout0[31] ,
+    \u_riscv_top.sram0_dout0[30] ,
+    \u_riscv_top.sram0_dout0[29] ,
+    \u_riscv_top.sram0_dout0[28] ,
+    \u_riscv_top.sram0_dout0[27] ,
+    \u_riscv_top.sram0_dout0[26] ,
+    \u_riscv_top.sram0_dout0[25] ,
+    \u_riscv_top.sram0_dout0[24] ,
+    \u_riscv_top.sram0_dout0[23] ,
+    \u_riscv_top.sram0_dout0[22] ,
+    \u_riscv_top.sram0_dout0[21] ,
+    \u_riscv_top.sram0_dout0[20] ,
+    \u_riscv_top.sram0_dout0[19] ,
+    \u_riscv_top.sram0_dout0[18] ,
+    \u_riscv_top.sram0_dout0[17] ,
+    \u_riscv_top.sram0_dout0[16] ,
+    \u_riscv_top.sram0_dout0[15] ,
+    \u_riscv_top.sram0_dout0[14] ,
+    \u_riscv_top.sram0_dout0[13] ,
+    \u_riscv_top.sram0_dout0[12] ,
+    \u_riscv_top.sram0_dout0[11] ,
+    \u_riscv_top.sram0_dout0[10] ,
+    \u_riscv_top.sram0_dout0[9] ,
+    \u_riscv_top.sram0_dout0[8] ,
+    \u_riscv_top.sram0_dout0[7] ,
+    \u_riscv_top.sram0_dout0[6] ,
+    \u_riscv_top.sram0_dout0[5] ,
+    \u_riscv_top.sram0_dout0[4] ,
+    \u_riscv_top.sram0_dout0[3] ,
+    \u_riscv_top.sram0_dout0[2] ,
+    \u_riscv_top.sram0_dout0[1] ,
+    \u_riscv_top.sram0_dout0[0] }),
+    .dout1({\u_riscv_top.sram0_dout1[31] ,
+    \u_riscv_top.sram0_dout1[30] ,
+    \u_riscv_top.sram0_dout1[29] ,
+    \u_riscv_top.sram0_dout1[28] ,
+    \u_riscv_top.sram0_dout1[27] ,
+    \u_riscv_top.sram0_dout1[26] ,
+    \u_riscv_top.sram0_dout1[25] ,
+    \u_riscv_top.sram0_dout1[24] ,
+    \u_riscv_top.sram0_dout1[23] ,
+    \u_riscv_top.sram0_dout1[22] ,
+    \u_riscv_top.sram0_dout1[21] ,
+    \u_riscv_top.sram0_dout1[20] ,
+    \u_riscv_top.sram0_dout1[19] ,
+    \u_riscv_top.sram0_dout1[18] ,
+    \u_riscv_top.sram0_dout1[17] ,
+    \u_riscv_top.sram0_dout1[16] ,
+    \u_riscv_top.sram0_dout1[15] ,
+    \u_riscv_top.sram0_dout1[14] ,
+    \u_riscv_top.sram0_dout1[13] ,
+    \u_riscv_top.sram0_dout1[12] ,
+    \u_riscv_top.sram0_dout1[11] ,
+    \u_riscv_top.sram0_dout1[10] ,
+    \u_riscv_top.sram0_dout1[9] ,
+    \u_riscv_top.sram0_dout1[8] ,
+    \u_riscv_top.sram0_dout1[7] ,
+    \u_riscv_top.sram0_dout1[6] ,
+    \u_riscv_top.sram0_dout1[5] ,
+    \u_riscv_top.sram0_dout1[4] ,
+    \u_riscv_top.sram0_dout1[3] ,
+    \u_riscv_top.sram0_dout1[2] ,
+    \u_riscv_top.sram0_dout1[1] ,
+    \u_riscv_top.sram0_dout1[0] }),
+    .wmask0({\u_riscv_top.sram0_wmask0[3] ,
+    \u_riscv_top.sram0_wmask0[2] ,
+    \u_riscv_top.sram0_wmask0[1] ,
+    \u_riscv_top.sram0_wmask0[0] }));
+ uart_i2c_usb_spi_top u_uart_i2c_usb_spi (.app_clk(wbd_clk_uart_skew),
+    .i2c_rstn(i2c_rst_n),
+    .i2cm_intr_o(i2cm_intr_o),
+    .reg_ack(wbd_uart_ack_i),
+    .reg_cs(wbd_uart_stb_o),
+    .reg_wr(wbd_uart_we_o),
+    .scl_pad_i(i2cm_clk_i),
+    .scl_pad_o(i2cm_clk_o),
+    .scl_pad_oen_o(i2cm_clk_oen),
+    .sda_pad_i(i2cm_data_i),
+    .sda_pad_o(i2cm_data_o),
+    .sda_padoen_o(i2cm_data_oen),
+    .spi_rstn(sspim_rst_n),
+    .sspim_sck(sspim_sck),
+    .sspim_si(sspim_si),
+    .sspim_so(sspim_so),
+    .sspim_ssn(sspim_ssn),
+    .uart_rstn(uart_rst_n),
+    .uart_rxd(uart_rxd),
+    .uart_txd(uart_txd),
+    .usb_clk(usb_clk),
+    .usb_in_dn(usb_dn_i),
+    .usb_in_dp(usb_dp_i),
+    .usb_intr_o(usb_intr_o),
+    .usb_out_dn(usb_dn_o),
+    .usb_out_dp(usb_dp_o),
+    .usb_out_tx_oen(usb_oen),
+    .usb_rstn(usb_rst_n),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_uart_rp),
+    .wbd_clk_uart(wbd_clk_uart_skew),
+    .cfg_cska_uart({\cfg_cska_uart_rp[3] ,
+    \cfg_cska_uart_rp[2] ,
+    \cfg_cska_uart_rp[1] ,
+    \cfg_cska_uart_rp[0] }),
+    .reg_addr({\wbd_uart_adr_o[7] ,
+    \wbd_uart_adr_o[6] ,
+    \wbd_uart_adr_o[5] ,
+    \wbd_uart_adr_o[4] ,
+    \wbd_uart_adr_o[3] ,
+    \wbd_uart_adr_o[2] ,
+    \wbd_uart_adr_o[1] ,
+    \wbd_uart_adr_o[0] }),
+    .reg_be({\wbd_uart_sel_o[3] ,
+    \wbd_uart_sel_o[2] ,
+    \wbd_uart_sel_o[1] ,
+    \wbd_uart_sel_o[0] }),
+    .reg_rdata({\wbd_uart_dat_i[31] ,
+    \wbd_uart_dat_i[30] ,
+    \wbd_uart_dat_i[29] ,
+    \wbd_uart_dat_i[28] ,
+    \wbd_uart_dat_i[27] ,
+    \wbd_uart_dat_i[26] ,
+    \wbd_uart_dat_i[25] ,
+    \wbd_uart_dat_i[24] ,
+    \wbd_uart_dat_i[23] ,
+    \wbd_uart_dat_i[22] ,
+    \wbd_uart_dat_i[21] ,
+    \wbd_uart_dat_i[20] ,
+    \wbd_uart_dat_i[19] ,
+    \wbd_uart_dat_i[18] ,
+    \wbd_uart_dat_i[17] ,
+    \wbd_uart_dat_i[16] ,
+    \wbd_uart_dat_i[15] ,
+    \wbd_uart_dat_i[14] ,
+    \wbd_uart_dat_i[13] ,
+    \wbd_uart_dat_i[12] ,
+    \wbd_uart_dat_i[11] ,
+    \wbd_uart_dat_i[10] ,
+    \wbd_uart_dat_i[9] ,
+    \wbd_uart_dat_i[8] ,
+    \wbd_uart_dat_i[7] ,
+    \wbd_uart_dat_i[6] ,
+    \wbd_uart_dat_i[5] ,
+    \wbd_uart_dat_i[4] ,
+    \wbd_uart_dat_i[3] ,
+    \wbd_uart_dat_i[2] ,
+    \wbd_uart_dat_i[1] ,
+    \wbd_uart_dat_i[0] }),
+    .reg_wdata({\wbd_uart_dat_o[31] ,
+    \wbd_uart_dat_o[30] ,
+    \wbd_uart_dat_o[29] ,
+    \wbd_uart_dat_o[28] ,
+    \wbd_uart_dat_o[27] ,
+    \wbd_uart_dat_o[26] ,
+    \wbd_uart_dat_o[25] ,
+    \wbd_uart_dat_o[24] ,
+    \wbd_uart_dat_o[23] ,
+    \wbd_uart_dat_o[22] ,
+    \wbd_uart_dat_o[21] ,
+    \wbd_uart_dat_o[20] ,
+    \wbd_uart_dat_o[19] ,
+    \wbd_uart_dat_o[18] ,
+    \wbd_uart_dat_o[17] ,
+    \wbd_uart_dat_o[16] ,
+    \wbd_uart_dat_o[15] ,
+    \wbd_uart_dat_o[14] ,
+    \wbd_uart_dat_o[13] ,
+    \wbd_uart_dat_o[12] ,
+    \wbd_uart_dat_o[11] ,
+    \wbd_uart_dat_o[10] ,
+    \wbd_uart_dat_o[9] ,
+    \wbd_uart_dat_o[8] ,
+    \wbd_uart_dat_o[7] ,
+    \wbd_uart_dat_o[6] ,
+    \wbd_uart_dat_o[5] ,
+    \wbd_uart_dat_o[4] ,
+    \wbd_uart_dat_o[3] ,
+    \wbd_uart_dat_o[2] ,
+    \wbd_uart_dat_o[1] ,
+    \wbd_uart_dat_o[0] }));
+ wb_host u_wb_host (.cpu_clk(\u_riscv_top.core_clk ),
+    .rtc_clk(\u_riscv_top.rtc_clk ),
+    .uartm_rxd(uartm_rxd),
+    .uartm_txd(uartm_txd),
+    .usb_clk(usb_clk),
+    .user_clock1(wb_clk_i),
+    .user_clock2(user_clock2),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_int),
+    .wbd_clk_wh(wbd_clk_wh),
+    .wbd_int_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .wbm_ack_o(wbs_ack_o),
+    .wbm_clk_i(wb_clk_i),
+    .wbm_cyc_i(wbs_cyc_i),
+    .wbm_rst_i(wb_rst_i),
+    .wbm_stb_i(wbs_stb_i),
+    .wbm_we_i(wbs_we_i),
+    .wbs_ack_i(wbd_int_ack_o),
+    .wbs_clk_i(wbd_clk_wh),
+    .wbs_clk_out(wbd_clk_int),
+    .wbs_cyc_o(wbd_int_cyc_i),
+    .wbs_err_i(wbd_int_err_o),
+    .wbs_stb_o(wbd_int_stb_i),
+    .wbs_we_o(wbd_int_we_i),
+    .cfg_clk_ctrl1({\cfg_clk_ctrl1[31] ,
+    \cfg_clk_ctrl1[30] ,
+    \cfg_clk_ctrl1[29] ,
+    \cfg_clk_ctrl1[28] ,
+    \cfg_clk_ctrl1[27] ,
+    \cfg_clk_ctrl1[26] ,
+    \cfg_clk_ctrl1[25] ,
+    \cfg_clk_ctrl1[24] ,
+    \cfg_clk_ctrl1[23] ,
+    \cfg_clk_ctrl1[22] ,
+    \cfg_clk_ctrl1[21] ,
+    \cfg_clk_ctrl1[20] ,
+    \cfg_clk_ctrl1[19] ,
+    \cfg_clk_ctrl1[18] ,
+    \cfg_clk_ctrl1[17] ,
+    \cfg_clk_ctrl1[16] ,
+    \cfg_clk_ctrl1[15] ,
+    \cfg_clk_ctrl1[14] ,
+    \cfg_clk_ctrl1[13] ,
+    \cfg_clk_ctrl1[12] ,
+    \cfg_clk_ctrl1[11] ,
+    \cfg_clk_ctrl1[10] ,
+    \cfg_clk_ctrl1[9] ,
+    \cfg_clk_ctrl1[8] ,
+    \cfg_clk_ctrl1[7] ,
+    \cfg_clk_ctrl1[6] ,
+    \cfg_clk_ctrl1[5] ,
+    \cfg_clk_ctrl1[4] ,
+    \cfg_clk_ctrl1[3] ,
+    \cfg_clk_ctrl1[2] ,
+    \cfg_clk_ctrl1[1] ,
+    \cfg_clk_ctrl1[0] }),
+    .cfg_clk_ctrl2({\cfg_clk_ctrl2[31] ,
+    \cfg_clk_ctrl2[30] ,
+    \cfg_clk_ctrl2[29] ,
+    \cfg_clk_ctrl2[28] ,
+    \cfg_clk_ctrl2[27] ,
+    \cfg_clk_ctrl2[26] ,
+    \cfg_clk_ctrl2[25] ,
+    \cfg_clk_ctrl2[24] ,
+    \cfg_clk_ctrl2[23] ,
+    \cfg_clk_ctrl2[22] ,
+    \cfg_clk_ctrl2[21] ,
+    \cfg_clk_ctrl2[20] ,
+    \cfg_clk_ctrl2[19] ,
+    \cfg_clk_ctrl2[18] ,
+    \cfg_clk_ctrl2[17] ,
+    \cfg_clk_ctrl2[16] ,
+    \cfg_clk_ctrl2[15] ,
+    \cfg_clk_ctrl2[14] ,
+    \cfg_clk_ctrl2[13] ,
+    \cfg_clk_ctrl2[12] ,
+    \cfg_clk_ctrl2[11] ,
+    \cfg_clk_ctrl2[10] ,
+    \cfg_clk_ctrl2[9] ,
+    \cfg_clk_ctrl2[8] ,
+    \cfg_clk_ctrl2[7] ,
+    \cfg_clk_ctrl2[6] ,
+    \cfg_clk_ctrl2[5] ,
+    \cfg_clk_ctrl2[4] ,
+    \cfg_clk_ctrl2[3] ,
+    \cfg_clk_ctrl2[2] ,
+    \cfg_clk_ctrl2[1] ,
+    \cfg_clk_ctrl2[0] }),
+    .cfg_cska_wh({\cfg_clk_ctrl1[7] ,
+    \cfg_clk_ctrl1[6] ,
+    \cfg_clk_ctrl1[5] ,
+    \cfg_clk_ctrl1[4] }),
+    .la_data_in({la_data_in[17],
+    la_data_in[16],
+    la_data_in[15],
+    la_data_in[14],
+    la_data_in[13],
+    la_data_in[12],
+    la_data_in[11],
+    la_data_in[10],
+    la_data_in[9],
+    la_data_in[8],
+    la_data_in[7],
+    la_data_in[6],
+    la_data_in[5],
+    la_data_in[4],
+    la_data_in[3],
+    la_data_in[2],
+    la_data_in[1],
+    la_data_in[0]}),
+    .wbm_adr_i({wbs_adr_i[31],
+    wbs_adr_i[30],
+    wbs_adr_i[29],
+    wbs_adr_i[28],
+    wbs_adr_i[27],
+    wbs_adr_i[26],
+    wbs_adr_i[25],
+    wbs_adr_i[24],
+    wbs_adr_i[23],
+    wbs_adr_i[22],
+    wbs_adr_i[21],
+    wbs_adr_i[20],
+    wbs_adr_i[19],
+    wbs_adr_i[18],
+    wbs_adr_i[17],
+    wbs_adr_i[16],
+    wbs_adr_i[15],
+    wbs_adr_i[14],
+    wbs_adr_i[13],
+    wbs_adr_i[12],
+    wbs_adr_i[11],
+    wbs_adr_i[10],
+    wbs_adr_i[9],
+    wbs_adr_i[8],
+    wbs_adr_i[7],
+    wbs_adr_i[6],
+    wbs_adr_i[5],
+    wbs_adr_i[4],
+    wbs_adr_i[3],
+    wbs_adr_i[2],
+    wbs_adr_i[1],
+    wbs_adr_i[0]}),
+    .wbm_dat_i({wbs_dat_i[31],
+    wbs_dat_i[30],
+    wbs_dat_i[29],
+    wbs_dat_i[28],
+    wbs_dat_i[27],
+    wbs_dat_i[26],
+    wbs_dat_i[25],
+    wbs_dat_i[24],
+    wbs_dat_i[23],
+    wbs_dat_i[22],
+    wbs_dat_i[21],
+    wbs_dat_i[20],
+    wbs_dat_i[19],
+    wbs_dat_i[18],
+    wbs_dat_i[17],
+    wbs_dat_i[16],
+    wbs_dat_i[15],
+    wbs_dat_i[14],
+    wbs_dat_i[13],
+    wbs_dat_i[12],
+    wbs_dat_i[11],
+    wbs_dat_i[10],
+    wbs_dat_i[9],
+    wbs_dat_i[8],
+    wbs_dat_i[7],
+    wbs_dat_i[6],
+    wbs_dat_i[5],
+    wbs_dat_i[4],
+    wbs_dat_i[3],
+    wbs_dat_i[2],
+    wbs_dat_i[1],
+    wbs_dat_i[0]}),
+    .wbm_dat_o({wbs_dat_o[31],
+    wbs_dat_o[30],
+    wbs_dat_o[29],
+    wbs_dat_o[28],
+    wbs_dat_o[27],
+    wbs_dat_o[26],
+    wbs_dat_o[25],
+    wbs_dat_o[24],
+    wbs_dat_o[23],
+    wbs_dat_o[22],
+    wbs_dat_o[21],
+    wbs_dat_o[20],
+    wbs_dat_o[19],
+    wbs_dat_o[18],
+    wbs_dat_o[17],
+    wbs_dat_o[16],
+    wbs_dat_o[15],
+    wbs_dat_o[14],
+    wbs_dat_o[13],
+    wbs_dat_o[12],
+    wbs_dat_o[11],
+    wbs_dat_o[10],
+    wbs_dat_o[9],
+    wbs_dat_o[8],
+    wbs_dat_o[7],
+    wbs_dat_o[6],
+    wbs_dat_o[5],
+    wbs_dat_o[4],
+    wbs_dat_o[3],
+    wbs_dat_o[2],
+    wbs_dat_o[1],
+    wbs_dat_o[0]}),
+    .wbm_sel_i({wbs_sel_i[3],
+    wbs_sel_i[2],
+    wbs_sel_i[1],
+    wbs_sel_i[0]}),
+    .wbs_adr_o({\wbd_int_adr_i[31] ,
+    \wbd_int_adr_i[30] ,
+    \wbd_int_adr_i[29] ,
+    \wbd_int_adr_i[28] ,
+    \wbd_int_adr_i[27] ,
+    \wbd_int_adr_i[26] ,
+    \wbd_int_adr_i[25] ,
+    \wbd_int_adr_i[24] ,
+    \wbd_int_adr_i[23] ,
+    \wbd_int_adr_i[22] ,
+    \wbd_int_adr_i[21] ,
+    \wbd_int_adr_i[20] ,
+    \wbd_int_adr_i[19] ,
+    \wbd_int_adr_i[18] ,
+    \wbd_int_adr_i[17] ,
+    \wbd_int_adr_i[16] ,
+    \wbd_int_adr_i[15] ,
+    \wbd_int_adr_i[14] ,
+    \wbd_int_adr_i[13] ,
+    \wbd_int_adr_i[12] ,
+    \wbd_int_adr_i[11] ,
+    \wbd_int_adr_i[10] ,
+    \wbd_int_adr_i[9] ,
+    \wbd_int_adr_i[8] ,
+    \wbd_int_adr_i[7] ,
+    \wbd_int_adr_i[6] ,
+    \wbd_int_adr_i[5] ,
+    \wbd_int_adr_i[4] ,
+    \wbd_int_adr_i[3] ,
+    \wbd_int_adr_i[2] ,
+    \wbd_int_adr_i[1] ,
+    \wbd_int_adr_i[0] }),
+    .wbs_dat_i({\wbd_int_dat_o[31] ,
+    \wbd_int_dat_o[30] ,
+    \wbd_int_dat_o[29] ,
+    \wbd_int_dat_o[28] ,
+    \wbd_int_dat_o[27] ,
+    \wbd_int_dat_o[26] ,
+    \wbd_int_dat_o[25] ,
+    \wbd_int_dat_o[24] ,
+    \wbd_int_dat_o[23] ,
+    \wbd_int_dat_o[22] ,
+    \wbd_int_dat_o[21] ,
+    \wbd_int_dat_o[20] ,
+    \wbd_int_dat_o[19] ,
+    \wbd_int_dat_o[18] ,
+    \wbd_int_dat_o[17] ,
+    \wbd_int_dat_o[16] ,
+    \wbd_int_dat_o[15] ,
+    \wbd_int_dat_o[14] ,
+    \wbd_int_dat_o[13] ,
+    \wbd_int_dat_o[12] ,
+    \wbd_int_dat_o[11] ,
+    \wbd_int_dat_o[10] ,
+    \wbd_int_dat_o[9] ,
+    \wbd_int_dat_o[8] ,
+    \wbd_int_dat_o[7] ,
+    \wbd_int_dat_o[6] ,
+    \wbd_int_dat_o[5] ,
+    \wbd_int_dat_o[4] ,
+    \wbd_int_dat_o[3] ,
+    \wbd_int_dat_o[2] ,
+    \wbd_int_dat_o[1] ,
+    \wbd_int_dat_o[0] }),
+    .wbs_dat_o({\wbd_int_dat_i[31] ,
+    \wbd_int_dat_i[30] ,
+    \wbd_int_dat_i[29] ,
+    \wbd_int_dat_i[28] ,
+    \wbd_int_dat_i[27] ,
+    \wbd_int_dat_i[26] ,
+    \wbd_int_dat_i[25] ,
+    \wbd_int_dat_i[24] ,
+    \wbd_int_dat_i[23] ,
+    \wbd_int_dat_i[22] ,
+    \wbd_int_dat_i[21] ,
+    \wbd_int_dat_i[20] ,
+    \wbd_int_dat_i[19] ,
+    \wbd_int_dat_i[18] ,
+    \wbd_int_dat_i[17] ,
+    \wbd_int_dat_i[16] ,
+    \wbd_int_dat_i[15] ,
+    \wbd_int_dat_i[14] ,
+    \wbd_int_dat_i[13] ,
+    \wbd_int_dat_i[12] ,
+    \wbd_int_dat_i[11] ,
+    \wbd_int_dat_i[10] ,
+    \wbd_int_dat_i[9] ,
+    \wbd_int_dat_i[8] ,
+    \wbd_int_dat_i[7] ,
+    \wbd_int_dat_i[6] ,
+    \wbd_int_dat_i[5] ,
+    \wbd_int_dat_i[4] ,
+    \wbd_int_dat_i[3] ,
+    \wbd_int_dat_i[2] ,
+    \wbd_int_dat_i[1] ,
+    \wbd_int_dat_i[0] }),
+    .wbs_sel_o({\wbd_int_sel_i[3] ,
+    \wbd_int_sel_i[2] ,
+    \wbd_int_sel_i[1] ,
+    \wbd_int_sel_i[0] }));
+endmodule

mpw_precheck/outputs/user_project_wrapper.magic.drc.mag

diff --git a/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag b/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..16219ac
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag
@@ -0,0 +1,154117 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647766512
+<< checkpaint >>
+rect -12658 -11586 596582 715522
+<< metal1 >>
+rect 71774 702992 71780 703044
+rect 71832 703032 71838 703044
+rect 72970 703032 72976 703044
+rect 71832 703004 72976 703032
+rect 71832 702992 71838 703004
+rect 72970 702992 72976 703004
+rect 73028 702992 73034 703044
+rect 331214 702992 331220 703044
+rect 331272 703032 331278 703044
+rect 332502 703032 332508 703044
+rect 331272 703004 332508 703032
+rect 331272 702992 331278 703004
+rect 332502 702992 332508 703004
+rect 332560 702992 332566 703044
+rect 202782 700340 202788 700392
+rect 202840 700380 202846 700392
+rect 203518 700380 203524 700392
+rect 202840 700352 203524 700380
+rect 202840 700340 202846 700352
+rect 203518 700340 203524 700352
+rect 203576 700340 203582 700392
+rect 536098 700340 536104 700392
+rect 536156 700380 536162 700392
+rect 543458 700380 543464 700392
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