sta scripts are updated
diff --git a/lef/merged_unpadded.lef.gz b/lef/merged_unpadded.lef.gz new file mode 100644 index 0000000..fa9351c --- /dev/null +++ b/lef/merged_unpadded.lef.gz Binary files differ
diff --git a/lib/sram_1rw1r_32_256_8_sky130_TT_1p8V_25C.lib b/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib similarity index 60% rename from lib/sram_1rw1r_32_256_8_sky130_TT_1p8V_25C.lib rename to lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib index 2c15e06..58c04a8 100644 --- a/lib/sram_1rw1r_32_256_8_sky130_TT_1p8V_25C.lib +++ b/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
@@ -1,4 +1,4 @@ -library (sram_1rw1r_32_256_8_sky130_TT_1p8V_25C_lib){ +library (sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C_lib){ delay_model : "table_lookup"; time_unit : "1ns" ; voltage_unit : "1V" ; @@ -35,14 +35,14 @@ default_max_fanout : 4.0 ; default_connection_class : universal ; - voltage_map ( VDD, 1.8 ); - voltage_map ( GND, 0 ); + voltage_map ( VCCD1, 1.8 ); + voltage_map ( VSSD1, 0 ); lu_table_template(CELL_TABLE){ variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1("0.00125, 0.005, 0.04"); - index_2("0.0017225, 0.00689, 0.02756"); + index_2("0.0017224999999999999, 0.006889999999999999, 0.027559999999999998"); } lu_table_template(CONSTRAINT_TABLE){ @@ -59,27 +59,27 @@ base_type : array; data_type : bit; bit_width : 32; - bit_from : 0; - bit_to : 31; + bit_from : 31; + bit_to : 0; } type (addr){ base_type : array; data_type : bit; bit_width : 8; - bit_from : 0; - bit_to : 7; + bit_from : 7; + bit_to : 0; } type (wmask){ base_type : array; data_type : bit; bit_width : 4; - bit_from : 0; - bit_to : 3; + bit_from : 3; + bit_to : 0; } -cell (sram_1rw1r_32_256_8_sky130){ +cell (sky130_sram_1kbyte_1rw1r_32x256_8){ memory(){ type : ram; address_width : 8; @@ -89,22 +89,22 @@ dont_use : true; map_only : true; dont_touch : true; - area : 167998.5528; + area : 190712.55; - pg_pin(vdd) { - voltage_name : VDD; + pg_pin(vccd1) { + voltage_name : VCCD1; pg_type : primary_power; } - pg_pin(gnd) { - voltage_name : GND; + pg_pin(vssd1) { + voltage_name : VSSD1; pg_type : primary_ground; } leakage_power () { - value : 0.009512; + value : 0.009516; } - cell_leakage_power : 0.009512; + cell_leakage_power : 0.009516; bus(din0){ bus_type : data; direction : input; @@ -118,28 +118,28 @@ timing_type : setup_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } } timing(){ timing_type : hold_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } } } @@ -158,14 +158,14 @@ related_pin : "clk0"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.449, 0.478, 0.595",\ - "0.449, 0.478, 0.595",\ - "0.449, 0.478, 0.595"); + values("0.339, 0.368, 0.484",\ + "0.339, 0.368, 0.484",\ + "0.339, 0.368, 0.484"); } cell_fall(CELL_TABLE) { - values("0.449, 0.478, 0.595",\ - "0.449, 0.478, 0.595",\ - "0.449, 0.478, 0.595"); + values("0.339, 0.368, 0.484",\ + "0.339, 0.368, 0.484",\ + "0.339, 0.368, 0.484"); } rise_transition(CELL_TABLE) { values("0.002, 0.005, 0.016",\ @@ -191,28 +191,28 @@ timing_type : setup_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } } timing(){ timing_type : hold_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } } } @@ -228,28 +228,28 @@ timing_type : setup_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } } timing(){ timing_type : hold_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } } } @@ -262,28 +262,28 @@ timing_type : setup_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } } timing(){ timing_type : hold_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } } } @@ -295,28 +295,28 @@ timing_type : setup_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } } timing(){ timing_type : hold_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } } } @@ -328,57 +328,57 @@ internal_power(){ when : "!csb0 & !web0"; rise_power(scalar){ - values("1.903307e+01"); + values("9.589466e+00"); } fall_power(scalar){ - values("1.903307e+01"); + values("9.589466e+00"); } } internal_power(){ when : "csb0 & !web0"; rise_power(scalar){ - values("1.903307e+01"); + values("9.589466e+00"); } fall_power(scalar){ - values("1.903307e+01"); + values("9.589466e+00"); } } internal_power(){ when : "!csb0 & web0"; rise_power(scalar){ - values("1.903307e+01"); + values("9.589466e+00"); } fall_power(scalar){ - values("1.903307e+01"); + values("9.589466e+00"); } } internal_power(){ when : "csb0 & web0"; rise_power(scalar){ - values("1.903307e+01"); + values("9.589466e+00"); } fall_power(scalar){ - values("1.903307e+01"); + values("9.589466e+00"); } } timing(){ timing_type :"min_pulse_width"; related_pin : clk0; rise_constraint(scalar) { - values("0.0595"); + values("0.8955"); } fall_constraint(scalar) { - values("0.0595"); + values("0.8955"); } } timing(){ timing_type :"minimum_period"; related_pin : clk0; rise_constraint(scalar) { - values("0.119"); + values("1.791"); } fall_constraint(scalar) { - values("0.119"); + values("1.791"); } } } @@ -397,14 +397,14 @@ related_pin : "clk1"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.449, 0.478, 0.595",\ - "0.449, 0.478, 0.595",\ - "0.449, 0.478, 0.595"); + values("0.339, 0.368, 0.484",\ + "0.339, 0.368, 0.484",\ + "0.339, 0.368, 0.484"); } cell_fall(CELL_TABLE) { - values("0.449, 0.478, 0.595",\ - "0.449, 0.478, 0.595",\ - "0.449, 0.478, 0.595"); + values("0.339, 0.368, 0.484",\ + "0.339, 0.368, 0.484",\ + "0.339, 0.368, 0.484"); } rise_transition(CELL_TABLE) { values("0.002, 0.005, 0.016",\ @@ -430,65 +430,28 @@ timing_type : setup_rising; related_pin : "clk1"; rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } } timing(){ timing_type : hold_rising; related_pin : "clk1"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - } - - bus(wmask1){ - bus_type : wmask; - direction : input; - capacitance : 0.006889999999999999; - max_transition : 0.04; - pin(wmask1[3:0]){ - timing(){ - timing_type : setup_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } } } @@ -501,28 +464,28 @@ timing_type : setup_rising; related_pin : "clk1"; rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); } } timing(){ timing_type : hold_rising; related_pin : "clk1"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); } } } @@ -534,39 +497,39 @@ internal_power(){ when : "!csb1"; rise_power(scalar){ - values("1.903307e+01"); + values("9.589466e+00"); } fall_power(scalar){ - values("1.903307e+01"); + values("9.589466e+00"); } } internal_power(){ when : "csb1"; rise_power(scalar){ - values("1.903307e+01"); + values("9.589466e+00"); } fall_power(scalar){ - values("1.903307e+01"); + values("9.589466e+00"); } } timing(){ timing_type :"min_pulse_width"; related_pin : clk1; rise_constraint(scalar) { - values("0.0595"); + values("0.8955"); } fall_constraint(scalar) { - values("0.0595"); + values("0.8955"); } } timing(){ timing_type :"minimum_period"; related_pin : clk1; rise_constraint(scalar) { - values("0.119"); + values("1.791"); } fall_constraint(scalar) { - values("0.119"); + values("1.791"); } } }
diff --git a/lib/sram_1rw1r_32_256_8_sky130_FF_1p8V_25C.lib b/lib/sram_1rw1r_32_256_8_sky130_FF_1p8V_25C.lib deleted file mode 100644 index 6548c39..0000000 --- a/lib/sram_1rw1r_32_256_8_sky130_FF_1p8V_25C.lib +++ /dev/null
@@ -1,575 +0,0 @@ -library (sram_1rw1r_32_256_8_sky130_FF_1p8V_25C_lib){ - delay_model : "table_lookup"; - time_unit : "1ns" ; - voltage_unit : "1V" ; - current_unit : "1mA" ; - resistance_unit : "1kohm" ; - capacitive_load_unit(1, pF) ; - leakage_power_unit : "1mW" ; - pulling_resistance_unit :"1kohm" ; - operating_conditions(OC){ - process : 1.0 ; - voltage : 1.8 ; - temperature : 25; - } - - input_threshold_pct_fall : 50.0 ; - output_threshold_pct_fall : 50.0 ; - input_threshold_pct_rise : 50.0 ; - output_threshold_pct_rise : 50.0 ; - slew_lower_threshold_pct_fall : 10.0 ; - slew_upper_threshold_pct_fall : 90.0 ; - slew_lower_threshold_pct_rise : 10.0 ; - slew_upper_threshold_pct_rise : 90.0 ; - - nom_voltage : 1.8; - nom_temperature : 25; - nom_process : 1.0; - default_cell_leakage_power : 0.0 ; - default_leakage_power_density : 0.0 ; - default_input_pin_cap : 1.0 ; - default_inout_pin_cap : 1.0 ; - default_output_pin_cap : 0.0 ; - default_max_transition : 0.5 ; - default_fanout_load : 1.0 ; - default_max_fanout : 4.0 ; - default_connection_class : universal ; - - voltage_map ( VDD, 1.8 ); - voltage_map ( GND, 0 ); - - lu_table_template(CELL_TABLE){ - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1("0.00125, 0.005, 0.04"); - index_2("0.0017225, 0.00689, 0.02756"); - } - - lu_table_template(CONSTRAINT_TABLE){ - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1("0.00125, 0.005, 0.04"); - index_2("0.00125, 0.005, 0.04"); - } - - default_operating_conditions : OC; - - - type (data){ - base_type : array; - data_type : bit; - bit_width : 32; - bit_from : 0; - bit_to : 31; - } - - type (addr){ - base_type : array; - data_type : bit; - bit_width : 8; - bit_from : 0; - bit_to : 7; - } - - type (wmask){ - base_type : array; - data_type : bit; - bit_width : 4; - bit_from : 0; - bit_to : 3; - } - -cell (sram_1rw1r_32_256_8_sky130){ - memory(){ - type : ram; - address_width : 8; - word_width : 32; - } - interface_timing : true; - dont_use : true; - map_only : true; - dont_touch : true; - area : 167998.5528; - - pg_pin(vdd) { - voltage_name : VDD; - pg_type : primary_power; - } - - pg_pin(gnd) { - voltage_name : GND; - pg_type : primary_ground; - } - - leakage_power () { - value : 0.009512; - } - cell_leakage_power : 0.009512; - bus(din0){ - bus_type : data; - direction : input; - capacitance : 0.006889999999999999; - memory_write(){ - address : addr0; - clocked_on : clk0; - } - pin(din0[31:0]){ - timing(){ - timing_type : setup_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - } - bus(dout0){ - bus_type : data; - direction : output; - max_capacitance : 0.027559999999999998; - min_capacitance : 0.0017224999999999999; - memory_read(){ - address : addr0; - } - pin(dout0[31:0]){ - timing(){ - timing_sense : non_unate; - related_pin : "clk0"; - timing_type : falling_edge; - cell_rise(CELL_TABLE) { - values("0.404, 0.43, 0.535",\ - "0.404, 0.43, 0.535",\ - "0.404, 0.43, 0.535"); - } - cell_fall(CELL_TABLE) { - values("0.404, 0.43, 0.535",\ - "0.404, 0.43, 0.535",\ - "0.404, 0.43, 0.535"); - } - rise_transition(CELL_TABLE) { - values("0.002, 0.004, 0.015",\ - "0.002, 0.004, 0.015",\ - "0.002, 0.004, 0.015"); - } - fall_transition(CELL_TABLE) { - values("0.002, 0.004, 0.015",\ - "0.002, 0.004, 0.015",\ - "0.002, 0.004, 0.015"); - } - } - } - } - - bus(addr0){ - bus_type : addr; - direction : input; - capacitance : 0.006889999999999999; - max_transition : 0.04; - pin(addr0[7:0]){ - timing(){ - timing_type : setup_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - } - - bus(wmask0){ - bus_type : wmask; - direction : input; - capacitance : 0.006889999999999999; - max_transition : 0.04; - pin(wmask0[3:0]){ - timing(){ - timing_type : setup_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - } - - pin(csb0){ - direction : input; - capacitance : 0.006889999999999999; - timing(){ - timing_type : setup_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - - pin(web0){ - direction : input; - capacitance : 0.006889999999999999; - timing(){ - timing_type : setup_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - - pin(clk0){ - clock : true; - direction : input; - capacitance : 0.006889999999999999; - internal_power(){ - when : "!csb0 & !web0"; - rise_power(scalar){ - values("2.114785e+01"); - } - fall_power(scalar){ - values("2.114785e+01"); - } - } - internal_power(){ - when : "csb0 & !web0"; - rise_power(scalar){ - values("2.114785e+01"); - } - fall_power(scalar){ - values("2.114785e+01"); - } - } - internal_power(){ - when : "!csb0 & web0"; - rise_power(scalar){ - values("2.114785e+01"); - } - fall_power(scalar){ - values("2.114785e+01"); - } - } - internal_power(){ - when : "csb0 & web0"; - rise_power(scalar){ - values("2.114785e+01"); - } - fall_power(scalar){ - values("2.114785e+01"); - } - } - timing(){ - timing_type :"min_pulse_width"; - related_pin : clk0; - rise_constraint(scalar) { - values("0.0535"); - } - fall_constraint(scalar) { - values("0.0535"); - } - } - timing(){ - timing_type :"minimum_period"; - related_pin : clk0; - rise_constraint(scalar) { - values("0.107"); - } - fall_constraint(scalar) { - values("0.107"); - } - } - } - - bus(dout1){ - bus_type : data; - direction : output; - max_capacitance : 0.027559999999999998; - min_capacitance : 0.0017224999999999999; - memory_read(){ - address : addr1; - } - pin(dout1[31:0]){ - timing(){ - timing_sense : non_unate; - related_pin : "clk1"; - timing_type : falling_edge; - cell_rise(CELL_TABLE) { - values("0.404, 0.43, 0.535",\ - "0.404, 0.43, 0.535",\ - "0.404, 0.43, 0.535"); - } - cell_fall(CELL_TABLE) { - values("0.404, 0.43, 0.535",\ - "0.404, 0.43, 0.535",\ - "0.404, 0.43, 0.535"); - } - rise_transition(CELL_TABLE) { - values("0.002, 0.004, 0.015",\ - "0.002, 0.004, 0.015",\ - "0.002, 0.004, 0.015"); - } - fall_transition(CELL_TABLE) { - values("0.002, 0.004, 0.015",\ - "0.002, 0.004, 0.015",\ - "0.002, 0.004, 0.015"); - } - } - } - } - - bus(addr1){ - bus_type : addr; - direction : input; - capacitance : 0.006889999999999999; - max_transition : 0.04; - pin(addr1[7:0]){ - timing(){ - timing_type : setup_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - } - - bus(wmask1){ - bus_type : wmask; - direction : input; - capacitance : 0.006889999999999999; - max_transition : 0.04; - pin(wmask1[3:0]){ - timing(){ - timing_type : setup_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - } - - pin(csb1){ - direction : input; - capacitance : 0.006889999999999999; - timing(){ - timing_type : setup_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - - pin(clk1){ - clock : true; - direction : input; - capacitance : 0.006889999999999999; - internal_power(){ - when : "!csb1"; - rise_power(scalar){ - values("2.114785e+01"); - } - fall_power(scalar){ - values("2.114785e+01"); - } - } - internal_power(){ - when : "csb1"; - rise_power(scalar){ - values("2.114785e+01"); - } - fall_power(scalar){ - values("2.114785e+01"); - } - } - timing(){ - timing_type :"min_pulse_width"; - related_pin : clk1; - rise_constraint(scalar) { - values("0.0535"); - } - fall_constraint(scalar) { - values("0.0535"); - } - } - timing(){ - timing_type :"minimum_period"; - related_pin : clk1; - rise_constraint(scalar) { - values("0.107"); - } - fall_constraint(scalar) { - values("0.107"); - } - } - } - - } -}
diff --git a/lib/sram_1rw1r_32_256_8_sky130_SS_1p8V_25C.lib b/lib/sram_1rw1r_32_256_8_sky130_SS_1p8V_25C.lib deleted file mode 100644 index 2403478..0000000 --- a/lib/sram_1rw1r_32_256_8_sky130_SS_1p8V_25C.lib +++ /dev/null
@@ -1,575 +0,0 @@ -library (sram_1rw1r_32_256_8_sky130_SS_1p8V_25C_lib){ - delay_model : "table_lookup"; - time_unit : "1ns" ; - voltage_unit : "1V" ; - current_unit : "1mA" ; - resistance_unit : "1kohm" ; - capacitive_load_unit(1, pF) ; - leakage_power_unit : "1mW" ; - pulling_resistance_unit :"1kohm" ; - operating_conditions(OC){ - process : 1.0 ; - voltage : 1.8 ; - temperature : 25; - } - - input_threshold_pct_fall : 50.0 ; - output_threshold_pct_fall : 50.0 ; - input_threshold_pct_rise : 50.0 ; - output_threshold_pct_rise : 50.0 ; - slew_lower_threshold_pct_fall : 10.0 ; - slew_upper_threshold_pct_fall : 90.0 ; - slew_lower_threshold_pct_rise : 10.0 ; - slew_upper_threshold_pct_rise : 90.0 ; - - nom_voltage : 1.8; - nom_temperature : 25; - nom_process : 1.0; - default_cell_leakage_power : 0.0 ; - default_leakage_power_density : 0.0 ; - default_input_pin_cap : 1.0 ; - default_inout_pin_cap : 1.0 ; - default_output_pin_cap : 0.0 ; - default_max_transition : 0.5 ; - default_fanout_load : 1.0 ; - default_max_fanout : 4.0 ; - default_connection_class : universal ; - - voltage_map ( VDD, 1.8 ); - voltage_map ( GND, 0 ); - - lu_table_template(CELL_TABLE){ - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1("0.00125, 0.005, 0.04"); - index_2("0.0017225, 0.00689, 0.02756"); - } - - lu_table_template(CONSTRAINT_TABLE){ - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1("0.00125, 0.005, 0.04"); - index_2("0.00125, 0.005, 0.04"); - } - - default_operating_conditions : OC; - - - type (data){ - base_type : array; - data_type : bit; - bit_width : 32; - bit_from : 0; - bit_to : 31; - } - - type (addr){ - base_type : array; - data_type : bit; - bit_width : 8; - bit_from : 0; - bit_to : 7; - } - - type (wmask){ - base_type : array; - data_type : bit; - bit_width : 4; - bit_from : 0; - bit_to : 3; - } - -cell (sram_1rw1r_32_256_8_sky130){ - memory(){ - type : ram; - address_width : 8; - word_width : 32; - } - interface_timing : true; - dont_use : true; - map_only : true; - dont_touch : true; - area : 167998.5528; - - pg_pin(vdd) { - voltage_name : VDD; - pg_type : primary_power; - } - - pg_pin(gnd) { - voltage_name : GND; - pg_type : primary_ground; - } - - leakage_power () { - value : 0.009512; - } - cell_leakage_power : 0.009512; - bus(din0){ - bus_type : data; - direction : input; - capacitance : 0.006889999999999999; - memory_write(){ - address : addr0; - clocked_on : clk0; - } - pin(din0[31:0]){ - timing(){ - timing_type : setup_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - } - bus(dout0){ - bus_type : data; - direction : output; - max_capacitance : 0.027559999999999998; - min_capacitance : 0.0017224999999999999; - memory_read(){ - address : addr0; - } - pin(dout0[31:0]){ - timing(){ - timing_sense : non_unate; - related_pin : "clk0"; - timing_type : falling_edge; - cell_rise(CELL_TABLE) { - values("0.494, 0.526, 0.654",\ - "0.494, 0.526, 0.654",\ - "0.494, 0.526, 0.654"); - } - cell_fall(CELL_TABLE) { - values("0.494, 0.526, 0.654",\ - "0.494, 0.526, 0.654",\ - "0.494, 0.526, 0.654"); - } - rise_transition(CELL_TABLE) { - values("0.002, 0.005, 0.018",\ - "0.002, 0.005, 0.018",\ - "0.002, 0.005, 0.018"); - } - fall_transition(CELL_TABLE) { - values("0.002, 0.005, 0.018",\ - "0.002, 0.005, 0.018",\ - "0.002, 0.005, 0.018"); - } - } - } - } - - bus(addr0){ - bus_type : addr; - direction : input; - capacitance : 0.006889999999999999; - max_transition : 0.04; - pin(addr0[7:0]){ - timing(){ - timing_type : setup_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - } - - bus(wmask0){ - bus_type : wmask; - direction : input; - capacitance : 0.006889999999999999; - max_transition : 0.04; - pin(wmask0[3:0]){ - timing(){ - timing_type : setup_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - } - - pin(csb0){ - direction : input; - capacitance : 0.006889999999999999; - timing(){ - timing_type : setup_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - - pin(web0){ - direction : input; - capacitance : 0.006889999999999999; - timing(){ - timing_type : setup_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk0"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - - pin(clk0){ - clock : true; - direction : input; - capacitance : 0.006889999999999999; - internal_power(){ - when : "!csb0 & !web0"; - rise_power(scalar){ - values("1.730279e+01"); - } - fall_power(scalar){ - values("1.730279e+01"); - } - } - internal_power(){ - when : "csb0 & !web0"; - rise_power(scalar){ - values("1.730279e+01"); - } - fall_power(scalar){ - values("1.730279e+01"); - } - } - internal_power(){ - when : "!csb0 & web0"; - rise_power(scalar){ - values("1.730279e+01"); - } - fall_power(scalar){ - values("1.730279e+01"); - } - } - internal_power(){ - when : "csb0 & web0"; - rise_power(scalar){ - values("1.730279e+01"); - } - fall_power(scalar){ - values("1.730279e+01"); - } - } - timing(){ - timing_type :"min_pulse_width"; - related_pin : clk0; - rise_constraint(scalar) { - values("0.0655"); - } - fall_constraint(scalar) { - values("0.0655"); - } - } - timing(){ - timing_type :"minimum_period"; - related_pin : clk0; - rise_constraint(scalar) { - values("0.131"); - } - fall_constraint(scalar) { - values("0.131"); - } - } - } - - bus(dout1){ - bus_type : data; - direction : output; - max_capacitance : 0.027559999999999998; - min_capacitance : 0.0017224999999999999; - memory_read(){ - address : addr1; - } - pin(dout1[31:0]){ - timing(){ - timing_sense : non_unate; - related_pin : "clk1"; - timing_type : falling_edge; - cell_rise(CELL_TABLE) { - values("0.494, 0.526, 0.654",\ - "0.494, 0.526, 0.654",\ - "0.494, 0.526, 0.654"); - } - cell_fall(CELL_TABLE) { - values("0.494, 0.526, 0.654",\ - "0.494, 0.526, 0.654",\ - "0.494, 0.526, 0.654"); - } - rise_transition(CELL_TABLE) { - values("0.002, 0.005, 0.018",\ - "0.002, 0.005, 0.018",\ - "0.002, 0.005, 0.018"); - } - fall_transition(CELL_TABLE) { - values("0.002, 0.005, 0.018",\ - "0.002, 0.005, 0.018",\ - "0.002, 0.005, 0.018"); - } - } - } - } - - bus(addr1){ - bus_type : addr; - direction : input; - capacitance : 0.006889999999999999; - max_transition : 0.04; - pin(addr1[7:0]){ - timing(){ - timing_type : setup_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - } - - bus(wmask1){ - bus_type : wmask; - direction : input; - capacitance : 0.006889999999999999; - max_transition : 0.04; - pin(wmask1[3:0]){ - timing(){ - timing_type : setup_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - } - - pin(csb1){ - direction : input; - capacitance : 0.006889999999999999; - timing(){ - timing_type : setup_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165",\ - "0.165, 0.165, 0.165"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk1"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052",\ - "-0.052, -0.052, -0.052"); - } - } - } - - pin(clk1){ - clock : true; - direction : input; - capacitance : 0.006889999999999999; - internal_power(){ - when : "!csb1"; - rise_power(scalar){ - values("1.730279e+01"); - } - fall_power(scalar){ - values("1.730279e+01"); - } - } - internal_power(){ - when : "csb1"; - rise_power(scalar){ - values("1.730279e+01"); - } - fall_power(scalar){ - values("1.730279e+01"); - } - } - timing(){ - timing_type :"min_pulse_width"; - related_pin : clk1; - rise_constraint(scalar) { - values("0.0655"); - } - fall_constraint(scalar) { - values("0.0655"); - } - } - timing(){ - timing_type :"minimum_period"; - related_pin : clk1; - rise_constraint(scalar) { - values("0.131"); - } - fall_constraint(scalar) { - values("0.131"); - } - } - } - - } -}
diff --git a/sta/Makefile b/sta/Makefile new file mode 100644 index 0000000..2027935 --- /dev/null +++ b/sta/Makefile
@@ -0,0 +1,51 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + +BLOCKS = glbl_cfg wb_interconnect mbist1 mbist2 wb_host +DEF = $(foreach block,$(BLOCKS), ../def/$(block).def) +CLEAN = $(foreach block,$(BLOCKS), clean-$(block)) + +OPENLANE_TAG = mpw3 +OPENLANE_IMAGE_NAME = dineshannayya/openlane:$(OPENLANE_TAG) +OPENLANE_NETLIST_COMMAND = "cd /project/sta && openroad -exit scripts/or_write_verilog.tcl | tee logs/$@.log" +OPENLANE_STA_COMMAND = "cd /project/sta && sta scripts/sta.tcl | tee logs/sta.log" + +all: $(BLOCKS) run_sta + +$(DEF) : + @echo "Missing $@. Please create a def for that design" + @exit 1 + +$(BLOCKS) : % : ../def/%.def create + docker run -it -v $(PWD)/..:/project -e DESIGN_NAME=$@ -u $(shell id -u $(USER)):$(shell id -g $(USER)) $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_NETLIST_COMMAND) + +run_sta: $(BLOCKS) + #sta inside the docker is crashing with segmentation fault, so are running sta outside the docker + #docker run -it -v $(PWD)/..:/project -e DESIGN_NAME=$@ -u $(shell id -u $(USER)):$(shell id -g $(USER)) $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_STA_COMMAND) + sta scripts/sta.tcl | tee logs/sta.log + +create: clean + @echo "create temp directory :)" + mkdir -p netlist + mkdir -p logs + mkdir -p reports + +clean: + @echo "clean everything :)" + rm -rf netlist + rm -rf logs + rm -rf reports +
diff --git a/sta/base.sdc b/sta/base.sdc new file mode 100644 index 0000000..689e7e8 --- /dev/null +++ b/sta/base.sdc
@@ -0,0 +1,896 @@ +# SPDX-FileCopyrightText: 2021 , Dinesh Annayya +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 +# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> + + +set_units -time ns +set ::env(WBM_CLOCK_PERIOD) "10" +set ::env(WBM_CLOCK_PORT) "wb_clk_i" +set ::env(WBM_CLOCK_NAME) "wbm_clk_i" + +set ::env(WBS_CLOCK_PERIOD) "10" +set ::env(WBS_CLOCK_PORT) "u_wb_host*mem_clk" +set ::env(WBS_CLOCK_NAME) "mem_clk" + +set ::env(BIST_CLOCK_PERIOD) "20" +set ::env(BIST_CLOCK_PORT) "u_wb_host*bist_clk" +set ::env(BIST_CLOCK_NAME) "bist_clk" + +###################################### +# WB MASTER Clock domain input output +###################################### +create_clock -name user_clock2 -period 100.0000 [get_ports {user_clock2}] +create_clock -name wbm_clk_i -period 10.0000 [get_ports {wb_clk_i}] +create_clock -name wbs_clk_i -period 10.0000 [get_pins {u_wb_host/wbs_clk_out}] + +set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -hold 0.1000 +set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -setup 0.2000 +set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -hold 0.1000 +set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -setup 0.2000 +set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -hold 0.1000 +set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -setup 0.2000 +set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -hold 0.1000 +set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -setup 0.2000 + +set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -hold 0.1000 +set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -setup 0.2000 +set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -hold 0.1000 +set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -setup 0.2000 +set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -hold 0.1000 +set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -setup 0.2000 +set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -hold 0.1000 +set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -setup 0.2000 + +set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -hold 0.1000 +set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -setup 0.2000 +set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -hold 0.1000 +set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -setup 0.2000 +set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -hold 0.1000 +set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -setup 0.2000 +set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -hold 0.1000 +set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -setup 0.2000 + +set_clock_groups -name async_clock -asynchronous \ + -group [get_clocks {user_clock2}]\ + -group [get_clocks {wbm_clk_i}]\ + -group [get_clocks {wbs_clk_i}] -comment {Async Clock group} + +set_input_delay 2.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wb_rst_i}] + +set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[*]}] +set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_cyc_i}] +set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}] +set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[*]}] +set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_stb_i}] +set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_we_i}] + +set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[*]}] +set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_cyc_i}] +set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}] +set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[*]}] +set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_stb_i}] +set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_we_i}] + + +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_ack_o}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}] + +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_ack_o}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}] +############################################################################### +# Environment +############################################################################### +set_load -pin_load 0.0334 [get_ports {wbs_ack_o}] +set_load -pin_load 0.0334 [get_ports {analog_io[28]}] +set_load -pin_load 0.0334 [get_ports {analog_io[27]}] +set_load -pin_load 0.0334 [get_ports {analog_io[26]}] +set_load -pin_load 0.0334 [get_ports {analog_io[25]}] +set_load -pin_load 0.0334 [get_ports {analog_io[24]}] +set_load -pin_load 0.0334 [get_ports {analog_io[23]}] +set_load -pin_load 0.0334 [get_ports {analog_io[22]}] +set_load -pin_load 0.0334 [get_ports {analog_io[21]}] +set_load -pin_load 0.0334 [get_ports {analog_io[20]}] +set_load -pin_load 0.0334 [get_ports {analog_io[19]}] +set_load -pin_load 0.0334 [get_ports {analog_io[18]}] +set_load -pin_load 0.0334 [get_ports {analog_io[17]}] +set_load -pin_load 0.0334 [get_ports {analog_io[16]}] +set_load -pin_load 0.0334 [get_ports {analog_io[15]}] +set_load -pin_load 0.0334 [get_ports {analog_io[14]}] +set_load -pin_load 0.0334 [get_ports {analog_io[13]}] +set_load -pin_load 0.0334 [get_ports {analog_io[12]}] +set_load -pin_load 0.0334 [get_ports {analog_io[11]}] +set_load -pin_load 0.0334 [get_ports {analog_io[10]}] +set_load -pin_load 0.0334 [get_ports {analog_io[9]}] +set_load -pin_load 0.0334 [get_ports {analog_io[8]}] +set_load -pin_load 0.0334 [get_ports {analog_io[7]}] +set_load -pin_load 0.0334 [get_ports {analog_io[6]}] +set_load -pin_load 0.0334 [get_ports {analog_io[5]}] +set_load -pin_load 0.0334 [get_ports {analog_io[4]}] +set_load -pin_load 0.0334 [get_ports {analog_io[3]}] +set_load -pin_load 0.0334 [get_ports {analog_io[2]}] +set_load -pin_load 0.0334 [get_ports {analog_io[1]}] +set_load -pin_load 0.0334 [get_ports {analog_io[0]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[37]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[36]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[35]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[34]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[33]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[32]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[31]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[30]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[29]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[28]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[27]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[26]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[25]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[24]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[23]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[22]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[21]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[20]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[19]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[18]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[17]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[16]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[15]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[14]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[13]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[12]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[11]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[10]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[9]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[8]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[7]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[6]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[5]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[4]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[3]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[2]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[1]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[0]}] +set_load -pin_load 0.0334 [get_ports {io_out[37]}] +set_load -pin_load 0.0334 [get_ports {io_out[36]}] +set_load -pin_load 0.0334 [get_ports {io_out[35]}] +set_load -pin_load 0.0334 [get_ports {io_out[34]}] +set_load -pin_load 0.0334 [get_ports {io_out[33]}] +set_load -pin_load 0.0334 [get_ports {io_out[32]}] +set_load -pin_load 0.0334 [get_ports {io_out[31]}] +set_load -pin_load 0.0334 [get_ports {io_out[30]}] +set_load -pin_load 0.0334 [get_ports {io_out[29]}] +set_load -pin_load 0.0334 [get_ports {io_out[28]}] +set_load -pin_load 0.0334 [get_ports {io_out[27]}] +set_load -pin_load 0.0334 [get_ports {io_out[26]}] +set_load -pin_load 0.0334 [get_ports {io_out[25]}] +set_load -pin_load 0.0334 [get_ports {io_out[24]}] +set_load -pin_load 0.0334 [get_ports {io_out[23]}] +set_load -pin_load 0.0334 [get_ports {io_out[22]}] +set_load -pin_load 0.0334 [get_ports {io_out[21]}] +set_load -pin_load 0.0334 [get_ports {io_out[20]}] +set_load -pin_load 0.0334 [get_ports {io_out[19]}] +set_load -pin_load 0.0334 [get_ports {io_out[18]}] +set_load -pin_load 0.0334 [get_ports {io_out[17]}] +set_load -pin_load 0.0334 [get_ports {io_out[16]}] +set_load -pin_load 0.0334 [get_ports {io_out[15]}] +set_load -pin_load 0.0334 [get_ports {io_out[14]}] +set_load -pin_load 0.0334 [get_ports {io_out[13]}] +set_load -pin_load 0.0334 [get_ports {io_out[12]}] +set_load -pin_load 0.0334 [get_ports {io_out[11]}] +set_load -pin_load 0.0334 [get_ports {io_out[10]}] +set_load -pin_load 0.0334 [get_ports {io_out[9]}] +set_load -pin_load 0.0334 [get_ports {io_out[8]}] +set_load -pin_load 0.0334 [get_ports {io_out[7]}] +set_load -pin_load 0.0334 [get_ports {io_out[6]}] +set_load -pin_load 0.0334 [get_ports {io_out[5]}] +set_load -pin_load 0.0334 [get_ports {io_out[4]}] +set_load -pin_load 0.0334 [get_ports {io_out[3]}] +set_load -pin_load 0.0334 [get_ports {io_out[2]}] +set_load -pin_load 0.0334 [get_ports {io_out[1]}] +set_load -pin_load 0.0334 [get_ports {io_out[0]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[127]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[126]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[125]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[124]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[123]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[122]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[121]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[120]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[119]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[118]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[117]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[116]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[115]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[114]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[113]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[112]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[111]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[110]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[109]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[108]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[107]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[106]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[105]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[104]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[103]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[102]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[101]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[100]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[99]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[98]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[97]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[96]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[95]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[94]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[93]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[92]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[91]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[90]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[89]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[88]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[87]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[86]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[85]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[84]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[83]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[82]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[81]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[80]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[79]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[78]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[77]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[76]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[75]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[74]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[73]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[72]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[71]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[70]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[69]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[68]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[67]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[66]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[65]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[64]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[63]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[62]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[61]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[60]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[59]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[58]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[57]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[56]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[55]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[54]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[53]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[52]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[51]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[50]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[49]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[48]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[47]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[46]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[45]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[44]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[43]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[42]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[41]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[40]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[39]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[38]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[37]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[36]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[35]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[34]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[33]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[32]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[31]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[30]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[29]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[28]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[27]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[26]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[25]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[24]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[23]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[22]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[21]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[20]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[19]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[18]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[17]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[16]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[15]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[14]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[13]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[12]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[11]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[10]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[9]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[8]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[7]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[6]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[5]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[4]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[3]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[2]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[1]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[0]}] +set_load -pin_load 0.0334 [get_ports {user_irq[2]}] +set_load -pin_load 0.0334 [get_ports {user_irq[1]}] +set_load -pin_load 0.0334 [get_ports {user_irq[0]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[28]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[27]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[26]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[25]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[24]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[23]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[22]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[21]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[20]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[19]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[18]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[17]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[16]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[15]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[14]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[13]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[12]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[11]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[10]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[9]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[8]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[7]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[6]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[5]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[4]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[3]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[2]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[1]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[0]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[122]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[121]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[120]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[118]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[117]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[116]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[115]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[114]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[113]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[112]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[111]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[110]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[109]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[108]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[107]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[106]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[105]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[104]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[103]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[102]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[101]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[100]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[99]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[98]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[97]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[96]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[95]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 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-lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}] + +## Case analysis +set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[0]}] +set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[1]}] +set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[2]}] +set_case_analysis 1 [get_pins {u_intercon/cfg_cska_wi[3]}] + +set_case_analysis 1 [get_pins {u_glbl/cfg_cska_glbl[0]}] +set_case_analysis 1 [get_pins {u_glbl/cfg_cska_glbl[1]}] +set_case_analysis 1 [get_pins {u_glbl/cfg_cska_glbl[2]}] +set_case_analysis 0 [get_pins {u_glbl/cfg_cska_glbl[3]}] + +set_case_analysis 1 [get_pins {u_mbist1/cfg_cska_mbist[0]}] +set_case_analysis 1 [get_pins {u_mbist1/cfg_cska_mbist[1]}] +set_case_analysis 1 [get_pins {u_mbist1/cfg_cska_mbist[2]}] +set_case_analysis 0 [get_pins {u_mbist1/cfg_cska_mbist[3]}] + +set_case_analysis 1 [get_pins {u_mbist2/cfg_cska_mbist[0]}] +set_case_analysis 1 [get_pins {u_mbist2/cfg_cska_mbist[1]}] +set_case_analysis 1 [get_pins {u_mbist2/cfg_cska_mbist[2]}] +set_case_analysis 0 [get_pins {u_mbist2/cfg_cska_mbist[3]}] + +set_case_analysis 1 [get_pins {u_mbist3/cfg_cska_mbist[0]}] +set_case_analysis 1 [get_pins {u_mbist3/cfg_cska_mbist[1]}] +set_case_analysis 1 [get_pins {u_mbist3/cfg_cska_mbist[2]}] +set_case_analysis 0 [get_pins {u_mbist3/cfg_cska_mbist[3]}] + +set_case_analysis 1 [get_pins {u_mbist4/cfg_cska_mbist[0]}] +set_case_analysis 1 [get_pins {u_mbist4/cfg_cska_mbist[1]}] +set_case_analysis 1 [get_pins {u_mbist4/cfg_cska_mbist[2]}] +set_case_analysis 0 [get_pins {u_mbist4/cfg_cska_mbist[3]}] + +set_case_analysis 1 [get_pins {u_mbist5/cfg_cska_mbist[0]}] +set_case_analysis 1 [get_pins {u_mbist5/cfg_cska_mbist[1]}] +set_case_analysis 1 [get_pins {u_mbist5/cfg_cska_mbist[2]}] +set_case_analysis 0 [get_pins {u_mbist5/cfg_cska_mbist[3]}] + +set_case_analysis 1 [get_pins {u_mbist6/cfg_cska_mbist[0]}] +set_case_analysis 1 [get_pins {u_mbist6/cfg_cska_mbist[1]}] +set_case_analysis 1 [get_pins {u_mbist6/cfg_cska_mbist[2]}] +set_case_analysis 0 [get_pins {u_mbist6/cfg_cska_mbist[3]}] + +set_case_analysis 1 [get_pins {u_mbist7/cfg_cska_mbist[0]}] +set_case_analysis 1 [get_pins {u_mbist7/cfg_cska_mbist[1]}] +set_case_analysis 1 [get_pins {u_mbist7/cfg_cska_mbist[2]}] +set_case_analysis 0 [get_pins {u_mbist7/cfg_cska_mbist[3]}] + +set_case_analysis 1 [get_pins {u_mbist8/cfg_cska_mbist[0]}] +set_case_analysis 1 [get_pins {u_mbist8/cfg_cska_mbist[1]}] +set_case_analysis 1 [get_pins {u_mbist8/cfg_cska_mbist[2]}] +set_case_analysis 0 [get_pins {u_mbist8/cfg_cska_mbist[3]}] + +set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[0]}] +set_case_analysis 1 [get_pins {u_wb_host/cfg_cska_wh[1]}] +set_case_analysis 1 [get_pins {u_wb_host/cfg_cska_wh[2]}] +set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[3]}] + +#disable clock gating check at static clock select pins +set_false_path -through [get_pins u_wb_host/u_wbs_clk_sel.u_mux/S] + +#Strobe is registered inside the wb_host before generating chip select +# So wbm_adr_i wbm_we_i wbm_sel_i wbm_dat_i are having 2 cycle setup + +set_multicycle_path -setup -from [get_ports {wbs_adr_i[*]}] 2 +set_multicycle_path -setup -from [get_ports {wbs_cyc_i}] 2 +set_multicycle_path -setup -from [get_ports {wbs_dat_i[*]}] 2 +set_multicycle_path -setup -from [get_ports {wbs_sel_i[*]}] 2 +set_multicycle_path -setup -from [get_ports {wbs_we_i}] 2 + +set_multicycle_path -hold -from [get_ports {wbs_adr_i[*]}] 2 +set_multicycle_path -hold -from [get_ports {wbs_cyc_i}] 2 +set_multicycle_path -hold -from [get_ports {wbs_dat_i[*]}] 2 +set_multicycle_path -hold -from [get_ports {wbs_sel_i[*]}] 2 +set_multicycle_path -hold -from [get_ports {wbs_we_i}] 2
diff --git a/sta/run_sta b/sta/run_sta new file mode 100755 index 0000000..744d864 --- /dev/null +++ b/sta/run_sta
@@ -0,0 +1,35 @@ + +\rm -rf netlist +\rm -rf logs +\rm -rf reports +mkdir netlist +mkdir logs +mkdir reports + +echo "#################################################" +echo "Genenerating Netlist winout power ports" +echo "#################################################" +export MERGED_LEF_UNPADDED=../lef/merged_unpadded.lef + +export DESIGN_NAME=sar_adc +openroad -exit scripts/or_write_verilog.tcl + +export DESIGN_NAME=wb_interconnect +openroad -exit scripts/or_write_verilog.tcl + +export DESIGN_NAME=syntacore +openroad -exit scripts/or_write_verilog.tcl + +export DESIGN_NAME=qspim +openroad -exit scripts/or_write_verilog.tcl + +export DESIGN_NAME=uart_i2cm_usb_spi +openroad -exit scripts/or_write_verilog.tcl + +export DESIGN_NAME=pinmux +openroad -exit scripts/or_write_verilog.tcl + +export DESIGN_NAME=wb_host +openroad -exit scripts/or_write_verilog.tcl + +sta scripts/sta.tcl | tee logs/sta.log
diff --git a/sta/scripts/or_write_verilog.tcl b/sta/scripts/or_write_verilog.tcl new file mode 100644 index 0000000..e24c97e --- /dev/null +++ b/sta/scripts/or_write_verilog.tcl
@@ -0,0 +1,30 @@ +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +set ::env(MERGED_LEF_UNPADDED) "../lef/merged_unpadded.lef" +set ::env(INPUT_DEF) "../def/$::env(DESIGN_NAME).def" +set ::env(SAVE_NETLIST) "netlist/$::env(DESIGN_NAME).v" + + +if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} { + puts stderr $errmsg + exit 1 +} + +if {[catch {read_def $::env(INPUT_DEF)} errmsg]} { + puts stderr $errmsg + exit 1 +} + +#write_verilog -include_pwr_gnd $::env(SAVE_POWER_NETLIST) +write_verilog $::env(SAVE_NETLIST) +
diff --git a/sta/scripts/sta.tcl b/sta/scripts/sta.tcl new file mode 100644 index 0000000..4ac4608 --- /dev/null +++ b/sta/scripts/sta.tcl
@@ -0,0 +1,134 @@ +# SPDX-FileCopyrightText: 2021 , Dinesh Annayya +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 +# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> + +set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib" +set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib" +set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib" +set ::env(DESIGN_NAME) "user_project_wrapper" +set ::env(BASE_SDC_FILE) "base.sdc" +set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8" +set ::env(SYNTH_DRIVING_CELL_PIN) "Y" +set ::env(SYNTH_CAP_LOAD) "17.65" +set ::env(WIRE_RC_LAYER) "met1" + +#To disable empty filler cell black box get created +#set link_make_black_boxes 0 + + +set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um +define_corners wc bc tt +read_liberty -corner bc $::env(LIB_FASTEST) +read_liberty -corner wc $::env(LIB_SLOWEST) +read_liberty -corner tt $::env(LIB_TYPICAL) + +read_lib -corner tt ../lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib +read_lib -corner tt ../lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib + +read_verilog netlist/glbl_cfg.v +read_verilog netlist/mbist1.v +read_verilog netlist/mbist2.v +read_verilog netlist/wb_host.v +read_verilog netlist/wb_interconnect.v +read_verilog ../verilog/gl/user_project_wrapper.v + +link_design $::env(DESIGN_NAME) + +read_spef -path u_mbist1 ../spef/mbist_top1.spef +read_spef -path u_mbist2 ../spef/mbist_top1.spef +read_spef -path u_mbist3 ../spef/mbist_top1.spef +read_spef -path u_mbist4 ../spef/mbist_top1.spef +read_spef -path u_mbist5 ../spef/mbist_top2.spef +read_spef -path u_mbist6 ../spef/mbist_top2.spef +read_spef -path u_mbist7 ../spef/mbist_top2.spef +read_spef -path u_mbist8 ../spef/mbist_top2.spef +read_spef -path u_wb_host ../spef/wb_host.spef +read_spef -path u_intercon ../spef/wb_interconnect.spef +read_spef -path u_glbl ../spef/glbl_cfg.spef +read_spef ../spef/user_project_wrapper.spef + + +read_sdc -echo $::env(BASE_SDC_FILE) + +# check for missing constraints +check_setup -verbose > reports/unconstraints.rpt + +set_operating_conditions -analysis_type single +# Propgate the clock +set_propagated_clock [all_clocks] + +report_tns +report_wns +#report_power +# +echo "################ CORNER : WC (MAX) TIMING Report ###################" > reports/timing_ss_max.rpt +report_checks -unique -slack_max -0.0 -path_delay max -group_count 100 -corner wc -format full_clock_expanded >> reports/timing_ss_max.rpt +report_checks -group_count 100 -path_delay max -path_group wbm_clk_i -corner wc -format full_clock_expanded >> reports/timing_ss_max.rpt +report_checks -group_count 100 -path_delay max -path_group wbs_clk_i -corner wc -format full_clock_expanded >> reports/timing_ss_max.rpt +report_checks -group_count 100 -path_delay max -path_group cpu_clk -corner wc -format full_clock_expanded >> reports/timing_ss_max.rpt +report_checks -group_count 100 -path_delay max -path_group rtc_clk -corner wc -format full_clock_expanded >> reports/timing_ss_max.rpt +report_checks -group_count 100 -path_delay max -path_group line_clk -corner wc -format full_clock_expanded >> reports/timing_ss_max.rpt +report_checks -path_delay max -corner wc >> reports/timing_ss_max.rpt + +echo "################ CORNER : WC (MIN) TIMING Report ###################" > reports/timing_ss_min.rpt +report_checks -unique -slack_max -0.0 -path_delay min -group_count 100 -corner wc -format full_clock_expanded >> reports/timing_ss_min.rpt +report_checks -group_count 100 -path_delay min -path_group wbm_clk_i -corner wc -format full_clock_expanded >> reports/timing_ss_min.rpt +report_checks -group_count 100 -path_delay min -path_group wbs_clk_i -corner wc -format full_clock_expanded >> reports/timing_ss_min.rpt +report_checks -group_count 100 -path_delay min -path_group cpu_clk -corner wc -format full_clock_expanded >> reports/timing_ss_min.rpt +report_checks -group_count 100 -path_delay min -path_group rtc_clk -corner wc -format full_clock_expanded >> reports/timing_ss_min.rpt +report_checks -group_count 100 -path_delay min -path_group line_clk -corner wc -format full_clock_expanded >> reports/timing_ss_min.rpt +report_checks -path_delay min -corner wc >> reports/timing_ss_min.rpt + +echo "################ CORNER : BC (MAX) TIMING Report ###################" > reports/timing_ff_max.rpt +report_checks -unique -slack_max -0.0 -path_delay max -group_count 100 -corner bc -format full_clock_expanded >> reports/timing_ff_max.rpt +report_checks -group_count 100 -path_delay max -path_group wbm_clk_i -corner bc -format full_clock_expanded >> reports/timing_ff_max.rpt +report_checks -group_count 100 -path_delay max -path_group wbs_clk_i -corner bc -format full_clock_expanded >> reports/timing_ff_max.rpt +report_checks -group_count 100 -path_delay max -path_group cpu_clk -corner bc -format full_clock_expanded >> reports/timing_ff_max.rpt +report_checks -group_count 100 -path_delay max -path_group rtc_clk -corner bc -format full_clock_expanded >> reports/timing_ff_max.rpt +report_checks -group_count 100 -path_delay max -path_group line_clk -corner bc -format full_clock_expanded >> reports/timing_ff_max.rpt +report_checks -path_delay max -corner bc >> reports/timing_ff_max.rpt + +echo "################ CORNER : BC (MIN) TIMING Report ###################" > reports/timing_ff_min.rpt +report_checks -unique -slack_max -0.0 -path_delay min -group_count 100 -corner bc -format full_clock_expanded >> reports/timing_ff_min.rpt +report_checks -group_count 100 -path_delay min -path_group wbm_clk_i -corner bc -format full_clock_expanded >> reports/timing_ff_min.rpt +report_checks -group_count 100 -path_delay min -path_group wbs_clk_i -corner bc -format full_clock_expanded >> reports/timing_ff_min.rpt +report_checks -group_count 100 -path_delay min -path_group cpu_clk -corner bc -format full_clock_expanded >> reports/timing_ff_min.rpt +report_checks -group_count 100 -path_delay min -path_group rtc_clk -corner bc -format full_clock_expanded >> reports/timing_ff_min.rpt +report_checks -group_count 100 -path_delay min -path_group line_clk -corner bc -format full_clock_expanded >> reports/timing_ff_min.rpt +report_checks -path_delay min -corner bc >> reports/timing_ff_min.rpt + + +echo "################ CORNER : TT (MAX) TIMING Report ###################" > reports/timing_tt_max.rpt +report_checks -unique -slack_max -0.0 -path_delay max -group_count 100 -corner tt -format full_clock_expanded >> reports/timing_tt_max.rpt +report_checks -group_count 100 -path_delay max -path_group wbm_clk_i -corner tt -format full_clock_expanded >> reports/timing_tt_max.rpt +report_checks -group_count 100 -path_delay max -path_group wbs_clk_i -corner tt -format full_clock_expanded >> reports/timing_tt_max.rpt +report_checks -group_count 100 -path_delay max -path_group cpu_clk -corner tt -format full_clock_expanded >> reports/timing_tt_max.rpt +report_checks -group_count 100 -path_delay max -path_group rtc_clk -corner tt -format full_clock_expanded >> reports/timing_tt_max.rpt +report_checks -group_count 100 -path_delay max -path_group line_clk -corner tt -format full_clock_expanded >> reports/timing_tt_max.rpt +report_checks -path_delay max -corner tt >> reports/timing_tt_max.rpt + +echo "################ CORNER : TT (MIN) TIMING Report ###################" > reports/timing_tt_min.rpt +report_checks -unique -slack_max -0.0 -path_delay min -group_count 100 -corner tt -format full_clock_expanded >> reports/timing_tt_min.rpt +report_checks -group_count 100 -path_delay min -path_group wbm_clk_i -corner tt -format full_clock_expanded >> reports/timing_tt_min.rpt +report_checks -group_count 100 -path_delay min -path_group wbs_clk_i -corner tt -format full_clock_expanded >> reports/timing_tt_min.rpt +report_checks -group_count 100 -path_delay min -path_group cpu_clk -corner tt -format full_clock_expanded >> reports/timing_tt_min.rpt +report_checks -group_count 100 -path_delay min -path_group rtc_clk -corner tt -format full_clock_expanded >> reports/timing_tt_min.rpt +report_checks -group_count 100 -path_delay min -path_group line_clk -corner tt -format full_clock_expanded >> reports/timing_tt_min.rpt +report_checks -path_delay min -corner tt >> reports/timing_tt_min.rpt + + +report_checks -path_delay min_max + +#exit