mbist test clean-up and RTL fix for MBIST ERror insertion
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index d87238f..9ced77b 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus +PATTERNS = wb_port user_mbist_test1 all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports/Makefile deleted file mode 100644 index 5237a05..0000000 --- a/verilog/dv/io_ports/Makefile +++ /dev/null
@@ -1,96 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -## PDK -PDK_PATH = $(PDK_ROOT)/sky130A - -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel - -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_BEHAVIOURAL_MODELS = ../ - -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf - -## Simulation mode: RTL/GL -SIM_DEFINES = -DFUNCTIONAL -DSIM -SIM?=RTL - -.SUFFIXES: - -PATTERN = io_ports - -all: ${PATTERN:=.vcd} - -hex: ${PATTERN:=.hex} - -%.vvp: %_tb.v %.hex -ifeq ($(SIM),RTL) - iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ - $< -o $@ -else - iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - $< -o $@ -endif - -%.vcd: %.vvp - vvp $< - -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env - ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ - # to fix flash base address - sed -i 's/@10000000/@00000000/g' $@ - -%.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ - -check-env: -ifndef PDK_ROOT - $(error PDK_ROOT is undefined, please export it before running make) -endif -ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) - $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) -endif -ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) - $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) -endif -# check for efabless style installation -ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) -SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE -endif - -# ---- Clean ---- - -clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log - -.PHONY: clean hex all
diff --git a/verilog/dv/io_ports/io_ports.c b/verilog/dv/io_ports/io_ports.c deleted file mode 100644 index 0b23571..0000000 --- a/verilog/dv/io_ports/io_ports.c +++ /dev/null
@@ -1,72 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020 Efabless Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * SPDX-License-Identifier: Apache-2.0 - */ - -// This include is relative to $CARAVEL_PATH (see Makefile) -#include "verilog/dv/caravel/defs.h" -#include "verilog/dv/caravel/stub.c" - -/* - IO Test: - - Configures MPRJ lower 8-IO pins as outputs - - Observes counter value through the MPRJ lower 8 IO pins (in the testbench) -*/ - -void main() -{ - /* - IO Control Registers - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | - - Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | - - - Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | - - */ - - /* Set up the housekeeping SPI to be connected internally so */ - /* that external pin changes don't affect it. */ - - reg_spimaster_config = 0xa002; // Enable, prescaler = 2, - // connect to housekeeping SPI - - // Connect the housekeeping SPI to the SPI master - // so that the CSB line is not left floating. This allows - // all of the GPIO pins to be used for user functions. - - // Configure lower 8-IOs as user output - // Observe counter value in the testbench - reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - -} -
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v deleted file mode 100644 index f7628bc..0000000 --- a/verilog/dv/io_ports/io_ports_tb.v +++ /dev/null
@@ -1,169 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none - -`timescale 1 ns / 1 ps - -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" - -module io_ports_tb; - reg clock; - reg RSTB; - reg CSB; - reg power1, power2; - reg power3, power4; - - wire gpio; - wire [37:0] mprj_io; - wire [7:0] mprj_io_0; - - assign mprj_io_0 = mprj_io[7:0]; - // assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]}; - - assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; - // assign mprj_io[3] = 1'b1; - - // External clock is used by default. Make this artificially fast for the - // simulation. Normally this would be a slow clock and the digital PLL - // would be the fast clock. - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - end - - initial begin - $dumpfile("io_ports.vcd"); - $dumpvars(0, io_ports_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (25) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end - $display("%c[1;31m",27); - `ifdef GL - $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed"); - `else - $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); - `endif - $display("%c[0m",27); - $finish; - end - - initial begin - // Observe Output pins [7:0] - wait(mprj_io_0 == 8'h01); - wait(mprj_io_0 == 8'h02); - wait(mprj_io_0 == 8'h03); - wait(mprj_io_0 == 8'h04); - wait(mprj_io_0 == 8'h05); - wait(mprj_io_0 == 8'h06); - wait(mprj_io_0 == 8'h07); - wait(mprj_io_0 == 8'h08); - wait(mprj_io_0 == 8'h09); - wait(mprj_io_0 == 8'h0A); - wait(mprj_io_0 == 8'hFF); - wait(mprj_io_0 == 8'h00); - - `ifdef GL - $display("Monitor: Test 1 Mega-Project IO (GL) Passed"); - `else - $display("Monitor: Test 1 Mega-Project IO (RTL) Passed"); - `endif - $finish; - end - - initial begin - RSTB <= 1'b0; - CSB <= 1'b1; // Force CSB high - #2000; - RSTB <= 1'b1; // Release reset - #170000; - CSB = 1'b0; // CSB can be released - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - power3 <= 1'b0; - power4 <= 1'b0; - #100; - power1 <= 1'b1; - #100; - power2 <= 1'b1; - #100; - power3 <= 1'b1; - #100; - power4 <= 1'b1; - end - - always @(mprj_io) begin - #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); - end - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD3V3 = power1; - wire VDD1V8 = power2; - wire USER_VDD3V3 = power3; - wire USER_VDD1V8 = power4; - wire VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vssio (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (USER_VDD3V3), - .vdda2 (USER_VDD3V3), - .vssa1 (VSS), - .vssa2 (VSS), - .vccd1 (USER_VDD1V8), - .vccd2 (USER_VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - spiflash #( - .FILENAME("io_ports.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), // not used - .io3() // not used - ); - -endmodule -`default_nettype wire
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c deleted file mode 100644 index e4d0a2d..0000000 --- a/verilog/dv/mprj_stimulus/mprj_stimulus.c +++ /dev/null
@@ -1,134 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020 Efabless Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * SPDX-License-Identifier: Apache-2.0 - */ - -// This include is relative to $CARAVEL_PATH (see Makefile) -#include "verilog/dv/caravel/defs.h" - -// -------------------------------------------------------- - -void main() -{ - // The upper GPIO pins are configured to be output - // and accessble to the management SoC. - // Used to flag the start/end of a test - // The lower GPIO pins are configured to be output - // and accessible to the user project. They show - // the project count value, although this test is - // designed to read the project count through the - // logic analyzer probes. - // I/O 6 is configured for the UART Tx line - uint32_t testval; - - reg_spimaster_config = 0xa002; // Enable, prescaler = 2 - - reg_mprj_datal = 0x00000000; - reg_mprj_datah = 0x00000000; - - reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;; - reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;; - reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; - reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; - reg_mprj_io_33 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; - reg_mprj_io_32 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; - - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - - reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_9 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_8 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_7 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; - - reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; - - // Set UART clock to 64 kbaud (enable before I/O configuration) - reg_uart_clkdiv = 625; - reg_uart_enable = 1; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - /* TEST: Recast channels 35 to 32 to allow input to user project */ - /* This is done locally only: Do not run reg_mprj_xfer! */ - reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; - - // Configure LA probes [31:0], [127:64] as inputs to the cpu - // Configure LA probes [63:32] as outputs from the cpu - reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] - reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32] - reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64] - reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96] - - // Flag start of the test - reg_mprj_datal = 0xAB400000; - - // Set Counter value to zero through LA probes [63:32] - reg_la1_data = 0x00000000; - - // Configure LA probes from [63:32] as inputs to disable counter write - reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; - - reg_mprj_datal = 0xAB410000; - reg_mprj_datah = 0x00000000; - - // Test ability to force data on channel 37 - // NOTE: Only the low 6 bits of reg_mprj_datah are meaningful - reg_mprj_datah = 0xffffffca; - reg_mprj_datah = 0x00000000; - reg_mprj_datah = 0x0f0f0fc5; - reg_mprj_datah = 0x00000000; - - // Test ability to read back data generated by the user project - // on the "monitored" outputs. Read from the lower 16 bits and - // copy the value to the upper 16 bits. - - testval = reg_mprj_datal; - reg_mprj_datal = ((testval & 0xff8) << 9) & 0xffff0000; - - // Flag end of the test - reg_mprj_datal = 0xAB510000; -} -
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v deleted file mode 100644 index 1409015..0000000 --- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v +++ /dev/null
@@ -1,157 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype wire - -`timescale 1 ns / 1 ps - -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" -`include "tbuart.v" - -module mprj_stimulus_tb; - // Signals declaration - reg clock; - reg RSTB; - reg CSB; - reg power1, power2; - reg power3, power4; - - wire HIGH; - wire LOW; - wire TRI; - assign HIGH = 1'b1; - assign LOW = 1'b0; - assign TRI = 1'bz; - - wire gpio; - wire uart_tx; - wire [37:0] mprj_io; - wire [15:0] checkbits; - wire [3:0] status; - - // Signals Assignment - assign checkbits = mprj_io[31:16]; - assign status = mprj_io[35:32]; - assign uart_tx = mprj_io[6]; - assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - end - - initial begin - $dumpfile("mprj_stimulus.vcd"); - $dumpvars(0, mprj_stimulus_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (150) begin - repeat (1000) @(posedge clock); - end - $display("%c[1;31m",27); - $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed"); - $display("%c[0m",27); - $finish; - end - - initial begin - wait(checkbits == 16'hAB40); - $display("Monitor: mprj_stimulus test started"); - wait(status == 4'ha); - wait(status == 4'h5); - // Value 0009 reflects copying user-controlled outputs to memory and back - // to management-controlled outputs. - wait(checkbits == 16'h0009); - wait(checkbits == 16'hAB51); - $display("Monitor: mprj_stimulus test Passed"); - #10000; - $finish; - end - - // Reset Operation - initial begin - RSTB <= 1'b0; - CSB <= 1'b1; // Force CSB high - #2000; - RSTB <= 1'b1; // Release reset - #170000; - CSB = 1'b0; // CSB can be released - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - #200; - power1 <= 1'b1; - #200; - power2 <= 1'b1; - end - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD3V3 = power1; - wire VDD1V8 = power2; - wire VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vssio (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (VDD3V3), - .vdda2 (VDD3V3), - .vssa1 (VSS), - .vssa2 (VSS), - .vccd1 (VDD1V8), - .vccd2 (VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - - spiflash #( - .FILENAME("mprj_stimulus.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), // not used - .io3() // not used - ); - - // Testbench UART - tbuart tbuart ( - .ser_rx(uart_tx) - ); - -endmodule -`default_nettype wire
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/user_mbist_test1/Makefile similarity index 68% rename from verilog/dv/mprj_stimulus/Makefile rename to verilog/dv/user_mbist_test1/Makefile index 3a73b99..761ad58 100644 --- a/verilog/dv/mprj_stimulus/Makefile +++ b/verilog/dv/user_mbist_test1/Makefile
@@ -29,29 +29,37 @@ UPRJ_VERILOG_PATH ?= ../../../verilog UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl UPRJ_BEHAVIOURAL_MODELS = ../ +UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/mbist/include -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf ## Simulation mode: RTL/GL SIM_DEFINES = -DFUNCTIONAL -DSIM SIM?=RTL +DUMP?=OFF .SUFFIXES: -PATTERN = mprj_stimulus +PATTERN = user_mbist_test1 all: ${PATTERN:=.vcd} -hex: ${PATTERN:=.hex} +vvp: ${PATTERN:=.vvp} -%.vvp: %_tb.v %.hex +%.vvp: %_tb.v ifeq ($(SIM),RTL) - iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ + ifeq ($(DUMP),OFF) + iverilog -g2005-sv $(SIM_DEFINES) -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ + -I $(UPRJ_INCLUDE_PATH1) \ $< -o $@ + else + iverilog -g2005-sv -DWFDUMP $(SIM_DEFINES) -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ + -I $(UPRJ_INCLUDE_PATH1) \ + $< -o $@ + endif else iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ @@ -62,17 +70,6 @@ %.vcd: %.vvp vvp $< -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env - ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ - # to fix flash base address - sed -i 's/@10000000/@00000000/g' $@ - -%.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ - check-env: ifndef PDK_ROOT $(error PDK_ROOT is undefined, please export it before running make) @@ -80,9 +77,9 @@ ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) endif -ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) - $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) -endif +#ifeq (,$(wildcard $(GCC64_PREFIX)-gcc )) +# $(error $(GCC64_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) +#endif # check for efabless style installation ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE @@ -91,6 +88,6 @@ # ---- Clean ---- clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + rm -f *.vvp *.vcd *.log -.PHONY: clean hex all +.PHONY: clean all
diff --git a/verilog/dv/user_mbist_test1/run_iverilog b/verilog/dv/user_mbist_test1/run_iverilog new file mode 100755 index 0000000..e66b863 --- /dev/null +++ b/verilog/dv/user_mbist_test1/run_iverilog
@@ -0,0 +1,31 @@ +# ////////////////////////////////////////////////////////////////////////////// +# // SPDX-FileCopyrightText: 2021, Dinesh Annayya +# // +# // Licensed under the Apache License, Version 2.0 (the "License"); +# // you may not use this file except in compliance with the License. +# // You may obtain a copy of the License at +# // +# // http://www.apache.org/licenses/LICENSE-2.0 +# // +# // Unless required by applicable law or agreed to in writing, software +# // distributed under the License is distributed on an "AS IS" BASIS, +# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# // See the License for the specific language governing permissions and +# // limitations under the License. +# // SPDX-License-Identifier: Apache-2.0 +# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +# // ////////////////////////////////////////////////////////////////////////// + +#iverilog without Dump +# +iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I /home/dinesha/workarea/efabless/MPW-3/pdk/sky130A \ +-I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/dv/caravel \ +-I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/rtl \ +-I ../ -I ../../../verilog/rtl \ +-I ../../../verilog/rtl/mbist/include \ +user_mbist_test1_tb.v -o user_mbist_test1.vvp + + +vvp user_mbist_test1.vvp | tee test.log + +\rm -rf user_mbist_test1.vvp
diff --git a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v new file mode 100644 index 0000000..688eb04 --- /dev/null +++ b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
@@ -0,0 +1,360 @@ +//////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +////////////////////////////////////////////////////////////////////// +//// //// +//// Standalone User validation Test bench //// +//// //// +//// //// +//// Description //// +//// This is a standalone test bench to validate the //// +//// Digital core MBIST logic through External WB i/F. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 18 Oct 2021, Dinesh A //// +//// //// +////////////////////////////////////////////////////////////////////// + +`default_nettype wire + +`timescale 1 ns / 1 ns + +`include "uprj_netlists.v" + +module user_mbist_test1_tb; + reg clock; + reg wb_rst_i; + reg power1, power2; + reg power3, power4; + + reg wbd_ext_cyc_i; // strobe/request + reg wbd_ext_stb_i; // strobe/request + reg [31:0] wbd_ext_adr_i; // address + reg wbd_ext_we_i; // write + reg [31:0] wbd_ext_dat_i; // data output + reg [3:0] wbd_ext_sel_i; // byte enable + + wire [31:0] wbd_ext_dat_o; // data input + wire wbd_ext_ack_o; // acknowlegement + wire wbd_ext_err_o; // error + + // User I/O + wire [37:0] io_oeb; + wire [37:0] io_out; + wire [37:0] io_in; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + reg test_fail; + reg [31:0] read_data; + event error_insert; + + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + end + + `ifdef WFDUMP + initial begin + $dumpfile("simx.vcd"); + $dumpvars(4, user_mbist_test1_tb); + end + `endif + + initial begin + wb_rst_i <= 1'b1; + #100; + wb_rst_i <= 1'b0; // Release reset + + #200; // Wait for reset removal + repeat (10) @(posedge clock); + $display("Monitor: Standalone User Test Started"); + + // Remove Wb Reset + wb_user_core_write('h3080_0004,'h1); + + repeat (2) @(posedge clock); + #1; + // Set the Bist Enable and Bist Run + wb_user_core_write('h3080_0008,'h003); + + // Remove WB and BIST RESET + wb_user_core_write('h3080_0004,'h003); + + test_fail = 0; + + // BIST Test without any MEMORY ERROR // + fork + begin + // Check for MBIST Done + read_data = 'h0; + while (read_data[0] != 1'b1) begin + wb_user_core_read('h3080_000C,read_data); + end + // Check Is there is any BIST Error + if(read_data[1:0] == 2'b11) test_fail = 1; + end + begin + // Loop for BIST TimeOut + repeat (200000) @(posedge clock); + // $display("+1000 cycles"); + test_fail = 1; + end + join_any + + disable fork; //disable pending fork activity + + if(test_fail == 0) begin + $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Passed"); + end else begin + $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Failed"); + end + $display("###################################################"); + + wb_user_core_write('h3080_0008,'h000); + // Apply WB and BIST RESET + wb_user_core_write('h3080_0004,'h000); + // Set the Bist Enable and Bist Run + wb_user_core_write('h3080_0008,'h003); + // Remove WB and BIST RESET + wb_user_core_write('h3080_0004,'h003); + // BIST Test without One MEMORY ERROR // + fork + begin + // Check for MBIST Done + read_data = 'h0; + while (read_data[0] != 1'b1) begin + wb_user_core_read('h3080_000C,read_data); + end + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [6:3] - Bist Error Cnt - 4'h1 + if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 + end + // Single bit Error Insertion + begin + while(1) begin + repeat (1) @(posedge clock); + #1; + if(u_top.u_sram_2kb.web0 == 1'b0 && u_top.u_sram_2kb.addr0 == 'h10) begin + force u_top.u_sram_2kb.din0 = u_top.mem_din_b & 16'hFFFE; + -> error_insert; + end else begin + release u_top.u_sram_2kb.din0; + end + end + end + begin + // Loop for BIST TimeOut + repeat (200000) @(posedge clock); + // $display("+1000 cycles"); + test_fail = 1; + end + join_any + disable fork; //disable pending fork activity + + if(test_fail == 0) begin + $display("Monitor: Step-2: BIST Test with One Memory Error insertion test Passed"); + end else begin + $display("Monitor: Step-2: BIST Test with One Memory Error insertion test Failed"); + end + $display("###################################################"); + + $finish; + end + +wire USER_VDD1V8 = 1'b1; +wire VSS = 1'b0; + + +user_project_wrapper u_top( +`ifdef USE_POWER_PINS + .vccd1(USER_VDD1V8), // User area 1 1.8V supply + .vssd1(VSS), // User area 1 digital ground +`endif + .wb_clk_i (clock), // System clock + .user_clock2 (1'b1), // Real-time clock + .wb_rst_i (wb_rst_i), // Regular Reset signal + + .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request + .wbs_stb_i (wbd_ext_stb_i), // strobe/request + .wbs_adr_i (wbd_ext_adr_i), // address + .wbs_we_i (wbd_ext_we_i), // write + .wbs_dat_i (wbd_ext_dat_i), // data output + .wbs_sel_i (wbd_ext_sel_i), // byte enable + + .wbs_dat_o (wbd_ext_dat_o), // data input + .wbs_ack_o (wbd_ext_ack_o), // acknowlegement + + + // Logic Analyzer Signals + .la_data_in ('0) , + .la_data_out (), + .la_oenb ('0), + + + // IOs + .io_in (io_in) , + .io_out (io_out) , + .io_oeb (io_oeb) , + + .user_irq () + +); + +`ifndef GL // Drive Power for Hold Fix Buf + // All standard cell need power hook-up for functionality work + initial begin + + force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8; + force u_top.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8; + force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS; + force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS; + + force u_top.u_wb_host.u_buf_bist_rst.VPWR =USER_VDD1V8; + force u_top.u_wb_host.u_buf_bist_rst.VPB =USER_VDD1V8; + force u_top.u_wb_host.u_buf_bist_rst.VGND =VSS; + force u_top.u_wb_host.u_buf_bist_rst.VNB = VSS; + + force u_top.u_wb_host.u_clkbuf_bist.VPWR =USER_VDD1V8; + force u_top.u_wb_host.u_clkbuf_bist.VPB =USER_VDD1V8; + force u_top.u_wb_host.u_clkbuf_bist.VGND =VSS; + force u_top.u_wb_host.u_clkbuf_bist.VNB = VSS; + + force u_top.u_wb_host.u_clkbuf_mem.VPWR =USER_VDD1V8; + force u_top.u_wb_host.u_clkbuf_mem.VPB =USER_VDD1V8; + force u_top.u_wb_host.u_clkbuf_mem.VGND =VSS; + force u_top.u_wb_host.u_clkbuf_mem.VNB = VSS; + + end +`endif + + + + + +task wb_user_core_write; +input [31:0] address; +input [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h1; // write + wbd_ext_dat_i =data; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read; +input [31:0] address; +output [31:0] data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read_check; +input [31:0] address; +output [31:0] data; +input [31:0] cmp_data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + user_mbist_test1_tb.test_fail = 1; + end else begin + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + end + repeat (2) @(posedge clock); +end +endtask + + +endmodule +`default_nettype wire
diff --git a/verilog/rtl/mbist/include/mbist_def.svh b/verilog/rtl/mbist/include/mbist_def.svh index 12879e1..10fb2ea 100644 --- a/verilog/rtl/mbist/include/mbist_def.svh +++ b/verilog/rtl/mbist/include/mbist_def.svh
@@ -40,19 +40,21 @@ // BIST STIMULATION SELECT parameter BIST_STI_SIZE = 5; -parameter BIST_STI_WD = 12; -parameter BIST_STIMULUS_TYPE1 = 12'b100100100100; -parameter BIST_STIMULUS_TYPE2 = 12'b100010101011; -parameter BIST_STIMULUS_TYPE3 = 12'b110011100010; -parameter BIST_STIMULUS_TYPE4 = 12'b000010101011; -parameter BIST_STIMULUS_TYPE5 = 12'b010011100010; -parameter BIST_STIMULUS_TYPE6 = 12'b000000000000; -parameter BIST_STIMULUS_TYPE7 = 12'b000000000000; -parameter BIST_STIMULUS_TYPE8 = 12'b000000000000; +parameter BIST_STI_WD = 15; +// Additional 3'b000 added at end of each stimulus to flush out the comparion +// result + to handle error fix case +parameter BIST_STIMULUS_TYPE1 = 15'b100100100100000; +parameter BIST_STIMULUS_TYPE2 = 15'b100010101011000; +parameter BIST_STIMULUS_TYPE3 = 15'b110011100010000; +parameter BIST_STIMULUS_TYPE4 = 15'b000010101011000; +parameter BIST_STIMULUS_TYPE5 = 15'b010011100010000; +parameter BIST_STIMULUS_TYPE6 = 15'b000000000000000; +parameter BIST_STIMULUS_TYPE7 = 15'b000000000000000; +parameter BIST_STIMULUS_TYPE8 = 15'b000000000000000; // Operation -parameter BIST_OP_SIZE = 3; +parameter BIST_OP_SIZE = 4; // BIST ADDRESS REPAIR //parameter BIST_RAD_WD_I = BIST_ADDR_WD;
diff --git a/verilog/rtl/mbist/src/mbist_data_cmp.sv b/verilog/rtl/mbist/src/mbist_data_cmp.sv index dc3bbaa..ee6d19e 100644 --- a/verilog/rtl/mbist/src/mbist_data_cmp.sv +++ b/verilog/rtl/mbist/src/mbist_data_cmp.sv
@@ -49,12 +49,14 @@ parameter BIST_RAD_WD_O = BIST_ADDR_WD) ( output logic error, - output logic error_fix, + output logic error_correct, output logic correct, output logic [BIST_ADDR_WD-1:0] error_addr, + output logic [3:0] error_cnt, input logic clk, input logic rst_n, input logic compare, + input logic addr_inc_phase, input logic read_invert, input logic [BIST_DATA_WD-1:0] comp_data, input logic [BIST_DATA_WD-1:0] rxd_data, @@ -62,7 +64,7 @@ ); -logic [3:0] error_cnt; +logic mask_compare; logic [BIST_DATA_WD-1:0] exp_data; logic comp_status; @@ -74,7 +76,7 @@ if(!rst_n) begin comp_status <= 1'b0; error_addr <= 'b0; - end else if(compare) begin + end else if(compare && !mask_compare) begin comp_status <= |(exp_data ^ rxd_data); error_addr <= addr; end else begin @@ -82,21 +84,26 @@ end end +// Due to cycle diference between compare and write opperation +// There is chance two error reported for same address +// To avoid this, once error is detected, comparision is masked +// unit the next address phase always @(posedge clk or negedge rst_n) begin if(!rst_n) begin - error_cnt <= 'b0; - error_fix <='b0; - correct <='b0; - end else if(comp_status == 0) begin - error_fix <= 1'b0; - end else if(error_cnt < BIST_ERR_LIMIT ) begin - error_cnt <= error_cnt+1; - error_fix <= 1'b1; - correct <='b1; + error_cnt <= 'b0; + correct <='b0; + mask_compare <= 'b0; + end else if(mask_compare && addr_inc_phase) begin + mask_compare <= 1'b0; + end else if(comp_status && (error_cnt < BIST_ERR_LIMIT) ) begin + error_cnt <= error_cnt+1; + mask_compare <= 1'b1; + correct <='b1; end end -assign error = (error_cnt < BIST_ERR_LIMIT) ? 1'b0 : comp_status; +assign error = (error_cnt < BIST_ERR_LIMIT) ? 1'b0 : 1'b1; +assign error_correct = (error_cnt < BIST_ERR_LIMIT) ? comp_status : 1'b0; endmodule
diff --git a/verilog/rtl/mbist/src/mbist_fsm.sv b/verilog/rtl/mbist/src/mbist_fsm.sv index 7d0ae23..37f3f95 100644 --- a/verilog/rtl/mbist/src/mbist_fsm.sv +++ b/verilog/rtl/mbist/src/mbist_fsm.sv
@@ -112,7 +112,7 @@ end else begin cmd_phase <= 0; cmp_phase <= 1; - run_op <= 1; + run_op <= 1; if(last_op && !(last_addr && op_reverse)) run_addr <= 1; if(last_addr && last_op)
diff --git a/verilog/rtl/mbist/src/mbist_mux.sv b/verilog/rtl/mbist/src/mbist_mux.sv index f210375..cd2ebe2 100755 --- a/verilog/rtl/mbist/src/mbist_mux.sv +++ b/verilog/rtl/mbist/src/mbist_mux.sv
@@ -103,7 +103,7 @@ assign mem_cen_b = (bist_en) ? !bist_wr : func_cen_b; assign mem_web_b = (bist_en) ? !bist_wr : func_web_b; -assign mem_mask_b = (bist_en) ? {BIST_MASK_WD'(1'b1)} : func_mask_b; +assign mem_mask_b = (bist_en) ? {{BIST_MASK_WD}{1'b1}} : func_mask_b; assign mem_clk_a = (bist_en) ? bist_clk : func_clk_a; assign mem_clk_b = (bist_en) ? bist_clk : func_clk_b; @@ -115,11 +115,11 @@ assign func_dout_a = mem_dout_a; mbist_repair_addr u_repair_A( - .AddressOut (mem_addr_a ), + .AddressOut (mem_addr_a ), .Correct (bist_correct ), .AddressIn (addr_a ), - .clk (CLKA_sel ), + .clk (mem_clk_a ), .rst_n (rst_n ), .Error (bist_error ), .ErrorAddr (bist_error_addr )
diff --git a/verilog/rtl/mbist/src/mbist_op_sel.sv b/verilog/rtl/mbist/src/mbist_op_sel.sv index 5234801..5a18501 100644 --- a/verilog/rtl/mbist/src/mbist_op_sel.sv +++ b/verilog/rtl/mbist/src/mbist_op_sel.sv
@@ -63,6 +63,7 @@ input logic rst_n , // Reset input logic scan_shift , // Scan Shift input logic sdi , // Scan data in + input logic re_init , // Re-init when there is error correction input logic run , // Run input logic [BIST_STI_WD-1:0] stimulus @@ -83,13 +84,15 @@ always @(posedge clk or negedge rst_n) begin if(!rst_n) op_sel <= {1'b1,{(BIST_OP_SIZE-1){1'b0}}}; else if(scan_shift) op_sel <= {sdi, op_sel[BIST_OP_SIZE-2:1]}; + else if(re_init) op_sel <= {1'b1,{(BIST_OP_SIZE-1){1'b0}}}; // need fix for pmbist moode else if(run) op_sel <= {op_sel[0],op_sel[BIST_OP_SIZE-1:1]}; end assign op_updown = stimulus[BIST_STI_WD-1]; assign op_reverse = stimulus[BIST_STI_WD-2]; assign op_repeatflag = stimulus[BIST_STI_WD-3]; -assign last_op = op_sel[0]; +// Re-wind the operation, when the is error correct +assign last_op = (re_init) ? 1'b0 : op_sel[0];
diff --git a/verilog/rtl/mbist/src/mbist_top.sv b/verilog/rtl/mbist/src/mbist_top.sv index 7f02c2c..f2310e3 100644 --- a/verilog/rtl/mbist/src/mbist_top.sv +++ b/verilog/rtl/mbist/src/mbist_top.sv
@@ -58,6 +58,9 @@ input logic bist_load, input logic bist_sdi, + output logic [3:0] bist_error_cnt, + output logic bist_correct, + output logic bist_error, output logic bist_done, output logic bist_sdo, @@ -116,16 +119,14 @@ //--------------------------------- // SDI => SDO diasy chain -// bist_sdi => bist_addr_sdo => bist_sti_sdo => bist_op_sdo => bist_pat_sdo +// bist_sdi => bist_addr_sdo => bist_sti_sdo => bist_op_sdo => bist_sdo // --------------------------------- logic bist_addr_sdo ; logic bist_sti_sdo ; logic bist_op_sdo ; logic bist_pat_sdo ; -logic bist_error ; -logic bist_error_fix ; -logic bist_correct ; +logic bist_error_correct ; logic [BIST_ADDR_WD-1:0]bist_error_addr ; // bist address logic [BIST_ADDR_WD-1:0]bist_addr ; // bist address @@ -253,6 +254,7 @@ .rst_n (rst_n ), .scan_shift (bist_shift ), .sdi (bist_sti_sdo ), + .re_init (bist_error_correct ), .run (run_op ), .stimulus (stimulus ) @@ -273,12 +275,12 @@ u_pat_sel ( .pat_last (last_pat ), .pat_data (pat_data ), - .sdo (bist_pat_sdo ), + .sdo (bist_sdo ), .clk (bist_clk ), .rst_n (rst_n ), .run (run_pat ), .scan_shift (scan_shift ), - .sdi (bist_sdo ) + .sdi (bist_op_sdo ) ); @@ -297,10 +299,13 @@ u_cmp ( .error (bist_error ), - .error_fix (bist_error_fix ), + .error_correct (bist_error_correct ), + .correct ( ), // same signal available at bist mux .error_addr (bist_error_addr ), + .error_cnt (bist_error_cnt ), .clk (bist_clk ), .rst_n (rst_n ), + .addr_inc_phase (run_addr ), .compare (compare ), .read_invert (op_invert ), .comp_data (pat_data ), @@ -327,10 +332,10 @@ .bist_en (bist_en ), .bist_addr (bist_addr ), .bist_wdata (bist_wdata ), - .bist_clk (mem_clk ), + .bist_clk (bist_clk ), .bist_wr (bist_wr ), .bist_rd (bist_rd ), - .bist_error (bist_error_fix), + .bist_error (bist_error_correct), .bist_error_addr (bist_error_addr), .bist_correct (bist_correct ),
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index a92be97..96d897c 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -23,7 +23,12 @@ `include "gl/user_project_wrapper.v" `include "gl/user_proj_example.v" `else - `include "user_project_wrapper.v" + `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v" + `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v" + `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v" + `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v" + + `include "user_project_wrapper.v" `include "mbist/src/mbist_addr_gen.sv"
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 6e21693..bdbd434 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -105,6 +105,9 @@ wire bist_load; wire bist_sdi; +wire [3:0] bist_error_cnt; +wire bist_correct; +wire bist_error; wire bist_done; wire bist_sdo; @@ -167,6 +170,9 @@ .bist_load (bist_load ), .bist_sdi (bist_sdi ), + .bist_error_cnt (bist_error_cnt ), + .bist_correct (bist_correct ), + .bist_error (bist_error ), .bist_done (bist_done ), .bist_sdo (bist_sdo ), @@ -214,6 +220,9 @@ .bist_load (bist_load ), .bist_sdi (bist_sdi ), + .bist_error_cnt (bist_error_cnt ), + .bist_correct (bist_correct ), + .bist_error (bist_error ), .bist_done (bist_done ), .bist_sdo (bist_sdo ),
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv index 48a2264..f3470cf 100644 --- a/verilog/rtl/wb_host/src/wb_host.sv +++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -98,6 +98,9 @@ output logic bist_load, output logic bist_sdi, + input logic [3:0] bist_error_cnt, + input logic bist_correct, + input logic bist_error, input logic bist_done, input logic bist_sdo, @@ -176,8 +179,8 @@ assign wbm_rst_n = !wbm_rst_i; assign wbs_rst_n = !wbm_rst_i; -sky130_fd_sc_hd__bufbuf_16 u_buf_wb_rst (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n)); -sky130_fd_sc_hd__bufbuf_16 u_buf_cpu_rst (.A(cfg_glb_ctrl[1]),.X(bist_rst_n)); +sky130_fd_sc_hd__bufbuf_16 u_buf_wb_rst (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n)); +sky130_fd_sc_hd__bufbuf_16 u_buf_bist_rst (.A(cfg_glb_ctrl[1]),.X(bist_rst_n)); // To reduce the load/Timing Wishbone I/F, Strobe is register to create @@ -255,7 +258,7 @@ assign bist_sdi = cfg_bist_ctrl[4]; // BIST Status -assign cfg_bist_status = {30'h0,bist_done,bist_sdo}; +assign cfg_bist_status = {24'h0,bist_sdo,bist_error_cnt,bist_correct,bist_error,bist_done}; always @( *) @@ -328,7 +331,7 @@ // Slave Port .wbs_rst_n (wbs_rst_n ), - .wbs_clk_i (wbs_clk_i ), + .wbs_clk_i (mem_clk ), .wbs_cyc_o (wbs_cyc_o ), .wbs_stb_o (wbs_stb_o ), .wbs_adr_o (wbs_adr_o ), @@ -350,7 +353,7 @@ assign func_din_b = wbs_dat_o; assign func_clk_a = mem_clk; -assign func_cen_a = !(wbs_stb_o == 1'b0 && wbs_we_o == 1'b0); +assign func_cen_a = !(wbs_stb_o == 1'b1 && wbs_we_o == 1'b0); assign func_addr_a = wbs_adr_o[10:2]; assign wbs_dat_i = func_dout_a;