blob: e2984a488d5575dfe9f0a1071bdb0d08ec5ecaf9 [file] [log] [blame]
v {xschem version=2.9.8 file_version=1.2
* Copyright 2021 Stefan Frederik Schippers
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
}
G {type=stdcell
vhdl_stop=true
verilog_stop=true
format="@name @pinlist @VCCPIN @VSSPIN @VCCBPIN @VSSBPIN @symname"
template="name=x1 VCCPIN=VCC VSSPIN=VSS VCCBPIN=VCC VSSBPIN=VSS"
generic_type="VCCPIN=string VSSPIN=string VCCBPIN=string VSSBPIN=string"
extra="VCCPIN VSSPIN VCCBPIN VSSBPIN"}
V {}
S {}
E {}
L 4 40 -40 60 -40 {}
L 4 40 40 60 40 {}
L 4 -60 -40 -40 -40 {}
L 4 -60 0 -40 0 {}
L 4 -60 40 -40 40 {}
B 5 57.5 -42.5 62.5 -37.5 {name=S dir=out verilog_type=wire}
B 5 57.5 37.5 62.5 42.5 {name=C dir=out verilog_type=wire}
B 5 -62.5 -42.5 -57.5 -37.5 {name=A dir=in}
B 5 -62.5 -2.5 -57.5 2.5 {name=B dir=in}
B 5 -62.5 37.5 -57.5 42.5 {name=CI dir=in}
P 4 5 -40 -50 -40 50 40 50 40 -50 -40 -50 {}
T {@name} -23.75 -25 0 0 0.2 0.2 {}
T {@symname} -35 -65 0 0 0.2 0.2 {}
T {S} 35 -45 0 1 0.2 0.2 {}
T {C} 35 35 0 1 0.2 0.2 {}
T {A} -35 -45 0 0 0.2 0.2 {}
T {B} -35 -5 0 0 0.2 0.2 {}
T {CI} -35 35 0 0 0.2 0.2 {}